TPS54340B-Q1 [TI]
具有 Eco-Mode™ 的汽车类、4.5V 至 42V 输入、3.5A 降压转换器;
| 型号： | TPS54340B-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-Mode™ 的汽车类、4.5V 至 42V 输入、3.5A 降压转换器 转换器 |
| 文件： | 总45页 (文件大小：2267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
采用 Eco-mode™ 的 4.5V 至 42V 输入、3.5A TPS54340B-Q1 降压直流/
直流转换器
1 特性
2 应用
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 的下列结果：
•
车辆附件：全球卫星定位 (GPS)（请参见
SLVA412），娱乐系统，高级驾驶员辅助系统
(ADAS)，紧急呼叫系统 (eCall)
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
•
USB 专用充电端口和电池充电器（请参见
SLVA464）
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H1C
•
•
工业自动化和电机控制
12V 和 24V 工业、汽车和通信电源系统
器件组件充电模式 (CDM) ESD 分类等级 C3B
•
•
可在轻负载条件下实现高效率，采用脉冲跳跃 Eco-
mode™
3 说明
TPS54340B-Q1 是一款配有集成型高侧 MOSFET 的
42V、3.5A 降压稳压器。按照 ISO 7637 标准，此器件
能够耐受的抛负载脉冲高达 45V。电流模式控制提供
了简单的外部补偿和灵活的组件选择。低纹波脉冲跳跃
模式可将无负载电源电流降至 146μA。当启用引脚被
拉至低电平时，关断电源电流被减少至 1μA。
92mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
146μA 静态运行电流和 2μA 关断电流
100kHz 至 2.5MHz 可调开关频率
同步至外部时钟
可在轻负载条件下使用集成型引导 (BOOT) 再充电
场效应晶体管 (FET) 实现低压降
欠压闭锁在内部设定为 4.3V，但可用一个使能引脚上
的外部电阻分压器将之提高。该器件可在内部控制输出
电压启动斜坡，从而控制启动过程并消除过冲。
•
•
•
•
•
可调欠压闭锁 (UVLO) 电压和迟滞
0.8V 1% 内部电压基准
8 引脚 HSOP 封装，带有 PowerPAD™封装
宽开关频率范围可实现对效率或者外部组件尺寸进行的
优化。频率折返和热关断在过载条件下保护内部和外部
组件。
-40°C 至 150°C TJ 运行范围
使用 TPS54340B-Q1 并借助 WEBENCH® 电源设
计器创建定制设计方案
TPS54340B-Q1 器件可提供 8 引脚耐热增强型 HSOP
PowerPAD 封装。
器件信息(1)
器件型号
封装
HSOP (8)
封装尺寸（标称值）
TPS54340B-Q1
4.89mm × 3.90mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
简化电路原理图
效率与负载电流间的关系
100
90
V
VIN
TPS54340B-Q1
EN
IN
80
V
= 5V
OUT
70
60
50
40
30
20
10
0
BOOT
V
V
= 3.3V
OUT
OUT
SW
RT/CLK
COMP
R1
FB
R3
V
= 12V
IN
GND
fsw = 600 kHz
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Copyright © 2016, Texas Instruments Incorporated
I
- Output Current - A
O
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDX5
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Applications ................................................ 23
Power Supply Recommendations...................... 35
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 RT/CLK Timing Requirements .................................. 5
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 36
10.3 Estimated Circuit Area .......................................... 36
11 器件和文档支持 ..................................................... 37
11.1 器件支持................................................................ 37
11.2 文档支持................................................................ 37
11.3 社区资源................................................................ 37
11.4 商标....................................................................... 37
11.5 静电放电警告......................................................... 37
11.6 Glossary................................................................ 38
12 机械、封装和可订购信息....................................... 38
7
4 修订历史记录
日期
修订版本
注释
2017 年2 月
*
最初发布。
2
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP
Top View
BOOT
VIN
1
2
3
4
8
7
6
5
SW
GND
COMP
FB
PowerPAD
9
EN
RT/CLK
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the output switches off until the capacitor is refreshed.
BOOT
1
O
O
I
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
COMP
EN
6
3
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
FB
5
7
I
Inverting input of the transconductance (gm) error amplifier.
Ground
GND
—
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
reenabled and the operating mode returns to resistor frequency programming.
RT/CLK
4
I
SW
8
9
2
I
—
I
The source of the internal high-side power MOSFET and switching node of the converter.
GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation.
Input supply voltage with 4.5-V to 42-V operating range.
Thermal Pad
VIN
Copyright © 2017, Texas Instruments Incorporated
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TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
45
8.4
53
3
UNIT
VIN
EN
BOOT
Input voltage
FB
V
–0.3
–0.3
–0.3
COMP
3
RT/CLK
BOOT-SW
3.6
8
Output voltage
SW
–0.6
–2
45
45
150
150
V
SW, 10-ns Transient
Operating junction temperature
Storage temperature
–40
–65
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VO + Vdo
0.8
NOM
MAX
42
UNIT
V
(1)
VIN
VO
IO
Supply input voltage
Output voltage
58.8
3.5
V
Output current
0
A
TJ
Junction Temperature
–40
150
°C
(1) See Equation 1 in the Feature Description section.
6.4 Thermal Information
TPS54340B-Q1
THERMAL METRIC(1)(2)
DDA (HSOP)
8 PINS
42
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
45.8
23.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
5.9
ψJB
23.4
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
4
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
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ZHCSG11 –FEBRUARY 2017
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
4.1
42
V
V
Internal undervoltage lockout
threshold
Rising
4.3
4.48
Internal undervoltage lockout
threshold hysteresis
325
2.25
146
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
4.5
μA
Operating: nonswitching
supply current
FB = 0.9 V, TA = 25°C
175
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold 50 mV
1.1
1.2
–4.6
–1.2
–3.4
346
1.3
V
Input current
μA
Enable threshold –50 mV
–0.58
–2.2
-1.8
-4.5
Hysteresis current
Enable to COMP active
INTERNAL SOFT-START TIME
Soft-Start Time
μA
VIN = 12 V , TA = 25°C
µs
fSW = 500 kHz, 10% to 90%
fSW = 2.5 MHz, 10% to 90%
2.1
ms
ms
Soft-Start Time
0.42
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
92
0.808
190
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier
transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
350
μS
Error amplifier
transconductance (gM) during –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
77
μS
soft-start
Error amplifier DC gain
Min unity gain bandwidth
VFB = 0.8 V
10,000
2500
V/V
kHz
Error amplifier source and
sink
V(COMP) = 1 V, 100-mV overdrive
±30
12
μA
COMP to SW current
transconductance
A/V
CURRENT LIMIT
All VIN and temperatures, Open Loop(1)
All temperatures, VIN = 12 V, Open Loop(1)
VIN = 12 V, TA = 25°C, Open Loop(1)
4.5
4.5
5.2
5.5
5.5
5.5
60
6.8
6.25
5.85
Current limit threshold
A
Current limit threshold delay
ns
THERMAL SHUTDOWN
Thermal shutdown
176
12
°C
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
1.55
1.2
2
V
V
RT/CLK low threshold
0.5
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
6.6 RT/CLK Timing Requirements
MIN
NOM
MAX
UNIT
Minimum CLK input pulse width
15
ns
Copyright © 2017, Texas Instruments Incorporated
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TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT
mode
100
450
160
2500
550
kHz
kHz
kHz
ƒSW
Switching frequency
RT = 200 kΩ
500
Switching frequency range using
CLK mode
2300
RT/CLK falling edge to SW rising
edge delay
Measured at 500 kHz with RT
resistor in series
55
78
ns
PLL lock in time
Measured at 500 kHz
μs
6
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
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ZHCSG11 –FEBRUARY 2017
6.8 Typical Characteristics
0.25
0.814
0.809
0.804
0.799
0.794
0.789
0.784
VIN = 12 V
BOOT-SW = 3 V
BOOT-SW = 6 V
0.2
0.15
0.1
0.05
0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G001
G002
Figure 1. ON Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
6.5
VIN = 12 V
TJ = −40°C
TJ = 25°C
TJ = 150°C
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
−50
−25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
TJ − Junction Temperature (°C)
VIN − Input Voltage (V)
G003
G004
Figure 3. Switch Current Limit vs Junction Temperature
Figure 4. High-side Switch Current Limit vs Input Voltage
550
500
ƒSW (kHz) = 92417 × RT (kΩ)−0.991
RT = 200 kΩ, VIN = 12 V
540
450
RT (kΩ) = 101756 × fSW (kHz)−1.008
530
520
510
500
490
480
470
460
450
400
350
300
250
200
150
100
50
0
200
−50
−25
0
25
50
75
100
125
150
300
400
500
600
700
800
900 1000
TJ − Junction Temperature (°C)
RT/CLK − Resistance (kΩ)
G005
G006
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance
Low-Frequency Range
Copyright © 2017, Texas Instruments Incorporated
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Typical Characteristics (continued)
2500
500
450
400
350
300
250
200
VIN = 12 V
2000
1500
1000
500
0
0
50
100
150
200
−50
−25
0
25
50
75
100
125
150
RT/CLK − Resistance (kΩ)
TJ − Junction Temperature (°C)
G007
G008
Figure 7. Switching Frequency vs RT/CLK Resistance
High-Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
120
1.3
VIN = 12 V
VIN = 12 V
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
110
100
90
80
70
60
50
40
30
20
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G009
G010
Figure 9. EA Transconductance During Soft Start vs
Junction Temperature
Figure 10. EN Pin Voltage vs Junction Temperature
−0.5
−4
VIN = 5 V,IEN = Threshold+50mV
VIN = 12 V,IEN = Threshold+50mV
−0.7
−0.9
−1.1
−1.3
−1.5
−1.7
−1.9
−2.1
−2.3
−2.5
−4.1
−4.2
−4.3
−4.4
−4.5
−4.6
−4.7
−4.8
−4.9
−5
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
Tj − Junction Temperature (°C)
100
125
150
TJ − Junction Temperature (°C)
G011
G012
Figure 11. EN Pin Current vs Junction Temperature
Figure 12. EN Pin Current vs Junction Temperature
8
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG11 –FEBRUARY 2017
Typical Characteristics (continued)
−2.5
−2.7
−2.9
−3.1
−3.3
−3.5
−3.7
−3.9
−4.1
−4.3
−4.5
100
75
50
25
0
VFB Falling
VFB Rising
VIN = 12 V
125 150
−50
−25
0
25
50
75
100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TJ − Junction Temperature (°C)
VFB (V)
G112
G013
Figure 13. EN Pin Current Hysteresis vs
Junction Temperature
Figure 14. Switching Frequency vs FB
3
3
VIN = 12 V
TJ = 25°C
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
−50
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
TJ − Junction Temperature (°C)
G014
VIN − Input Voltage (V)
G016
Figure 15. Shutdown Supply Current vs
Junction Temperature
Figure 16. Shutdown Supply Current vs Input Voltage (VIN
)
210
190
170
150
130
110
90
210
190
170
150
130
110
90
VIN = 12 V
70
−50
70
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
TJ − Junction Temperature (°C)
G016
VIN − Input Voltage (V)
G018
Figure 17. VIN Supply Current vs Junction Temperature
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
2.6
4.5
4.4
4.3
4.2
4.1
4
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
2.5
2.4
2.3
2.2
2.1
2
3.9
3.8
3.7
UVLO Start Switching
UVLO Stop Switching
1.9
1.8
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75 100 125 150
Tj − Junction Temperature (°C)
TJ − Junction Temperature (°C)
G018
G019
Figure 19. BOOT-SW UVLO vs Junction Temperature
Figure 20. Input Voltage UVLO vs Junction Temperature
10
V
T
= 12V,
IN
= 25oC
9
8
7
6
5
J
4
3
2
1
0
100 300 500 700 900 110013001500 17001900 2100 2300 2500
Switching Frequency (KHz)
G021
Figure 21. Soft-Start Time vs Switching Frequency
10
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ZHCSG11 –FEBRUARY 2017
7 Detailed Description
7.1 Overview
The TPS54340B-Q1 device is a 42-V, 3.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. The device implements constant-frequency current-mode control, which reduces output capacitance
and simplifies external frequency compensation. The wide switching-frequency range of 100 kHz to 2500 kHz
allows for either efficiency or size optimization when selecting the output filter components. The switching
frequency is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-
locked loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turnon to a falling edge of an
external clock signal.
The TPS54340B-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin adjusts the
input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 146 μA under no load condition (not
switching). When the device is disabled, the supply current is 1 μA.
The integrated 92-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54340B-Q1 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340B-Q1 device to operate at
high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply
voltage of the application. The minimum output voltage is the internal 0.8-V feedback reference.
Output-overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than
106% of the desired output voltage.
The TPS54340B-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to
reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When
the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the
nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency during start-up and
overcurrent fault conditions to help maintain control of the inductor current.
Copyright © 2017, Texas Instruments Incorporated
11
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
7.2 Functional Block Diagram
EN
VIN
Shutdown
Thermal
Shutdown
UVLO
Enable
OV
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Current
Sense
Skip
Error
Amplifier
PWM
FB
Comparator
BOOT
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft-Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012A 0192789
/opyright © 2017, Çexas Lnstruments Lncorporated
RT/CLK
GND
POWERPAD
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54340B-Q1 device uses fixed-frequency peak-current-mode control with adjustable switching frequency.
The output voltage is compared through external resistors connected to the FB pin to an internal voltage
reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error
amplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET
switch current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin
voltage increases and decreases as the output current increases and decreases. The device implements current
limiting by clamping the COMP-pin voltage to a maximum level. The pulse skipping Eco-mode is implemented
with a minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54340B-Q1 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
12
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TPS54340B-Q1
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ZHCSG11 –FEBRUARY 2017
Feature Description (continued)
7.3.3 Pulse Skip Eco-mode™
The TPS54340B-Q1 device operates in a pulse skipping Eco-mode at light-load currents to improve efficiency by
reducing switching and gate-drive losses. If the output voltage is within regulation and the peak-switch current at
the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at
light-load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54340B-Q1 device senses and controls peak switch current, not the
average load current. Therefore the load current at which the device enters Eco-mode is dependent on the
output inductor value. The circuit in Figure 33 enters Eco-mode at about 31.4-mA output current. As the load
current approaches zero, the device enters a pulse-skip mode during which it draws only 146-μA input quiescent
current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54340B-Q1 device provides an integrated-bootstrap voltage regulator. A small capacitor between the
BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor refreshes
when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the
BOOT capacitor is 0.1 μF. For stable performance over temperature and voltage, TI recommends a ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.
When operating with a low-voltage difference from input to output, the high-side MOSFET of the TPS54340B-Q1
device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops to less than 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high-output voltages, it is disabled at 24-V output and reenabled when the output reaches 21.5 V.
Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty
cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during
dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-
side diode voltage, and the printed-circuit-board resistance.
calculates the minimum input voltage required to regulate the output voltage and ensure proper operation of the
device. This calculation must include tolerance of the component specifications and the variation of these
specifications at their maximum operating temperature in the application.
VOUT + VF + Rdc ´IOUT
V min =
IN ( )
+ RDS on ´I
( )
- VF
OUT
D
where
•
•
•
•
VF = Schottky diode forward voltage
RDC = DC resistance of inductor plus PCB
RDS(on) = High-side MOSFET resistance
D = Effective duty cycle of 99%.
(1)
During high-duty-cycle (low-dropout) conditions, the inductor-current ripple increases when the BOOT capacitor
recharges which results in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to ensure a monotonic start-up. Equation 2
calculates the minimum input voltage for this condition.
Copyright © 2017, Texas Instruments Incorporated
13
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
VOmax = Dmax × (VVINmin – IOmax × RDS(on) + VF) – VF – IOmax × Rdc
where
•
•
•
•
•
Dmax ≥ 0.9
RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)
VB2SW = VBOOT + VF
VBOOT = (1.41 × VVIN – 0.554 – VF × ƒsw × 10–6 – 1.847 × 103 × IB2SW) / (1.41 + ƒsw × 10-6)
IB2SW = 100 × 10–6
A
(2)
7.3.5 Error Amplifier
The TPS54340B-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error
amplifier compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage
reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-
start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. TI recommends using divider resistors with a 1% tolerance or better.
Select the low-side resistor RLS for the desired divider current, and use Equation 3 to calculate RHS. To improve
efficiency at light loads, consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors from the FB input current may become noticeable.
Vout - 0.8V
æ
ö
RHS = RLS
´
ç
÷
0.8 V
è
ø
(3)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54340B-Q1 device is enabled when the VIN-pin voltage rises above 4.3 V and the EN-pin voltage
exceeds the enable threshold of 1.2 V. The TPS54340B-Q1 device is disabled when the VIN pin voltage falls to
less than 4 V, or when the EN pin voltage is less than 1.2 V. The EN pin has an internal pullup current source,
I1, of 1.2 μA that enables operation of the TPS54340B-Q1 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled to less than 1.2 V, the
3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (for example 4.5 V) and withstand high input
voltages (for example 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of
8.4 V during the high-input voltage condition. TI recommends using a Zener diode to clamp the pin voltage below
the absolute maximum rating.
14
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TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
Feature Description (continued)
VIN
TPS54340B-Q1
i1 ihys
VIN
R
R
UVLO1
UVLO1
10 kW
EN
EN
Node
5.8 V
Optional
VEN
R
R
UVLO2
UVLO2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Adjustable Undervoltage Lockout
(UVLO)
Figure 23. Internal EN Clamp
V
- V
STOP
START
R
=
UVLO1
I
HYS
(4)
(5)
V
ENA
R
=
UVLO2
V
- V
ENA
START
+ I
1
R
UVLO1
7.3.8 Internal Soft-Start
The TPS54340-Q1 device has an internal digital soft-start that ramps the reference voltage from 0 V to the final
value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6
1024
t
(ms) =
SS
f
(kHz)
SW
(6)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft start resets. The
soft start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54340B-Q1 device is adjustable over a wide range from 100 kHz to 2500 kHz
by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 7 or Equation 8 or the curves in Figure 5 and Figure 6. To reduce the solution size one
typically sets the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum
input voltage, and minimum controllable on time must be considered. The minimum-controllable on time is
typically 135 ns which limits the maximum operating frequency in applications with high input-to-output step-down
ratios. The maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed
discussion of the maximum switching frequency is provided in Accurate Current Limit Operation and Maximum
Switchign Frequency.
101756
f sw (kHz)1.008
RT (kW) =
(7)
92417
RT (kW)0.991
f sw (kHz) =
(8)
Copyright © 2017, Texas Instruments Incorporated
15
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switchign Frequency
The TPS54340B-Q1 device implements peak-current-mode control in which the COMP-pin voltage controls the
peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-
side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets
the peak switch-current limit. The TPS54340B-Q1 device provides an accurate current limit threshold with a
typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor
current. The relationship between the inductor value and the peak inductor current is shown in Figure 24.
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = V /L x tCLdelay
IN
tCLdelay
tON
Figure 24. current limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54340B-Q1 device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as
the FB pin voltage falls from 0.8 V to 0 V. The TPS54340B-Q1 device uses a digital-frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short circuit events, the
inductor current exceeds the peak current limit because of the high input voltage and the minimum-controllable
on time. When the shorted load forces the output voltage low, the inductor current decreases slowly during the
switch-off time. The frequency foldback effectively increases the off time by increasing the period of the switching
cycle providing more time for the inductor current to ramp down.
With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is
controlled by frequency-foldback protection. Equation 10 calculates the maximum switching frequency at which
the inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating frequency
must not exceed the calculated value.
Equation 9 calculates the maximum switching-frequency limitation set by the minimum-controllable on time and
the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required at maximum input voltage.
æ
ç
ö
÷
IO ´Rdc + VOUT + Vd
1
fSW maxskip
=
´
(
)
ç
÷
tON
VIN -IO ´RDS on + Vd
( )
è
ø
(9)
16
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
Feature Description (continued)
æ
ç
ö
÷
ICL ´Rdc + VOUT sc + Vd
fDIV
( )
fSW(shift)
=
´
ç
÷
tON
VIN -ICL ´RDS on + Vd
( )
è
ø
where
•
•
•
•
•
•
•
•
•
•
IO is the output current
ICL is the current limit
Rdc is the inductor resistance
VIN is the maximum input voltage
VOUT is the output voltage
VOUT(SC) is the output voltage during short
Vd is the diode voltage drop
RDS(on) is the switch ON-resistance
tON is the controllable ON-time
fDIV is the frequency divide equals (1, 2, 4, or 8)
(10)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin receives a frequency-synchronization signal from an external system clock. To implement this
synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 25. The square wave applied to the RT/CLK pin must switch lower than 0.5 V but higher than 1.7 V, and it
must have a pulse-width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The
rising edge of the SW synchronizes to the falling edge of RT/CLK pin signal. The external synchronization circuit
must be designed so that the default-frequency set-resistor is connected from the RT/CLK pin to ground when
the synchronization signal is off. When using a low-impedance signal source, the frequency set resistor is
connected in parallel with an AC-coupling capacitor to a termination resistor (for example 50 Ω) as shown in
Figure 25. The two resistors in series provide the default-frequency setting resistance when the signal source is
turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. TI
recommends to AC-couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin.
The first time that the RT/CLK is pulled above the PLL threshold, the TPS54340B-Q1 device switches from the
RT-resistor free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is
removed and the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The
switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device
transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs.
During the transition from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150
kHz and then increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is
reapplied to the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital-frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system clock in
continuous-conduction mode (CCM), discontinuous-conduction mode (DCM), and pulse-skip mode (Eco-Mode).
SPACER
TPS54340B-Q1
PLL
TPS54340B-Q1
PLL
RT/CLK
RT
RT/CLK
RT
Hi-Z
Clock
Source
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Synchronizing to a System Clock
Copyright © 2017, Texas Instruments Incorporated
17
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
SW
SW
EXT
EXT
IL
IL
Figure 26. Plot of Synchronizing in CCM
Figure 27. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 28. Plot of Synchronizing in Eco-Mode™
7.3.12 Overvoltage Protection
The TPS54340B-Q1 device incorporates an output-overvoltage-protection (OVP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients in designs with low-output
capacitance. For example, when the power-supply output is overloaded, the error amplifier compares the actual
output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage
for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the
peak current limit threshold. When the overload condition is removed, the regulator output rises and the error
amplifier output transitions to the normal operating level. In some applications, the power-supply output voltage
increases faster than the response of the error amplifier output resulting in an output overshoot.
18
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
Feature Description (continued)
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB-pin
voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB-pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54340B-Q1 device provides an internal thermal shutdown to protect the device when the junction
temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the
thermal trip threshold. Once the die temperature falls to less than 164°C, the device reinitiates the power-up
sequence controlled by the internal soft-start circuitry.
7.3.14 Small-Signal Model for Loop Response
Figure 29 shows an equivalent model for the TPS54340B-Q1 control loop, which is simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 3350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor Ro
and capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small-signal response of the frequency compensation. Plotting a/b provides the small-
signal response of the overall loop. The dynamic loop response is evaluated by replacing RL with a current
source with the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
V
O
Power Stage
gm 12 A/V
ps
a
b
R
R1
ESR
R
COMP
L
c
FB
C
OUT
0.8 V
CO
RO
R3
C1
gm
ea
C2
R2
350 mA/V
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Small-Signal Model for Loop Response
7.3.15 Simple Small-Signal Model for Peak-Current-Mode Control
Figure 30 describes a simple small-signal model that is used to design the frequency compensation. The
TPS54340B-Q1 power stage is approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control-to-output transfer function is shown in
Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP-pin voltage (node c in Figure 29) is the power-stage transconductance,
gmPS. The gmPS for the TPS54340B-Q1 device is 12 A/V. The low-frequency gain of the power stage is the
product of the transconductance and the load resistance as shown in Equation 12.
Copyright © 2017, Texas Instruments Incorporated
19
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load is problematic at first glance, but fortunately the dominant pole moves with the load current
(see Equation 13). The combined effect is highlighted by the dashed line in the right half of Figure 30. As the
load current decreases, the gain increases and the pole frequency lowers, which keeps the 0-dB crossover
frequency the same as load conditions vary. The type of output capacitor chosen determines whether the ESR
zero has a profound effect on the frequency compensation design. Because the phase margin is increased by
the ESR zero of the output capacitor (see Equation 14), the use of high-ESR aluminum-electrolytic capacitors
reduces the number frequency compensation components required to stabilize the overall loop.
V
O
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
Figure 30. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
ç
è
ö
÷
ø
s
1+
1+
2p´ fZ
VOUT
= Adc ´
VC
æ
ç
è
ö
÷
ø
s
2p´ fP
(11)
(12)
Adc = gmps ´ RL
1
f
=
P
C
´R ´ 2p
L
OUT
(13)
(14)
1
f
=
Z
C
´R
´ 2p
OUT
ESR
7.3.16 Small-Signal Model for Frequency Compensation
The TPS54340B-Q1 device uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency-compensation circuits. The compensation circuits, Type 2A, Type 2B, and Type 1, are
shown in Figure 31. Type 2 circuits are typically implemented in high-bandwidth power-supply designs using low
-ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum-
electrolytic or tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to
the small-signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown
in Figure 31. See Application and Implementation for a design example using a Type-2A network with a low-ESR
output capacitor.
Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
20
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TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
Feature Description (continued)
V
O
R1
FB
Type 2A
Type 2B
Type 1
gm
ea
R
COMP
Vref
C2
R3
C1
R3
R2
C2
C
O
O
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 32. Frequency Response of the Type-2A and Type-2B Frequency Compensation
Aol(V/V)
Ro =
gmea
gmea
(15)
(16)
CO
=
2p ´ BW (Hz)
æ
ç
è
ö
÷
ø
s
1+
2p´ fZ1
EA = A0´
æ
ç
è
ö æ
ö
÷
ø
s
s
1+
´ 1+
÷ ç
2p´ fP1
2p´ fP2
ø è
(17)
(18)
(19)
R2
A0 = gmea ´ Ro ´
R1 + R2
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
1
P1=
2p´Ro´ C1
(20)
21
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Feature Description (continued)
1
Z1=
2p´R3´ C1
(21)
(22)
1
P2 =
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
(23)
(24)
1
P2 =
type 1
2p ´ RO ´ (C2 + CO
)
7.4 Device Functional Modes
The TPS54340B-Q1 device is designed to operate with input voltages above 4.5 V. When the VIN voltage is
above the 4.3 V, typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device
is active. If the VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the
EN voltage falls below the 1.2-V threshold, the device stops switching and enters a shutdown mode with low
supply current of 2 µA typical.
The TPS54340B-Q1 device will operate in CCM when the output current is enough to keep the inductor current
above 0 A at the end of each switching period. As a nonsynchronous converter, it will enter DCM at low-output
currents when the inductor current falls to 0 A before the end of a switching period. At very low-output current,
the COMP voltage will drop to the pulse-skipping threshold, and the device operates in a pulse-skipping Eco-
mode. In this mode, the high-side MOSFET does not switch every switching period. This operating mode
reduces power loss while regulating the output voltage. For more information on Eco-mode see the Pulse Skip
Eco-mode™ section.
22
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TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54340B-Q1 device is a 42-V, 3.5-A, step-down regulator with an integrated high-side MOSFET. This
device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output
current of 3.5 A. Example applications are: 12 V and 24 V industrial, automotive, and communications power
systems. Use the following design procedure to select component values for the TPS54340B-Q1 device. This
procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
Calculations can be done with the excel spreadsheet (SLVC452) located on the product page.
8.2 Typical Applications
8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 3.5-A Output
L1
5.6 μH
VOUT
0.1 μF
C4
3.3 V, 3.5 A
C6
U1
TPS54340B-Q1 (DDA)
D1
100 μF
B560C
1
2
3
4
8
R5
31.6 kΩ
BOOT
VIN
SW
GND
COMP
FB
6 V to 42 V
C1
7
6
5
VIN
EN
C2
2.2μF
GND
FB
R1
FB
RT/CLK
365 kΩ
2.2 μF
R4
11.5 kΩ
9
C8
R6
10.2 kΩ
R2 R3
86.6 kΩ 162 kΩ
47 pF
GND
C5
GND
5600 pF
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 33. 3.3-V Output TPS54340B-Q1 Design Example
8.2.1.1 Design Requirements
To start the design process, a few parameters must be known. These requirements are typically determined at
the system level. Table 1 shows the design parameters for this example.
Copyright © 2017, Texas Instruments Incorporated
23
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
Typical Applications (continued)
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
3.3 V
Output voltage
Transient response 0.875-A to 2.625 A-load step
Maximum output current
ΔVOUT = 4 %
3.5 A
Input voltage
12 V nominal, 6 V to 42 V
0.5% of VOUT
5.75 V
Output voltage ripple
Start Input voltage (rising VIN)
Stop Input Voltage (falling VIN)
4.5 V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54340B-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible, because this produces the smallest solution size. High switching frequency allows
for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage, and the frequency-foldback protection.
Equation 9 and Equation 10 calculate the upper limit of the switching frequency for the regulator. Choose the
lower value result from the two equations. Switching frequencies higher than these values results in pulse
skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340B-Q1. For this example, the output voltage is 3.3
V and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 9. To ensure overcurrent runaway is not a concern during short circuits use
Equation 10 to determine the maximum switching frequency for frequency-foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92
mΩ, a current limit value of 4.7 A, and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 33. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
3.5 A x 21 mW + 3.3 V + 0.7 V
42 V - 3.5 A x 92 mW + 0.7 V
æ
ö
fSW(maxskip)
=
´
= 712 kHz
ç
÷
135ns
è
ø
(25)
24
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
8
4.7 A x 21 mW + 0.1 V + 0.7 V
42 V - 4.7 A x 92 mW + 0.7 V
æ
ö
fSW(shift)
=
´
= 1260 kHz
ç
÷
135 ns
è
ø
(26)
(27)
101756
600 (kHz)1.008
RT (kW) =
= 161 kW
8.2.1.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple-current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer, however, the following guidelines can be used.
For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 is desirable. When
using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of
the current-mode PWM-control system, the inductor ripple current must always be greater than 150 mA for stable
PWM operation. In a wide input voltage regulator, the best choice is a relatively large inductor ripple current
which provides sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. Not exceeding the RMS current and saturation current ratings of the inductor is
important. The RMS and peak inductor current are determined by Equation 30 and Equation 31. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the
regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current increases up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54340B-Q1, which is nominally 5.5 A.
V
- VOUT
IN max
(
VOUT
)
42 V - 3.3 V
3.5 A x 0.3
3.3 V
LO min
=
´
=
´
= 4.8 mH
(
)
IOUT ´KIND
V
´ fSW
42 V ´ 600 kHz
IN max
(
)
(28)
(29)
spacer
IRIPPLE
V
OUT ´(V
- VOUT )
IN max
(
)
3.3 V x (42 V - 3.3 V)
=
=
= 0.905 A
V
´LO ´ fSW
42 V x 5.6 mH x 600 kHz
IN max
(
)
spacer
2
æ
ö
2
V
´ V
- V
OUT
(
OUT
)
æ
ç
ç
è
ö
÷
÷
ø
IN max
(
3.3 V ´ 42 V - 3.3 V
)
(
)
1
ç
ç
÷
1
2
2
I
=
I
(
+
´
=
3.5 A
(
+
´
= 3.5 A
)
)
OUT
÷
L rms
(
)
12
V
´L ´ f
12
42 V ´ 5.6 mH ´ 600 kHz
O
SW
IN max
(
)
ç
÷
è
ø
(30)
spacer
IL peak = IOUT
IRIPPLE
0.905 A
2
+
= 3.5 A +
= 3.95 A
(
)
2
(31)
Copyright © 2017, Texas Instruments Incorporated
25
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
8.2.1.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor must supply
the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator generally requires two or more clock cycles for the control loop to sense the change in output voltage
and adjust the peak switch current in response to the higher load. The output capacitance must be large enough
to supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 32 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒSW
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A – 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum-
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high-
to-low load current. The catch diode of the regulator does not sink current so energy stored in the inductor
produces an output-voltage overshoot when the load current rapidly decreases. A typical load-step response is
shown in Figure 34. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and VI is the initial voltage. For this example, the worst-case load step is from 2.625 A to
0.875 A. The output voltage increases during this load transition, and the stated maximum in our specification is
4% of the output voltage, which makes Vf = 1.04 × 3.3 = 3.432. VI is the initial capacitor voltage, which is the
nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 38.6 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒSW is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 34 yields 11.4 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR must be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance deratings for aging, temperature, and DC bias increases this minimum value. For this example, 100-
μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, which is well above the
minimum required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 36 calculates the RMS ripple current that the output capacitor must support. For this example,
Equation 36 yields 261 mA.
2´ DI
2 ´ 1.75 A
OUT
C
>
=
= 44.9 mF
OUT
f
´ DV
600 kHz x 0.13 V
SW
OUT
(32)
2
(OH ) (OL )
2
2.625 A2 - 0.875 A2
I
-
I
(
)
(
)
= 38.6 mF
COUT > LO
x
= 5.6 mH x
2
2
3.432 V2 - 3.3 V2
V
-
V
I
( ) ( )
(
)
f
(
)
(33)
1
1
1
1
C
>
´
=
x
= 11.4 mF
OUT
8´ f
8 x 600 kHz
16.5 mV
0.905 A
æ
ç
è
ö
÷
ø
æ
ö
V
SW
ORIPPLE
ç
è
÷
ø
I
RIPPLE
(34)
26
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
V
16.5 mV
0.905 A
ORIPPLE
R
<
=
= 18 mW
ESR
I
RIPPLE
(35)
(36)
V
´ V
(
IN max
(
- V
OUT
OUT
)
=
IN max
(
3.3 V ´ 42 V - 3.3 V
)
(
)
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
I
=
= 261 mA
COUT(rms)
12 ´ V
´L ´ f
O
SW
)
8.2.1.2.5 Catch Diode
The TPS54340B-Q1 device requires an external catch diode between the SW pin and GND. The selected diode
must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340B-Q1
device.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 V at
5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is
used to calculate the total power dissipation, including conduction losses and AC losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode is
2.42 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
)
V
(
- V
´ I
´ Vf d
OUT
)
IN max
OUT
C
´ f
´
V
IN
+ Vf d
IN max
(
(
)
j
SW
P =
+
=
D
V
2
(
)
2
42 V - 3.3 V ´ 3.5 A x 0.7 V
(
)
42 V
300 pF x 600 kHz x (42 V + 0.7 V)
+
= 2.42 W
2
(37)
8.2.1.2.6 Input Capacitor
The TPS54340B-Q1 device requires a high-quality ceramic-type X5R or X7R input-decoupling capacitor with at
least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to DC-bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater
than the maximum input current ripple of the TPS54340B-Q1 device. Equation 38 calculates the input ripple
current.
The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor.
Selecting a dielectric material that is more stable overtemperature minimizes capacitance variations due to
temperature. X5R and X7R ceramic dielectrics are generally selected for switching regulator capacitors, because
they have a high capacitance-to-volume ratio and are fairly stable over temperature. The input capacitor must
also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias
across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support the
maximum input voltage. Common-standard ceramic-capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V, or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
Copyright © 2017, Texas Instruments Incorporated
27
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
The input capacitance value determines the input ripple voltage of the regulator. Equation 39 calculates the input
voltage ripple. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒSW = 600 kHz, yields an input
voltage ripple of 331 mV and a RMS input ripple current of 1.74 A.
V
- V
OUT
)
= 3.5 A
(
IN min
(
6 V - 3.3 V
)
V
(
)
3.3 V
6 V
OUT
I
= I
x
x
´
= 1.74 A
OUT
CI rms
(
)
V
V
6 V
IN min
(
IN min
(
)
)
(38)
(39)
I
´ 0.25
3.5 A ´ 0.25
OUT
DV
=
=
= 331 mV
IN
C
´ f
4.4 mF ´ 600 kHz
IN
SW
Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
1 to 4.7
1
EIA SIZE
VOLTAGE (V)
DIALECTRIC
COMMENTS
100
50
1210
GRM32 series
Murata
100
50
1206
2220
2225
1812
1210
1210
1812
GRM31 series
VJ X7R series
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
50
100
50
Vishay
TDK
100
100
50
X7R
C series C4532
C series C3225
100
50
50
100
50
AVX
X7R dielectric series
1 to 4.7
1 to 2.2
100
8.2.1.2.7 Bootstrap-Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. TI
recommends a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher
voltage rating.
8.2.1.2.8 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) is adjusted using an external voltage divider on the EN pin of the
TPS54340B-Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising, and
one for power-down or brown-outs when the input voltage is falling. For the example design, the supply turns on
and starts switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts
switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO-threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 4 and Equation 5 calculate the necessary resistance values. For the
example application, a 365 kΩ between VIN and EN (RUVLO1) and a 86.6 kΩ between EN and ground (RUVLO2
)
are required to produce the 8-V and 6.25-V start and stop voltages.
V
- V
STOP
5.75 V - 4.5 V
START
R
=
=
= 368 kW
UVLO1
I
3.4 mA
HYS
(40)
V
1.2 V
5.75 V - 1.2 V
ENA
R
=
=
= 87.8 kW
UVLO2
V
- V
ENA
START
+1.2 mA
+ I
1
365 kW
R
UVLO1
(41)
28
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
8.2.1.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 3, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Because of the
input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but
can also introduce noise immunity problems.
VOUT - 0.8 V
3.3 V - 0.8 V
æ
ö
RHS = RLS
x
= 10.2 kW x
= 31.9 kW
ç
÷
0.8 V
0.8 V
è
ø
(42)
8.2.1.2.10 Minimum VIN
To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the
device must be above the value calculated with Equation 43 . Using the typical values for the RDS(on), RDC, and
VF in this application example, the minimum input voltage is 3.83 V. The BOOT-SW = 3 V curve in Figure 1 was
used for RDS(on) = 0.12 Ω because the device will be operating with low drop out. When operating with low
dropout, the BOOT-SW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed
every switching cycle. In the final application, the values of RDS(on), RDC, and VF used in this equation must
include tolerance of the component specifications and the variation of these specifications at their maximum
operating temperature in the application.
In this application example the calculated minimum input voltage is near the input voltage UVLO for the
TPS54340B-Q1 so the device may turn off before going into drop out.
VOUT + VF + Rdc ´IOUT
V
min =
+ RDS on ´I
- VF
(
)
( )
IN
OUT
0.99
3.3V + 0.5V + 0.0206W´3.5A
V
min =
( )
+ 0.12W´3.5A - 0.5V = 3.83V
IN
0.99
(43)
8.2.1.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10-times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1, must be calculated using Equation 44 and
Equation 45. For COUT, use a derated value of 70 μF. Use equations Equation 46 and Equation 47 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of
modulator pole and the switching frequency. Equation 46 yields 33.1 kHz and Equation 47 gives 26.9 kHz. Use
the lower value of Equation 46 or Equation 47 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT max
(
)
3.5 A
fP mod
=
=
2´ p´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
= 2411 Hz
(
)
(44)
1
1
f
=
=
= 455 kHz
Z mod
(
)
2´ p´R
´ C
2 ´ p ´ 5 mW ´ 70 mF
ESR
OUT
(45)
(46)
f
=
f
f
=
2411 Hz x 455 kHz = 33.1 kHz
co
p(mod) x z(mod)
f
600 kHz
SW
f
=
f
=
2411 Hz x
= 26.9 kHz
co
p(mod) x
2
2
(47)
Copyright © 2017, Texas Instruments Incorporated
29
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
To determine the compensation resistor, R4, use Equation 48. Assume the power-stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V, and 350 μA/V, respectively. R4 is calculated as 11.6 kΩ, and a standard value of 11.5 kΩ is selected.
Use Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
æ
ç
è
ö
÷
ø
æ 2´ p´ f ´ C
ö
÷
ø
V
OUT
æ
ç
è
ö
÷
ø
2´ p´ 26.9 kHz ´ 70 mF
12 A / V
3.3 V
æ
ö
co
OUT
R4 =
x
=
x
= 11.6 kW
ç
ç
÷
gmps
V
x gmea
0.8 V x 350 mA / V
è
ø
è
REF
(48)
1
1
C5 =
=
= 5740 pF
2´ p´R4 x f
2´ p´11.5 kW x 2411 Hz
p(mod)
(49)
A compensation pole is implemented if desired by adding capacitor C8 in parallel with the series combination of
R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the compensation
pole. The selected value of C8 is 47 pF for this design example.
C
x R
ESR
70 mF x 5 mW
OUT
C8 =
=
= 30.4 pF
R4
11.5 kW
(50)
(51)
1
1
C8 =
=
= 46.1 pF
R4 x f sw x p
11.5 kW x 600 kHz x p
8.2.1.2.12 Power Dissipation Estimate
The following formulas estimate the power dissipation of the TPS54340B-Q1 device under continuous-conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous-
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). For example calculations of the design example with the 12-V typical input voltage, see
Equation 52 through Equation 55.
æ
ç
è
ö
÷
ø
V
3.3 V
12 V
2
2
OUT
P
= I
´R
´
= 3.5 A ´ 92 mW ´
= 0.31 W
(
)
COND
OUT
DS on
( )
V
IN
(52)
(53)
(54)
spacer
P
= V ´ f
´I
´ t
= 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
rise
SW
IN
SW
OUT
spacer
P
= V ´ Q ´ f
= 12 V ´ 3nC´ 600 kHz = 0.022 W
SW
GD
IN
G
spacer
P
= V ´ I = 12 V ´ 146 mA = 0.0018 W
IN Q
Q
where
•
•
•
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
ƒSW is the switching frequency (Hz)
trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
(55)
(56)
Therefore,
P
= P
+ P
+ P + P = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
TOT
COND
SW GD Q
For given TA,
T = T + R ´P
TOT
J
A
TH
(57)
30
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
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ZHCSG11 –FEBRUARY 2017
For given TJ(max) = 150°C
TA max = TJ max - RTH ´PTOT
(
)
(
)
where
•
•
•
•
•
•
Ptot is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
(58)
Additional power losses occur in the regulator circuit due to the inductor AC and DC losses, the catch diode, and
PCB trace resistance impacting the overall efficiency of the regulator.
8.2.1.2.13 Discontinuous Conduction Mode and Eco-mode™ Boundary
With an input voltage of 12 V, the power supply enters discontinuous-conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 μA with no load.
8.2.1.3 Application Curves
V
IN
C4: I
OUT
C4
C3: V
OUT
ac coupled
C3
VOUT -3.3 V offset
Time = 4 ms/div
Time = 100 ms/div
Figure 35. Line Transient (8 V to 40 V)
Figure 34. Load Transient
C1: V
IN
C1: V
IN
C1
C3
C3: EN
C1
C3: EN
C2: V
C2: V
OUT
C3
C2
OUT
C2
Time = 2 ms/div
Time = 2 ms/div
Figure 36. Start-up With VIN
Figure 37. Start-up With EN
Copyright © 2017, Texas Instruments Incorporated
31
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
C1: SW
C1: SW
C1
C4
C1
C4: I
L
C4: I
L
C2: V
ac coupled
OUT
C2
C4
C2
C2: V
ac coupled
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 38. Output Ripple CCM
Figure 39. Output Ripple DCM
C1: SW
C1: SW
C1
C1
C4: I
L
C4: I
L
C4
C2
C2: V
ac coupled
C3: V
IN
ac coupled
OUT
C2
C4
Time = 2 ms/div
Time = 2 ms/div
Figure 40. Output Ripple PSM
Figure 41. Input Ripple CCM
C1: SW
C1: SW
C1
C4
C4: I
L
C4
C3
C4: I
L
C3: V
IN
ac coupled
C3
C3: V
ac coupled
OUT
V
V
= 5.5 V
= 5 V
IN
No Load
EN Floating
OUT
Time = 2 ms/div
Time = 20 ms/div
Figure 42. Input Ripple DCM
Figure 43. Low Dropout Operation
32
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
100
90
100
90
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
6Vin
6Vin
12Vin
24Vin
36Vin
42Vin
36Vin
42Vin
12Vin
24Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.001
0.01
0.1
1
I
- Output Current - A
I - Output Current - A
O
O
Figure 44. Efficiency vs Load Current
Figure 45. Light-Load Efficiency
100
90
100
90
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
6Vin
6Vin
36Vin
42Vin
36Vin
42Vin
12Vin
24Vin
12Vin
24Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.001
0.01
0.1
1
I
- Output Current - A
I - Output Current - A
O
O
Figure 46. Efficiency vs Load Current
Figure 47. Light-Load Efficiency
180
1
60
40
0.8
Phase
120
60
0
0.6
0.4
0.2
0
20
Gain
0
-0.2
0.4
-0.6
-0.8
-1
6- 0
-20
-120
-180
-40
-60
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
100
1000
10000
100000
1000000
I
- Output Current - A
Frequency - Hz
O
Figure 48. Overall Loop-Frequency Response
Figure 49. Regulation vs Load Current
Copyright © 2017, Texas Instruments Incorporated
33
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
0.3
0.2
0.1
0
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
V
- Input Voltage - V
IN
Figure 50. Regulation vs Input Voltage
8.2.2 Inverting Power Supply
The TPS54340B-Q1 device can be used to convert a positive input voltage to a negative output voltage.
Example applications are amplifiers requiring a negative power supply. For a more detailed example, see
SLVA317.
VIN
+
Cin
Cboot
Lo
SW
GND
BOOT
VIN
Cd
R1
R2
+
GND
Co
TPS54340B-Q1
FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero Cpole
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 51. TPS54340B-Q1 Inverting Power Supply from Application Note (SLVA317)
34
Copyright © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
8.2.3 Split-Rail Power Supply
The TPS54340B-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative
output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and
negative voltage power supply. For a more detailed example, see SLVA369.
VOPOS
+
Copos
VIN
+
Cin
Cboot
SW
GND
BOOT
VIN
GND
Lo
Cd
R1
R2
+
Coneg
TPS54340B-Q1
VONEG
FB
EN
COMP
RT/CLK
Rcomp
Czero Cpole
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 52. TPS54340B-Q1 Split-Rail Power Supply Based on Application Note (SLVA369)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 42V. This input supply must
remain within this range. If the input supply is located more than a few inches from the TPS54340B-Q1
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 53 for a PCB layout example.
•
To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
•
Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode
of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the output inductor.
Because the SW connection is the switching node, the catch diode and output inductor should be located
close to the SW pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
•
The GND pin should be tied directly to the power pad under the IC and the PowerPAD™. The PowerPAD
should be connected to internal PCB ground planes using multiple vias directly under the IC.
•
•
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
•
•
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has
been shown to produce good results, and is meant as a guideline.
Copyright © 2017, Texas Instruments Incorporated
35
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
10.2 Layout Example
Vout
Output
Capacitor
Output
Inductor
Topside
Ground
Area
Route Boot Capacitor
Catch
Diode
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
VIN
SW
GND
COMP
FB
Vin
EN
UVLO
RT/CLK
Compensation
Network
Adjust
Resistor
Divider
Resistors
Frequency
Thermal VIA
Signal VIA
Set Resistor
Figure 53. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of Figure 33, the estimated PCB area is 1.025 in2 (661 mm2). This area
does not include test points or connectors. If the area must be reduced, then this can be done by using a two
sided assembly, and replacing the 0603 sized passives with a smaller-sized equivalent.
36
版权 © 2017, Texas Instruments Incorporated
TPS54340B-Q1
www.ti.com.cn
ZHCSG11 –FEBRUARY 2017
11 器件和文档支持
11.1 器件支持
11.1.1 使用 WEBENCH® 工具定制设计方案
请单击此处，使用 TPS54340B-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《利用 TPS54260 创建 GSM 电源》，SLVA412。
《利用 TPS54240 和 TPS2511 创建供 USB 设备使用的通用车载充电器》，SLVA464。
《利用降压稳压器创建反向电源》，SLVA317。
《使用宽输入电压降压稳压器创建分裂轨电源》，SLVA369。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
版权 © 2017, Texas Instruments Incorporated
37
TPS54340B-Q1
ZHCSG11 –FEBRUARY 2017
www.ti.com.cn
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
38
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54340BQDDAQ1
TPS54340BQDDARQ1
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
5434BQ
5434BQ
2500 RoHS & Green
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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