TPS54372-Q1 [TI]
适用于 DDR 应用、具有跟踪和端接功能的汽车类 3V 至 6V、3A 降压转换器;
| 型号： | TPS54372-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 DDR 应用、具有跟踪和端接功能的汽车类 3V 至 6V、3A 降压转换器 双倍数据速率 转换器 |
| 文件： | 总19页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Size
6,4 mm X 6,6 mm
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TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
3-A OUTPUT TRACKING/TERMINATION SYNCHRONOUS PWM
SWITCHER WITH INTEGRATED FETs (SWIFT)
FEATURES
DESCRIPTION
D
D
D
Qualified for Automotive Applications
As a member of the SWIFT family of dc/dc regulators,
the TPS54372 low-input voltage high-output current
synchronous-buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush currents;
and a status output to indicate valid operating
conditions.
Tracks Externally Applied Reference Voltage
60-mΩ MOSFET Switches for High Efficiency
at 3-A Continuous Output Source or Sink
Current
D
D
6% to 90% V Output Tracking Range
I
Wide PWM Frequency:
Fixed 350 kHz or Adjustable 280 kHz to
700 kHz
D
D
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
The TPS54372 is available in a thermally enhanced
20-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. Texas Instruments provides
evaluation modules and the SWIFT designer software
tool to aid in quickly achieving high-performance power
supply designs to meet aggressive equipment
development cycles.
D
DDR Memory Termination Voltage
D
Active Termination of GTL and SSTL
High-Speed Logic Families
D
D
DAC Controlled High Current Output Stage
Precision Point of Load Power Supply
SIMPLIFIED SCHEMATIC
SIMPLIFIED SCHEMATIC
TRANSIENT RESPONSE
Input
VDDQ
V = 5 V,
VIN
PH
VTTQ
I
V
= 1.25 V
O
TPS54372
BOOT
PGND
REFIN
VBIAS
COMP
VSENSE
AGND
0 A to
2.25 A
Compensation
Network
t − Time − 25 ms/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2008, Texas Instruments Incorporated
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION{
}
T
REFIN VOLTAGE
PACKAGE
Plastic HTSSOP (PWP)
PART NUMBER
J
§
−40°C to 125°C
0.2 V to 1.75 V
TPS54372QPWPRQ1
†
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
The PWP package is available taped and reeled as indicated by the R suffix to the device type (i.e., TPS54372QPWPRQ1). See the application
section of the data sheet for PowerPAD drawing and layout information.
‡
§
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
TPS54372
−0.3 V to 7 V
−0.3 V to 6 V
−0.3 V to 4 V
−0.3 V to 17 V
−0.3 V to 7 V
−0.6 V to 6 V
Internally limited
6 mA
VIN, ENA
RT
V
V
Input voltage range
I
VSENSE, REFIN
BOOT
VBIAS, COMP, STATUS
PH
Output voltage range
Source current
O
PH
I
O
COMP, VBIAS
PH
6 A
COMP
6 mA
I
S
Sink current
ENA, STATUS
AGND to PGND
10 mA
Voltage differential
0.3 V
T
T
Operating virtual junction temperature range
Storage temperature
−40°C to 150°C
−65°C to 150°C
300°C
J
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
6
UNIT
V
V
T
Input voltage
3
I
Operating junction temperature
−40
125
°C
J
(1)(2)
DISSIPATION RATINGS
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T = 25°C
T = 70°C
T = 85°C
A
A
A
POWER RATING POWER RATING POWER RATING
(3)
20 Pin PWP with solder
26.0°C/W
57.5°C/W
3.85 W
1.73 W
2.11 W
0.96 W
1.54 W
0.69 W
20 Pin PWP without solder
(1)
For more information on the PWP package, see the Texas Instruments technical brief (SLMA002).
Test board conditions:
(2)
1. 3” x 3”, four layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. Ten thermal vias (see Recommended Land Pattern in the Applications Section of this data sheet)
Maximum power dissipation may be limited by overcurrent protection.
(3)
2
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TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS
T = –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
SUPPLY VOLTAGE, VIN
V
Input voltage range
Quiescent current
3
6
9.6
IN
f = 350 kHz, RT open, PH pin open
6.2
8.4
1
s
f = 386 kHz, RT = 160 kΩ, PH pin open
12.8
1.4
I
mA
s
(Q)
Shutdown, ENA = 0 V
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
2.8
3
V
V
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.7
2.7
115
2.5
mV
µs
(1)
Rising and falling edge deglitch, UVLO
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I
= 0
2.8
2.95
100
V
(VBIAS)
(2)
µA
REGULATION
Line regulation
(1)(3)
(1)(3)
I = 1.5 A, f = 350 kHz, T = 125°C
0.07
0.03
%/V
%/A
L
s
J
Load regulation
OSCILLATOR
Internally set free running frequency
I = 0 A to 3 A, f = 350 kHz, T = 125°C
L
s
J
RT open
265
252
290
663
350
280
312
700
0.75
1
440
308
350
762
kHz
kHz
(1)
RT = 180 kΩ (1% resistor to AGND)
RT = 160 kΩ (1% resistor to AGND)
Externally set free running frequency range
(1)
RT = 68 kΩ (1% resistor to AGND)
(1)
Ramp valley
V
V
(1)
Ramp amplitude (peak-to-peak)
(1)
Minimum controllable on time
200
ns
(1)
Maximum duty cycle
90%
ERROR AMPLIFIER
(1)
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND
90
3
110
5
dB
MHz
V
(1)
Parallel 10 kΩ, 160 pF COMP to AGND
(1)
Error amplifier common mode input voltage range Powered by internal LDO
0
VBIAS
250
Input bias current, VSENSE
VSENSE = V
60
nA
ref
(1)
Output voltage slew rate (symmetric), COMP
1
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding deadtime)
(1)
10-mV overdrive
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, ENA
Enable hysteresis voltage, ENA
0.82
2.6
1.2
0.03
2.5
1.4
V
V
(1)
(1)
Falling edge deglitch, ENA
µs
ms
(1)
Internal slow-start time
3.35
4.1
STATUS
Output saturation voltage, STATUS
Leakage current, STATUS
I
= 2.5 mA
0.18
0.3
1
V
sink
V = 3.6 V
µA
I
(1)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 8.
(2)
(3)
3
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T = –40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
V = 3 V
4
6.5
7.5
I
Current limit
A
V = 6 V
I
4.5
(1)
Current limit leading edge blanking time
100
200
ns
ns
(1)
Current limit total response time
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
°C
°C
Thermal shutdown hysteresis
OUTPUT POWER MOSFETS
(4)
(4)
V = 6 V
59
85
88
I
r
Power MOSFET switches
mΩ
DS(on)
V = 3 V
I
136
(1)
(2)
(3)
(4)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 8.
Matched MOSFETs low-side r
production tested, high-side r
production tested.
DS(on)
DS(on)
HTSSOP PowerPAD
(TOP VIEW)
1
20
19
18
17
16
15
14
13
12
11
AGND
VSENSE
COMP
STATUS
BOOT
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
2
3
4
5
6
7
PH
PH
PH
PH
8
9
10
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor and RT resistor.
Connect the PowerPAD connection to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
ENA
3
Error amplifier output. Connect the frequency compensation network from COMP to VSENSE.
19
Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and places
device in a low quiescent current state.
PGND
11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the
input and output supply returns and negative terminals of the input and output capacitors. A single point connection to AGND
is recommended.
PH
6−10 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
RT
20
18
4
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f .
s
REFIN
STATUS
External reference input. High impedance input to slow-start and error amplifier circuits.
Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal shutdown
signal is active. Otherwise, STATUS is high.
VBIAS
VIN
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high-quality, low-ESR 10-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
4
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TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
Enable
Comparator
REG
Falling
Edge
Deglitch
ENA
SHUTDOWN
VIN
ILIM
Comparator
1.2 V
VIN
Thermal
Shutdown
150°C
Hysteresis: 0.03
Leading
Edge
Blanking
2.5 µs
V
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.95 V
Sense FET
Deglitch
Hysteresis: 0.16
V
30 mΩ
VDDQ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
tt
PH
REFIN
Slow-start
(0.25 V/ms minimum)
+
−
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
Error
Amplifier
PWM
Comparator
VIN
25 ns Adaptive
Dead Time
30 mΩ
PGND
OSC
TPS54372
STATUS
SS_DIS
VSENSE
COMP
RT
5
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
90
120
750
650
550
VIN = 3.3 V
VIN = 5 V
= 3 A
80
70
60
50
40
30
20
I
= 3 A
O
I
O
100
80
60
450
40
RT = Open
350
250
20
0
10
0
−40
0
25
85
125
−40
0
25
85
125
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
Figure 2
Figure 3
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
JUNCTION TEMPERATURE
LOAD CURRENT
3.80
800
700
600
2.25
2
T
− 125°C
J
f
= 700 kHz
3.65
3.50
s
1.75
1.5
RT = 68 kΩ
RT = 100 kΩ
RT = 180 kΩ
V = 3.3 V
I
3.35
1.25
500
400
300
200
1
3.20
3.05
V = 5 V
I
0.75
0.5
0.25
0
2.90
2.75
−40
0
25
85
125
−40
0
25
85
125
0
1
2
3
4
T
J
− Junction Temperature − °C
I
− Load Current − A
T
J
− Junction Temperature − °C
L
Figure 4
Figure 5
Figure 6
ERROR AMPLIFIER
OPEN LOOP RESPONSE
0
140
120
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
L
−20
−40
−60
−80
A
100
80
60
40
20
Phase
Gain
−100
−120
−140
−160
−180
−200
0
−20
1
10 100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 7
6
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TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
APPLICATION INFORMATION
Figure 8 shows the schematic diagram for a typical
TPS54372 application. The TPS54372 (U1) can provide
up to 3 A of output current at a nominal output voltage of
one half of V
(typically 1.25 V). For proper operation,
DDQ
the PowerPAD underneath the integrated circuit
TPS54372 is soldered directly to the printed-circuit board.
TP2
J1
2
V
I
1
TP9
GND
TP3
J2
1
C4
10 µF
U1
VDDQ
TPS54372PWP
TP1
2
GND
1
2
3
4
5
6
7
8
9
20
R6
AGND
RT
ENA
C13
10 kΩ
19
18
0.1 µF
VSENSE
COMP
REFIN
VBIAS
VIN
17
16
15
14
13
12
11
R2
C2
470 pF
STATUS
36.5 kΩ
R7
10 kΩ
C12
BOOT
PH
0.1 µF
R5
71.5 kΩ
C9
VIN
1 µF
PH
VIN
C6
0.047 pF
C1
12 pF
PH
PGND
PGND
PGND
TP8
PH
10
PH
PwrPAD
21
C8
10 µF
R3
1.21 kΩ
R1
10 kΩ
C3
1500 pF
TP4
TP5
J2
1
2
1
2
VTTQ
GND
L1
1 µH
+
+
R4
2.4 Ω
C10
150 µF
C11
1 µF
C7
150 µF
TP7
C5
3300 pF
TP6
Figure 8. Application Circuit
COMPONENT SELECTION
FEEDBACK CIRCUIT
The values for these components are selected to provide
fast transient response times. Components R1 R2, R3,
C1, C2, and C3 forms the loop compensation network for
the circuit. For this design, a Type 3 topology is used. The
transfer function of the feedback network is chosen to
provide maximum closed loop gain available with open
loop characteristics of the internal error amplifier. Closed
loop crossover frequency is typically between 80 kHz and
125 kHz for input from 3 V to 6 V.
The values for the components used in this design
example were selected for good transient response and
small PCB area. Special polymer capacitors are utilized in
the output filter circuit. A small size, small value output
inductor is also used. Compensation network components
are chosen to maximize closed loop bandwidth and
provide good transient response characteristics.
Additional design information is available at www.ti.com.
INPUT VOLTAGE
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5 kΩ
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68-kΩ to 180-kΩ resistor
between RT (pin 20) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:
The input voltage is a nominal 3.3 or 5 VDC. The input filter
(C4) is a 10-µF ceramic capacitor (Taiyo Yuden).
Capacitor C8, a 10-µF ceramic capacitor (Taiyo Yuden)
that provides high frequency decoupling of the TPS54372
from the input supply, must be located as close as possible
to the device. Ripple current is carried in both C4 and C8,
and the return path to PGND should avoid the current
circulating in the output capacitors C7, C10, and C11.
500 kHz
Switching Frequency
R +
100 [kW]
(1)
7
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
recommended layout for a 2-layer board with the bottom
layer representing the system ground plane.
Documentation for the TPS54372 evaluation module can
be found on the Texas Instruments web site under the
TPS54372 product folder.
OUTPUT FILTER
The output filter is composed of a 1-µH inductor and
two 150-µF capacitors. The inductor is a low dc resistance
(0.010 Ω) type, Vishay IHLP−2525CZ−01 1-µH, 8.5-A
rated dc output. The capacitors used are 150 µF, 6.3-V
special polymer types.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
GROUNDING AND PowerPAD LAYOUT
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
The TPS54372 has two internal grounds (analog and
power). Inside the TPS54372, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54372,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground areas are
recommended. The analog ground area should be tied to
the power ground area directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground area are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54372. The power ground areas as well as the
powerpad mounting area should be tied to any internal
ground planes using multiple vias. The layout of the
TPS54372 evaluation module is representative of a
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside PowerPAD Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0227
0.0600
0.0400
0.2560
0.2454
0.1010
0.0400
0.0600
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For PowerPAD. 5mm
Stencils may Require 10 Percent
Larger Area
Minimum Recommended Top
Side Analog Ground Area
Figure 9. Recommended Land Pattern for 20-Pin PWP PowerPAD
8
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TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
PERFORMANCE GRAPHS
LOAD REGULATION
vs
OUTPUT CURRENT
LINE REGULATION
EFFICIENCY
vs
INPUT VOLTAGE
1.253
vs
OUTPUT CURRENT
100
1.255
f
T
= 700 kHz,
s
95
I
= 0 A
= 25°C,
O
A
1.252
1.251
1.25
1.253
1.251
V = 5 V,
I
90
85
V
= 1.25 V
O
I
= 1.5 A
O
80
75
70
65
I
= 3 A
O
1.249
1.247
1.245
1.249
f
= 700 kHz,
s
60
55
50
f
= 700 kHz,
T
V
= 25°C,
= 1.25 V
s
A
1.248
1.247
V = 5 V,
V
I
O
= 1.25 V
O
0
1
2
3
4
0
1
2
3
4
3
4
5
6
I
− Output Current − A
V − Input Voltage − V
I
I
− Output Current − A
O
O
Figure 10
Figure 11
Figure 12
SLOW-START TIMING
TRANSIENT RESPONSE
OUTPUT RIPPLE VOLTAGE
V = 5 V,
V = 5 V,
I
I
f
I
= 700 kHz,
= 3 A,
s
V
= 1.25 V
V
= 1.25 V
O
O
O
V = 5 V,
I
V
= 1.25 V
O
0 A to
2.25 A
t − Time − 25 ms/div
t −Time − 2.5 ms/div
t − Time − 1 µs/div
Figure 15
Figure 13
Figure 14
AMBIENT TEMPERATURE
vs
LOAD CURRENT
SOURCE-SINK TRANSIENT RESPONSE
125
V = 5 V,
I
115
105
95
V
= 1.25 V
O
V = 5 V
I
85
V = 3.3 V
I
75
(1)
65
Safe Operating Area
55
45
T
V
= 25°C,
= 1.25 V
A
35
25
−1.5 A to 1.5 A
O
0
1
2
3
4
t − Time − 100 µs/div
I
− Load Current − A
L
(1)
Figure 16
Safe operating area is applicable to the test board conditions listed
in the dissipation rating table section of this data sheet.
Figure 17
9
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
VBIAS with ac or digital switching noise may degrade
performance. The VBIAS pin may be a useful as a
reference voltage for external circuits.
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54372 incorporates an undervoltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
VOLTAGE REFERENCE
The REFIN pin provides an input for a user supplied
tracking voltage. Typically this input is one half of V
.
DDQ
The input range for this external reference is 0.2 V to
1.75 V. Above this level, the internal bandgap reference
overrides the externally supplied reference voltage.
ENABLE (ENA)
The enable pin, ENA, provides a digital control to enable
or disable (shutdown) the TPS54372. An input voltage of
1.4 V or greater ensures the TPS54372 is enabled. An
input of 0.82 V or less ensures the device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to an internally fixed
value of 350 kHz by leaving the RT pin unconnected
(floating). If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor to the RT pin to ground. The switching frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
SLOW-START
(2)
100 kW
Switching Frequency +
500 [kHz]
R
The slow-start circuit provides start-up slope control of the
output voltage to limit in-rush currents. The nominal
internal slow-start rate is 0.25 V/ms with the minimum rate
being 0.35 V/ms. When the voltage on REFIN rises faster
than the internal slope or is present when device operation
is enabled, the output rises at the internal rate. If the
reference voltage on REFIN rises more slowly, then the
output rises at approximately the same rate as REFIN.
The following table summarizes the frequency selection
configurations:
SWITCHING
RT PIN
FREQUENCY
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 180 kΩ to 68 kΩ
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND. External loading
on VBIAS is allowed, with the caution that internal circuits
require a minimum VBIAS of 2.7 V and external loads on
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54372 apart from most dc/dc
converters. The user has a wide range of output L and C
filter components to suit the particular application needs.
Type 2 or type 3 compensation can be employed using
external compensation components.
10
www.ti.com
TPS54372-Q1
SGLS267E − OCTOBER 2004 − REVISED JUNE 2008
on until the voltage at the gate of the high-side MOSFET
is below 2 V. The high-side and low-side drivers are
designed with 300-mA source and sink capability to
quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side drive is
supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω. bootstrap
switch connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
OVERCURRENT PROTECTION
The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge
blanking circuit prevents false tripping of the current limit
when the high-side switch is turning on. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54372 is capable of sinking current continuously
until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal limit trip point. This sequence repeats
until the fault condition is removed.
STATUS
The status pin is an open drain output that indicates when
internal conditions are sufficient for proper operation.
STATUS can be coupled back to a system controller or
monitor circuit to indicate that the termination or tracking
regulator is ready for start-up. STATUS is high impedance
when the TPS54372 is operating or ready to be enabled.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the gate drive voltage to the low-side
FET is below 2 V, while the low-side driver does not turn
STATUS is active low if any of the following occur:
D
D
D
VIN < UVLO threshold
VBIAS or internal reference have not settled.
Thermal shutdown is active.
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54372QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P54372Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54372-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: TPS54372
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54372QPWPRQ1 HTSSOP PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 20
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPS54372QPWPRQ1
2000
Pack Materials-Page 2
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