TPS543820RPYR-ET [TI]
4V 至 18V、8A 同步降压转换器扩展温度范围 | RPY | 14 | -55 to 150;
| 型号： | TPS543820RPYR-ET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4V 至 18V、8A 同步降压转换器扩展温度范围 | RPY | 14 | -55 to 150 转换器 |
| 文件： | 总46页 (文件大小：3479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS543820E
ZHCSM41A –MAY 2020 –REVISED JUNE 2021
TPS543820E 具有内部补偿高级电流模式控制功能的TPS543820 4V 至18V 输
入、83668A 同步SWIFT™ 降压转换器
1 特性
2 应用
• 固定频率、内部补偿高级电流模式(ACM) 控制
• 集成式25mΩ和6.5mΩMOSFET
• 输入电压范围：4V 至18V
• 支持国防、航空航天和医疗应用
– 额定结温范围为-55°C 至+150°C
• 加固型通信
• 铁路运输
• 航电设备和飞机控制
• 输出电压范围：0.5V 至7V
• 三种可选的PWM 斜坡选项，可优化控制环路性能
• 五种可选的开关频率：500kHz、750kHz、1MHz、
1.5MHz 和2.2MHz
3 说明
TPS543820E 是一款高效的 18V、8A 同步降压转换
器，其中采用了内部补偿固定频率高级电流模式控制。
该器件能够在以高达2.2MHz 的开关频率运行时提供高
效率。该器件采用 2.5mm × 3mm 小型 HotRod™
VQFN 封装，并且在高频率下具有很高的效率，因此
成为需要小解决方案尺寸的设计的理想选择。固定频率
控制器可以在 500kHz 至2.2MHz 范围内运行，并且可
以通过 SYNC 引脚与外部时钟同步。其他功能包括高
精度电压基准、可选的软启动时间、单调启动至预偏置
输出、可选的电流限制、可调UVLO（通过EN 引脚实
现）以及全套故障保护。
• 与一个外部时钟同步
• 0.5V，整个温度范围内的电压基准精度为±0.5%
• 可选的软启动时间：0.5ms、1ms、2ms 和4ms
• 单调启动至预偏置输出
• 可选的电流限制，支持8A 和6A 运行
• 具有可调节输入欠压锁定功能的使能端
• 电源正常输出监视器
• 输出过压、输出欠压、输入欠压、过流和过热保护
• -55°C 至150°C 的工作结温范围
• 2.5mm × 3mm 14 引脚VQFN-HR 封装，间距为
0.5mm
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS543820E
VQFN-HR (14)
2.50mm x 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
96
92
88
84
80
76
VIN
VIN
BP5
EN
BOOT
SW
SW
VOUT
TPS543820E
PGOOD
SYNC/FSEL
MODE
FB
AGND
72
PGND
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
68
12 V to 1.2 V, 1 MHz
12 V to 1.8 V, 1 MHz
64
60
简化版原理图
0
1
2
3
4
5
Output Current (A)
6
7
8
效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEE0
TPS543820E
ZHCSM41A –MAY 2020 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Applications.................................................. 17
9 Power Supply Recommendations................................34
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................37
11.1 接收文档更新通知................................................... 37
11.2 支持资源..................................................................37
11.3 Trademarks............................................................. 37
11.4 静电放电警告...........................................................37
11.5 术语表..................................................................... 37
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
Information.................................................................... 38
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2020) to Revision A (June 2021)
Page
• Changed 10-ns transient to 20-ns transient........................................................................................................4
• Changed VIN to SW, transient 20 ns min value to -6......................................................................................... 4
• Changed SW, transient 20 ns min value to -5.................................................................................................... 4
• Changed max VOUT to 7 V..................................................................................................................................4
• Added TOFF(min) max value................................................................................................................................. 5
• Added text for considering minimum off-time for fsw selection.........................................................................18
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5 Pin Configuration and Functions
4
3
2
SYNC/
FSEL
AGND
BP5
EN
5
6
7
1
14 BOOT
13 SW
VIN
8
9
12 VIN
10
PGND
11 PGND
SW
图5-1. 14-Pin VQFN-HR RPY Package (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Frequency select and external clock synchronization. A resistor to ground sets the switching
frequency of the device. An external clock can also be applied to this pin to synchronize the
switching frequency.
SYNC/FSEL
1
I
MODE
2
3
I
A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude.
Open-drain power good indicator
PGOOD
O
Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor
divider to set the output voltage.
FB
4
I
AGND
BP5
5
6
-
Ground return for internal analog circuits
O
Internal 4.5-V regulator output. Bypass this pin with a 2.2-μF capacitor to AGND.
Enable pin. Float to enable, enable/disable with an external signal, or adjust the input
undervoltage lockout with a resistor divider.
EN
7
I
I
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical.
A 10-nF to 100-nF capacitor from each VIN to PGND close to IC is required.
VIN
8, 12
Ground return for the power stage. This pin is internally connected to the source of the low-
side MOSFET.
PGND
SW
9, 11
10
-
O
O
Switch node of the converter. Connect this pin to the output inductor.
Return path for the internal high-side MOSFET gate driver bootstrap capacitor. Connect a
capacitor from BOOT to this pin. The SW pins are connected internally.
SW
13
Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to
SW.
BOOT
14
I
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
-0.3
-0.3
-6
MAX
20
20
25
25
6
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
VIN
VIN to SW, DC
V
VIN to SW, transient 20 ns
BOOT
V
-0.3
-0.3
-0.3
-0.3
-5
V
BOOT to SW
V
EN, PGOOD, MODE, SYNC/FSEL, FB
SW, DC
6
V
20
22
V
SW, transient 20 ns
V
Operating junction
temperature, TJ
Operating junction temperature, TJ
-55
150
150
°C
°C
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
±2000
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
NOM
MAX
18
UNIT
Input voltage
Output voltage
Output current
TJ
VIN
V
V
VOUT
0.5
7
IOUT
8
A
Operating junction temperature
External clock frequency
-55
150
2600
°C
kHz
fSYNC
400
6.4 Thermal Information
TPS543820E
THERMAL METRIC(1)
RPY (QFN, JEDEC)
RPY (QFN, TI EVM)
14 PINS
UNIT
14 PINS
58.9
37.8
7.3
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
29.1
°C/W
°C/W
°C/W
°C/W
°C/W
Not applicable (2)
Not applicable (2)
1.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.9
7.2
13.4
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM layout.
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6.5 Electrical Characteristics
TJ = –55°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
IQ(VIN)
VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1
MHz
VIN operating non-switching supply current
1200
1600
µA
ISD(VIN)
VIN shutdown supply current
VIN UVLO rising threshold
VIN UVLO hysteresis
VEN = 0 V, VVIN = 12 V
VIN rising
15
4
25
µA
V
3.9
4.1
150
mV
ENABLE AND UVLO
VEN(rise)
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
EN rising, enable switching
EN falling, disable switching
1.2
1.1
1.25
V
V
VEN(fall)
1.05
0.4
VEN(hyst)
100
1.5
mV
µA
µA
EN pin sourcing current
EN pin sourcing current
VEN = 1.1 V
VEN = 1.3 V
11.6
INTERNAL LDO BP5
VBP5
Internal LDO BP5 output voltage
BP5 dropout voltage
VVIN = 12 V
4.5
75
V
350
mV
mA
V
VIN –VBP5, VVIN = 3.8 V
BP5 short-circuit current limit
VVIN = 12 V
REFERENCE VOLTAGE
VFB
Feedback Voltage
Input leakage current into FB pin
497.5
500
1
502.5
mV
nA
TJ = –55°C to 150°C
VFB = 500 mV, non-switching, VVIN = 12 V,
VEN = 0 V
IFB(LKG)
SWITCHING FREQUENCY AND OSCILLATOR
fSW
Switching frequency
Switching frequency
Switching frequency
Switching frequency
Switching frequency
450
675
500
750
550
825
kHz
kHz
kHz
kHz
kHz
RMODE = 24.3 kΩ
RMODE = 17.4 kΩ
RMODE = 11.8 kΩ
RMODE = 8.06 kΩ
RMODE = 4.99 kΩ
fSW
fSW
900
1000
1500
2200
1100
1650
2420
fSW
1350
1980
fSW
SYNCHRONIZATION
VIH(sync)
VIL(sync)
High-level input voltage
Low-level input voltage
1.8
V
V
0.8
SOFT-START
tSS1
Soft-start time
Soft-start time
Soft-start time
Soft-start time
0.5
1
ms
ms
ms
ms
RMODE = 1.78 kΩ
RMODE = 2.21 kΩ
RMODE = 2.74 kΩ
RMODE = 3.32 kΩ
tSS2
tSS3
2
tSS4
4
POWER STAGE
RDS(on)HS
RDS(on)LS
VBOOT-SW(UV_r)
VBOOT-SW(UV_f)
TON(min)
TOFF(min)
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
BOOT-SW UVLO rising threshold
BOOT-SW UVLO falling threshold
Minimum ON pulse width
TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V
TJ = 25°C, VBP5 = 4.5 V
VBOOT-SW rising
25
6.5
3.2
2.8
30
mΩ
mΩ
V
VBOOT-SW falling
V
IOUT > ½ IL_PK-PK
37
ns
Minimum OFF pulse width (1)
115
140
ns
CURRENT SENSE AND OVERCURRENT PROTECTION
IOC_HS_pk1
IOC_HS_pk2
IOC_LS_src1
IOC_LS_src2
IOC_LS_snk
High-side peak current limit
High-side peak current limit
Low-side sourcing current limit
Low-side sourcing current limit
Low-side sinking current limit
11.7
8.6
12.2
9
12.7
9.6
A
A
A
A
A
RMODE = 1.78 kΩ
RMODE = 22.1 kΩ
RMODE = 1.78 kΩ
RMODE = 22.1 kΩ
Current into SW pin
9.4
10.4
7.4
11.3
8.5
6.2
2.95
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
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TJ = –55°C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overvoltage-protection (OVP) threshold
voltage
VOVP
VFB rising
VFB falling
120
% VREF
Undervoltage-protection (UVP) threshold
voltage
VUVP
80
% VREF
POWER GOOD
PGOOD threshold
PGOOD threshold
PGOOD threshold
PGOOD threshold
VFB rising (Fault)
VFB falling (Good)
VFB rising (Good)
VFB falling (Fault)
113
105
89
116
108
92
119 % VREF
111 % VREF
95 % VREF
87 % VREF
81
84
Leakage current into PGOOD pin when
open drain output is high
IPGOOD(LKG)
VPG(low)
VPGOOD = 4.7 V
5
µA
PGOOD low-level output voltage
Min VIN for valid PGOOD output
IPGOOD = 2 mA, VIN = 12 V
0.5
1
V
V
0.9
HICCUP
Hiccup time before re-start
Output discharge resistance
7*tSS
ms
OUTPUT DISCHARGE
VVIN = 12 V, VSW = 0.5 V, power conversion
disabled.
RDischg
100
Ω
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
165
12
175
°C
°C
THYST
(1) Specified by design. Not production tested.
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6.6 Typical Characteristics
TA = 25°C
100
96
92
88
84
80
76
72
68
64
60
1.8
1.6
1.4
1.2
1
12 V to 1 V, 750 kHz
12 V to 1 V, 1 MHz
12 V to 1 V, 1.5 MHz
12 V to 1 V, 2.2 MHz
0.8
0.6
0.4
0.2
0
12 V to 1 V, 750 kHz
12 V to 1 V, 1 MHz
12 V to 1 V, 1.5 MHz
12 V to 1 V, 2.2 MHz
0
1
2
3
Output Current (A)
4
5
6
7
8
8
8
0
1
2
3
Output Current (A)
4
5
6
7
8
8
8
L = 470 nH, 2.5 mΩtypical
L = 470 nH, 2.5 mΩtypical
图6-1. Efficiency vs Output Current
图6-2. Power Loss vs Output Current
100
1.6
12 V to 0.8 V, 1 MHz
96
92
88
84
80
76
72
68
64
60
12 V to 1 V, 1 MHz
12 V to 1.2 V, 1 MHz
12 V to 1.8 V, 1 MHz
1.4
1.2
1
0.8
0.6
0.4
0.2
0
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
12 V to 1.2 V, 1 MHz
12 V to 1.8 V, 1 MHz
0
1
2
3
Output Current (A)
4
5
6
7
0
1
2
3
Output Current (A)
4
5
6
7
L = 470 nH, 2.5 mΩtypical
L = 470 nH, 2.5 mΩtypical
图6-3. Efficiency vs Output Current
图6-4. Power Loss vs Output Current
100
2.4
VOUT = 1.8 V, L = XGL5030-901
VOUT = 2.5 V, L = XGL5030-901
VOUT = 3.3 V, L = XGL5050-122
VOUT = 5 V, L = XGL5050-122
2.2
95
90
85
80
75
70
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VOUT = 1.8 V, L = XGL5030-901
VOUT = 2.5 V, L = XGL5030-901
VOUT = 3.3 V, L = XGL5050-122
VOUT = 5 V, L = XGL5050-122
0
1
2
3
Output Current (A)
4
5
6
7
0
1
2
3
Output Current (A)
4
5
6
7
VIN = 12 V
fSW = 1.0 MHz
VIN = 12 V
fSW = 1.0 MHz
图6-5. Efficiency vs Output Current –1.8-V to 5.0- 图6-6. Power Loss vs Output Current –1.8-V to
V Output
5.0-V Output
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60
70
65
60
55
50
45
40
35
30
25
Nat conv
100 LFM
Nat conv
100 LFM
200 LFM
400 LFM
55
200 LFM
400 LFM
50
45
40
35
30
25
2
2.5
3
3.5
4
4.5
Output Current (A)
5
5.5
6
6.5
7
7.5
8
2
2.5
3
3.5
4
4.5
Output Current (A)
5
5.5
6
6.5
7
7.5
8
VIN = 12 V
fSW = 1.0 MHz
TA = 25 °C
VIN = 12 V
fSW = 1.0 MHz
TA = 25 °C
图6-7. Junction Temperature vs Output Current – 图6-8. Junction Temperature vs Output Current –
1-V Output 3.3-V Output
0.505
0.504
0.503
0.502
0.501
0.5
3
2.5
2
VIN = 4 V
VIN = 12 V
VIN = 18 V
1.5
1
0.499
0.498
0.497
0.496
0.495
0.5
0
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
Junction Temperature (èC)
Junction Temperature (èC)
VEN = 1.1 V
图6-9. Regulated FB Voltage vs Junction
图6-10. EN Pin Current vs Junction Temperature
Temperature
12.5
12
11.5
11
10.5
10
VIN = 4 V
VIN = 12 V
VIN = 18 V
9.5
-75
-50
-25
0
25
50
75
100 125 150
Junction Temperature (èC)
VEN = 1.3 V
图6-11. EN Pin Current vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS543820E device is a 8-A, high-performance, synchronous buck converter with two integrated N-channel
MOSFETs. The TPS543820E has a maximum operating junction temperature of 150°C, making it suitable for
high-ambient temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V
and the output voltage range is 0.5 V to 7 V. The device features a fixed-frequency Advanced Current Mode
control with a switching frequency of 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when
selecting output filter components. The switching frequency of the device can be synchronized to an external
clock applied to the SYNC pin.
Advanced Current Mode (ACM) is an emulated peak current control topology. It supports stable static and
transient operation without complex external compensation design. This control architecture includes an internal
ramp generation network that emulates inductor current information, enabling the use of low-ESR output
capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-
noise ratio for good noise immunity. The TPS543820E has three ramp options (see 节 7.3.6 for details) to
optimize the internal loop for various inductor and output capacitor combinations with only a single resistor to
AGND. The TPS543820E is easy-to-use and allows low external component count with fast load transient
response. Fixed-frequency operation also provides ease-of-filter design to overcome EMI noise.
7.2 Functional Block Diagram
BP5
VIN
BP5_UVLO
CLK
UVLO
VIN_UVLO
UVLO
SYNC/
FSEL
Linear Regulator
EN_UVLO
Oscillator
Cramp
ILIM
Pinstrap
Detect
Boot
Charge
BOOT
MODE
VREF
Soft-Start
Control
EN_UVLO
EN
FB
UVLO
ACM
Controller
Control
Logic
SW
BP5
OV/UV
Comparators
PGND
Thermal
Shutdown
Fault Logic
BOOT
SW
UVLO
HS and LS
Current Sense
OC_FLT
OC_FLT
ILIM
VIN_UVLO
BP5_UVLO
AGND
PGOOD
7.3 Feature Description
7.3.1 VIN Pins and VIN UVLO
The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the
power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO
circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO
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threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV. A voltage divider connected to the EN
pin can adjust the input voltage UVLO as appropriate. See 节7.3.2 for more details.
7.3.2 Enable and Adjustable UVLO
The EN pin provides on/off control of the device. Once the EN pin voltage exceeds its threshold voltage, the
device begins its start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters a low operating current state. The EN pin has an internal pullup current source, Ip,
allowing it to be floated to enable the device by default. It is important to ensure that leakage currents of anything
connected to the EN pin do not exceed the minimum EN pullup current or the device may not be able to start. If
an application requires controlling the EN pin, an open drain or open collector output logic can be interfaced with
the pin.
When the EN pin voltage exceeds its threshold voltage and the VIN pin voltage exceeds its VIN UVLO threshold,
the device begins its start-up sequence. First, the BP5 LDO is enabled and charges the external BP5 capacitor.
Once the voltage on the BP5 pin exceeds its UVLO threshold, the device enters a power-on delay. During the
power-on delay, the values of the pinstrap resistors on the MODE pin (see 节7.3.8) and SYNC/FSEL pin (see 节
7.3.4) are determined and the control loop is initialized. The power-on delay is typically 600 μs. After the power-
on delay, soft start begins.
4.0V
VIN
1.2V
EN
3.6V
BP5 LDO
Power-on
delay
BP5 LDO
Startup
SW pulses are omitted to
simplify the illustration
……
SW
VOUT
图7-1. Start-up Sequence
An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown
in 图 7-2. The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no
external components are connected. The pullup current is also used to control the voltage hysteresis for the
UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can
be calculated using 方程式 1 and 方程式 2. When using the adjustable UVLO function, 500 mV or greater
hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed
from the EN pin to ground to filter any glitches on the input voltage.
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VIN
EN
Ip
Ih
RENT
+
œ
RENB
图7-2. Adjustable UVLO Using EN
≈
∆
«
’
÷
VENFALLING
VSTART
ì
- V
STOP
VENRISING ◊
RENT
=
≈
’
VENFALLING
I ì 1-
+ I
h
∆
÷
p
VENRISING ◊
«
(1)
(2)
RENT ì VENFALLING
RENB
=
VSTOP - VENFALLING + RENT ì I +I
p
h
7.3.3 Adjusting the Output Voltage
The output voltage is programmed with a resistor divider from the output (VOUT) to the FB pin shown in 图 7-3. It
is recommended to use 1% tolerance or better divider resistors. Starting with a fixed value for the bottom
resistor, typically 10 kΩ, use 方程式3 to calculate the top resistor in the divider.
VOUT
RFBT
FB
œ
0.5 V
+
RFBB
图7-3. FB Resistor Divider
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(3)
7.3.4 Switching Frequency Selection
The switching frequency of the device can be selected by connecting a resistor (RFSEL) between the SYNC/
FSEL pin and AGND. The frequency options and their corresponding programming resistors are listed in 表 7-1.
It is required to use a 1% tolerance resistor or better.
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表7-1. Switching Frequency Selection
RFSEL ALLOWED NOMINAL
RECOMMENDED E96
STANDARD VALUE (1%) (kΩ)
RECOMMENDED E12
STANDARD VALUE (1%) (kΩ)
Fsw (kHz)
RANGE (1%) (kΩ)
24.3
17.4
11.8
8.06
4.99
27
18
500
750
≥24.0
17.4-18.0
11.8-12.1
8.06-8.25
≤5.11
12
1000
1500
2200
8.2
4.7
7.3.5 Switching Frequency Synchronization to an External Clock
The device can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL
pin with a duty cycle from 20% to 80%. The clock can either be applied before the device starts up or during
operation. If the clock is to be applied before the device starts, a resistor between SYNC/FSEL and AGND is not
needed. If the clock is to be applied after the device starts, then the clock frequency should be within ±20% of
the frequency set by the SYNC/FSEL resistor. When the clock is applied after the device starts, the device will
begin synchronizing to this clock after counting four consectutive switching cycles with a clock pulse present.
This is shown in 图7-4.
7.3.5.1 Internal PWM Oscillator Frequency
When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the
external clock is not present, the device will default to the internal PWM oscillator frequency.
If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set
by the RFSEL resistor according to 表7-1. The device switches at this frequency until the external clock is applied
or anytime the external clock is not present.
If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device will
determine the internal clock frequency by decoding the external clock frequency. 表 7-2 shows the decoding of
the internal PWM oscillator frequency based on the external clock frequency.
表7-2. Internal Oscillator Frequency Decode
EXTERNAL SYNC CLOCK FREQUENCY (kHz)
DECODED INTERNAL PWM OSCILLATOR FREQUENCY (kHz)
400 - 600
600 - 857
500
750
857 - 1200
1200 - 1810
1810 - 2640
1000
1500
2200
The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the
external clock frequency is to be within that tolerance range, it is possible for the internal PWM oscillator
frequency to be decoded as either the frequency above or below that threshold. Since the internal frequency is
what is used in case of the loss of the synchronization clock, it is recommended that the output LC filter and
ramp selection are chosen to be stable for either frequency. 表 7-3 shows the tolerance range of the decode
thresholds. If the external clock is to be within any of these ranges, it is recommended to ensure converter
stability for both possible internal PWM oscillator frequencies.
表7-3. Frequency Decode Thresholds
MINIMUM (kHz)
TYPICAL (kHz)
MAXIMUM (kHz)
570
814
600
857
630
900
1140
1736
1200
1810
1260
1884
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7.3.5.2 Loss of Synchronization
If at any time during operation, there is a loss of synchronization, the device will default to the internal PWM
oscillator frequency until the synchronization clock returns. Once the clock is no longer present, the device will
switch at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without
clock pulses, the device will operate at the normal internal PWM oscillator frequency. This is demonstrated in 图
7-4.
SW (5 V/div)
VOUT AC (10 mV/div)
SYNC (5 V/div)
Time (4 µs/div)
图7-4. Clock Synchronization Transitions
7.3.5.3 Interfacing the SYNC/FSEL Pin
If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is
enabled, a high impedance buffer is recommended to ensure proper detection of the RFSEL value. 图 7-5 shows
the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure
proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC
voltage is available and the buffers output is high impedance before the device tries to detect the RFSEL value.
When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA.
BP5
OE
VCC
SYNC/FSEL
RFSEL
图7-5. Interfacing the SYNC/FSEL Pin with a Buffer
7.3.6 Ramp Amplitude Selection
The TPS543820E uses VIN, duty cycle, and low-side FET current information to generate an internal ramp. The
ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP
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can be selected with a resistor to AGND on the MODE pin (see 节 7.3.8). The capacitor options are 1 pF, 2 pF,
and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop
bandwidth. 图7-6 and 图7-7 show how the loop changes with each ramp setting for the schematic in 节8.2.3.
60
40
20
0
180
150
120
90
60
30
0
-30
-60
-90
-120
-20
-40
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
100 200 5001000
10000
Frequency (Hz)
100000
1000000
100 200 5001000
10000
Frequency (Hz)
100000
1000000
图7-7. Loop Phase vs Ramp Settings
图7-6. Loop Gain vs Ramp Settings
7.3.7 Soft Start and Prebiased Output Start-up
During start-up, the device softly ramps the reference voltage to reduce inrush currents. There are four options
for the soft-start time, which is the time it takes for the reference to ramp to 0.5 V: 0.5 ms, 1 ms, 2 ms, and 4 ms.
The soft-start time is selected with a resistor to AGND on the MODE pin (see 节7.3.8).
The device prevents current from being discharged from the output during start-up when a prebiased output
condition exists. It does this by operating in discontinuous conduction mode (DCM) during the first 16 cycles to
prevent the device from sinking current. This ensures the output voltage will be smooth and monotonic during
soft start.
7.3.8 Mode Pin
The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, RMODE
,
between MODE and AGND. 表 7-4 lists the resistor values for the available options. It is required to use a 1%
tolerance resistor or better. See 节 7.3.10 for the corresponding current limit thresholds for the "High" and "Low"
settings.
表7-4. MODE Pin Selection
CURRENT LIMITS
CRAMP (pF)
SOFT-START TIME (ms)
RMODE (kΩ)
1.78
2.21
2.74
3.32
4.02
4.87
5.9
High
1
1
1
1
2
2
2
2
4
4
4
4
1
1
1
0.5
1
High
High
2
High
4
High
0.5
1
High
High
2
7.32
9.09
11.3
High
4
High
0.5
1
High
14.3
18.2
22.1
26.7
33.2
High
2
High
4
Low
0.5
1
Low
Low
2
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表7-4. MODE Pin Selection (continued)
CURRENT LIMITS
CRAMP (pF)
SOFT-START TIME (ms)
RMODE (kΩ)
40.2
49.9
60.4
76.8
102
137
174
243
412
Low
Low
Low
Low
Low
Low
Low
Low
Low
1
2
2
2
2
4
4
4
4
4
0.5
1
2
4
0.5
1
2
4
7.3.9 Power Good (PGOOD)
The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the
FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a 256-µs
deglitch time, the PGOOD pin is de-asserted and the pin floats. A pullup resistor between the values of 10 kΩ
and 100 kΩ to a voltage source that is 5.5 V or less is recommended. PGOOD is in a defined state once the VIN
input voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or
greater than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PGOOD pin is pulled
low. PGOOD is immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters
thermal shutdown.
7.3.10 Current Protection
The protects against overcurrent events by cycle-by-cycle current limiting both the high-side MOSFET and low-
side MOSFET. In an extended overcurrent condition, the device will enter hiccup. Different protections are active
during positive inductor current and negative inductor current conditions.
7.3.10.1 Positive Inductor Current Protection
The current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to
settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned
off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls
below the low-side MOSFET overcurrent threshold. This effectively limits the peak current in the case of a short
circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup.
The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received
from the controller, the device skips processing that PWM pulse. The device does not turn the high-side
MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent
threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate
counters for the high-side and low-side overcurrent events. If the off-time is too short, the low-side overcurrent
may not trip. The low-side overcurrent will, however, begin tripping after the high-side peak overcurrent limit is hit
as hitting the peak current limit shortens the on-time and lengthens the off-time.
Both the high-side and low-side positive overcurrent thresholds are programmable using the MODE pin. Two
sets of thresholds are available ("High" and "Low"), which are summarized in 表 7-5. The values for these
thresholds are obtained using open-loop measurements with a DC current in order to accurately specify the
values. In real applications, the inductor current will ramp and the ramp rate will be a function of the voltage
across the inductor (VIN - VOUT) as well as the inductance value. This ramp rate combined with delays in the
current sense circuitry can result in slightly different values than specified. The current at which the high-side
overcurrent limit takes effect can be slightly higher than specified, and the current at which the low-side
overcurrent limit takes effect can be slightly lower than specified.
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表7-5. Overcurrent Thresholds
HIGH-SIDE OVERCURRENT TYPICAL
VALUE (A)
LOW-SIDE OVERCURRENT TYPICAL VALUE
(A)
MODE PIN CURRENT LIMIT SETTING
High
Low
12.2
9.0
10.4
7.4
7.3.10.2 Negative Inductor Current Protection
Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is
immediately turned off. The next high-side MOSFET turnon is determined by the clock and PWM comparator.
The negative overcurrent threshold minimum value is 2.95 A. Similar to the positive inductor current protections,
the actual value of the inductor current when the current sense comparators trip will be a function of the current
ramp rate. As a result the current at which the negative inductor current limit takes effect can be slightly more
negative than specified.
7.3.11 Output Overvoltage and Undervoltage Protection
The device incorporates both output overvoltage and undervoltage protection. If an overvoltage is detected, the
device tries to discharge the output voltage to a safe level before attempting to restart. When the overvoltage
threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent threshold is
reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero. Then, the low-
side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. This process
repeats until the output voltage falls back into the PGOOD window. Once this happens, the device restarts and
goes through a soft start cycle. The device does not wait the hiccup time before restarting.
When an undervoltage condition is detected, the device will enter hiccup where it waits seven soft-start cycles
before restarting. Undervoltage protection is enabled after soft start is complete.
7.3.12 Overtemperature Protection
When the die temperature exceeds 165°C, the device turns off. Once the die temperatures falls below the
hysteresis level, typically 12°C, the device restarts. While waiting for the temperature to fall below the hysteresis
level, the device does not switch or attempt to hiccup to restart. Once the temperature falls below this level, the
device restarts without going through hiccup.
7.3.13 Output Voltage Discharge
When the device is enabled, but the high-side FET and low-side FET are disabled due to a fault condition, the
output voltage discharge mode is enabled. This mode turns on the discharge FET from SW to PGND to
discharge the output voltage. The discharge FET is turned off when the converter is ready to resume switching,
either after the fault clears or after the wait time before hiccup is over.
The output voltage discharge mode is activated by any of below fault events:
1. High-side or low-side positive overcurrent
2. Thermal shutdown
3. Output voltage undervoltage
4. VIN UVLO
7.4 Device Functional Modes
7.4.1 Forced Continuous-Conduction Mode
The TPS543820E operates in forced continuous-conduction mode (FCCM) throughout normal operation.
7.4.2 Discontinuous Conduction Mode during Soft Start
During soft start, the converter operates in discontinuous conduction mode (DCM) during the first 16 PWM
cycles. During this time, a zero-cross detect comparator is used to turn off the low-side MOSFET when the
current reaches zero amps. This prevents the discharge of any pre-biased conditions on the output. After 16
cycles of DCM, the converter enters FCCM mode.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS543820E is a synchronous buck regulator designed for 4-V to 18-V input and 8-A load. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
8.2 Typical Applications
8.2.1 1.0-V Output, 1-MHz Application
VIN
VIN
CI1
CI2
CHF1
0402
50V
CHF2
0402
50V
CBULK
35V
100uF
0805
25V
10uF
0805
25V
10uF
LO
U2
VIN
XEL5030-601MEC
600nH
0.1uF
0.1uF
VOUT
8
12
10
13
SW
FB
SW
SW
VIN
CBT
RBT
2.2
CO1
0805
10V
CO2
0805
10V
CO3
1210
6.3V
47µF
CO4
1210
6.3V
47µF
7
1
2
3
6
14
4
EN
EN
BOOT
FB
PGND
VIN
Net-Tie
0402
50V
0.1uF
FSEL
MODE
PGOOD
BP5
SYNC/FSEL
MODE
PGOOD
22uF
22uF
VO_SNS
RENT
16.9k
5
AGND
VO_SNS
BODE
RBODE
10.0
9
11
CFF
PGND
PGND
PGND
BP5
Net-Tie
RPG
10k
180pF
TPS543820RPYR-ET
RENB
6.04k
RFSEL RMODE
11.8k 4.87k
RFBT
4.99k
CBP5
0603
2.2µF
10V
PGND
AGND
FB
Note: RBODE for measurement purposes only
RFBB
4.99k
AGND
AGND
图8-1. 12-V Input, 1.0-V Output, 1-MHz Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters shown in 表8-1.
表8-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4.5 to 13.2 V, 12 V nominal
Output voltage (VOUT
Output current rating (IOUT
Switching frequency (fSW
)
1.0 V
8 A
)
)
1000 kHz
10 mV
Steady state output ripple voltage
Output current load step
Transient response
3 A
± 30 mV (± 3%)
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency
The first step is to decide on a switching frequency. The TPS543820E can operate at five different frequencies
from 500 kHz to 2.2 MHz. The fSW is set by the resistor value from the FSEL pin to ground. Typically the highest
switching frequency possible is desired because it produces the smallest solution size. A high switching
frequency allows for smaller inductors and output capacitors compared to a power supply that switches at a
lower frequency. The main tradeoff made with selecting a higher switching frequency is extra switching power
loss, which hurts the efficiency of the regulator.
The maximum switching frequency for a given application can be limited by the minimum on-time of the
regulator. The maximum fSW can be estimated with 方程式4. Using the maximum minimum on-time of 40 ns and
13.2-V maximum input voltage for this application, the maximum switching frequency is 1890 kHz. The selected
switching frequency must also consider the tolerance of the switching frequency. A switching frequency of 1000
kHz was selected for a good balance of solution size and efficiency. To set the frequency to 1000 kHz, the
selected FSEL resistor is 11.8 kΩper 表7-1.
VOUT
V max
IN
1
fSW max =
ì
(
)
tonmin
(4)
图 8-2 shows the maximum recommended input voltage versus output voltage for each FSEL frequency. This
graph uses a minimum on-time of 45 ns and includes the 10% tolerance of the switching frequency. A minimum
on-time of 45 ns is used in this graph to provide margin to the minimum controllable on-time to ensure pulses are
not skipped at no load. At light loads, the dead-time between the low-side MOSFET turning off and high-side
MOSFET turning on contributes to the minimum SW node pulse-width.
图8-2. Maximum Input Voltage vs Output Voltage
In high output voltage applications, the minimum off-time must also be considered when selecting the switching
frequency. When hitting the minimum off-time limits, the operating duty cycle will max out and the output voltage
will begin to drop with the input voltage. 方程式 5 calculates the maximum switching frequency to avoid this limit.
This equation requires the DC resistance of the inductor, RDCR, selected in the following step. A preliminary
estimate of 10 mΩ can be used but this should be recalculated based on the specifications of the inductor
selected. If operating near the maximum fSW limited by the minimum off-time, the increase in resistance at higher
temperature must be considered.
: ; : ;
min F VOUT F IOUT max × kRDCR + RDS ON _HS o
: ;
V
IN
:
;
fSW max =
:
;
:
;
tOFF _MIN max × @V min F IOUT max × kRDS ON _HS F RDS ON _LS oA
:
;
:
;
:
;
IN
(5)
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8.2.1.2.2 Output Inductor Selection
To calculate the value of the output inductor, use 方程式 6. KIND is a ratio that represents the amount of inductor
ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.
Choosing small inductor ripple currents can degrade the transient response performance. The inductor ripple,
KIND, is normally from 0.1 to 0.4 for the majority of applications giving a peak to peak ripple current range of 0.8
A to 3.2 A. The recommended minimum target Iripple is 0.6 A or larger.
For this design example, KIND = 0.2 is used and the inductor value is calculated to be 0.58 µH. An inductor with
an inductance of 0.6 µH is selected. It is important that the RMS (Root Mean Square) current and saturation
current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from 方程式 8
and 方程式 9. For this design, the RMS inductor current is 8 A, and the peak inductor current is 8.8 A. The
chosen inductor is a XEL5030-601. It has a saturation current rating of 22 A, an RMS current rating of 21.4 A,
and a typical DC series resistance of 4.44 mΩ.
The peak current through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in 方程式 9. In transient conditions, the inductor current can increase up to the switch current
limit of the device. For this reason, the most conservative approach is to specify the current ratings of the
inductor based on the switch current limit rather than the steady-state peak inductor current.
Vinmax - Vout
Io ´ Kind
Vout
L1 =
´
Vinmax ´ ¦sw
(6)
(7)
vertical spacer
Vinmax - Vout
Vout
Iripple =
´
L1
Vinmax ´ ¦sw
vertical spacer
ILrms = Io2
æ
ç
è
ö2
÷
1
Vo ´ (Vinmax - Vo)
Vinmax ´ L1 ´ ¦sw
+
´
12
ø
(8)
(9)
vertical spacer
Iripple
2
ILpeak = Iout +
表 8-2 shows recommended E6 standard inductor values for other common output voltages with a 1-MHz fSW
.
Using an inductance outside this recommended range typically works but the performance can be affected and
should be evaluated. The recommended value is calculated for a nominal input voltage of 12 V. The minimum
values are calculated with the maximum input voltage of 18 V. The maximum values are calculated with with an
input voltage of 5-V for all but the 5-V output. For the 5-V output, an 8-V input is used.
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MAXIMUM
表8-2. Recommended Inductor Values
OUTPUT
SWITCHING
MINIMUM
RECOMMENDED
RECOMMENDED
VOLTAGE (V) FREQUENCY (kHz) INDUCTANCE (µH) INDUCTANCE FOR 8 A INDUCTANCE FOR 6 A INDUCTANCE (µH)
(µH)
0.47
0.68
1
(µH)
0.47
1
1
0.33
0.47
0.68
1
1
1.8
3.3
5
1.5
1.5
2.2
1000
1.5
1.5
1.5
8.2.1.2.3 Output Capacitor
There are two primary considerations for selecting the value of the output capacitor: the output voltage ripple
and how the regulator responds to a large change in load current. The output capacitance needs to be selected
based on the more stringent of these criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to
sense the change in the output voltage then adjust the peak switch current in response to the change in load.
The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically the loop
bandwidth is near fSW / 10. 方程式 10 estimates the minimum output capacitance necessary, where ΔIOUT is the
change in output current and ΔVOUT is the allowable change in the output voltage.
For this example, the transient load response is specified as a 3% change in VOUT for a load step of 3 A.
Therefore, ΔIOUT is 3 A and ΔVOUT is 30 mV. Using this target gives a minimum capacitance of 159 μF. This
value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic
capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response.
DIOUT
DVOUT
1
COUT
>
ì
fSW
10
2pì
(10)
In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator
responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down
after a load step down can be the limiting factor. 方程式11 estimates the minimum output capacitance necessary
to limit the change in the output voltage after a load step down. Using the 0.6-µH inductance selected gives a
minimum capacitance of 90 µF.
2
LOUT ì DIOUT
COUT
>
2ì DVOUT ì VOUT
(11)
方程式 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In
this case, the target maximum steady state output voltage ripple is 10 mV. Under this requirement, 方程式 12
yields 19 µF.
1
1
Co >
´
Voripple
8 ´ ¦sw
Iripple
(12)
where
• ΔIOUT is the change in output current
• ΔVOUT is the allowable change in the output voltage
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• fsw is the regulators switching frequency
• Voripple is the maximum allowable steady state output voltage ripple
• Iripple is the inductor ripple current
Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum
amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on
the MODE pin. 方程式 13 estimates the minimum capacitance needed for loop stability. This equation sets the
minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum
value. See 图 8-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 1-V output,
the minimum ratio is 35 and with this ratio, 方程式13 gives a minimum capacitance of 52 µF.
2
≈
∆
«
’
÷
Ratio
1
COUT
>
ì
2pì fSW ◊ LOUT
(13)
方程式 14 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification and this shows the ESR should be less than 6 mΩ. In this case, ceramic capacitors are used
and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple.
Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and
failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data
sheet specifies the RMS value of the maximum ripple current. 方程式15 can be used to calculate the RMS ripple
current the output capacitor needs to support. For this application, 方程式 15 yields 445 mA and ceramic
capacitors typically have a ripple current rating much higher than this.
Voripple
Resr <
Iripple
(14)
vertical spacer
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(15)
Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors since they have a high
capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected
with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic
capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website.
For this application example, two 22-µF, 10-V, X7S, 0805 and two 47-µF, 6.3-V, X7R, 1210 ceramic capacitors
each with 2 mΩ of ESR are used. The two 22-µF capacitors are used since they have a higher resonance
frequency and can help reduce the output ripple caused by parasitic inductance. With the four parallel
capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer's website
is 142 µF. There is almost no DC bias derating at 1 V. This design was able to use less than the calculated
minimum because the loop crossover frequency was above the fSW / 10 estimate as shown in the Load
Transient graph in the Application Curves.
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8.2.1.2.4 Input Capacitor
Input decoupling ceramic capacitors type X5R, X7R, or similar from VIN to PGND that are placed as close as
possible to the IC are required. A total of at least 10 µF of capacitance is required and some applications can
require a bulk capacitance. At least 1 µF of bypass capacitance is recommended as close as possible to each
VIN pin to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed as close as possible to
both VIN pins 8 and 12 on the same side of the board of the device to provide high frequency bypass to reduce
the high frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum RMS input current. The RMS input current can be calculated using 方程式16.
For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the
maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel
have been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the
capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input
voltage of 12 V. A 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top
power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 方程式 17. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using
the nominal design example values of Ioutmax = 8 A, CIN = 5.4 μF, and fSW = 1000 kHz, the input voltage ripple
with the 12 V nominal input is 113 mV and the RMS input ripple current with the 4.5 V minimum input is 3.3 A.
Vinmin - Vout
(
)
Vout
Icirms = Iout ´
´
Vinmin
Vinmin
(16)
vertical spacer
Vout
Vin
Vout
≈
«
’
Ioutmaxì 1-
ì
∆
÷
◊
Vin
DVin =
Cinì fSW
(17)
8.2.1.2.5 Adjustable Undervoltage Lockout
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The
UVLO has two thresholds: one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply is set to turn on and start
switching once the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 3.95 V (UVLO stop or disable). In this example,
these start and stop voltages set by the EN resistor divider were selected to have more hysteresis than the
internally fixed VIN UVLO.
方程式 1 and 方程式 2 can be used to calculate the values for the upper and lower resistor values. For these
equations to work, VSTART must be 1.1 × VSTOP due to the EN pin's voltage hysteresis. For the voltages
specified, the standard resistor value used for RENT is 16.9 kΩ and for RENB is 6.04 kΩ.
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8.2.1.2.6 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by RFBT and RFBB from the output node to the FB pin. It
is recommended to use 1% tolerance or better resistors. For this example design, 4.99 kΩ was selected for
RFBB. Using 方程式18, RFBT is calculated as 4.99 kΩ. This is a standard 1% resistor.
≈
∆
«
’
VOUT
VREF
RFBT = RFBB
ì
-1
÷
◊
(18)
If the PCB layout does not use the recommended AGND to PGND connection in 节 10.1, noise on the feedback
pin can degrade the output voltage regulation at max load. Use a smaller RFBB of 1.00 kΩ minimizes the impact
of this noise.
8.2.1.2.7 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. The
capacitor must be rated for at least 10-V to minimize DC bias derating.
A resistor must be added in series with the BOOT capacitor to slow down the turnon of the high-side MOSFET
and rising edge overshoot on the SW pin for applications with input voltage greater than 13.5 V. This comes with
the trade off of more power loss and lower efficiency. As a best prectice, include a 0-Ω placeholder in all
prototype designs in case parasitic inductance in the PCB layout results in more voltage overshoot at the SW pin
than is normal. This helps keep the voltage within the ratings of the device and reduces the high frequency noise
on the SW node. The recommended BOOT resistor value to decrease the SW pin overshoot is 2.2 Ω.
8.2.1.2.8 BP5 Capacitor Selection
A 2.2-µF ceramic capacitor must be connected between the BP5 pin and AGND for proper operation. The
capacitor must be rated for at least 10 V to minimize DC bias derating.
8.2.1.2.9 PGOOD Pullup Resistor
A 10-kΩ resistor is used to pull up the power good signal when FB conditions are met. The pullup voltage
source must be less than the 6-V absolute maximum of the PGOOD pin.
8.2.1.2.10 Current Limit Selection
The MODE pin is used to select between two current limit settings. Select the current limit setting whose
minimum is greater than at least 1.1 times the maximum steady state peak current. This is to provide margin for
component tolerance and load transients. For this design, the minimum current limit should be greater than 9.64
A so the high current limit setting is selected.
8.2.1.2.11 Soft-Start Time Selection
The MODE pin is used to select between four different soft-start times. This is useful if a load has specific timing
requirements for the output voltage of the regulator. A longer soft-start time is also useful if the output
capacitance is very large and would require large amounts of current to quickly charge the output capacitors to
the output voltage level. The large currents necessary to charge the capacitor can reach the current limit or
cause the input voltage rail to sag due excessive current draw from the input power supply. Limiting the output
voltage slew rate solves both of these problems. The example design has the soft-start time set to 1.0 ms. With
this soft-start time the current required to charge the output capacitors to the nominal output voltage is only 0.14
A.
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8.2.1.2.12 Ramp Selection and Control Loop Stability
The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends
on VOUT, fSW, LOUT, and COUT. To get started, calculate LC double pole frequency using 方程式 19. The ratio
between fSW and fLC should then be calculated. Based on this ratio and the output voltage, the recommended
ramp setting should be selected using 图 8-3. With a 1-V output, the 1-pF ramp is recommended for ratios
between approximately 35 and 58, the 2-pF ramp is recommended for ratios between approximately 58 and 86,
and the 4-pF ramp is recommended for ratios greater than approximately 86. In general, it is best to use the
largest ramp capacitor the design will support. Increasing the ramp capacitor improves transient response but
can reduce stability margin or increase on-time jitter.
For this design, fLC is 17.5 kHz and the ratio is 57 which is on the border of the 1-pF and 2-pF ramp settings.
Through bench evaluation, it was found that the design had sufficient stability margin with the 2-pF ramp so this
setting was selected for the best transient response. The recommended ramp settings given by 图 8-3 include
margin to account for potential component tolerances and variations across operating conditions so it is possible
to use a higher ramp setting as shown in this example.
1
fLC
=
2ì pì LOUT ìCOUT
(19)
5.5
5
4.5
4
4 pF
3.5
3
2 pF
2.5
2
1 pF
1.5
1
0.5
20
30
40
50
60
fSW/fLC
70
80
90
100
图8-3. Recommended Ramp Settings
Use a feedforward capacitor (CFF) in parallel with the upper feedback resistor (RFBT) to add a zero into the
control loop to provide phase boost. Include a placeholder for this capacitor as the zero it provides can be
required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the
zero. The pole and zero frequency are not independent so as a result, once the zero location is chosen, the pole
is fixed as well. The zero is placed at 1/4 the fSW by calculating the value of CFF with 方程式 20. The calculated
value is 128 pF —round this down to the closest standard value of 120 pF.
Using bench measurements of the AC response, the feedforward capacitor for this example design was
increased to 180 pF to improve the transient response.
1
CFF
=
fSW
pìRFBT
ì
2
(20)
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It is possible to use larger feedforward capacitors to further improve the transient response but take care to
ensure there is a minimum of -9-dB gain margin in all operating conditions. The feedforward capacitor injects
noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node.
Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 100-Ω resistor in series
with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB
layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer
together degrading the phase boost the feedforward capacitor provides.
When using higher ESR output capacitors, such as polymer or tantalum, their ESR zero (fESR) should be
accounted for. The ESR zero can be calculated using 方程式 21. If the ESR zero frequency is less than the
estimated bandwidth of 1/10th the fSW, it can affect the gain margin and phase margin. A series R-C from the FB
pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this
design so the effect of the ESR zero is ignored.
1
fESR
=
2ì pìCOUT ìRESR
(21)
8.2.1.2.13 MODE Pin
The MODE resistor is set to 4.87 kΩ to select the high current limit setting, 1.0-ms soft-start and the 2 pF ramp.
See 表7-4 for the full list of the MODE pin settings.
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8.2.1.3 Application Curves
图8-4. Efficiency
图8-5. Load Regulation
60
40
20
0
180
120
60
0
-20
-60
Gain
Phase
-40
-120
1000000
100 200 5001000
10000
Frequency (Hz)
100000
VIN = 12 V
ROUT = 0.3 Ω
图8-6. Line Regulation
图8-7. Bode Plot
EN (2 V/div)
VOUT AC (20 mV/div)
BP5 (5 V/div)
VOUT (500 mV/div)
IOUT (1 A/div)
PGOOD (5 V/div)
Time (400 µs/div)
Time (100 µs/div)
VIN = 12 V
IOUT(DC) = 1.5 A
ISTEP = 3 A at 1A/µs
VIN = 12 V
IOUT = 0 A
图8-8. Load Transient
图8-9. EN Start-up –Measuring BP5
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EN (2 V/div)
EN (2 V/div)
SW (10 V/div)
SW (10 V/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
Time (400 µs/div)
PGOOD (5 V/div)
Time (400 µs/div)
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 0 A
图8-10. EN Startup –Measuring SW
图8-11. EN Shutdown
EN (2 V/div)
EN (2 V/div)
SW (10 V/div)
IOUT (5 A/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (400 µs/div)
Time (400 µs/div)
VIN = 12 V
VIN = 12 V
IOUT = 0 A
ROUT = 0.2 Ω
图8-13. EN Start-up –0.5-V Prebias
图8-12. EN Start-up –With Load
VIN (10 V/div)
VIN (10 V/div)
EN (2 V/div)
EN (2 V/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (400 µs/div)
Time (1 ms/div)
ROUT = 0.3 Ω
ROUT = 0.3 Ω
图8-14. VIN Start-up
图8-15. VIN Shutdown
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VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
Time (1 µs/div)
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 6 A
图8-16. Output Ripple –No Load
图8-17. Output Ripple –6-A Load
VIN AC (10 mV/div)
VIN AC (50 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
Time (1 µs/div)
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 6 A
图8-18. Input Ripple –No Load
图8-19. Input Ripple –6-A Load
VIN = 12 V
VIN = 12 V
图8-20. Overcurrent Protection –Overload
图8-21. Overcurrent Protection –Short
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VIN = 12 V
图8-22. Overcurrent Protection –Hiccup and Recover
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8.2.2 1.0-V Output, 1.5-MHz Application
VIN
VIN
CI1
CI2
CHF1
0402
50V
CHF2
0402
50V
LO
CBULK
35V
100uF
0805
25V
10uF
0805
25V
10uF
XEL4030-471MEB
470nH
U2
VIN
0.1uF
0.1uF
VOUT
8
12
10
13
SW
FB
SW
SW
VIN
CBT
RBT
0
CO1
0805
10V
CO2
0805
10V
7
1
2
3
6
14
4
EN
EN
BOOT
FB
PGND
Net-Tie
0402
50V
0.1uF
FSEL
MODE
PGOOD
BP5
SYNC/FSEL
MODE
PGOOD
47µF
47µF
VO_SNS
5
AGND
VO_SNS
RBODE
10.0
9
11
CFF
PGND
PGND
PGND
BP5
Net-Tie
RPG
10k
470pF
TPS543820RPYR-ET
RFSEL RMODE
8.06k 4.87k
BODE
RFBT
1.00k
CBP5
0603
2.2µF
10V
PGND
AGND
FB
Note: RBODE for measurement purposes only
RFBB
1.00k
AGND
AGND
图8-23. 12-V Input, 1.0-V Output, 1.5-MHz Schematic
8.2.2.1 Design Requirements
表8-3. Design Parameters
PARAMETER
Input voltage range (VIN)
Output voltage (VOUT
Output current rating (IOUT
Switching frequency (fSW
EXAMPLE VALUE
4 to 13.2 V, 12 V nominal
)
1.0 V
8 A
)
)
1500 kHz
10 mV
Steady state output ripple voltage
Output current load step
Transient response
3 A
± 30 mV (± 3%)
8.2.2.2 Detailed Design Procedure
Follow the design procedure in 节8.2.1.2 for selecting the external components in this example application.
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8.2.2.3 Application Curves
VOUT AC (20 mV/div)
IOUT (1 A/div)
Time (40 µs/div)
VIN = 12 V
IOUT(DC) = 1.5 A
ISTEP = 3 A at 1A/µs
图8-25. Load Transient
图8-24. Efficiency
60
40
20
0
180
120
60
0
-20
-60
Gain
Phase
-40
-120
1000000
100 200 5001000
10000
Frequency (Hz)
100000
VIN = 12 V
ROUT = 0.3 Ω
图8-26. Load Regulation
图8-27. Bode Plot
VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
Time (1 µs/div)
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 6 A
图8-28. Output Ripple –No Load
图8-29. Output Ripple –6-A Load
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8.2.3 3.3-V Output, 1.0-MHz Application
VIN
VIN
CI1
CI2
CHF1
0402
50V
CHF2
0402
50V
CBULK
35V
100uF
0805
25V
10uF
0805
25V
10uF
LO
U2
VIN
XEL5050-182MEC
1.8µH
0.1uF
0.1uF
VOUT
8
10
13
SW
FB
SW
SW
12
VIN
CBT
RBT
0
CO1
0805
10V
CO2
0805
10V
7
1
2
3
6
14
4
EN
EN
BOOT
FB
PGND
VIN
Net-Tie
0402
50V
0.1uF
FSEL
MODE
PGOOD
BP5
SYNC/FSEL
MODE
PGOOD
47µF
47µF
VO_SNS
RENT
16.9k
5
AGND
VO_SNS
RBODE
10.0
9
11
CFF
PGND
PGND
PGND
BP5
Net-Tie
RPG
10k
33pF
TPS543820RPYR-ET
RENB
6.04k
RFSEL RMODE
11.8k 174k
BODE
RFBT
28.0k
CBP5
0603
2.2µF
10V
PGND
AGND
FB
Note: RBODE for measurement purposes only
RFBB
4.99k
AGND
AGND
图8-30. 12-V Input, 3.3-V Output, 1.0-MHz Schematic
8.2.3.1 Design Requirements
For this design example, use the parameters shown in 表8-4.
表8-4. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4 to 13.2 V, 12 V nominal
Output voltage (VOUT
Output current rating (IOUT
Switching frequency (fSW
)
3.3 V
6 A
)
)
1000 kHz
10 mV
Steady state output ripple voltage
Output current load step
Transient response
3 A
± 99 mV (± 3%)
8.2.3.2 Detailed Design Procedure
Follow the design procedure in 节8.2.1.2 for selecting the external components in this example application.
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8.2.3.3 Application Curves
100
95
90
85
80
75
70
65
60
VOUT AC (100 mV/div)
IOUT (1 A/div)
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
Time (100 µs/div)
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
5.5
6
VIN = 12 V
IOUT(DC) = 1.5 A ISTEP = 3 A at 1A/µs
图8-32. Load Transient
图8-31. Efficiency
60
40
20
0
180
120
60
0.5
0.4
0.3
0.2
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-20
-60
Gain
Phase
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
-40
-120
1000000
100 200 5001000
10000
Frequency (Hz)
100000
VIN = 12 V
ROUT = 1.1 Ω
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
5.5
6
图8-34. Bode Plot
图8-33. Load Regulation
VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
Time (1 µs/div)
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 6 A
图8-35. Output Ripple –No Load
图8-36. Output Ripple –6-A Load
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9 Power Supply Recommendations
The TPS543820E is designed to operate from an input voltage supply range between 4 V and 18 V. This supply
voltage must be well regulated. Proper bypassing of the input supply is critical for proper electrical performance,
as is the PCB layout and the grounding scheme. A minimum of 4 μF (after derating) ceramic capacitance, type
X5R or better, must be placed near the device. TI recommends splitting the ceramic input capacitance equally
between the VIN and PGND pins on each side of the device resulting in at least 2 µF of ceramic capacitance on
each side of the device.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. See 图 10-1 for a PCB layout example. Key guidelines
to follow for the layout are:
• VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat
dissipation.
• Place a 10-nF to 100-nF capacitor from each VIN to PGND pin and place them as close as possible to the
device on the same side of the PCB. Place the remaining ceramic input capacitance next to these high
frequency bypass capacitors. The remaining input capacitance can be placed on the other side of the board
but use as many vias as possible to minimize impedance between the capacitors and the pins of the IC.
• Use multiple vias near the PGND pins and use the layer directly below the device to connect them together.
This helps to minimize noise and can help heat dissipation.
• Use vias near both VIN pins and provide a low impedance connection between them through an internal
layer.
• Place the inductor as close as possible to the device to minimize the length of the SW node routing.
• Place the BOOT-SW capacitor as close as possible to the BOOT and SW pins.
• Place the BP5 capacitor as close as possible to the BP5 and AGND pins.
• Place the bottom resistor in the FB divider as close as possible to the FB and AGND pins of the IC. Also keep
the upper feedback resistor and the feedforward capacitor near the IC. Connect the FB divider to the output
voltage at the desired point of regulation.
• Use multiple vias in the AGND island to connect it back to internal PGND layers. Do not place these vias
between the BP5 capacitor and the AGND pin. These vias will conduct switching currents between the BP5
capacitor and PGND. Placing the vias near the AGND pin can add noise to the FB divider.
• Return the FSEL and MODE resistors to a quiet AGND island.
10.2 Layout Example
VIN
PGND
0805
0402
0402
0402
0402
0402
MODE
PGOOD
FB
4mm x 4mm
VOUT
AGND
Avoid vias
here
0402
0402
0402
0402
0805
Connect AGND to PGND
near the BP5 cap
VIN
PGND
图10-1. Example PCB Layout
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10.2.1 Thermal Performance
Test Conditions: fSW = 1 MHz, Vin = 12 V, Vout = 1 V, Iout = 8 A, Inductor = 600 nH (4.44 mΩ typ), Ambient
temperature = 25°C
图10-2. Thermal Image at 25°C Ambient
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS543820RPYR-ET
ACTIVE
VQFN-HR
RPY
14
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-55 to 150
3820ET
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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12-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS543820RPYR-ET
VQFN-
HR
RPY
14
3000
180.0
12.4
2.8
3.3
1.1
4.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RPY 14
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS543820RPYR-ET
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPY0014A
3.1
2.9
A
B
PIN 1 IDENTIFICATION
2.6
2.4
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.475
1.275
0.825
2X
0.325
0.625
2X
0.225
(0.1) TYP
2X (0.325)
2X SQ(0.15)
6
8
5
0.9875
9
0.8
0.275
2X
0.175
2X (0.225)
(0.25)
0.5
PKG
0.425
7X
0.325
(0.15)
11
0.75
0.65
0.475
2X
0.275
0.75
4X
0.55
1
14
0.525
12
2X (0.25)
0.45
PIN 1 ID
C0.15
2X
0.325
4X
0.35
0.1
0.3
0.2
C
A B
7X
A
0.4
0.3
0.05
C
2X
0.1
C
B
0.05
C
0.1
0.05
C A B
C
4225171/D 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPY0014A
(1.575)
2X (0.35)
2X (0.925)
2X
2X (0.625)
2X (0.275)
7X
(0.25)
2X (0.575)
(0.4)
14
12
2X (0.85)
2X (0.4)
1
11
2X (0.225)
(0.7)
(0.35)
PKG
(0.2375)
(0.25)
(0.5)
2X (0.225)
9
(0.8)
(0.9875)
(1.025)
(1.1624)
5
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
6
8
2X (0.851)
7X (0.575)
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1-9 & 11-14
PAD 10
SOLDER MASK DETAILS
NOT TO SCALE
4225171/D 08/2022
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RPY0014A
(1.537)
2X (0.35)
2X (0.925)
7X (0.25)
2X
2X (0.625)
2X
(0.35)
(0.225)
2X (0.575)
12
14
2X (0.85)
1
11
2X (0.225)
(0.7)
(0.388)
2X (0.35)
PKG
(0.5)
(0.2375)
(0.25)
2X (0.225)
9
(0.7756)
(0.9875)
(1.025)
(1.1624)
5
EXPOSED METAL
TYP
6
8
2X (0.85)
(R0.05) TYP
7X (0.575)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SOLDER PASTE COVERAGE:
PIN 1 & 5: 93%; PIN 9 &11: 91%; PIN 10: 96%
SCALE: 20X
4225171/D 08/2022
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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