TPS54388CQRTERQ1 [TI]
汽车 2.95V 至 6V、3A、2MHz 同步降压转换器 | RTE | 16 | -40 to 125;
| 型号： | TPS54388CQRTERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车 2.95V 至 6V、3A、2MHz 同步降压转换器 | RTE | 16 | -40 to 125 开关 转换器 |
| 文件： | 总40页 (文件大小：3413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54388C-Q1
ZHCSL73B –OCTOBER 2016 –REVISED JUNE 2021
TPS54388C-Q1 汽车类2.95V 至6V、3A、2MHz 同步降压转换器
TPS54388C-Q1 器件集成了 MOSFET，通过实施电流
模式控制来减少外部组件数量，通过启用高达 2MHz
的开关频率来减小电感器尺寸，并借助小型 3mm x
3mm 热增强型 QFN 封装更大限度减小 IC 尺寸，从而
实现小型设计。
1 特性
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 功能安全型
– 有助于进行功能安全系统设计的文档
• 两个可在3A 负载下获得高效率的12mΩ（典型
值）MOSFET
TPS54388C-Q1 器件可在工作温度范围内以±1% 的精
确电压基准(Vref) 为多种负载提供精确调节。
集成式 12mΩ MOSFET 和 515μA（典型值）的电源
电流，可最大限度提升效率。使用使能引脚进入关断模
式，可将关断电源电流降低至5.5µA（典型值）。
• 200kHz 至2MHz 开关频率
• 在工作温度范围（–40°C 至+150°C）内具有0.8V
± 1% 电压基准
• 与外部时钟同步
内部欠压锁定设置为2.45V，但通过使能引脚上的电阻
器网络对阈值编程，可提高该设置值。缓启动引脚可设
置输出电压启动斜升。一个开漏电源正常信号表示输出
处于其标称电压值的93% 至107% 之内。
• 可调缓启动和排序
• 欠压(UV) 和过压(OV) 电源正常输出
• –40°C 至+150°C 的工作结温范围
• 热增强型3mm × 3mm 16 引脚WQFN 封装
• 与TPS54418 引脚兼容
频率折返和热关断功能负责在过流情况下保护器件。
器件信息(1)
• 推出更新版本产品：TPS62813-Q1 采用具有可湿
性侧面的2mm x 3mm QFN 封装的6V 降压转换器
封装尺寸（标称值）
器件型号
封装
TPS54388C-Q1
WQFN (16)
3.00mm × 3.00mm
2 应用
(1) 有关所有的可用封装，请参阅数据表末尾的可订购产品附录。
• 低电压、高密度电源系统
• 针对高性能DSP、FPGA、ASIC 和微处理器的负
载点调节
• 宽带、网络及光纤通信基础设施
3 说明
TPS54388C-Q1 器件是一款具有两个集成 MOSFET
的全功能6V、3A、同步降压电流模式转换器。
100
C(BOOT)
V(VIN) = 3 V
TPS54388C-Q1
95
V(VIN)
C(I)
VIN
BOOT
V(VIN) = 5 V
90
R4
R5
L(O)
EN
PH
85
VO
C(O)
80
75
R1
R2
PWRGD
VSENSE
70
65
60
SS/TR
RT/CLK
COMP
C(SS)
Rt
GND
AGND
f
= 500 kHz
R3
C1
(SW)
Thermal Pad
55
50
VO = 1.8 V
0
1
2
3
4
5
6
Output Current (A)
简化原理图
效率曲线
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDQ8
TPS54388C-Q1
ZHCSL73B –OCTOBER 2016 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................32
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Documentation Support.......................................... 35
11.2 接收文档更新通知................................................... 35
11.3 支持资源..................................................................35
11.4 Trademarks............................................................. 35
11.5 静电放电警告...........................................................35
11.6 术语表..................................................................... 35
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................13
Information.................................................................... 35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2019) to Revision B (June 2021)
Page
• 向“特性”添加了功能安全要点和新推出的类似产品.........................................................................................1
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
Changes from Revision * (October 2016) to Revision A (December 2019)
Page
• 首次公开发布......................................................................................................................................................1
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English Data Sheet: SLVSDQ8
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5 Pin Configuration and Functions
VIN
VIN
1
2
3
4
12 PH
11 PH
10 PH
Thermal
Pad
GND
GND
9
SS/TR
图5-1. RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
AGND
5
Connect analog ground electrically to GND close to the device.
—
The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor that is
below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor
recharges.
BOOT
13
O
Error amplifier output, and input to the output-switch current comparator. Connect frequency-
compensation components to this pin.
COMP
EN
7
O
I
Enable pin, internal pullup-current source. Pull below 1.2 V to disable. Float to enable. One can use this
pin to set the on-off threshold (adjust UVLO) with two additional resistors.
15
3
GND
PH
Power ground. Directly connect this pin electrically to the thermal pad under the device.
—
4
10
11
12
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET
O
An open-drain output; asserted low if output voltage is low due to thermal shutdown, overcurrent, over-
or undervoltage, or EN shutdown.
PWRGD
RT/CLK
SS/TR
14
8
O
I
Resistor-timing or external-clock input pin
Slow start and tracking. An external capacitor connected to this pin sets the output-voltage rise time.
Another use of this pin is for tracking.
9
I
1
2
VIN
I
Input supply voltage, 2.95 V to 6 V
16
6
VSENSE
I
Inverting node of the transconductance (gm) error amplifier
Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any
internal PCB ground planes using multiple vias for good thermal performance.
Thermal pad
(1) I = input, O = output
—
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English Data Sheet: SLVSDQ8
TPS54388C-Q1
ZHCSL73B –OCTOBER 2016 –REVISED JUNE 2021
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–2
MAX
UNIT
VIN
7
7
EN
BOOT
PH + 7
3
VSENSE
Input voltage
V
COMP
3
PWRGD
SS/TR
7
3
RT/CLK
BOOT-PH
7
7
Output voltage
PH
7
V
PH 10-ns transient
EN
10
100
100
100
10
Source current
Sink current
µA
RT/CLK
COMP
µA
mA
µA
°C
PWRGD
SS/TR
100
150
125
150
Junction temperature, TJ
Ambient temperature, TA
Storage temperature, Tstg
–40
–40
–65
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
Corner pins (1, 16, 4, 5, 8, 9, 12, and 13)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature (unless otherwise noted)
MIN
2.95
–40
NOM
MAX
6
UNIT
V(VIN)
TA
Input voltage
V
Operating ambient temperature
125
°C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDQ8
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6.4 Thermal Information
TPS54388C-Q1
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
43.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.1
15.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.7
ψJT
15.5
ψJB
RθJC(bot)
3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
TJ = –40°C to 150°C, V(VIN) = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN UVLO start
VIN UVLO stop
2.28
2.45
5.5
2.5
V
Internal undervoltage lockout threshold
2.6
Shutdown supply current
Quiescent current, I(q)
15
V(EN) = 0 V, 25°C, 2.95 V ≤V(VIN) ≤6 V
μA
μA
515
750
V(SENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ
ENABLE AND UVLO (EN PIN)
Rising
1.25
1.18
Enable threshold
Input current
V
Falling
Enable threshold + 50 mV
–1.6
–1.6
μA
Enable threshold –50 mV
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
0.79
0.8 0.811
V
2.95 V ≤V(VIN) ≤6 V, –40°C <TJ < 150°C
MOSFET
V(BOOT-PH) = 5 V
V(BOOT-PH) = 2.95 V
V(VIN) = 5 V
12
16
13
17
30
30
30
30
High-side switch resistance
Low-side switch resistance
mΩ
mΩ
V(VIN) = 2.95 V
ERROR AMPLIFIER
Input current
2
nA
Error-amplifier transconductance (gm)
245
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
μS
Error-amplifier transconductance (gm) during
slow start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
V(VSENSE) = 0.4 V
79
μS
Error amplifier source and sink
V(COMP) = 1 V, 100-mV overdrive
±20
25
μA
COMP to high-side FET current gm
S
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TJ = –40°C to 150°C, V(VIN) = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT LIMIT
Current limit threshold
3.7
6.5
A
THERMAL SHUTDOWN
Thermal shutdown
168
20
°C
°C
Hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
200
400
300
75
2000
600
kHz
kHz
kHz
ns
Switching frequency
500
Rt = 400 kΩ
Switching frequency range using CLK mode
Minimum CLK pulse duration
RT/CLK voltage
2000
0.5
1.6
0.6
V
Rt = 400 kΩ
RT/CLK high threshold
2.5
V
RT/CLK low threshold
0.4
V
Delay from RT/CLK falling edge to PH rising
edge
Measure at 500 kHz with RT resistor in series with
device pin
90
45
ns
PLL lock-in time
Measure at 500 kHz
μs
PH (PH PIN)
Measured at 50% point on PH, IO = 3 A
75
Minimum on-time
ns
Measured at 50% point on PH, V(VIN) = 6 V,
IO = 0 A
120
Prior to skipping off pulses, BOOT-PH = 2.95 V,
IO = 3 A
Minimum off-time
60
ns
Rise time
V(VIN) = 6 V, 6 A
V(VIN) = 6 V, 6 A
2.25
2
V/ns
Fall time
BOOT (BOOT PIN)
BOOT charge resistance
BOOT-PH UVLO
V(VIN) = 5 V
16
Ω
V(VIN) = 2.95 V
2.1
V
SLOW START AND TRACKING (SS/TR PIN)
Charge current
V(SS/TR) = 0.4 V
2
50
μA
mV
V
SS/TR to VSENSE matching
SS/TR to reference crossover
SS/TR discharge voltage (overload)
SS/TR discharge current (overload)
V(SS/TR) = 0.4 V
98% of normal reference voltage
V(VSENSE) = 0 V
1.1
61
mV
µA
V(VSENSE) = 0 V, V(SS/TR) = 0.4 V
350
SS discharge current (UVLO, EN, thermal
fault)
V(VIN) = 5 V, V(SS/TR) = 0.5 V
1.9
mA
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault)
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling (Good)
VSENSE falling
91
93
VSENSE threshold
% Vref
109
107
2
Hysteresis
% Vref
nA
Output-high leakage
On-resistance
V(VSENSE) = Vref, V(PWRGD) = 5.5 V
7
56
100
1.6
Ω
Output low
I(PWRGD) = 3 mA
0.3
0.65
V
Minimum VIN for valid output
V
V(PWRGD) < 0.5 V at 100 μA
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English Data Sheet: SLVSDQ8
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6.6 Typical Characteristics
525
520
515
510
505
500
495
490
485
0.025
0.023
High-Side rDS(on), V(VIN) = 3.3 V
Low-Side rDS(on), V(VIN) = 3.3 V
0.021
0.019
0.017
0.015
0.013
0.011
0.009
0.007
0.005
High-Side rDS(on), V(VIN) = 5 V
Low-Side rDS(on), V(VIN) = 5 V
480
475
–50
–25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 5 V
Rt = 400 kΩ
图6-1. High-Side and Low-Side rDS(on) vs
Temperature
图6-2. Frequency vs Temperature
8
0.807
7.5
0.805
0.803
0.801
0.799
0.797
0.795
0.793
0.791
V
= 3.3 V
7
6.5
6
(VIN)
5.5
5
V
= 5 V
(VIN)
4.5
4
3.5
3
–50
–25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
图6-3. High-Side Current Limit vs Temperature
图6-4. Voltage Reference vs Temperature
2000
1800
1600
1400
1200
1000
800
100
V(VSENSE) Falling
75
V(VSENSE) Rising
50
25
0
600
400
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V(VSENSE) (V)
200
80
180
380
480
580
680
780
880
980
280
Resistance (kΩ)
图6-6. Switching Frequency vs V(VSENSE)
图6-5. Switching Frequency vs RT Resistance,
Low-Frequency Range
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105
100
95
310
290
270
250
230
210
90
85
80
75
70
65
190
170
60
55
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
V(VIN) = 3.3 V
图6-8. Transconductance (Slow Start) vs Junction
图6-7. Transconductance vs Temperature
Temperature
1.3
1.29
1.28
–3
–3.1
–3.2
–3.3
–3.4
–3.5
–3.6
–3.7
–3.8
V(VIN) = 3.3 V, rising
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
V(VIN) = 3.3 V, falling
1.19
1.18
1.17
1.16
1.15
–3.9
–4
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
图6-9. EN Pin Voltage vs Temperature
V(VIN) = 5 V
V(EN) = Threshold + 50 mV
图6-10. EN Pin Current vs Temperature
–1
–1.4
–1.2
–1.4
–1.6
–1.8
–2
–1.6
–1.8
–2
–2.2
–2.4
–2.6
–2.2
–2.4
–2.6
–2.8
–3
–2.8
–3
–50
–25
0
25
50
75
100
125
150
–50 –30
–10 10
30
50
70
90
110
130 150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 5 V
V(VIN) = 5 V
V(EN) = Threshold –50 mV
图6-12. Charge Current vs Temperature
图6-11. EN Pin Current vs Temperature
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2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
8
7
6
5
4
3
2
UVLO Start Switching
UVLO Stop Switching
1
0
2
-50
-25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
图6-13. Input Voltage vs Temperature
图6-14. Shutdown Supply Current vs Temperature
8
800
7
6
5
4
3
2
700
600
500
400
300
200
1
0
3
3.5
4
4.5
5
5.5
6
–50
–25
0
25
50
75
100
125
150
Input Voltage (V)
Junction Temperature (°C)
TJ = 25°C
V(VIN) = 3.3 V
图6-15. Shutdown Supply Current vs Input Voltage
图6-16. VIN Supply Current vs Junction
Temperature
800
700
600
500
400
110
108
106
104
102
100
98
V(VSENSE) Rising,
V(VSENSE) Falling,
PWRGD Asserted
PWRGD Deasserted
V(VSENSE) Rising,
PWRGD Asserted
V(VSENSE) Falling,
96
PWRGD Deasserted
94
92
300
200
90
88
–50
–25
0
25
50
75
100
125
150
–50 –25
0
25
50
75
Junction Temperature (°C)
100
125
150
Junction Temperature (°C)
TJ = 25°C
V(VIN) = 5 V
图6-17. VIN Supply Current vs Input Voltage
图6-18. PWRGD Threshold vs Temperature
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100
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
10
0
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
V(VIN) = 5 V V(SS/TR) = 0.4 V
Junction Temperature (°C)
V(VIN) = 5 V
图6-20. SS/TR-to-VSENSE Offset vs Temperature
图6-19. PWRGD On-Resistance vs Temperature
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7 Detailed Description
7.1 Overview
The TPS54388C-Q1 device is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-
channel MOSFETs. To improve performance during line and load transients, the device implements a constant-
frequency, peak-current-mode control, which reduces output capacitance and simplifies external frequency-
compensation design. The wide switching-frequency range of 200 kHz to 2000 kHz allows for efficiency and size
optimization when selecting the output-filter components. A resistor to ground on the RT/CLK pin sets the
switching frequency. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the
power-switch turnon to a falling edge of an external system clock.
The TPS54388C-Q1 device has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup
current source that one can use to adjust the input-voltage undervoltage lockout (UVLO) with two external
resistors. In addition, the pullup current provides a default condition, allowing the device to operate when the EN
pin is floating. The total operating current for the device is typically 515 μA when not switching and under no
load. With the device disabled, the supply current is typically 5.5 μA.
The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents
up to 3 A.
The TPS54388C-Q1 device reduces the external component count by integrating the boot recharge diode. A
capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A
UVLO circuit monitors the boot-capacitor voltage and turns off the high-side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54388C-Q1 device to operate approaching 100%
duty cycle. The lower limit for stepping down the output voltage is the 0.8-V reference.
The TPS54388C-Q1 device has a power-good comparator (PWRGD) with 2% hysteresis.
The TPS54388C-Q1 device minimizes excessive output overvoltage transients by taking advantage of the
overvoltage power-good comparator. A regulated output voltage exceeding 109% of the nominal voltage
activates the overvoltage comparator, turning off the high-side MOSFET and masking it from turning on until the
output voltage is lower than 107% of the nominal voltage.
A use of the SS/TR (slow start pr tracking) pin is to minimize inrush currents or provide power-supply sequencing
during power up. Couple a small-value capacitor to the pin for slow start. Discharging the SS/TR pin before the
output powers up ensures a repeatable restart after an overtemperature fault, UVLO fault, or disabled condition.
The use of a frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault
conditions to help limit the inductor current.
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7.2 Functional Block Diagram
PWRGD
EN
VIN
i(1)
i(hys)
Shutdown
Thermal
Shutdown
UVLO
Enable
Comparator
91%
Logic
Shutdown
Shutdown
Logic
109%
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
COMP Clamp
Current
Sense
Error
Amplifier
PWM
Comparator
VSENSE
SS/TR
BOOT
Logic and PWM
Latch
Shutdown
Logic
Slope
Compensation
S
PH
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
With PLL
GND
TPS54388C-Q1 Block Diagram
RT/CLK
AGND
Thermal Pad
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54388C-Q1 device uses an adjustable fixed-frequency, peak-current-mode control. An error amplifier,
which drives the COMP pin, compares the output voltage through external resistors on the VSENSE pin to an
internal voltage reference. An internal oscillator initiates the turnon of the high-side power switch. The device
compares the error-amplifier output to the high-side power-switch current. When the sensed voltage derived
from the power-switch current reaches the COMP voltage level, the high-side power switch turns off and the low-
side power switch turns on. The COMP pin voltage increases and decreases as the output current increases and
decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level, and
also implements a minimum clamp for improved transient-response performance.
7.3.2 Slope Compensation and Output Current
The TPS54388C-Q1 device adds a compensating ramp to the switch-current signal. This slope compensation
prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains
constant over the full duty-cycle range.
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7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
The TPS54388C-Q1 device has an integrated boot regulator and requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic
capacitor should be 0.1 μF. TI recommends a ceramic capacitor with an X7R- or X5R-grade dielectric with a
voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage.
The TPS54388C-Q1 design improves dropout by operating at 100% duty cycle as long as the BOOT-to-PH pin
voltage is greater than 2.2 V. A UVLO circuit turns off the high-side MOSFET, allowing for the low-side MOSFET
to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the
BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh
the capacitor. Thus, the effective duty cycle of the switching regulator is high.
7.3.4 Error Amplifier
The TPS54388C-Q1 device has a transconductance amplifier that it uses as an error amplifier. The error
amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage
reference. The transconductance of the error amplifier is 245 μS during normal operation. When the voltage of
VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is typically greater than
79 μS, but less than 245 μS.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable band-gap circuit. The band-gap and scaling circuits produce 0.8 V at the non-inverting
input of the error amplifier.
7.4 Device Functional Modes
7.4.1 Adjusting the Output Voltage
A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using divider
resistors with 1% tolerance or better. Start with 100 kΩ for the R1 resistor and use 方程式 1 to calculate R2. To
improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is
more susceptible to noise, and voltage errors from the VSENSE input current are noticeable.
æ
ç
è
ö
÷
ø
0.8 V
R2 = R1´
VO - 0.8 V
(1)
TPS54388C-Q1
V
O
R1
R2
VSENSE
-
0.8 V
+
图7-1. Voltage-Divider Circuit
7.4.2 Enable Functionality and Adjusting Undervoltage Lockout
The VIN pin voltage on the VIN pin falling below 2.6 V disables the TPS54388C-Q1 device. If an application
requires a higher undervoltage lockout (UVLO), use the EN pin as shown in 图 7-2 to adjust the input voltage
UVLO by using two external resistors. TI recommends using the EN resistors to set the UVLO falling threshold
(V(STOP)) above 2.6 V. Set the rising threshold (V(START)) to provide enough hysteresis to allow for any input
supply variations. The EN pin has an internal pullup current source that provides the default condition of
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TPS54388C-Q1 operation when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, the circuitry adds an
additional 1.6 μA of hysteresis. Pulling the EN pin below 1.18 V removes the 1.6 μA. This additional current
facilitates input voltage hysteresis.
TPS54388C-Q1
I
hys
VIN
1.6 mA
I
1
R1
R2
1.6 mA
+
EN
-
图7-2. Adjustable Undervoltage Lockout
æ
ç
ç
è
ö
÷
÷
ø
V
(ENFALLING)
V
- V
(STOP)
(START)
V
(ENRISING)
R1 =
æ
ç
(1) ç
è
ö
÷
÷
ø
V
(ENFALLING)
I
1-
+ I
(hys)
V
(ENRISING)
(2)
where
• V(ENFALLING) = 1.18 V
• V(ENRISING) = 1.25 V
• I(1) = 1.6 µA
• I(hys) = 1.6 µA
R1´ V
(ENFALLING)
R2 =
V
(STOP) - V(ENFALLING) + R1´(I(1) + I(hys)
)
(3)
7.4.3 Slow-Start or Tracking Pin
The TPS54388C-Q1 device regulates to the lower of the SS/TR pin and the internal reference voltage. A
capacitor on the SS/TR pin to ground implements a slow-start time. The TPS54388C-Q1 device has an internal
pullup current source of 2 μA, which charges the external slow-start capacitor. 方程式 4 calculates the required
slow-start capacitor value, where t(SS/TR) is the desired slow start time in ms, I(SS/TR) is the internal slow start
charging current of 2 μA, and Vref is the internal voltage reference of 0.8 V.
t(SS/TR) (ms) ´ I(SS/TR) (mA)
C(SS/TR) (nF) =
V
(V)
ref
(4)
If during normal operation, VIN goes below UVLO, the EN pin goes below 1.2 V, or a thermal shutdown event
occurs, the TPS54388C-Q1 device stops switching. On VIN going above UVLO, the release or pulling high of
EN, or exit from a thermal shutdown, SS/TR discharges to below 60 mV before re-initiation of a power-up
sequence. The VSENSE voltage follows the SS/TR pin voltage with a 50-mV offset up to 85% of the internal
voltage reference. When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
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7.4.4 Sequencing
One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD
pins. Implementation of the sequential method uses an open-drain or open-collector output of the power-on-
reset pin of another device. 图 7-3 shows the sequential method. Couple the power-good to the EN pin on the
TPS54388C-Q1 device to enable the second power supply once the primary supply reaches regulation.
One can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up
and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in
方程式4. 图7-5 shows the ratiometric method.
TPS54388C-Q1
PWRGD
EN
EN
EN1
SS/TR
SS/TR
EN2
PWRGD
VO(1)
图7-3. Sequential Start-Up Sequence
VO(2)
图7-4. Sequential Start-Up Using EN and PWRGD
TPS54388C-Q1
EN1
SS/TR1
EN
PWRGD1
SS
TPS54388C-Q1
VO(1)
EN2
VO(2)
SS/TR2
PWRGD2
图7-6. Ratiometric Start-Up With VO(1) Leading
图7-5. Schematic for Ratiometric Start-Up
VO(2)
Sequence
One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network
of R1 and R2 shown in 图 7-7 to the output of the power supply that requires tracking, or to another voltage
reference source. Using 方程式 5 and 方程式 6, one can calculate the tracking resistors to initiate VO(2) slightly
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before, after, or at the same time as VO(1). VO(1) – VO(2) is 0 V for simultaneous sequencing. Including V(ssoffset)
and I(SS/TR) as variables in the equations minimizes the effect of the inherent SS/TR-to-VSENSE offset (V(ssoffset)
)
in the slow-start circuit and the offset created by the pullup current source (I(ss)) and tracking resistors. Because
the SS/TR pin requires pulling below 60 mV before starting after an EN, UVLO, or thermal-shutdown fault, select
the tracking resistors carefully to ensure the device can restart after a fault. Make sure the calculated R1 value
from 方程式 5 is greater than the value calculated in 方程式 7 to ensure the device can recover from a fault. As
the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(ssoffset) becomes larger as the
slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in 图7-6.
VO(1)
V
(ssoffset)
R1 =
´
V
I(SS/TR)
ref
(5)
V
´ R1
ref
R2 =
VO(1) - V
ref
(6)
(7)
R1 > 2930´ VO(1) - 145 ´ (VO(1) - VO(2)
)
TPS54388C-Q1
BOOT1
EN1
PH1
EN1
SS2
VO(1)
SS/TR1
PWRGD1
VO(1)
VO(2)
TPS54388C-Q1
BOOT2
R1
R2
EN2
PH2
VO(2)
SS/TR2
VSENSE2
PWRGD2
图7-8. Ratiometric Start-Up Using Coupled SS/TR
Pins
图7-7. Ratiometric and Simultaneous Start-Up
Sequence
7.4.5 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54388C-Q1 device is adjustable over a wide range from 200 kHz to 2000
kHz by placing a resistor on the RT/CLK pin with a value calculated by 方程式 8. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The voltage on
RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use 方程式8 or the
curve in 图6-5.
247 530 (MW/s)
1.0533
Rt kW =
( )
f(SW)
kHz
(
)
(8)
(9)
131 904 (MW/s)
0.9492
f
kHz =
( )
(SW)
Rt
kW
( )
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To reduce the solution size, one would typically set the switching frequency as high as possible, but consider
tradeoffs of the efficiency, maximum input voltage, and minimum controllable on-time.
The minimum controllable on-time is typically 60 ns at full-current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
7.4.6 Overcurrent Protection
The TPS54388C-Q1 device implements a cycle-by-cycle current limit. During each switching cycle, the device
compares a voltage derived from the high-side switch current to the voltage on the COMP pin. When the
instantaneous switch-current voltage intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin
high, increasing the switch current. An internal clamp on the error-amplifier output functions as a switch-current
limit.
7.4.7 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54388C-
Q1 device implements a frequency shift. Without this frequency shift, during an overcurrent condition the low-
side MOSFET might not turn off long enough to reduce the current in the inductor, causing a current runaway.
With frequency shift, during an overcurrent condition there is a switching-frequency reduction from 100% to 50%,
then 25%, as the voltage decreases from 0.8 V to 0 V on the VSENSE pin. The frequency shift allows the low-
side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching
frequency increases as the voltage on VSENSE increases from 0 V to 0.8 V. See 图6-6 for details.
7.4.8 Reverse Overcurrent Protection
The TPS54388C-Q1 device implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
7.4.9 Synchronize Using the RT/CLK Pin
The RT/CLK pin synchronizes the converter to an external system clock. See 图 7-9. To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns.
If the square wave pulls the pin above the PLL upper threshold, a mode change occurs, and the pin becomes a
synchronization input. The CLK mode disables the internal amplifier, and the pin becomes a high-impedance
clock input to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the mode
returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6
V and higher than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge
of PH synchronizes to the falling edge of the RT/CLK pin.
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TPS54388C-Q1
SYNC Clock = 2 V/div
RT/CLK
PLL
PH = 2 V/div
Clock
Source
Rt
图7-9. Synchronizing to a System Clock
Time = 500 ns/div
图7-10. Plot of Synchronizing to a System Clock
7.4.10 Power Good (PWRGD Pin)
The output of the PWRGD pin is an open-drain MOSFET. The output goes low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends
using a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. PWRGD is
in a valid state once the VIN input voltage is greater than 1.1 V.
7.4.11 Overvoltage Transient Protection
The TPS54388C-Q1 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold,
which is 109% of the internal voltage reference. If the VSENSE pin voltage goes higher than the OVTP
threshold, the high-side MOSFET turns off, preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET turns on in
the next clock cycle.
7.4.12 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 148°C, the device reinitiates the power-up sequence
by discharging the SS/TR pin to below 60 mV. The thermal shutdown hysteresis is 20°C.
7.4.13 Small-Signal Model for Loop Response
图 7-11 shows an equivalent model for the TPS54388C-Q1 control loop, which one can model in a circuit-
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μS. One can model the error amplifier using an ideal voltage-
controlled current source. The resistor R0 and capacitor C0 model the open-loop gain and frequency response
of the amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the
frequency-response measurements. Plotting a over c vs frequency shows the small-signal response of the
frequency compensation. Plotting a over b vs frequency shows the small-signal response of the overall loop.
Check the dynamic loop response by replacing R(L) with a current source that has the appropriate load-step
amplitude and step rate in a time-domain analysis.
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PH
VO
Power Stage
25 S
a
b
R(ESR)
R1
R(L)
COMP
c
VSENSE
0.8 V
C(OUT)
R3
C1
C0
gm
245 µS
R0
C2
R2
图7-11. Small-Signal Model for Loop Response
7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
图 7-11 is a simple small-signal model that one can use to understand how to design the frequency
compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output
capacitor and load resistor approximates the TPS54388C-Q1 power stage. 方程式 10 shows the control-to-
output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current divided by the change in COMP pin voltage (node c in 图 7-11) is the power-stage
transconductance. The gm for the TPS54388C-Q1 device is 25 S. The low-frequency gain of the power-stage
frequency response is the product of the transconductance and the load resistance as shown in 方程式 11. As
the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with load may seem problematic at first glance, but the dominant pole moves with load current (see 方
程式 12). The dashed line in the right half of 图 7-12 highlights the combined effect. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for varying load conditions, which makes it easier to design the frequency compensation.
VO
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
图7-12. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
ö
s
1+
1+
ç
ç
è
÷
÷
ø
2p × f(z)
VO
= A(dc)
´
V
æ
ç
ç
è
ö
÷
÷
ø
(C)
s
2p × f(p)
(10)
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A(dc) = gm(ps) ´ R(L)
(11)
1
f(p)
=
C
(OUT) ´ R(L) ´ 2p
(12)
(13)
1
f(z)
=
C
(OUT) ´ R(ESR) ´ 2p
7.4.15 Small-Signal Model for Frequency Compensation
The TPS54388C-Q1 device uses a transconductance amplifier for the error amplifier and readily supports two of
the commonly used frequency-compensation circuits. 图 7-13 shows the compensation circuits. The most-likely
implementation of Type 2B circuits is in high-bandwidth power-supply designs using low-ESR output capacitors.
Type 2A contains one additional high-frequency pole to attenuate high-frequency noise.
VO
R1
VSENSE
Type 2A
Type 2B
COMP
gm
ea
CO
Vref
R3
C1
C2
R3
RO
R2
5pF
C1
图7-13. Types of Frequency Compensation
The design guidelines for TPS54388C-Q1 loop compensation are as follows:
1. Calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using 方程式14 and 方程式15. The output
capacitor (C(OUT)) may require derating if the output voltage is a high percentage of the capacitor rating. Use
the manufacturer information for the capacitor to derate the capacitor value. Use 方程式16 and 方程式17 to
estimate a starting point for the crossover frequency, f(c). 方程式16 is the geometric mean of the modulator
pole and the ESR zero, and 方程式17 is the mean of the modulator pole and the switching frequency. Use
the lower value of 方程式16 or 方程式17 as the maximum crossover frequency.
IO(max)
f(p,mod)
=
2p´ VO ´ C(OUT)
(14)
1
f(z,mod)
=
2p´R(ESR) ´ C(OUT)
(15)
(16)
f(c)
=
f
(p,mod) ´ f(z,mod)
f(SW)
f(c)
=
f(p,mod)
´
2
(17)
(18)
2. Determine R3 using 方程式18.
2p´ f(c) ´ VO ´ C(OUT)
R3 =
g
m(ea) ´ V ´ gm(ps)
ref
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where
• gm(ea) is the amplifier gain (245 μS)
• gm(ps) is the power-stage gain (25 S)
3. Place a compensation zero at the dominant pole:
1
f(p)
=
C
(OUT) ´ R(L) ´ 2p
(19)
(20)
4. Determine C1 using 方程式20.
R
(L) ´ C(OUT)
C1 =
R3
vertical spacer
5. C2 is optional. Use it, if necessary, to cancel the zero from the ESR of C(OUT)
.
R
(ESR) ´ C(OUT)
C2 =
R3
(21)
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
Details on how to use this device in automotive applications appear throughout this device specification. The
following sections provide the typical application use case with equations and methods on selecting the external
components, as well as layout guidelines.
8.2 Typical Application
TPS54388C-Q1
图8-1. High-Frequency, 1.8-V Output Power-Supply Design With Adjusted UVLO
8.2.1 Design Requirements
This example details the design of a high-frequency switching-regulator design using ceramic output capacitors.
To start the design process, it is necessary to know a few parameters. Determination of these parameters is
typically at the system level. For this example, start with the following known parameters:
表8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage
1.8 V
Transient response, 1-A to 2-A load step
Maximum output current
Input voltage
ΔV(out) = 5%
3 A
5 V nominal, 3 V to 5 V
< 30 mV p-p
1000 kHz
Output-voltage ripple
Switching frequency, f(sw)
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8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, one would choose the highest
switching frequency possible to produce the smallest solution size. The high switching frequency allows for
lower-valued inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter
performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an
ultimate goal, select a moderate switching frequency of 1 MHz to achieve both a small solution size and high-
efficiency operation. Using 方程式 8, calculate R5 to be 180 kΩ. Choose a standard 1% 182-kΩ value for the
design.
8.2.2.2 Output Inductor Selection
The inductor selected works for the entire TPS54388C-Q1 input-voltage range. To calculate the value of the
output inductor, use 方程式 22. The k(IND) coefficient represents the amount of inductor ripple current relative to
the maximum output current. The output capacitor filters the inductor ripple current. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a
ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, k(IND) is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use k(IND) = 0.3, and the inductor value calculates to be 1.36 μH. For this design,
choose the nearest standard value of 1.5 μH. For the output-filter inductor, it is important not to exceed the rms-
current and saturation-current ratings. Find the rms and peak inductor current using 方程式24 and 方程式25.
For this design, the rms inductor current is 3.01 A and the peak inductor current is 3.72 A. The chosen inductor
is a Coilcraft XLA4020-152ME_ or equivalent. It has a saturation current rating 0f 9.6 A and an RMS current
rating of 7.5 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch-current limit rather than the peak inductor current.
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VI(max) - VO
VO
L1 =
´
I
O ´ k(IND)
V
I(max) ´ f(SW)
(22)
(23)
VI(max) - VO
VO
I(ripple)
=
´
L1
V
I(max) ´ f(SW)
æ
ö2
÷
÷
ø
VO ´ (VI(max) - VO )
VI(max) ´ L1 ´ f(SW)
1
2
I(Lrms)
=
IO
+
´ ç
ç
è
12
(24)
(25)
I(ripple)
I(Lpeak) = IO +
8.2.2.3 Output Capacitor
2
Three primary considerations must be considered for selecting the value of the output capacitor. The output
capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large
change in load current. Base the output-capacitance selection on the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for
the regulator where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after removal of the input power. The regulator is temporarily not able to supply sufficient output
current if there is a large, fast increase in the current requirement of the load, such as transitioning from no load
to a full load. The regulator usually requires two or more clock cycles for the control loop to see the change in
load current and output voltage and then adjust the duty cycle to react to the change. The output capacitor must
be large enough to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for two clock cycles while only
allowing a tolerable amount of droop in the output voltage. 方程式 26 shows the minimum output capacitance
necessary to meet this requirement.
For this example, the specification for transient-load response is a 5% change in VO for a load step from 0 A (no
load) to 1.5 A (50% load). For this example, ΔIO = 1.5 A –0 A = 1.5 A and ΔVO = 0.05 × 1.8 V = 0.09 V. Using
these numbers gives a minimum capacitance of 33 μF. This value does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation.
方程式 27 calculates the minimum output capacitance needed to meet the output-voltage ripple specification. In
this case, the maximum output-voltage ripple is 30 mV. Under this requirement, 方程式27 yields 2.3 µF.
2 ´ DIO
C(OUT)
>
f
(SW) ´ DVO
(26)
where
• ΔIO is the change in output current
• f(SW) is the regulator switching frequency
• ΔVO is the allowable change in the output voltage
1
1
C(OUT)
>
´
VO(ripple)
8´ f(SW)
I(ripple)
(27)
where
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• f(SW) is the switching frequency
• VO(ripple) is the maximum allowable output voltage ripple
• I(ripple) is the inductor ripple current
Use 方程式 28 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. 方程式 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Factoring in additional capacitance deratings for aging, temperature, and dc bias increases this minimum value.
For this example, use two 22-μF, 10-V X5R ceramic capacitors with 3 mΩ of ESR.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. Select an output capacitor that can support the inductor ripple current. Some capacitor data sheets
specify the root-mean-square (rms) value of the maximum ripple current. Use 方程式 29 to calculate the rms
ripple current that the output capacitor must support. For this application, 方程式29 yields 333 mA.
VO(ripple)
R(ESR)
<
I(ripple)
(28)
(29)
VO ´ (VI(max) - VO )
12 ´ VI(max) ´ L1 ´ f(SW)
I(Co,rms)
=
8.2.2.4 Input Capacitor
The TPS54388C-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at
least 4.7 μF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance
includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of
the TPS54388C-Q1 device. Calculate the input ripple current using 方程式30.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. Minimize the capacitance variations due to temperature by selecting a dielectric material that is stable
over temperature. X5R and X7R ceramic dielectrics are the usual selection for power regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output-
capacitor selection must also take dc bias into account. The capacitance value of a capacitor decreases as the
dc bias across that capacitor increases.
This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum
input voltage. For this example, the selection is one 10-μF 10-V and one 0.1-μF 10-V capacitor in parallel. The
input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple
using 方程式 31. Using the design example values, IO(max) = 3 A, C(IN) = 10 μF, and f(SW) = 1 MHz, yields an
input voltage ripple of 76 mV and an rms input ripple current of 1.47 A.
V
(
- VO
)
VO
I(min)
I(Ci,rms) = IO
´
´
VI(min)
VI(min)
(30)
(31)
I
O(max) ´ 0.25
DVI =
C(IN) ´ f(SW)
8.2.2.5 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. Slow start is useful if a load requires a controlled rate of voltage
slew. Another use for slow start is if the output capacitance is large and would require large amounts of current
to charge the capacitor quickly to the output-voltage level. The large current necessary to charge the capacitor
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may make the TPS54388C-Q1 device reach the current limit, or excessive current draw from the input power
supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these
problems.
Calculate the slow-start capacitor value using 方程式 32. For the example circuit, the slow-start time is not too
critical because the output-capacitor value is 44 μF, which does not require much current to charge to 1.8 V.
The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10-nF capacitor. In
the TPS54388C-Q1 device, I(SS/TR) is 2.2 μA and Vref is 0.8 V.
t(SS) (ms) ´ I(SS/TR) (mA)
C(SS) (nF) =
V
(V)
ref
(32)
8.2.2.6 Bootstrap Capacitor Selection
Connect a 0.1-μF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends
using a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher
voltage rating.
8.2.2.7 Output-Voltage and Feedback-Resistor Selection
For the example design, the R6 selection is 100 kΩ. Using 方程式 33, calculate R7 as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
V
ref
R7 =
´ R6
VO - V
ref
(33)
Because of the internal design of the TPS54388C-Q1 device, there is a minimum output-voltage limit for any
given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above
0.8 V, an output voltage limit may exist due to the minimum controllable on-time. In this case, 方程式 34 gives
the minimum output voltage:
V
O(min) = t(ONmin) ´ f(SWmax) ´ VI(max) - IO(min) ´ 2´ rDS(on) - I
(
´ R(L) + rDS(on)
O(min)
)
(
)
(34)
where
• VO(min) = minimum achievable output voltage
• t(ONmin) = minimum controllable on-time (65 ns typical, 120 ns with no load)
• f(SWmax) = maximum switching frequency, including tolerance
• VI(max) = maximum input voltage
• IO(min) = minimum load current
• rDS(on) = minimum high-side MOSFET on-resistance (15 mΩ–19 mΩ)
• R(L) = series resistance of output inductor
There is also a maximum achievable output voltage, which is limited by the minimum off-time. 方程式 35 gives
the maximum output voltage.
VO(max) = 1- t(OFFmax) ´ f(SWmax) ´ V
(
- IO(max) ´ 2´rDS(on) - I
)
´ R(L) + rDS(on)
O(max)
) ( I(min)
(
)
(35)
where
• VO(max) = maximum achievable output voltage
• t(OFFmax) = maximum off-time (60 ns, typical)
• f(SWmax) = maximum switching frequency, including tolerance
• VI(min) = minimum input voltage
• IO(max) = maximum load current
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• rDS(on) = maximum high-side MOSFET on-resistance (19 mΩ–30 mΩ)
• R(L) = series resistance of output inductor
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8.2.2.8 Compensation
The industry uses several techniques to compensate dc-dc regulators. The method presented here is easy to
calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and
90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS54388C-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is
usually lower than the crossover frequency used in the calculations.
To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using 方程式 36 and 方程式 37.
For C(OUT), derating the capacitor is not necessary, as the 1.8-V output is a small percentage of the 10-V
capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for
the capacitor to derate the capacitor value. Use 方程式 38 and 方程式 39 to estimate a starting point for the
crossover frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. 方程式 38 is the
geometric mean of the modulator pole and the ESR zero, and 方程式 39 is the mean of the modulator pole and
the switching frequency. 方程式 38 yields 85.3 kHz and 方程式 39 gives 54.9 kHz. Use the lower value of 方程式
38 or 方程式 39 as the approximate crossover frequency. For this example, f(c) is 56 kHz. Next, calculate the
values of the compensation components. Use a resistor in series with a capacitor to create a compensating zero.
A capacitor in parallel with these two components forms the compensating pole (if needed).
IO(max)
f(p,mod)
=
2p´ VO ´ C(OUT)
(36)
1
f(z,mod)
=
2p´R(ESR) ´ C(OUT)
(37)
(38)
f(c)
=
f
(p,mod) ´ f(z,mod)
f(SW)
f(c)
=
f(p,mod)
´
2
(39)
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use 方程式40 to calculate the resistor value for the
compensation network. In this example, the anticipated crossover frequency (f(c)) is 56 kHz. The power-
stage gain (gm(ps)) is 25 S and the error-amplifier gain (gm(ea)) is 245 μS.
2p´ f(c) ´ VO ´ C(OUT)
R3 =
g
m(ea) ´ V ´ gm(ps)
ref
(40)
2. Place a compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the
capacitor for the compensation network using 方程式41.
R0´ C0
C3 =
R3
(41)
3. One can include an additional pole to attenuate high-frequency noise. In this application, the extra pole is not
necessary.
From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.
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8.2.2.9 Power-Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous-conduction mode
(CCM) operation. The power dissipation of the IC (PT) includes conduction loss (P(con)), dead-time loss (P(d)),
switching loss (P(SW)), gate-drive loss (P(gd)) and supply-current loss (P(q)).
2
= IO ´ rDS(on)(Temp)
P
(con)
(42)
where
• IO is the output current (A)
• rDS(on)(Temp) is the on-resistance of the high-side MOSFET at a given temperature (Ω)
P
= f(SW)´ IO ´0.7´ 60´10-9
(d)
(43)
(44)
where
• f(SW) is the switching frequency (Hz)
= 1/2 ´ VI ´ IO ´ f(SW) ´8´10-9
P
(SW)
where
• VI is the input voltage (V)
= 2 ´ VI ´ f(SW) ´ 2´10-9
P
(gd)
(45)
(46)
P
= VI ´ 515´10-6
(q)
Therefore:
PT = P(con) + P(d) + P(SW) + P(gd) + P
(q)
(47)
(48)
For a given TA, use 方程式48 to calculate the junction temperature.
TJ = TA + RqJA ´ PT
where
• TJ is the junction temperature (°C)
• TA is the ambient temperature (°C)
• RθJA is the thermal resistance of the package (°C/W)
• PT is the total device power dissipation (W)
For a given TJ(max) = 150°C, use 方程式49 to calculate the maximum ambient temperature.
TA(max) = TJ(max) - RqJA ´ PT
(49)
where
• TJ(max) is maximum junction temperature (°C)
• TA(max) is maximum ambient temperature (°C)
Additional power losses occur in the regulator circuit because of the inductor ac and dc losses and trace
resistance that impact the overall efficiency of the regulator.
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8.2.3 Application Curves
100
90
100
90
80
70
60
50
40
30
20
10
0
80
V(VIN) = 3.3 V
70
V(VIN) = 5 V
V(VIN) = 5 V
V(VIN) = 3.3 V
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
VO = 1.8 V
VO = 1.8 V
图8-3. Efficiency vs Load Current
图8-2. Efficiency vs Load Current
100
100
2.5 V
1.8 V
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
2.5 V
1.8 V
1.5 V
1.2 V
1.05V
3.3 V
1.05 V
1.2 V
1.5 V
55
50
55
50
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
V(VIN) = 3.3 V
f(SW) = 1 MHz
TA = 25°C
V(VIN) = 5 V
f(SW) = 1 MHz
TA = 25°C
图8-4. Efficiency vs Load Current
图8-5. Efficiency vs Load Current
V
= 2 V/div
V
= 2 V/div
(VIN)
(VIN)
EN = 1 V/div
EN = 1 V/div
SS/TR = 1 V/div
SS/TR = 1 V/div
V
= 1 V/div
O
V
= 1 V/div
O
Time = 5 ms/div
Time = 500 ms/div
图8-6. Power Up VO, V(VIN)
图8-7. Power Down VO, V(VIN)
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V(VIN) = 5 V/div
VO = 100 mV/div (ac-coupled)
VO = 2 V/div
EN = 2 V/div
IO = 1 A/div (0-A to 1.5-A load step)
PWRGD = 5 V/div
Time = 5 ms/div
Time = 200 µs/div
图8-8. Transient Response, 1.5-A Step
图8-9. Power Up VO, V(VIN)
V(VIN) = 5 V/div
VO = 20 mV/div (ac-coupled)
VO = 2 V/div
PH = 2 V/div
EN = 2 V/div
PWRGD = 5 V/div
Time = 500 ns/div
Time = 5 ms/div
图8-10. Power Up VO, EN
图8-11. Output Ripple, 3 A
60
50
180
150
120
90
V(VIN) = 100 mV/div (ac coupled)
40
30
20
60
10
30
0
0
–10
–20
–30
–40
–50
–60
–30
–60
–90
–120
–150
–180
PH = 2 V/div
Gain
Phase
10
100
1000
10k
100k
1M
Frequency - Hz
V(VIN) = 5 V
IO = 3 A
Time = 500 ns/div
图8-13. Closed-Loop Response
图8-12. Input Ripple, 3 A
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0.4
0.3
0.4
0.3
0.2
0.1
0.2
V(VIN) = 5 V
0.1
0
0
V(VIN) = 3.3 V
–0.1
–0.1
–0.2
–0.3
–0.4
–0.2
–0.3
–0.4
0
0.5
1
1.5
2
2.5
3
3
3.5
4
4.5
5
5.5
6
Output Current (A)
Input Voltage (V)
图8-14. Load Regulation vs Load Current
IO = 2 A
图8-15. Regulation vs Input Voltage
9 Power Supply Recommendations
By design, the TPS54388C-Q1 device works with an analog supply voltage range of 2.95 V to 6 V. Ensure good
regulation for the input supply, and connect the supply to the VIN pins with the appropriate input capacitor as
calculated in the 节 8.2.2.4 section. If the input supply is located more than a few inches from the TPS54388C-
Q1 device, the design may require extra capacitance in addition to the recommended value.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. The signal paths, which conduct fast-changing currents
or voltages, can interact with stray inductance or parasitic capacitance in several ways to generate noise or
degrade the power-supply performance. Take care to minimize the loop area formed by the bypass-capacitor
connections and the VIN pins. See 图 10-1 for a PCB layout example. Tie the GND pins and AGND pin directly
to the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias
directly under the IC. Use additional vias to connect the top-side ground area to any internal planes near the
input and output capacitors. For operation at full-rated load, the top-side ground area, along with any additional
internal ground planes, must provide adequate heat-dissipating area.
Locate the input bypass capacitor as close to the IC as possible. Route the PH pin to the output inductor.
Because the PH connection is the switching node, locate the output inductor close to the PH pins, and minimize
the area of the PCB conductor to prevent excessive capacitive coupling. Also. locate the boot capacitor close to
the device. Connect the sensitive analog ground connections for the feedback voltage divider, compensation
components, slow-start capacitor, and frequency-set resistor to a separate analog ground trace as shown. The
RT/CLK pin is particularly sensitive to noise, so locate the Rt resistor as close as possible to the IC, and connect
it with minimal lengths of trace. Place the additional external components approximately as shown. It may be
possible to obtain acceptable performance with alternative PCB layouts. However, this layout, meant as a
guideline, produces good results.
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
BOOT
CAPACITOR
VIN
INPUT
OUTPUT
INDUCTOR
VIN
PH
PH
PH
SS
VOUT
BYPASS
CAPACITOR
VIN
OUTPUT
FILTER
EXPOSED
POWERPAD
AREA
CAPACITOR
GND
GND
PH
SLOW START
CAPACITOR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
图10-1. PCB Layout Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDQ8
34
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Product Folder Links: TPS54388C-Q1
TPS54388C-Q1
ZHCSL73B –OCTOBER 2016 –REVISED JUNE 2021
www.ti.com.cn
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Enable Functionality and Adjusting Undervoltage Lockout for TPS57112-Q1 (SLVA784)
• Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices With Low Impendence External
Clock Drivers (SLVA755)
• TPS57112-Q1 High Frequency (2.35 MHz) Operation (SLVA743)
• TPS54388EVM User's Guide (SLVU962)
• TPS54388-Q1 Pin Open and Short Test Results (SLVA581)
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2023 Texas Instruments Incorporated
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35
Product Folder Links: TPS54388C-Q1
English Data Sheet: SLVSDQ8
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54388CQRTERQ1
ACTIVE
WQFN
RTE
16
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
5438Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54388CQRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS54388CQRTERQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS54388QRTERQ1
2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down Switcher With Integrated FETs
TI
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