TPS544C26 [TI]
4V 至 16V、35A SVID 和 I²C 同步降压转换器;
| 型号： | TPS544C26 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4V 至 16V、35A SVID 和 I²C 同步降压转换器 转换器 |
| 文件： | 总135页 (文件大小：5392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS544C26
ZHCSR16 –SEPTEMBER 2022
TPS544C26 具有SVID 和I2C 接口的4V 至16V 输入、35A 同步降压转换器
1 特性
2 应用
• 提供适用于SVID 电源轨的单芯片电源
• 符合Intel® VR13 SVID 标准
• 服务器和云计算POL
• 硬件加速器
• 网络接口卡
• 提供具有NVM 的I2C 接口，用于配置、遥测
(V/I/T) 和故障报告
3 说明
• 可实现输入功率监控，用于DDR5 存储器RAPL
• 集成4.0mΩ 和1.0mΩ MOSFET，可实现35A 持续
电流运行
• 输入电压：4V 至16V (绝对最大值为18V)
• 支持5V 外部偏置，可提高效率并实现2.7V 最小输
入电压
TPS544C26 器件是一款高度集成的降压转换器，采用
D-CAP+控制拓扑，可实现快速瞬态响应。所有可编程
参数均可通过I2C 接口进行配置，而且可作为新的默认
值存储在 NVM 中，以尽可能减少外部组件数量。这些
特性使得该器件非常适合空间受限型应用。
• 可编程输出电压范围为0.25V 至3.04V
• 可编程输出电压压摆率为1.25mV/µs 至10mV/µs
• 提供精密电压基准和差分遥感，可实现高输出精度
TPS544C26 器件专为 Intel 服务器和 SoC 平台中的中
低电流 SVID 电源轨而设计。TPS544C26 器件具有
SVID 和I2C 接口功能，可配置为单相CPU 电源轨。
– 0°C 至85°C 结温范围内的Vout 容差为±0.5%
– –40°C 至125°C 结温范围内的Vout 容差为
±1%
该器件具有过流、过压、欠压和过热保护功能。
TPS544C26 器件提供全套（包括输出电压、输出电流
和 IC 温度）遥测功能。此外，TPS544C26 器件还通
过外部感应电阻器提供输入功率监控。
• 具有D-CAP+™ 控制拓扑，可实现快速瞬态响应
• 支持所有陶瓷输出电容器
• 提供可编程内部环路补偿，包括压降补偿
• 提供可选逐周期谷值电流限制
TPS544C26 是一款无铅器件，符合RoHS 标准，无需
豁免。
• 在DCM 或FCCM 运行模式下，可选工作频率为
0.6MHz 至1.2MHz
• 提供安全启动至预偏置输出
• 可编程软启动时间为1ms 至16ms
• 可编程软停止时间为0.5ms 至4ms
• 提供开漏电源正常状态输出(VRRDY) 和灾难性故
障指示灯(CAT_FAULT#)
• 提供可编程过流、过压、欠压、过热保护
• 采用5mm × 6mm 37 引脚WQFN-FCRLF 封装，
引脚间距为0.5mm
封装信息
封装尺寸（标称
值）
封装(1)
器件型号
RXX（WQFN-FCRLF，
37）
TPS544C26
5.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
95
90
85
80
75
70
65
60
Vin
PVIN
BOOT
PHASE
SW
VCC/VDRV
Vout
Load
PGND
VOSNS
EN
EN
GOSNS
VR Ready
VRRDY
CAT_FAULT#
CAT_FAULT#
6
DNC
NC
SV_ALERT#
SV_DIO
SV_CLK
37
SVID
Interface
I2C_ADDR
I2
Interface
C
I2C_SCL
I2C_SDA
55
PVIN=12V
AGND
VOUT=1.1V
fSW=800kHz
Use the internal LDO
Use an external 5V bias
50
45
VINSENP
VINSNSM
P12V
P12V_DDR_XXXX
IIN sensing resistor
0
5
10
15
20
25
30
Iout (A)
简化原理图
典型效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFW7
TPS544C26
ZHCSR16 –SEPTEMBER 2022
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 37
7.6 Register Maps...........................................................42
8 Application and Implementation................................ 116
8.1 Application Information............................................116
8.2 Typical Application.................................................. 116
8.3 Power Supply Recommendations...........................120
8.4 Layout..................................................................... 121
9 Device and Documentation Support..........................124
9.1 Documentation Support.......................................... 124
9.2 接收文档更新通知................................................... 124
9.3 支持资源..................................................................124
9.4 Trademarks.............................................................124
9.5 Electrostatic Discharge Caution..............................124
9.6 术语表..................................................................... 124
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics..............................................15
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................36
Information.................................................................. 125
10.1 Tape and Reel Information....................................125
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
September 2022
*
Advance Information release
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5 Pin Configuration and Functions
29
30
31
32
33
34
35
36
36
35
34
33
32
31
30
29
I2C_SDA
VRRDY
CAT_FAULT#
EN
28
27
26
25
24
23
22
21
20
19
1
2
1
2
28
27
26
25
24
23
22
21
20
19
CAT_FAULT#
EN
I2C_SDA
VRRDY
VINSENP
VINSENM
VCC/VDRV
DNC
3
3
BOOT
PHASE
PVIN
VINSENP
VINSENM
VCC/VDRV
DNC
BOOT
PHASE
PVIN
4
4
5
5
NC
37
NC
37
6
6
PVIN
PVIN
7
PVIN
PGND
7
PGND
PVIN
8
PVIN
PGND
8
PGND
PVIN
9
PVIN
PGND
9
PGND
PVIN
10
PGND
PGND
10
PGND
PGND
18
17
16
15
14
13
12
11
11
12
13
14
15
16
17
18
图5-2. RXX 37-pin WQFN-FCRLF Package (Bottom
图5-1. RXX 37-pin WQFN-FCRLF Package (Top
View)
View)
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
AGND
BOOT
32
G
Ground pin, reference point for internal control circuitry.
Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor
from this pin to PHASE pin. A high temperature (X7R) 0.1 μF or greater value ceramic
capacitor is recommended.
26
28
6
P
O
Catastrophic Fault indicator, open-drain. The CAT_FAULT# indicator asserts low when any
catastrophic fault event (over-voltage, under-voltage and over-temperature) happens.
During nominal operation, the CAT_FAULT# indicator holds high.
CAT_FAULT#
DNC
Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating.
Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on
pin 6.
—
Enable pin, an active-high input pin that, when asserted high, causes the converter to
begin its soft-start sequence for its output voltage rail. When de-asserted low, the
converter must de-assert VRRDY and begin the shutdown sequence of the output voltage
rail and continue to completion.
EN
27
I
Negative input of the differential remote sense circuit, connect to the ground sense point
on the load side.
GOSNS
31
29
I
I
The I2C address of the device is set by tying an external resistor between this pin and
AGND.
I2C_ADDR
I2C_SCL
I2C_SDA
NC
36
I
I2C serial clock pin, open drain.
1
37
I/O
I2C bi-directional serial data pin, open drain.
Not connected. This pin is floating internally. Pin 37 and pin 6 can be shorted together.
Power ground for the internal power stage.
—
PGND
G
7–10, 19
Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap
capacitor from BOOT pin to this pin.
PHASE
PVIN
25
—
P
Power input for both the power stage. PVIN is the input of the internal VCC LDO as well.
20–24
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表5-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
SVID active low ALERT# signal, open drain. This output is asserted to indicate the status
of the converter has changed.
SV_ALERT#
35
O
SV_CLK
SV_DIO
34
33
I
SVID clock pin, open drain.
I/O
SVID bi-directional data pin, open drain.
Output switching terminal of the power converter. Connect these pins to the output
inductor.
SW
O
11–18
Internal VCC LDO output and also the input for gate driver circuit. An external 5-V bias can
be connected to this pin to save the power losses on the internal LDO. The voltage source
on this pin powers both the internal control circuitry and the gate driver. A 2.2 μF (or 4.7
μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC/VDRV pin
to PGND pins to decouple the noise generated by driver circuitry. Check layout guidelines
for more details.
VCC/VDRV
5
P
Negative input for the input power telemetry. Connect to the negative side of the input
power sense resistor. Input voltage is also sensed at this pin. To minimize the impact from
switching noise, a ceramic decoupling capacitor with at least 100 pF capacitance is
required from this pin to PGND. Check layout guidelines for more details.
VINSENM
4
I
Positive input for the input power telemetry. Connect to the positive side of the input power
sense resistor. To minimize the impact from switching noise, a ceramic decoupling
capacitor with at least 100-pF capacitance is required from this pin to PGND. Check layout
guidelines for more details.
VINSENP
VOSNS
VRRDY
3
30
2
I
I
Positive input of the differential remote sense circuit, connect to the Vout sense point on
the load side.
Voltage regulator “Ready”output signal. The VRRDY indicator is asserted when the
controller is ready to accept SVID commands after the EN is asserted. VRRDYalso de-
asserts low when a shutdown fault occurs. This open-drain output requires an external
pullup resistor.
O
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–1.5
–0.3
–3.0
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
18
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Sink current
TJ
PVIN
18
V
PVIN –SW, DC
26
V
PVIN –SW, transient < 10 ns
SW –PGND, DC
18
V
SW, transient < 10 ns
BOOT –PGND
21.5
23.5
5.5
5.5
18
V
V
V
BOOT –SW
VCC/VDRV
V
PHASE
V
VINSENP, VINSENM
EN, VOSNS, SM_ADDR, VRRDY, CAT_FAULT#
SV_CLK, SV_DIO, SV_ALERT#, SM_CLK, SM_DIO
GOSNS –AGND
20
V
5.5
5.5
0.3
1.9
10
V
V
V
DNC, NC
V
VRRDY
mA
°C
°C
Operating junction temperature
Storage temperature
150
150
–40
–55
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002 (2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VOUT
Output voltage range (programmed through SVID interface)
PVIN when VCC/VDRV is powered by the
0.5
3.04
V
4.0
16
16
V
V
internal LDO
VIN
Input voltage
PVIN when VCC/VDRV is powered by a
valid external bias
2.7
VBIAS
IOUT
Input voltage
VCC/VDRV external bias
4.75
5.3
35
V
A
Output current range
Pin voltage
VINSENP, VINSENM
8
–0.1
–0.1
–0.1
16
V
Pin voltage
EN, VRRDY, CAT_FAULT#
SV_CLK, SV_DIO, SV_ALERT#
SM_CLK, SM_DIO
5.3
1.5
5.3
10
V
Pin voltage
V
Pin voltage
V
IVRRDY
VRRDY input current capability
mA
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Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
125
UNIT
TJ
Operating junction temperature
°C
–40
6.4 Thermal Information
DEVICE
THERMAL METRIC(1)
RXX (QFN, JEDEC)
RXX (QFN, TI EVM)
37 PINS
UNIT
37 PINS
26.0
7.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Not applicable(2)
Not applicable(2)
0.2
3.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
3.6
5.6
ψJB
RθJC(bot)
3.3
Not applicable(2)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The thermal test or simulation setup is not applicable to a TI EVM layout.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
PVIN operating input range
PVIN quiescent current
4
18
9
V
Non-switching, PVIN = 12 V, VEN = 0 V, no
bias on VCC/VDRV pin
IQ(PVIN)
7.5
30
mA
5 V external bias on VCC/VDRV pin, regular
IVCC
VCC/VDRV external bias current
VCC/VDRV quiescent current
switching. TJ = 25°C, PVIN = 12 V, VOUT
1.1 V, VEN = 2 V, fSW = 1 MHz
=
mA
mA
5V external bias on VCC/VDRV pin, non-
IQ(VCC)
switching. PVIN = 12V, VEN = 2 V, VFB
VREF + 50 mV
=
5
UVLO
PVIN rising, VIN_OV_FAULT_LIMIT register
(55h) = 0b
PVINOV
PVIN overvoltage rising threshold
PVIN overvoltage rising threshold
16.5
18.5
V
V
PVIN rising, VIN_OV_FAULT_LIMIT register
(55h) = 1b
PVINOV
PVINOV
PVIN falling. PVIN_OVF status bit, once it is
set, cannot be cleared unless PVIN falls
below the PVIN overvoltage falling threshold
PVIN overvoltage falling threshold
13.5
V
VIN_ON
VIN_ON
VIN_ON
PVIN turn-on voltage
PVIN turn-on voltage
PVIN turn-on voltage
PVIN rising, VIN_ON register (35h) = 00b
PVIN rising, VIN_ON register (35h) = 01b
PVIN rising, VIN_ON register (35h) = 10b
10
9
V
V
V
8
PVIN rising, VIN_ON register (35h) = 11b.
Ignore VIN_ON setting, and use VCC UVLO
rising threshold to enable the device.
VIN_ON
PVIN turn-on voltage
Disabled
V
VIN_OFF
VIN_OFF
VIN_OFF
VIN_OFF
VIN_OFF
VIN_OFF
VIN_OFF
VIN_OFF
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN turn-off voltage
PVIN falling, VIN_OFF register (36h) = 000b
PVIN falling, VIN_OFF register (36h) = 000b
PVIN falling, VIN_OFF register (36h) = 001b
PVIN falling, VIN_OFF register (36h) = 010b
PVIN falling, VIN_OFF register (36h) = 011b
PVIN falling, VIN_OFF register (36h) = 100b
PVIN falling, VIN_OFF register (36h) = 101b
PVIN falling, VIN_OFF register (36h) = 110b
reserved
4.2
V
V
V
V
V
V
V
V
9.5
8.5
7.5
6.5
5.5
4.2
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PVIN falling, VIN_OFF register (36h) =
111b. Ignore VIN_OFF setting, and use
VCC UVLO falling threshold to disable the
device.
VIN_OFF
PVIN turn-off voltage
Disabled
V
PVIN rising, 5V external bias on VCC/VDRV
pin
PVINUVLO(R)
PVINUVLO(F)
PVIN UVLO rising threshold
2.0
1.8
2.55
3.0
2.8
V
PVIN falling, 5V external bias on VCC/
VDRV pin
PVIN UVLO falling threshold
PVIN UVLO hysteresis
2.3
V
V
PVINUVLO(H)
ENABLE
VEN(R)
0.25
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
EN rising, enable switching
EN falling, disable switching
1.14
0.94
1.19
0.98
0.21
1.24
1.02
V
V
VEN(F)
VEN(H)
V
tEN(DIG)
EN Deglitch Time
0.2
87
µs
kΩ
EN internal pulldown resistor
EN to AGND
103
119
INTERNAL VCC LDO
Delay from VCC UVLO to I2C ready to
communicate
tdelay(uvlo_I2C)
VCC/VDRV >= 3 V
TBD
ms
Internal VCC LDO output voltage
Internal VCC LDO output voltage
VCC UVLO rising threshold
VCC UVLO falling threshold
VCC UVLO hysteresis
PVIN= 4 V, IVCC(load) = 5 mA
PVIN= 5 V to 16 V, IVCC(load) = 5 mA
VCC rising
3.925
4.28
3.69
3.49
3.97
4.44
3.75
3.55
0.2
4.0
4.55
3.81
3.61
V
V
V
V
V
VCC falling
PVIN –VVCC, PVIN = 4 V, IVCC(load) = 45
mA
VCC LDO dropout voltage
90
144
200
226
mV
mA
VCC LDO short-circuit current limit
PVIN = 5 V
150
VOUT VOLTAGE
Output Voltage controlled through
SVID interface
Output voltage range by SetVID & SetWP
commands
0.5
3.04
V
Output Voltage controlled through
SVID interface
Output voltage resolution by SetVID &
SetWP commands
5
2.78
5.5
mV
Output Voltage controlled through
SVID interface
SVID fast slew rate, register (AFh)
DVS_CFG = 010b
2.5
5
3.06 mV/µs
6.1 mV/µs
12.2 mV/µs
Output Voltage controlled through
SVID interface
SVID fast slew rate, register (AFh)
DVS_CFG = 100b
Output Voltage controlled through
SVID interface
SVID fast slew rate, register (AFh)
DVS_CFG = 110b
10
11.1
Output Voltage controlled through
SVID interface
SVID OFFSET range
127
Step
Step
V
–127
Output Voltage controlled through
SVID interface
SVID OFFSET resolution
1
5
Output Voltage controlled through I2C
interface
Output voltage range by register (A6h)
VOUT_CMD
0.5
3.04
Output Voltage controlled through I2C
interface
Output voltage resolution by register (A6h)
VOUT_CMD
mV
Output voltage transition slew rate by
register (A6h) VOUT_CMD, register (AFh)
DVS_CFG = 010b
Output Voltage controlled through I2C
interface
0.625
1.25
2.5
mV/µs
mV/µs
mV/µs
Output voltage transition slew rate by
register (A6h) VOUT_CMD, register (AFh)
DVS_CFG = 100b
Output Voltage controlled through I2C
interface
Output voltage transition slew rate by
register (A6h) VOUT_CMD, register (AFh)
DVS_CFG = 110b
Output Voltage controlled through I2C
interface
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output Voltage controlled through I2C
interface
I2C offset (register (A8h) VID_OFFSET)
range, 5mV VID step
63
mV
–63
Output Voltage controlled through I2C
interface
I2C offset (register (A8h) VID_OFFSET)
resolution, 5mV VID step
0.5
mV
mV
mV
V
Output Voltage controlled through I2C
interface
I2C offset (register (A8h) VID_OFFSET)
range, 10mV VID step
127
–127
Output Voltage controlled through I2C
interface
I2C offset (register (A8h) VID_OFFSET)
resolution, 10mV VID step
1.0
0.75
1.1
TJ = 0°C to 85°C, VOUT = 0.75 V, VVOSNS
VGOSNS
–
VOUT(ACC)
VOUT(ACC)
VOUT(ACC)
VOUT(ACC)
VOUT(ACC)
Output voltage accuracy
Output voltage accuracy
Output voltage accuracy
Output voltage accuracy
Output voltage accuracy
0.744
1.0945
1.791
0.756
1.1055
1.809
TJ = 0°C to 85°C, VOUT = 1.1 V, VVOSNS
–
V
VGOSNS
TJ = 0°C to 85°C, VOUT = 1.8 V, VVOSNS
–
1.8
V
VGOSNS
TJ = –40°C to 125°C, VOUT = 0.75 V,
0.7425
1.089
0.75
0.7575
1.111
V
V
V
VOSNS–VGOSNS
TJ = –40°C to 125°C, VOUT = 1.1 V,
VOSNS–VGOSNS
TJ = –40°C to 125°C, VOUT = 1.8 V,
VOSNS–VGOSNS
VVOSNS = 1.8 V
1.1
V
VOUT(ACC)
IVOS
Output voltage accuracy
VOSNS input current
1.782
1.8
111
1.818
130
V
V
µA
SWITCHING FREQUENCY
TJ = –40°C to 125°C, PVIN = 12 V, VOUT
1.1 V, no load, FREQUENCY_SWITCH
register (33h) = 00b
=
=
=
=
fSW(FCCM)
fSW(FCCM)
fSW(FCCM)
fSW(FCCM)
Switching frequency, FCCM operation
540
720
600
800
660
880
kHz
kHz
kHz
kHz
TJ = –40°C to 125°C, PVIN = 12 V, VOUT
1.1 V, no load, FREQUENCY_SWITCH
register (33h) = 01b
Switching frequency, FCCM operation
Switching frequency, FCCM operation
Switching frequency, FCCM operation
TJ = –40°C to 125°C, PVIN = 12 V, VOUT
1.1 V, no load, FREQUENCY_SWITCH
register (33h) = 10b
900
1000
1200
1100
1320
TJ = –40°C to 125°C, PVIN = 12 V, VOUT
1.1 V, no load, FREQUENCY_SWITCH
register (33h) = 11b
1080
STARTUP
VVCC = 4.5 V, register (60h) TON_DELAY =
00b
tON(DLY)
Power on sequence delay
Power on sequence delay
Power on sequence delay
Power on sequence delay
Power off sequence delay
Power off sequence delay
Power off sequence delay
Power off sequence delay
Soft-start time
0.5
1.0
1.5
2.0
0
0.55
1.1
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
VVCC = 4.5 V, register (60h) TON_DELAY =
01b
tON(DLY)
tON(DLY)
tON(DLY)
tOFF(DLY)
tOFF(DLY)
tOFF(DLY)
tOFF(DLY)
tON(Rise)
tON(Rise)
tON(Rise)
VVCC = 4.5 V, register (60h) TON_DELAY =
10b
1.65
2.2
VVCC = 4.5 V, register (60h) TON_DELAY =
11b
VVCC = 4.5 V, register (64h) TOFF_DELAY =
00b
0.05
1.1
VVCC = 4.5 V, register (64h) TOFF_DELAY =
01b
1.0
1.5
2.0
1.0
2.0
4.0
VVCC = 4.5 V, register (64h) TOFF_DELAY =
10b
1.65
2.2
VVCC = 4.5 V, register (64h) TOFF_DELAY =
11b
VVCC = 4.5 V, register (61h) TON_RISE =
000b
1.1
VVCC = 4.5 V, register (61h) TON_RISE =
001b
Soft-start time
2.2
VVCC = 4.5 V, register (61h) TON_RISE =
010b
Soft-start time
4.4
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
Soft-start time
Soft-start time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVCC = 4.5 V, register (61h) TON_RISE =
011b
tON(Rise)
tON(Rise)
8.0
8.8
ms
VVCC = 4.5 V, register (61h) TON_RISE =
1xxb
16.0
2.2
17.6
2.44
ms
VVCC = 4.5 V, register (65h) TOFF_FALL =
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
Soft-stop slew rate, VOUT controlled by SVID 00b, Vboot = 1.1V, PROTOCOL ID = 07h,
5mV VID step
2.00
1.00
0.50
0.25
3.27
1.64
0.82
0.41
V/ms
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 01b, Vboot = 1.1V, PROTOCOL ID = 07h,
5mV VID step
1.1
0.55
0.275
3.6
1.22
0.61
0.31
4.00
2.00
1.00
0.50
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 10b, Vboot = 1.1V, PROTOCOL ID = 07h,
5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 11b, Vboot = 1.1V, PROTOCOL ID = 07h,
5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 00b, Vboot = 1.8V, PROTOCOL ID = 04h,
10mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 01b, Vboot = 1.8V, PROTOCOL ID = 04h,
10mV VID step
1.8
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 10b, Vboot = 1.8V, PROTOCOL ID = 04h,
10mV VID step
0.9
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by SVID 11b, Vboot = 1.8V, PROTOCOL ID = 04h,
10mV VID step
0.45
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
tOFF(Fall)
2.00
1.00
0.50
0.25
3.27
1.64
0.82
0.41
2.2
1.1
2.44
1.22
0.61
0.31
4.00
2.00
1.00
0.50
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
00b, PROTOCOL ID = 07h, 5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
01b, PROTOCOL ID = 07h, 5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
0.55
0.275
3.6
10b, PROTOCOL ID = 07h, 5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
11b, PROTOCOL ID = 07h, 5mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
00b, PROTOCOL ID = 04h, 10mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
1.8
01b, PROTOCOL ID = 04h, 10mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
0.9
10b, PROTOCOL ID = 04h, 10mV VID step
VVCC = 4.5 V, register (65h) TOFF_FALL =
Soft-stop slew rate, VOUT controlled by I2C
0.45
11b, PROTOCOL ID = 04h, 10mV VID step
POWER STAGE
RDSON(HS)
RDSON(HS)
RDSON(LS)
RDSON(LS)
tON(min)
High-side MOSFET on-resistance
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
Low-side MOSFET on-resistance
Minimum ON pulse width
TJ = 25°C, PVIN = 12 V, VBOOT-SW = 4.5 V
TJ = 25°C, PVIN = 12 V, VBOOT-SW = 5.0 V
TJ = 25°C, PVIN = 12 V, VVCC = 4.5 V
TJ = 25°C, PVIN = 12 V, VVCC = 5 V
VVCC = 4.5 V
4
3.91
1
mΩ
mΩ
mΩ
mΩ
ns
0.98
50
VVCC = 4.5 V, IO=1.5A, VOUT = VOUT(set)
20 mV, SW falling edge to rising edge
–
tOFF(min)
Minimum OFF pulse width
180
ns
BOOT CIRCUIT
IBOOT(LKG)
BOOT leakage current
VEN = 2 V, VBOOT-SW = 5 V
150
µA
V
VBOOT-SW(UV_F)
BOOT-SW UVLO falling threshold
2.60
2.76
OVERCURRENT PROTECTION
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0000b
ILS(OC)
8.5
10
11.5
A
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0001b
ILS(OC)
10.2
13.5
17.1
18
12
15
19
20
25
26
30
33
35
39
40
40
10
15
20
25
30
35
40
13.8
16.5
20.9
22
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0010b
ILS(OC)
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0011b
ILS(OC)
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0100b
ILS(OC)
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0101b
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCL)
ILS(OCW)
ILS(OCW)
ILS(OCW)
ILS(OCW)
ILS(OCW)
ILS(OCW)
ILS(OCW)
22.5
23.4
27
27.5
28.6
33
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0110b
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 0111b
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 1000b
29.7
31.5
35.1
36
36.3
38.5
42.9
44
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 1001b
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 1010b
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 1011b
Low-side valley overcurrent limit
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_FAULT_LIMIT (46h) = 11xxb
36
44
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 000b
8.5
11.5
16.5
22
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 001b
13.5
18
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 010b
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 011b
22.5
27
27.5
33
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 100b
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 101b
31.5
36
38.5
44
Low-side valley overcurrent warning
(TPS544C26)
Valley current limit on LS FET,
IOUT_OC_WARN_LIMIT (4Ah) = 11xb
Sinking current limit on LS FET,
ILS(NOC)
ILS(NOC)
ILS(NOC)
ILS(NOC)
ILS(NOC)
ILS(NOC)
Low-side negative overcurrent limit
Low-side negative overcurrent limit
Low-side negative overcurrent limit
Low-side negative overcurrent limit
Low-side negative overcurrent limit
Low-side negative overcurrent limit
A
A
A
A
A
A
IOUT_NOC_LIMIT (B4h) = 00b, ICCMAX
15A
≥
–18
–8.5
–20
–10
–15
–7.5
–12
–6
–22
–11.5
–16.5
–8.63
–13.8
–6.9
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 00b, ICCMAX
10 A
≤
≥
≤
≥
≤
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 01b, ICCMAX
15A
–13.5
–6.37
–10.2
–5.1
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 01b, ICCMAX
10 A
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 10b, ICCMAX
15A
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 10b, ICCMAX
10 A
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 11b, ICCMAX
15A
ILS(NOC)
Low-side negative overcurrent limit
A
≥
≤
–8.5
–10
–11.5
Sinking current limit on LS FET,
IOUT_NOC_LIMIT (B4h) = 11b, ICCMAX
10 A
ILS(NOC)
Low-side negative overcurrent limit
A
–4.25
–5
–5.75
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 00b,
enter DCM
IZC
IZC
IZC
IZC
IZC
IZC
IZC
IZC
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
Zero-cross detection current threshold
1200
1500
900
1200
0
mA
mA
mA
mA
mA
mA
mA
mA
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 00b,
exit DCM
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 01b,
enter DCM
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 01b,
exit DCM
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 10b,
enter DCM
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 10b,
exit DCM
300
–300
0
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 11b,
enter DCM
VIN = 12 V, VVCC = 4.5 V, SEL_ZC = 11b,
exit DCM
Response delay before entering Hiccup
Response delay before entering Hiccup
Response delay before entering Hiccup
Response delay before entering Hiccup
Hiccup sleep time before a restart
UV RESPONSE_DELAY = 00b
UV RESPONSE_DELAY = 01b
UV RESPONSE_DELAY = 10b
UV RESPONSE_DELAY = 11b
2
16
µs
µs
µs
µs
ms
64
256
56
OUTPUT OVP AND UVP
Vout tracking overvoltage protection (OVP)
threshold, offset above Vout
(VOSNS – GOSNS) rising. (40h)
VOUT_OV_FAULT_LIMIT = 00b
VOVP
VOVP
VOVP
VOVP
80
120
160
240
100
150
200
120
180
240
360
mV
mV
mV
Vout tracking overvoltage protection (OVP)
threshold, offset above Vout
(VOSNS – GOSNS) rising. (40h)
VOUT_OV_FAULT_LIMIT = 01b
Vout tracking overvoltage protection (OVP)
threshold, offset above Vout
(VOSNS – GOSNS) rising. (40h)
VOUT_OV_FAULT_LIMIT = 10b
Vout tracking overvoltage protection (OVP)
threshold, offset above Vout
(VOSNS – GOSNS) rising. (40h)
VOUT_OV_FAULT_LIMIT = 11b
300
2
mV
µs
Vout tracking OVP de-glitch time
(VOSNS – GOSNS) rising. (CFh)
FAULT_CTRL2, SEL_FIX_OVF = 0b, and
(CCh) PROTOCOL_ID_SVID,
PROTOCOL_ID<7:6> = 01b or 10b (5mV
step)
VFixOV
VFixOV
VFixOV
VFixOV
Vout fixed OVP threshold, 5mV step
1.425
1.71
2.33
2.93
1.5
1.8
2.4
1.575
1.89
2.47
3.07
V
V
V
(VOSNS – GOSNS) rising. (CFh)
FAULT_CTRL2, SEL_FIX_OVF = 1b, and
(CCh) PROTOCOL_ID_SVID,
PROTOCOL_ID<7:6> = 01b or 10b (5mV
step)
Vout fixed OVP threshold, 5mV step
Vout fixed OVP threshold, 10mV step
(VOSNS – GOSNS) rising. (CFh)
FAULT_CTRL2, SEL_FIX_OVF = 0b, and
(CCh) PROTOCOL_ID_SVID,
PROTOCOL_ID<7:6> = 00b or 11b (10mV
step)
(VOSNS – GOSNS) rising. (CFh)
FAULT_CTRL2, SEL_FIX_OVF = 1b, and
(CCh) PROTOCOL_ID_SVID,
PROTOCOL_ID<7:6> = 00b or 11b (10mV
step)
Vout fixed OVP threshold, 10mV step
Vout fixed OVP de-glitch time
3.0
2
V
µs
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vout tracking undervoltage protection (UVP)
threshold, offset below Vout
(VOSNS – GOSNS) falling. (44h)
VOUT_UV_FAULT_LIMIT = 00b
VUVP
VUVP
VUVP
VUVP
mV
–120
–150
–180
Vout tracking undervoltage protection (UVP)
threshold, offset below Vout
(VOSNS – GOSNS) falling. (44h)
VOUT_UV_FAULT_LIMIT = 01b
mV
mV
mV
–160
–160
–240
–200
–200
–300
–240
–240
–360
Vout tracking undervoltage protection (UVP)
threshold, offset below Vout
(VOSNS – GOSNS) falling. (44h)
VOUT_UV_FAULT_LIMIT = 10b
Vout tracking undervoltage protection (UVP)
threshold, offset below Vout
(VOSNS – GOSNS) falling. (44h)
VOUT_UV_FAULT_LIMIT = 11b
(45h) VOUT_UV_FAULT_RESPONSE,
RESPONSE_DELAY<1:0> = 00b. From UV
detection to tri-state of the power FETs
Vout tracking UVP response delay time
Vout tracking UVP response delay time
Vout tracking UVP response delay time
Vout tracking UVP response delay time
2
16
4
17.6
µs
µs
µs
µs
(45h) VOUT_UV_FAULT_RESPONSE,
RESPONSE_DELAY<1:0> = 01b. From UV
detection to tri-state of the power FETs
14.4
57.6
(45h) VOUT_UV_FAULT_RESPONSE,
RESPONSE_DELAY<1:0> = 10b. From UV
detection to tri-state of the power FETs
64
70.4
(45h) VOUT_UV_FAULT_RESPONSE,
RESPONSE_DELAY<1:0> = 11b. From UV
detection to tri-state of the power FETs
230.4
256
281.6
VR READY AND CATASTROPHIC FAULT
VOL(VRRDY) VRRDY pin output low-level voltage
IVRRDY = 10 mA, VIN = 12 V, VVCC = 4.5 V
Rpullup = 10 kΩ, VVRRDY = 5 V
300
5
mV
µA
VRRDY pin Leakage current when open
drain output is high
ILKG(VRRDY)
PVIN = 0 V, VEN = 0 V, Rpullup = 10 kΩ,
Min VCC for valid VRRDY pin output
1.2
300
5
V
V
VRRDY ≤0.3 V
CAT_FAULT# pin output low-level voltage
210
40
mV
µA
Rpullup = 4.99 kΩ, Vpullup = 3.3 V
Rpullup = 4.99 kΩ, Vpullup = 3.3 V
CAT_FAULT# pin Leakage current when
open drain output is high
OUTPUT DISCHARGE
VIN = 12 V, VVCC = Internal LDO, VVOSNS
0.5 V, EN=0V
=
Output discharge on VOSNS pin
Ω
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Junction temperature rising
(C0h) ICC_MAX = 40 A
153
166
30
°C
°C
TJ(HYS)
MEASUREMENT SYSTEM (I2C)
MIOUT(rng) Output current measurement range
0
40
A
A
(C0h) ICC_MAX = 40 A, 0 ≤IOUT ≤4 A, –
40°C ≤TJ ≤125°C
MIOUT(acc)
Output current measurement accuracy
Output current measurement accuracy
Output current measurement accuracy
0.625
–0.625
(C0h) ICC_MAX = 40 A, IOUT = 12 A, –
40°C ≤TJ ≤125°C
MIOUT(acc)
8%
6%
–8%
–6%
(C0h) ICC_MAX = 40 A, 24 A ≤IOUT < 40
A, –40°C ≤TJ ≤125°C
MIOUT(acc)
MIOUT(lsb)
Output current measurement bit resolution
Output voltage measurement range
(C0h) ICC_MAX = 40 A
0.1563
A
V
MVOUT(rng)
0
3.04
19
0.75 V ≤VOUT ≤1.5 V, PROTOCOL ID =
07h, 5mV VID step
MVOUT(acc)
Output voltage measurement accuracy
Output voltage measurement accuracy
mV
mV
–19
1.5 V < VOUT ≤3.0 V, PROTOCOL ID =
04h, 10mV VID step
MVOUT(acc)
37.5
–37.5
MVOUT(lsb)
MVOUT(lsb)
Output voltage measurement bit resolution
Output voltage measurement bit resolution
PROTOCOL ID = 07h, 5mV VID step
PROTOCOL ID = 04h, 10mV VID step
6.25
12.5
mV
mV
(6Bh) PIN_OP_WARN_LIMIT = 000b (360
W)
MPIN(rng)
MPIN(acc)
Input power measurement range
0
360
W
W
Input power measurement accuracy
datapoint
Room Temp, 12V, 15A, 180W
180
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input power measurement accuracy
datapoint
MPIN(acc)
Room Temp, 12V, 25A, 300W
300
W
MPIN(acc)
MPIN(lsb)
MVIN(rng)
Input power measurement accuracy
Input power measurement bit resolution
Input voltage measurement range
%
8
%
W
V
16
VINSNSM –AGND
Input voltage measurement accuracy
datapoint
MVIN(acc)
MVIN(acc)
MVIN(acc)
8
12
16
V
V
V
VINSNSM –AGND. TJ = 0℃to 85℃
Input voltage measurement accuracy
datapoint
VINSNSM –AGND. TJ = 0℃to 85℃
VINSNSM –AGND. TJ = 0℃to 85℃
Input voltage measurement accuracy
datapoint
MVIN(acc)
MVIN(lsb)
Input voltage measurement accuracy
%
0
%
8 V≤VINSNSM ≤16 V
VINSNSM –AGND
Input voltage measurement bit resolution
V
A
(B3h) PIN_SENSE_RES = 100b (1.0 mΩ),
101b (0.5 mΩ)
MIIN(rng)
MIIN(acc)
MIIN(acc)
Input current measurement range
32
Input current measurement accuracy
datapoint
Room temp, PIN_SENSE_RES set
accordingly
15
25
A
A
Input current measurement accuracy
datapoint
Room temp, PIN_SENSE_RES set
accordingly
MIIN(acc)
MIIN(lsb)
Input current measurement accuracy
Input current measurement bit resolution
Internal temperature sense range
%
%
A
MTSNS(rng)
125
°C
–40
Internal temperature sense accuracy
datapoint
MTSNS(acc)
MTSNS(acc)
MTSNS(acc)
MTSNS(acc)
MTSNS(acc)
-40
0
°C
°C
°C
°C
°C
Internal temperature sense accuracy
datapoint
Internal temperature sense accuracy
datapoint
25
85
125
Internal temperature sense accuracy
datapoint
Internal temperature sense accuracy
datapoint
MTSNS(acc)
MTSNS(lsb)
Internal temperature sense accuracy
%
%
–40°C ≤TJ ≤125°C
Internal temperature sense bit resolution
°C
SVID Timing and Physical Characteristics
CPAD_SVID
CPIN_SVID
SVID pin pad capacitance(1)
SVID pin capacitance(1)
0
0
4
5
pF
pF
VDS max open drain buffer to accommodate
ringing on bus
VMAX_SVID
3.3
V
–1
VIL_SVID
SV_CLK, SV_DIO input low voltage
SV_CLK, SV_DIO input high voltage
SV_CLK, SV_DIO input voltage hysteresis
0.45
0.54
0.05
0.5
0.55
0.64
V
V
V
VIH_SVID
VHYS_SVID
0.59
SV_DIO, SV_ALERT# pins pulldown
resistance
RRSVIDL
Open Drain Pulldown resistance
Input leakage current
4
8
13
20
Ω
ILKG_SVID
Pullup source = 5.5 V, off state
µA
SVID clock duty ratios (Period and duty
cycle are measured with respect to 0.5 x
VccIO)
DCLK_SVID
0.4
0.6
12
VR Clock to Data delay without board
parasitic
tCO_VR_SVID
ns
tSU_VR_SVID
tH_VR_SVID
Setup time of data at VR side
Hold time of data at VR side
CPU Clock to Data delay
7
14
ns
ns
ns
tCO_CPU_SVID
Measured at bump
0.65
–3.6
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; -40°C, 0°C, 25°C, 85°C, 125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted).
Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
ns
tSU_CPU_SVID
tH_CPU_SVID
SRF_DATA
Setup time of data at CPU side
Hold time of data at CPU side
Falling slew rate of SV_DIO(1)
Rising slew rate of SV_DIO(1)
3
ns
1.2
1.1
4
V/ns
V/ns
SV_DIO from 0.735V to 0.315V, Rpu=64.9Ω
SV_DIO from 0.315V to 0.735V, Rpu=64.9Ω
SRR_DATA
3.6
SV_ALERT# from 0.735V to 0.315V,
Rpu=75Ω
SRF_ALERT
Falling slew rate of SV_ALERT#(1)
1.25
4.2
3.3
V/ns
SV_ALERT# from 0.315V to 0.735V,
Rpu=75Ω
SRR_ALERT
FREQSVID
Rising slew rate of SV_ALERT#(1)
Max SVID Clock frequency Support
1.15
43
V/ns
MHz
I2C Timing and Physical Characteristics
FREQI2C
VIH_I2C
VIL_I2C
VHYS_I2C
NWRNVM
CBUS_I2C
CPIN_I2C
tH_STA
I2C operating frequency range
50
0.535
0.465
0.05
1000
0
1000
0.635
0.565
kHz
V
SM_CLK, SM_DIO High-level input voltage
SM_CLK, SM_DIO Low-level input voltage
SM_CLK, SM_DIO Input voltage hysteresis
Number of NVM writeable cycles (1)
I2C bus capacitance on each bus line(1)
I2C pin capacitance(1)
0.585
0.515
V
V
Cycles
pF
pF
µs
µs
µs
µs
µs
ns
–40°C ≤TJ ≤125°C
400
10
0
Hold time for a (repeated) START condition
Low period of SM_CLK
0.26
0.5
tLOW
tHIGH
High period of SM_CLK
0.26
0.26
0
tSU_STA
tH_I2C
Setup time for a repeated START condition
I2C DATA hold time
tSU_I2C
I2C DATA setup time
50
100 kHz class
400 kHz class
1000 kHz class
100 kHz class
400 kHz class
1000 kHz class
1000
300
ns
tR_I2C
SM_CLK and SM_DIO rise time(1)
ns
120
ns
1000
300
ns
tF_I2C
SM_CLK and SM_DIO fall time(1)
Setup time for a STOP condition
ns
120
ns
tSU_STO
tBUF
0.26
0.5
µs
Bus free time between a STOP and START
condition
µs
(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purpose of TI's
product warranty.
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6.6 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
0
9
8
7
6
5
4
3
2
1
0
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
VCC = Internal LDO VOUT = 1.1 V
PVIN = 12 V
VCC = Internal LDO
VOUT = 1.1 V
MODE = FCCM
MODE = FCCM
图6-1. Efficiency vs Output Current
图6-2. Power Dissipation vs Output Current
100
90
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
1
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
VCC = External 5-V
Bias
VOUT = 1.1 V
PVIN = 12 V
VCC = External 5-V
Bias
VOUT = 1.1 V
MODE = FCCM
MODE = FCCM
图6-3. Efficiency vs Output Current
图6-4. Power Dissipation vs Output Current
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100
90
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
1
0
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
VCC = External 5-V
Bias
VOUT = 1.1 V
PVIN = 12 V
VCC = External 5-V
Bias
VOUT = 1.1 V
MODE = DCM
MODE = DCM
图6-5. Efficiency vs Output Current
图6-6. Power Dissipation vs Output Current
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7 Detailed Description
7.1 Overview
The TPS544C26 device is highly integrated buck converter with D-CAP+ control topology for fast transient
response and reduced output capacitance. All programmable parameters can be configured by the I2C interface
and stored in NVM as the new default values to minimize the external component count. These features make
the device well-suited for space-constrained applications. The TPS544C26 device is designed for low-to-mid
current SVID rails in Intel’s server and SoC CPUs. The TPS544C26 device with SVID and I2C interface feature
can be configured for single phase CPU power rail.
Over-current, Over-voltage, and Under-voltage, Overtemperature protections are provided internally in the
device. The TPS544C26 device offers a full set of telemetry features, including output voltage, output current, IC
temperature, and input power monitoring through an external sensing resistor. TPS544C26 is a lead-free device
and is RoHS compliant without exemption.
7.2 Functional Block Diagram
VDRV
To ADC
On-die
Boot switch
DNC
NC
Temperature sense
OT Fault
BOOT
PVIN
VOUT OV/UV
Detection
VDIFF
VCC
EN_PWM
R1
R2
+
–
VOSNS
GOSNS
Integration
Loop Compensation
Driver Logic,
Anti-cross-
conduction,
VCOMP
Vramp
PWM
Ramp
Generator
SW
+
+
–
PWM
Control logic
VDRV
BOOT-SW
UVLO
VIsns
Current Sense
gain
VINSENP
VINSENM
Isense
Isense
VIN & IIN Sense
Valley current limit
Negative OC
Low-side current sense
PGND
Zero-cross detection
VDIFF
Adaptive
On-time
VDAC
Temp
Isns
Generator
PVIN
VCC/
VDRV
AFE and ADC
4.5V LDO
1.8V LDO
EN_PWM
SV_CLK
SV_DIO
AGND
Digital Core
&
SV_ALERT#
AGND
NVM
I2C_SCL
I2C_SDA
I2C_ADDR
EN
VRRDY
CAT_FAULT#
7.3 Feature Description
7.3.1 Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
TPS544C26 device has an internal 4.5-V LDO featuring input from PVIN and output to VCC/VDRV pin. When
the PVIN voltage rises, the internal LDO is enabled automatically and starts regulating LDO output voltage on
the VCC/VDRV pin. The VCC voltage provides the bias voltage for the internal analog circuitry in controller side
and the VDRV voltage provides the supply voltage for the power stage side.
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A 2.2-μF or 4.7-μF, at least 6.3-V rating ceramic capacitor must be closely placed from VCC/VDRV pin to
PGND pin to decouple the noise generated by driver circuitry. Referring this decoupling capacitor to AGND
introduces extra noise to the analog circuitry in controller, which likely causes more noise on digital interface
pins.
An external bias ranging 4.75-V to 5.30-V can be connect to VCC/VDRV pin and power the IC. This enhances
the efficiency of the solution because the VCC and VDRV power supply current now runs off this external bias
instead of the internal linear regulator.
A VCC UVLO circuit monitors the VCC/VDRV pin voltage and disables the switching when VCC falls below the
VCC UVLO falling threshold. Maintaining a stable and clean VCC/VDRV voltage is required for a smooth
operation of the device.
Considerations when using an external bias on the VDRV and VCC pin are shown below:
• Connect the external bias to VCC/VDRV pin.
• When the external bias is applied on the VCC/VDRV pin earlier than PVIN rail, the internal LDO is be always
forced off and the internal analog circuits have a stable power supply rail at their power enable.
• (Not recommended) When the external bias is applied on the VCC/VDRV pin late (for example, after PVIN
rail ramp-up), any power-up and power-down sequencing can be applied as long as there is no excess
current pulled out of the VCC/VDRV pin. Understand that an external discharge path on the VCC/VDRV pin,
which can pull a current higher than the current limit of the internal LDO, can potentially turn off VCC LDO
thereby shutting off the converter output.
• A good power-up sequence is: the external 5-V bias is applied first, then the 12 V bus is applied on PVIN,
and then EN signal goes high.
7.3.2 Input Undervoltage Lockout (UVLO)
The TPS544C26 device provides four independent UVLO functions for the broadest range of flexibility in start-up
control. While only the fixed VCC UVLO is required to enable I2C connectivity as well as PIN/IOUT/VOUT/
TEMPERATURE monitoring, all four UVLO functions must be met before switching can be enabled.
7.3.2.1 Fixed VCC UVLO
The TPS544C26 device has an internally fixed UVLO of 3.2 V (typical) on VCC to enable the digital core and
initiate power-on reset, including pin strap detection. The off-threshold on VCC is 3.1 V (typical). Once VCC level
rises above 3.2 V (typical) and stays above 3.1 V (typical), the I2C communication is enabled.
7.3.2.2 Fixed VDRV UVLO
The TPS544C26 device has an internally fixed UVLO of 3.6 V (typical) on VDRV to enable drivers for power
FETs and output voltage conversion. The off-threshold on VDRV is 3.4 V (typical).
7.3.2.3 Programmable PVIN UVLO
Two I2C commands ((35h) VIN_ON and (36h) VIN_OFF) allow the user to set PVIN voltage turn-on and turn-off
thresholds independently.
The highest register data value on each command (VIN_ON = 11b or VIN_OFF = 111b) utilizes multiple UVLO
circuitries (VCC, VDRV and PVIN UVLO) to enable or disable the power conversion. When VIN_ON = 11b is
selected, both PVIN > 2.55 V and VCC > 3.8 V conditions have to be satisfied to enable the power conversion.
When VIN_OFF = 111b is selected, either PVIN ≤ 2.3 V or VDRV ≤ 3.4 V disables the power conversion. This
particular configuration together with an external 5 V bias on VCC/VDRV pin allows power conversion under low
PVIN condition down to 2.7 V, as long as the external bias maintains at 5 V level to satify both the VCC rising
threshold (3.8 V typical) and the VDRV falling threshold (3.4 V typical).
表7-1. PVIN_ON Thresholds
PVIN_ON[1:0]
PVIN_ON Threshold (V)
00
01
10
10
9
8
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表7-1. PVIN_ON Thresholds (continued)
PVIN_ON[1:0]
PVIN_ON Threshold (V)
11
ON threshold by both PVIN and VCC conditions. See (35h) VIN_ON
表7-2. PVIN_OFF Thresholds
PVIN_OFF[2:0]
PVIN_OFF Threshold (V)
000
001
010
011
100
101
110
4.2
9.5
8.5
7.5
6.5
5.5
4.2
ON threshold by both PVIN and VDRV conditions. See (36h)
VIN_OFF
111
备注
If VIN_OFF is programmed higher than VIN_ON, the TPS544C26 device rapidly switches between
enabled and disabled while PVIN remains below VIN_OFF. Please set (35h) VIN_ON threshold
always greater than (36h) VIN_OFF threshold.
7.3.2.4 Enable
The TPS544C26 device offers precise enable, disable threshold on EN pin. The power stage switching is held
off until EN pin voltage rises above the logic high threshold (typically 1.2 V). The power stage switching is turned
off after EN pin voltage drops below the logic low threshold (typically 1 V).
EN pin has an internal filter to avoid unexpected ON or OFF due to short glitches. The deglitch time is set to 0.2
µs.
The recommended operating condition for EN pin is up to 5.3 V and the absolute maximum rating is 5.5 V. DO
NOT connect the EN pin to PVIN pin directly.
The TPS544C26 device remains disabled state when EN pin floats. EN pin is internally pulled down to AGND
through a 121-kΩ resistor.
7.3.3 Differential Remote Sense and Internal Feedback Divider
The TPS544C26 includes a fully integrated, internal, precision feedback divider and remote sense. Using both
the selectable feedback divider and precision adjustable reference, output voltages up to 3.04 V can be
obtained. The feedback divider can be programmed to divider ratios of 1:2 or 1:4 using the PROTOCOL_ID in
register (C2h) PROTOCOL_ID_SVID.
The recommended operating VOUT range is dependent upon the feedback divider ratio configured by
PROTOCOL_ID as follows:
表7-3. VOUT Step and Recommended VOUT Range
VOUT Control
Method
Internal FB Divider
Ratio
Recommended VOUT Range
(V)
VOUT_CTRL
VOUT Step
00b
01b
SVID only
SVID + I2C
I2C only
5 mV (PROTOCOL_ID = 01b or
10b)
1:2
1:4
0.25 to 1.52
0.5 to 3.04
10b or 11b
00b
SVID only
SVID + I2C
I2C only
10 mV (PROTOCOL_ID = 00b or
11b)
01b
10b or 11b
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Setting VOUT lower than the recommended range can negatively affect VOUT regulation accuracy. Setting
VOUT above the recommended range is not achievable due to internal hardware limitation.
备注
Do not to use extra external divider to set VOUT higher than the recommended range. Using external
divider leads to higher switching frequency than the desired value set in register (33h)
FREQUENCY_SWITCH. The switching frequency shift varies depending on the delta between internal
VOUT setting and the actual VOUT setting determined by the external divider. The more delta on
internal vs external VOUT, the higher switching frequency shift.
The TPS544C26 device offers true differential remote sense function which is implemented between VOSNS pin
and GOSNS pin. The output of the differential remote sense amplifier is internally fed into the control loop and
doesn’t come out to a package pin.
Differential remote sense function compensates a potential voltage drop on the PCB traces thus helps maintain
VOUT accuracy under steady state operation and load transient event. Connecting the VOSNS pin and GOSNS
pin to the remote location allows sensing the output voltage at a remote location. The connections from VOSNS
pin and GOSNS pin to the remote location must be a pair of PCB traces with at least 12 mil trace width, and
must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of
the remote sensing signal must be connected to GOSNS pin. The VOUT connection of the remote sensing
signal must be connected to VOSNS pin. To maintain stable output voltage and minimize the ripple, the pair of
remote sensing lines must stay away from any noise sources such as inductor and SW node, or high frequency
clock lines. It is recommended to shield the pair of remote sensing lines with ground planes above and below.
The recommended GOSNS operating range (refer to AGND pin) is −100 mV to +100 mV. In case of local sense
(no remote sensing), short GOSNS pin to AGND.
7.3.4 Set the Output Voltage and VID Table
The TPS544C26 device offers VOUT adjustment through either SVID interface (for example, VID related SVID
commands) or I2C interface (for example, (A6h) VOUT_CMD register). To allow flexibility and also avoid conflict,
the device utilizes VOUT_CTRL[1:0] bits in register (A0h) SYS_CFG_USER1 to select which interface or method
controls the VOUT level during the soft-start and nominal operation target. 表7-4 describes more details.
The VOUT_CTRL value is latched after the power conversion is enabled (EN=high). While the device is enabled,
a write to VOUT_CTRL bits are acknowledged but the VOUT control method does not change until an EN toggle
happens.
表7-4. VOUT Control Method
VOUT
Control
Method
Start-up
Nominal Operation
VOUT_
CTRL
Maximum VOUT
Limit
Further Restrictions
VOUT
VOUT Offset
VOUT
VOUT Offset
I2C register (A6h)
VOUT_CMD is always
ignored (ACK response for
a write but does nothing).
I2C register (A8h)
I2C_OFFSET is de-
activated (NACK response
for a write)
Set by SVID
register (33h)
OFFSET. This commands (such
offset is always
zero before
EN=high
Set by Vboot in
I2C register
(C2h)
PROTOCOL_ID_
SVID
Set by SVID
Set by SVID
register (33h)
OFFSET
SVID register
09h-0Ah
VIDoMAX
SVID
only
00b
as SetVID,
SetWP)
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表7-4. VOUT Control Method (continued)
VOUT
Control
Method
Start-up
Nominal Operation
VOUT_
CTRL
Maximum VOUT
Further Restrictions
Limit
VOUT
VOUT Offset
VOUT
VOUT Offset
Set by I2C
register (A8h)
I2C_OFFSET. A
new
I2C register (A6h)
VOUT_CMD is always
ignored (ACK response for
a write but does nothing).
SVID register (33h)
OFFSET is ignored (ACK
response for a write but
does nothing)
Set by Vboot in
I2C register
(C2h)
Set by SVID
I2C_OFFSET
Set by I2C
register (A8h)
SVID register
09h-0Ah
VIDoMAX
SVID +
I2C
commands (such value does not
01b
as SetVID,
SetWP)
take effect
immediately.
Instead, the new
value takes effect
on the next start-
up
PROTOCOL_ID_ I2C_OFFSET
SVID
Set by I2C
register (A8h)
I2C_OFFSET. A
new
Set by I2C
register (A6h)
VOUT_CMD. A
new VOUT_CMD
value takes effect
immediately.
SVID SetVID/SetWP
command and SVID
register (33h) OFFSET are
always ignored (ACK
response for a write but
does nothing)
Set by I2C
Set by I2C
register (A8h)
I2C_OFFSET
10b or
11b
I2C only register (A6h)
VOUT_CMD
17E in hex
I2C_OFFSET
value takes effect
immediately.
With VOUT_CTRL[1:0] = 00b or 01b (VOUT controlled by SVID), the initial output voltage can be set by the
Vboot during initial power up, with the range from 0.75 V to 1.8 V (see 表 7-5). Vboot value can be adjusted
through a write into the Vboot filed in I2C register (C2h) PROTOCOL_ID_SVID. Upon the acknowledge of the I2C
write, the new Vboot value is automatically copied into SVID (26h) Vboot register. With a successful I2C (15h)
STORE_USER_ALL command, this new value is saved into NVM. During next power-on sequence, TPS544C26
loads the saved Vboot value from NVM into both I2C Vboot field and SVID (26h) Vboot register. Once the soft-
start ramp finishes, the output voltage can be changed by sending SetVID or SetWP command to the device, or
sending a new SVID OFFSET value to the device.
With VOUT_CTRL[1:0] = 10b or 11b (VOUT controlled by I2C), the initial output voltage can be set by the
register (A6h) VOUT_CMD during initial power up. The available VOUT_CMD range is 0.25 V to 1.52 V for
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV), and 0.50 V to 3.04 V for PROTOCOL_ID = 00b or 11b
(VOUT step = 10 mV). Once the soft-start ramp finishes, the output voltage can be changed by sending new
value to I2C register (A6h) VOUT_CMD, or sending a new (A8h) I2C_OFFSET value to the device. Upon the
acknowledge of a I2C write into I2C register (A6h) VOUT_CMD or (A8h) I2C_OFFSET, the new value takes effect
immediately. With a successful I2C (15h) STORE_USER_ALL command, this new value is saved into NVM.
During next power-on sequence, TPS544C26 loads the saved value from NVM and use that value for the soft-
start.
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表7-5. Vboot Settings
Vboot in (C2h)
PROTOCOL_ID_SVID
PROTOCOL_ID in (C2h)
PROTOCOL_ID_SVID
VID code1 (Hex)
Vboot (V)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
00h
65h
6Fh
79h
83h
8Dh
97h
A1h
ABh
AFh
C9h
DDh
FBh
6Fh
79h
83h
0
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.20
1.25
1.35
1.50
1.60
1.70
1.80
Must set PROTOCOL_ID = 01b
or 10b (VOUT step = 5 mV)
Must set PROTOCOL_ID = 00b
or 11b (VOUT step = 10 mV)
1. VID code is not directly visiable to customer but shows up in I2C register (A7h) VID_SETTING and SVID
register (31h) VID_SETTING.
TPS544C26 always follows below VID table when setting output voltage, no matter through SVID interface or
I2C interface. When setting output voltage, aligning the VOUT value with PROTOCOL_ID (5 mV or 10 mV)
accordantly is important. An incorrect selection on the VOUT and PROTOCOL_ID value can result in a NACK
response for the write into (C2h) PROTOCOL_ID_SVID register. For example, a configuration of Vboot = 1.8 V
and PROTOCOL_ID = 01b (VOUT step 5 mV) results in a NACK response. Another example with
VOUT_CTRL[1:0] = 10b or 11b (VOUT controlled by I2C), setting VOUT_CMD to 2.5 V requires PROTOCOL_ID
= 00b or 11b (VOUT step 10 mV) and thus requires Vboot to be one of the 3 options of 1.6 V, 1.7 V and 1.8 V.
Even the Vboot value does not affect VOUT level for VOUT_CTRL[1:0] = 10b or 11b selection, a suitable Vboot
value is needed to pass the error check on Vboot and PROTOCOL_ID fields.
表7-6. VID Table for Output Voltage
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VID code
(Hex)
VID Code
(Hex)
VID Code
(Hex)
VID Code
(Hex)
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0.000
0.250
0.255
0.260
0.265
0.270
0.275
0.280
0.285
0.290
0.295
0.300
0.305
0.310
0.00
0.50
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
0.565
0.570
0.575
0.580
0.585
0.590
0.595
0.600
0.605
0.610
0.615
0.620
0.625
0.630
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.935
0.940
0.945
0.950
1.77
1.78
1.79
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
2.41
2.42
2.43
2.44
2.45
2.46
2.47
2.48
2.49
2.50
2.51
2.52
2.53
2.54
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表7-6. VID Table for Output Voltage (continued)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VID code
(Hex)
VID Code
(Hex)
VID Code
(Hex)
VID Code
(Hex)
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
0E
0F
10
11
0.315
0.320
0.325
0.330
0.335
0.340
0.345
0.350
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
0.400
0.405
0.410
0.415
0.420
0.425
0.430
0.435
0.440
0.445
0.450
0.455
0.460
0.465
0.470
0.475
0.480
0.485
0.490
0.495
0.500
0.505
0.510
0.515
0.520
0.525
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
0.635
0.640
0.645
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0.715
0.720
0.725
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
0.825
0.830
0.835
0.840
0.845
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.40
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
1.69
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
0.955
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
1.025
1.030
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
1.125
1.130
1.135
1.140
1.145
1.150
1.155
1.160
1.165
1.91
1.92
1.93
1.94
1.95
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
2.05
2.06
2.07
2.08
2.09
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
2.33
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
1.275
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
1.325
1.330
1.335
1.340
1.345
1.350
1.355
1.360
1.365
1.370
1.375
1.380
1.385
1.390
1.395
1.400
1.405
1.410
1.415
1.420
1.425
1.430
1.435
1.440
1.445
1.450
1.455
1.460
1.465
1.470
1.475
1.480
1.485
2.55
2.56
2.57
2.58
2.59
2.60
2.61
2.62
2.63
2.64
2.65
2.66
2.67
2.68
2.69
2.70
2.71
2.72
2.73
2.74
2.75
2.76
2.77
2.78
2.79
2.80
2.81
2.82
2.83
2.84
2.85
2.86
2.87
2.88
2.89
2.90
2.91
2.92
2.93
2.94
2.95
2.96
2.97
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
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表7-6. VID Table for Output Voltage (continued)
VOUT (V) VOUT (V)
VID code
(Hex)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VOUT (V) VOUT (V)
VID Code
(Hex)
VID Code
(Hex)
VID Code
(Hex)
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
5-mV
Step
10-mV
Step
39
3A
3B
3C
3D
3E
3F
0.530
0.535
0.540
0.545
0.550
0.555
0.560
1.06
1.07
1.08
1.09
1.10
1.11
1.12
79
7A
7B
7C
7D
7E
7F
0.850
0.855
0.860
0.865
0.870
0.875
0.880
1.70
1.71
1.72
1.73
1.74
1.75
1.76
B9
BA
BB
BC
BD
BE
BF
1.170
1.175
1.180
1.185
1.190
1.195
1.200
2.34
2.35
2.36
2.37
2.38
2.39
2.40
F9
FA
FB
FC
FD
FE
FF
1.490
1.495
1.500
1.505
1.510
1.515
1.520
2.98
2.99
3.00
3.01
3.02
3.03
3.04
7.3.5 Startup and Shutdown
Startup
The startup sequence includes three sequential periods. During the first period, the device does initialization
which includes building up internal LDOs and references, register value initialization, pin strap detection,
enabling digital interface, and so forth. The initialization, which is not gated by EN pin voltage, starts as long as
VCC/VDRV pin voltage is above the VCC UVLO rising threshold (3.2-V typical). The length of this period is
about 200 μs for TPS544C26 device. The I2C communication including both read and write operations is
allowed after finishing the initialization.
Once the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second
period, power-on delay. The power-on delay is programmable in TPS544C26 through register (60h)
TON_DELAY with minimum 0.5 ms delay and maximum 2 ms delay.
The VOUT soft-start is the third period. A soft-start ramp, which is an internal signal, starts when the chosen
power-on delay finishes. The soft-start time can be selected in register (61h) TON_RISE with options of 1 ms, 2
ms, 4 ms, 8 ms, and 16 ms. When starting up without pre-bias on the output, the VOUT ramps up from 0 V to
either the selected Vboot value or the programmabled VOUT_CMD value (depending on the VOUT_CTRL
setting) to avoid the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The
VOUT ramping up slew rate is determined by VOUT step (set by PROTOCOL_ID in register (C2h)
PROTOCOL_ID_SVID, Vboot and TON_RISE values, and the actual soft-start time can vary from the selected
TON_RISE value. 表7-7 shows more details.
For the startup with a pre-biased output the device limits current from being discharged from the prebiased
output voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns
on the high-side FET. Once the increasing reference voltage exceeds the feedback voltage which is internally
divided down from (VOSNS−GOSNS) level, the high-side SW pulses start. This enables a smooth startup with a
pre-biased output.
Once VOUT reaches the regulation value and VRRDY delay expires, the converter asserts VRRDY pin and
becomes ready for SVID commands. The VRRDY delay can be programmed in (A0h) SYS_CFG_USER1
register and the default value is set to 0 ms to meet SVID communication requirement.
表7-7. Soft-start Slew Rate and the Actual Soft-start Time
VOUT
Control
Method
VOUT_CTR
L
Soft-start Slew Rate
(V/ms)
VOUT Step
Actual Soft-start Time (ms)
00b
SVID only
SVID + I2C
I2C only
5 mV or 10 mV
5 mV or 10 mV
5 mV
Vboot / TON_RISE
Vboot / TON_RISE
1.1 V / TON_RISE
1.8 V / TON_RISE
TON_RISE
01b
(1 + I2C_OFFSET / Vboot) × TON_RISE
(VOUT_CMD + I2C_OFFSET) / 1.1 V × TON_RISE
(VOUT_CMD + I2C_OFFSET) / 1.1 V × TON_RISE
10b or 11b
10b or 11b
I2C only
10 mV
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Shutdown
The TPS544C26 device also offers programmable soft-stop feature through I2C register (65h) TOFF_FALL with
0.5 ms, 1 ms, 2 ms, and 4 ms options. The soft-stop feature force a controlled decrease of the output voltage
from regulation to 200 mV. Once Vout is discharged to 200 mV level the power stage stops switching and goes
to tri-state. There can be negative inductor current forced during the TOFF_FALL time to discharge the output
voltage. This feature can be enabled or disabled through I2C. Configuring EN_SOFT_STOP bit in register (A0h)
SYS_CFG_USER1 to value “0”disables the soft-stop feature and automatically sets TOFF_DELAY to 0 ms.
In the case of Soft-stop is enabled, after a stop condition is received and the selected TOFF_DELAY delay
expires, the TPS544C26 device enters the soft-stop operation during which the control loop actively controls the
discharge slew rate of the output voltage. The power stage continues switching while the internal reference
ramps down linearly. The discharge slew rate during this phase is determined by the selected boot up voltage
(not the current output voltage) and the selected TOFF_FALL time. Once Vout is discharged to 200 mV level the
power stage stops switching and goes to tri-state. The Vout discharge continues but the discharge slew rate is
controlled by the load current. With this discharge operation, the TPS544C26 device controls the soft-stop slew
rate rather the total soft-stop time, thus the total VOUT discharge time (a.k.a soft-stop time) can vary from the
register (65h) TOFF_FALL value. Another word, The TOFF_FALL time is utilized to set the internal reference
DAC ramp-down time from the regulation level to 0 mV. For example, under heavy load condition, the total soft-
stop time from VOUT regulation level to zero volt is likely shorter than the programmed TOFF_FALL value.
Under light load, the total soft-stop time likely becomes longer than the programmed TOFF_FALL value. Table
Soft-stop Slew Rate and the Actual Soft-stop Time shows more details.
In the case of soft-stop feature is disabled through the EN_SOFT_STOP bit in (A0h) SYS_CFG_USER1 register,
both high-side and low-side FET drivers are turned off immediately at the time when a stop condition is received
(as programmed by the (02h) ON_OFF_CONFIG command), and the output voltage discharge slew rate is
controlled by the external load.
表7-8. Soft-stop Slew Rate and the Actual Soft-stop Time
VOUT
Control
Method
VOUT_CTR
L
Soft-stop Slew Rate
(V/ms)
VOUT Step
Actual Soft-stop Time (ms)
(Current VOUT − 0.2 V) / Vboot × TOFF_FALL +
00b
SVID only
SVID + I2C
I2C only
5 mV or 10 mV
5 mV or 10 mV
5 mV
Vboot / TOFF_FALL
Vboot / TOFF_FALL
1.1 V / TOFF_FALL
1.8 V / TOFF_FALL
(1)
tDELAY
(Current VOUT − 0.2 V) / Vboot × TOFF_FALL +
01b
(1)
tDELAY
(Current VOUT − 0.2 V) / 1.1 V × TOFF_FALL + tDELAY
10b or 11b
10b or 11b
(1)
(Current VOUT − 0.2 V) / 1.8 V × TOFF_FALL + tDELAY
I2C only
10 mV
(1)
(1) Power stage switching ends at VOUT = 200 mV. tDELAY is determined by output capacitance and the load current.
space
7.3.6 Dynamic Voltage Slew Rate
TPS544C26 device offers (AFh) DVS_CFG register to set SetVID-Fast slew rate during dynamic voltage scaling.
SetVID command sets the new target voltage. During the output voltage transition, due to the quick charge or
discharge to output capacitors, the power stage sees extra inrush current. This inrush current plus load current
can trigger overcurrent protection when there is no sufficient room from OCL or NOC setting. For example, the
positive inductor current during VOUT step-up transition goes higher than nominal operation. If the LS valley
OCL threshold is set relatively low and doesn’t allow the extra inrush current, the inductor current is potentially
limited by the cycle-by-cycle overcurrent limit feature, thus the actual step-up slew rate is lower than the desired
value. Similar situation can happen to VOUT step-down transition with no load condition. The negative inductor
current during VOUT step-down transition goes more negative than nominal operation. However, the inductor
current is not allowed to go more negative than the Negative OC threshold. Thus, triggering NOC operation
during VOUT step-down transition results that the actual step-down slew rate is lower than the desired value.
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7.3.7 Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
TPS544C26 device supports adaptive voltage positioning (AVP) through DC Load Line (DCLL) setting in the
(ADh) COMP3 register. Use a non-zero DC load line reduces output voltage set-point as a function of the load
current, with a controlled slope. This feature is optional and the DCLL setting usually matches what the
processor suggests. If a processor doesn’t utilize Droop, setting DCLL to 0 mΩ is recommended to avoid
violating the VOUT tolerance band spec of the processor.
The DC load line provides two main benefits:
• Reducing the output voltage set-point, reduces the power consumption of the system, when the load current
is high.
• Adaptive voltage positioning increases the allowable undershoot and overshoot during load transient events.
Below figure compares example output voltage specifications for systems with zero load line and non-zero
load line. The nominal setting for the output voltage is chosen to be higher, to allow the entire transient
window as margin for transient overshoot and undershoot.
7.3.8 Loop Compensation
The TPS544C26 device provides several options for tuning the output voltage feedback and response to
transients. Register (A9h) COMP1_MAIN, (AAh) COMP2_MAIN and (ADh) COMP3 configure the control loop
compensation through these fields:
• DC Load Line: Selects the DC shift in output voltage corresponding to increased output current. See (ADh)
COMP3 for available options.
• AC Gain: The gain of the integration and AC paths can be selected independently. The AC and integration
gains both affect the small-signal bandwidth of the converter. The higher AC Gain, the faster the control loop
responds to an output voltage error or a change on the current sense signal. Too high AC Gain results in less
noise immunity (a.k.a higher jitter). See (A9h) COMP1_MAIN for available options.
• AC Load Line (ACLL): Selects the AC response to an output voltage error. Lower ACLL configuration directly
improves the load transient performance (less VOUT deviation). However, the control loop becomes noise
sensitive too low ACLL configuration. The ACLL also affects the settling and response time following a load
transient event. See (A9h) COMP1_MAIN for available options.
• Integration Gain: To maintain a good VOUT regulation over load, the control loop includes an integration
stage. Integration Gain selects the gain of the integration stage which affects the loop response to an output
voltage error. Given the integration time constant is several times of switching cycle time, the Integration Gain
affects the loop gain in middle frequency range. The gain of the integration and AC paths can be selected
independently. The integration and AC gains both affect the small-signal bandwidth of the converter. See
(AAh) COMP2_MAIN for available options.
• Integration Time Constant: The Integration Time Constant affects the settling and response time following an
output voltage error. See (AAh) COMP2_MAIN for available options.
• Ramp Amplitude: A ramp based on PVIN/VOUT/fSW information is generated inside the IC to improve jitter
performance. Smaller ramp settings result in faster response to load transient event, but also lead to
increased off-time jitter. Likewise, large ramp settings result in lower frequency jitter, but becomes slightly
slower to respond to an output voltage deviation. The ramp setting also affects the small-signal bandwidth of
the converter. See (AAh) COMP2_MAIN for available options.
7.3.9 Set Switching Frequency
TPS544C26 device provides programmable operation mode including the forced CCM operation for tight output
voltage ripple and auto-skipping Eco-mode for high light-load efficiency. The TPS544C26 device allows users to
select the switching frequency through (33h) FREQUENCY_SWITCH register and operation mode through
FCCM bit in (A0h) SYS_CFG_USER1. The available switching frequency options are 600 kHz, 800 kHz, 1 MHz
and 1.2 MHz.
The FCCM bit is set during initial power-on and latched after the power conversion is enabled (EN=high). While
the device is enabled, a write to FCCM bit ia acknowledged but the operation mode does not change until an EN
toggle happens.
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表7-9. Switching Frequency Options
(33h) FREQUENCY_SWITCH (Hex)
fSW (kHz)
00
01
02
03
600
800
1000
1200
7.3.10 Switching Node (SW)
The SW pins connect to the switching node of the power conversion stage. The SW pins act as the return path
for the high-side gate driver. During nominal operation, the voltage swing on SW normally traverses from below
ground to above the input voltage. Parasitic inductance in the PVIN to PGND loop (including the component
from the PCB layout and also the component inside the package) and the output capacitance (COSS) of both
power FETs form a resonant circuit that can produce high frequency (> 100 MHz) ringing on this node. The
voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. TPS544C26 high-
side gate driver is fine tuned to minimize the peak ringing amplitude so that a RC snubber on SW node is usually
not needed. However, it is highly recommended for the user to measure the voltage stress across either the
high-side or low-side FET and ensure that the peak ringing amplitude does not exceed the absolute maximum
rating limit listed in the Absolute Maximum Ratings table.
7.3.11 Overcurrent Limit and Low-side Current Sense
For a synchronous buck converter, the inductor current increases at a linear rate determined by the input
voltage, the output voltage, and the output inductor value during the high-side MOSFET on-time (ON time).
During the low-side MOSFET on-time (OFF time), this inductor current decreases linearly per slew rate
determined by the output voltage and the output inductor value. The inductor during the OFF time, even with a
negative slew rate, usually flows from the device SW node to the load the device which is said to be sourcing
current and the output current is declared to be positive. This section describes the overcurrent limit feature
based on the positive low-side current. The next section describes the overcurrent limit feature based on the
negative low-side current.
The positive overcurrent limit (OCL) feature in the TPS544C26 device is implemented to clamp low-side valley
current on a cycle-by-cycle basis. The inductor current is monitored during the OFF time by sensing the current
flowing through the low-side MOSFET. When the sensed low-side MOSFET current remains above the selected
OCL threshold, the low-side MOSFET stays ON until the sensed current level becomes lower than the selected
OCL threshold. This operation extends the OFF time and pushes the next ON time (where the high-side
MOSFET turns on) out. As a result, the OCL bit in (7Bh) STATUS_IOUT is set, also the average output current
sourced by the device is reduced. As long as the load pulls a heavy load where the sensed low-side valley
current exceeds the selected OCL threshold, the device continuously operates in this clamping mode which
extends the current OFF time and pushes the next ON time out. The device does not implement a fault response
circuit directly tied to the overcurrent limit circuit, instead, the VOUT Tracking UVF function is utilized to shuts the
device down under an overcurrent fault. During an overcurrent event, the current sunk by the load (IOUT
)
exceeds the current sourced by the device to the output capacitors, thus, the output voltage tends to decrease.
Eventually, when the output voltage falls below the selected undervoltage fault threshold, the VOUT Tracking
UVF comparator detects and shuts down the device after the UVF Response Delay (programmable in (45h)
VOUT_UV_FAULT_RESPONSE register). The device then responds to the Tracking UVF trigger per bit[3]
RESTART selection in (45h) VOUT_UV_FAULT_RESPONSE register. With the RESTART bit unset (value "0"),
the device latches OFF both high-side and low-side drivers. The latch is cleared with a reset of VCC or by
toggling the EN pin. With the RESTART bit set (value "1"), the device enters hiccup mode and re-starts
automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts. In other
words, the response to an overcurrent fault is set by the programmed UVF response.
If an OCL condition happens during a soft-start ramp the device still operates with the cycle-by-cycle current limit
based on the sensed low-side valley current. This operation can limit the energy charged into the output
capacitors thus the output voltage likely ramps up slower than the desired soft-start slew rate. During the soft-
start, the VOUT Tracking UVF comparator is disabled thus the device does not respond to a UVF event. Upon
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the completion of the soft-start, the VOUT Tracking UVF comparator is enabled, then the device starts
responding to the UVF event.
The OCL feature in the device is implemented by detecting the low-side valley current through analog circuitries
and has no relationship with the integrated Analog-to-Digital converter (ADC). The telemetry analog-front-end
gets an input from the low-side current sense circuit and average low-side MOSFET current from the start to the
end of each low-side MOSFET on time. By this method, the telemetry sub-system reports the load current
(IOUT) which is the average value of the inductor current but not peak or valley values.
7.3.12 Negative Overcurrent Limit
The TPS544C26 device is a synchronous Buck converter, thus the current can flow from the device to the load
or from the load into the device through SW node. When current is flowing from the device SW node to the load
the device is said to be sourcing current and the output current declared to be positive. When current is flowing
into the device SW node from the load, the device is said to be sinking current and the current is declared to be
negative.
The device offers a programmable, cycle-by-cycle negative overcurrent (NOC) limit through (B4h)
IOUT_NOC_LIMIT register. The available NOC thresholds which scale with ICC_MAX setting (see ICC_MAX)
are shown in 表 7-10. Similar with the positive overcurrent limit, the inductor current is monitored during the low-
side MOSFET ON period. To prevent too large negative current and a damage of low-side MOSFET, the device
turns off the low-side MOSFET after the detected on the low-side MOSFET exceeds the selected NOC limit. And
then the high-side FET is turned on for an on-time determined by PVIN, SEL_NOC_TON bit (see (ADh) COMP3)
and fSW setting).
The NOC operation usually happens after an overvoltage event but can also happen during VOUT step-down
transition with fast slew rate.
表7-10. Negative Overcurrent Limits
Negative Overcurrent Limits (A)
SEL_NOC[1:0]
ICC_MAX ≥15 A
ICC_MAX ≤10 A
00
01
10
11
−20
−15
−12
−10
−10
−7.5
−6
−5
7.3.13 Zero-Crossing Detection
TPS544C26 device implements an internal circuit for the zero inductor-current detection during skip-mode
operation. The fixed Z-C detection threshold is set to a slightly positive value such as 300 mA to compensate the
delay time of the Z-C detection circuit and avoid too-late detection. Depending on the inductor value, frequency,
VIN and Vout conditions, this can result diode conduction for a short period.
7.3.14 Input Overvoltage Protection
The TPS544C26 device actively monitors the PVIN input voltage. When the PVIN voltage level is above the
over-voltage threshold, TPS544C26 device stops switching and pulls VRRDY signal low. Two options are
provided for PVIN OV rising threshold in (55h) VIN_OV_FAULT_LIMIT register while the PVIN OV falling
threshold is always 13.5V.
Once the PVIN over-voltage fault is triggered, the device latches off until EN pin is toggled or PVIN is reset.
7.3.15 Output Overvoltage and Undervoltage Protection
The TPS544C26 device monitors the output voltage (VOSNS − GOSNS) to provide overvoltage (OV) and
undervoltage (UV) protection. The Tracking OVF and Tracking UVF thresholds both track to the VOUT setting
(commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD) but can be selected independently.
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VOUT Tracking UVF
The 表 7-11 shows the available tracking UVF thresholds. When the output voltage (VOSNS − GOSNS) drops
below the VOUT setting by the value configured in (44h) VOUT_UV_FAULT_LIMIT register, the tracking UVF
comparator detects and an internal UVF Response Delay counter selected in (45h)
VOUT_UV_FAULT_RESPONSE register begins. At the same time, the UVF bit in (7Ah) STATUS_VOUT register
is set. When the UVF Response Delay expires, the device responds to the UV fault per bit[3] RESTART
selection in (45h) VOUT_UV_FAULT_RESPONSE register. With the RESTART bit unset (value "0"), the device
latches OFF both high-side and low-side drivers. The latch is cleared with a reset of VCC or by re-toggling the
EN pin. With the RESTART bit set (value "1"), the device enters hiccup mode and re-starts automatically after a
hiccup sleep time of 56 ms, without limitation on the number of restart attempts.
The tracking UVF function is enabled only after the soft-start period completes.
During the UVF Response Delay, if the output voltage (VOSNS − GOSNS) rises above the UVF threshold, thus
not qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the
UVF threshold again, the UVF response delay timer re-starts from zero.
The TPS544C26 device also offers tracking UV Warning (UVW) function. The 表 7-12 shows the available
tracking UVW thresholds. When the output voltage (VOSNS − GOSNS) drops lower than the VOUT setting by
the value configured in (43h) VOUT_UV_WARN_LIMIT register, the tracking UVW comparator detects and the
UVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for UVW event.
表7-11. VOUT Tracking UV Fault Thresholds
SEL_UVF[1:0]
VOUT Tracking UVF Threshold (mV)
00
01
10
11
−150
−200
−200
−300
表7-12. VOUT Tracking UV Warning Thresholds
SEL_UVW[1:0]
VOUT Tracking UVW Threshold (mV)
00
01
10
11
−100
−150
−200
−300
VOUT Tracking OVF
The 表 7-13 shows the available tracking OVF thresholds. When the output voltage (VOSNS − GOSNS) rises
higher than the VOUT setting by the value configured in (40h) VOUT_OV_FAULT_LIMIT register, the tracking
OVF comparator detects and the device responds to the OV fault immediately per bit[3] RESTART selection in
(41h) VOUT_OV_FAULT_RESPONSE register. At the same time, the OVF bit in (7Ah) STATUS_VOUT register
is set. With the RESTART bit unset (value "0"), the device latches OFF the high-side MOSFET driver and turns
on the low-side MOSFET. The low-side MOSFET is kept ON until the sensed low-side negative current reaches
the selected negative overcurrent (NOC) limit (see (B4h) IOUT_NOC_LIMIT register). Upon reaching the NOC
limit, the low-side MOSFET is turned off, and the high-side MOSFET is turned on, for an on-time determined by
PVIN, SEL_NOC_TON bit (see (ADh) COMP3) and fSW setting. After the high-side MOSFET turns off the low-
side MOSFET turns on again and the negative current on low-side MOSFET is monitored to compare with the
selected NOC limit. The device operates in this cycle until the output voltage is fully discharged. Then the device
has high-side MOSFET latched OFF and low-side MOSFET latched ON. The latch is cleared with a reset of
VCC or by toggling the EN pin. With the RESTART bit set (value "1"), the device still discharge output voltage by
the NOC operation. However, the device activates hiccup mode and re-starts automatically after a hiccup sleep
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time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter starts right
after the OVF trigger.
The tracking OVF function is enabled only after the soft-start period completes.
The TPS544C26 device also offers tracking OV Warning (OVW) function. The 表 7-14 shows the available
tracking OVW thresholds. When the output voltage (VOSNS − GOSNS) rises higher than the VOUT setting by
the value configured in (42h) VOUT_OV_WARN_LIMIT register, the tracking OVW comparator detects and the
OVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for OVW event.
表7-13. VOUT Tracking OV Fault Thresholds
SEL_OVF[1:0]
VOUT Tracking OVF Threshold (mV)
00
01
10
11
+100
+150
+200
+300
表7-14. VOUT Tracking OV Warning Thresholds
SEL_OVW[1:0]
VOUT Tracking OVW Threshold (mV)
00
01
10
11
+100
+150
+200
+300
VOUT Fixed OVF
In parallel with VOUT tracking OVF the TPS544C26 device offers Fixed OVF feature. The Fixed OVF
comparator implments a constant reference which is configured in (B4h) IOUT_NOC_LIMIT register and the
reference level does not track with the VOUT setting. The Fixed OVF comparator is activated to monitor the
output voltage (VOSNS − GOSNS) all the time including power conversion off period (EN = low) and soft-start
period. Once the VOUT Fixed OVF is triggered, the OVF bit in (7Ah) STATUS_VOUT register is set, and the
device enters NOC operation immediately no matter the power conversion is enabled or not. The device
operates in NOC operation to fully discharge the output voltage. Then the device has high-side MOSFET latched
OFF and low-side MOSFET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. A
Fixed OVF event always leads to latch-off response and the selected OVF response in (41h)
VOUT_OV_FAULT_RESPONSE register does not affect the response for a Fixed OVF event.
Given the Fixed OVF comparator is always activated the device provides alternate protection to high-side
MOSFET damage cases. When the high-side MOSFET is damaged and short PVIN to the SW node, the output
voltage (VOSNS − GOSNS) rises quickly. The TPS544C26 device can detect this kind of event and turn on low-
side MOSFET to discharge the excess energy, thus protecting the load from damage.
In a case that the commanded VOUT is higher than the Fixed OVF threshold, the device triggers Fixed OV fault
and enters the NOC operation immediately. If this scenario happens before soft-start, the device never initiate
the soft-start ramp and enters latch-off directly. To avoid this situation, the Fixed OVF feature can be disabled
through the bit[2] EN_FIX_OVF in (B4h) IOUT_NOC_LIMIT register.
表7-15. VOUT Fixed OV Fault Thresholds
PROTOCOL_ID in (C2h)
PROTOCOL_ID_SVID
SEL_FIX_OVF[1] in (B4h)
VOUT Fixed OVF Threshold (V)
IOUT_NOC_LIMIT
PROTOCOL_ID = 01b or 10b (VOUT step =
5 mV)
0
1
1.5
1.8
PROTOCOL_ID = 01b or 10b (VOUT step =
5 mV)
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表7-15. VOUT Fixed OV Fault Thresholds (continued)
PROTOCOL_ID in (C2h)
PROTOCOL_ID_SVID
SEL_FIX_OVF[1] in (B4h)
VOUT Fixed OVF Threshold (V)
IOUT_NOC_LIMIT
PROTOCOL_ID = 00b or 11b (VOUT step =
10 mV)
0
1
2.4
3.0
PROTOCOL_ID = 00b or 11b (VOUT step =
10 mV)
7.3.16 Overtemperature Protection
To have full coverage for a potential overtemperature event, the TPS544C26 device implements three
overtemperature protection circuitries - two on the Controller die and one on the Power Stage (PS) die.
Programmable OTP by Monitoring the Controller Die Temperature
The on-die temperature sense circuit senses the controller die temperature. The sensed signal is fed into an
internal ADC and converted to the Controller die temperature which is reported as (8Dh)
READ_TEMPERATURE_1 through the Telemetry sub-system. This feature utilizes a digital comparator that
compares the output of the IC TEMPERATURE telemetry to the fault threshold selected in (4Fh)
OT_FAULT_LIMIT register. The device stops the SW switching when the sensed IC temperature goes beyond
the selected threshold. The device response to a Programmable OTP event is described in (50h)
OT_FAULT_RESPONSE.
Analog OTP by Monitoring the Controller Die Temperature
The sensed temperature signal is fed into an analog OTP circuit on the Controller die as well. An analog
comparator is utilized to compare the output of the Controller die temperature sensing circuit to a fixed threshold
(rising 166 °C typical). The device stops the SW switching when the sensed IC temperature goes beyond the
fixed threshold. The device response to an Analog OTP event is always the same as the Programmable OTP.
Given the fixed threshold (166 °C typical) for the Analog OTP is higher than the highest setting (150 °C typical)
in Programmable OTP, the Analog OTP is unlikely to trigger during the nominal operation.
Analog OTP by Monitoring the Power Stage Die Temperature
A temperature sensing circuit is implemented in the Power Stage (PS) die. This sensed is fed into an analog
OTP circuit on the PS die. An analog comparator is utilized to compare the output of the PS die temperature
sensing circuit to a fixed threshold (rising 166 °C typical). The device stops the SW switching when the sensed
IC temperature goes beyond the fixed threshold. Once the PS die temperature falls 30 °C below the rising
threshold, the device automatically restarts with an initiated soft-start. This Analog OTP is a non-latch protection.
7.3.17 VR Ready
The TPS544C26 device offers VRRDY output that asserts high when the converter output is within the target.
The VRRDY output stays low when the switching is disabled either by EN pin or through I2C (01h) OPERATION
command. The VRRDY function is activated after the soft-start ramp is completed. The VRRDY output is an
open-drain output and must be pulled up externally through a pull-up resistor (usually 10 kΩ). The
recommended VRRDY pull-up resistor value is 1 kΩto 100 kΩ.
7.3.18 Catastrophic Fault Alert: CAT_FAULT#
The device has CAT_FAULT# output on pin 28 which alerts the system to potentially catastrophic power supply
faults. The CAT_FAULT# output is an open-drain output and must be pulled up externally through a pullup
resistor. The recommended CAT_FAULT# pull-up resistor value is 3.3 kΩ to 10 kΩ while pulling up to 3.3 V
voltage source through a 4.99 kΩ resistor is commonly used. The CAT_FAULT# function is activated after VCC/
VDRV pin voltage rises above VCC UVLO rising threshold (3.2V typical) regardless of by EN pin logic level.
Fault conditions which assert the CAT_FAULT# pin include:
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• Over-voltage fault detected by fixed VOUT OVP
• Over-voltage fault detected by tracking VOUT OVP
• Under-voltage fault detected by tracking VOUT UVP, including the an UV fault caused by overcurrent event
• Over-temperature fault (based on the threshold set through I2C in (4Fh) OT_FAULT_LIMIT register)
• Powerstage OT or VDRV_UV faults (Either fault asserts PS_FLT status bit in (80h) STATUS_MFR register)
Once asserted low by a fault event CAT_FAULT# pin latches low until a reset of PVIN or an EN toggle.
7.3.19 Telemetry
The telemetry sub-system in the controller core supports the following measurements:
• Input voltage (direct measurement)
• Input current (direct measurement)
• Output voltage (direct measurement)
• Output current (direct measurement)
• Controller die temperature (direct measurement)
• Input Power (Calculation, the product of the input voltage and the input current)
The ADC output is a single conversion of each measurement without rolling window averaging for fast refresh
rate of these key system parameter. All above parameters are measured sequentially while the Input current and
Output current are measured more often than the others. This sequence design allows each IIN or IOUT
telemetry value to be updated within 95 µs, while each of the rest of telemetry value to be updated within 190 µs.
Input Power Telemetry (VIN/IIN/PIN)
The input voltage sense telemetry senses the voltage level on pin 4 VINSENM. The device offers internal divider
to minimize the external component count and save solution size. The VIN reporting range is limited from 8 V to
16 V to improve the reporting resolution. For any VIN value less than 8 V, the VIN reports 8 V. For any VIN value
higher than 16 V, the VIN reports 16 V. For example, the READ_VIN reports 8 V for a VIN = 6 V condition. The
VIN conversion equation is:
VIN = READ_VIN × 0.03125 + 8
(1)
Where
• VIN is the voltage level seen on pin 4 VINSENM
• READ_VIN is the I2C (88h) READ_VIN register value in decimal
The input current sense telemetry senses the differntial voltage level across pin 3 VINSENP and pin 4
VINSENM. A high accuracy sensing resistor in series with the input bus is commonly used for this feature.
Together with the setting in (B3h) PIN_SENSE_RES register, the ADC converts the sensed differential voltage to
input current in amp. The device offers internal gain stage to minimize the external component count and save
solution size. Given the sensed differential voltage is in millivolts range and to avoid impact from the switching
noise on the input bus, a ceramic bypass capacitor is required on each pin (pin 3 VINSENP and pin 4 VINSENM)
referring to PGND and the recommended value is at least 100 pF with X7R temperature characterisitic. The IIN
conversion equation is:
IIN_MAX
256
IIN = READ_IIN ×
(2)
Where
• IIN is the input current level flowing through the choosen IIN sensing resistor
• READ_IIN is the I2C (89h) READ_IIN register value in decimal
• IIN_MAX is a maximum input current value selected in I2C (B3h) PIN_SENSE_RES register
The input power reported in (97h) READ_PIN register is a simple calculation, which is the product of the
measured raw input voltage and the measured raw input current. The calculation does not use the register value
in (88h) READ_VIN and (89h) READ_IIN. The PIN conversion equation is:
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PIN_MAX
255
PIN = READ_PIN ×
(3)
Where
• PIN is the calculated input power value
• READ_PIN is the I2C (97h) READ_PIN register value in decimal
• PIN_MAX is a maximum input power value selected in I2C (6Bh) PIN_OP_WARN_LIMIT register
When input power feature is not used, follow below connection for pin 3 VINSENP and pin 4 VINSENM so that
the device can report the input voltage level on PVIN node:
1. Short pin 3 VINSENP to pin 4 VINSENM,
2. Place a 0.1 µF ceramic bypass capacitor on pin 4 VINSENM referring to AGND,
3. Connect pin 4 VINSENM to PVIN node of TPS544C26 device.
VOUT and IOUT Telemetry
The output voltage sense telemetry senses the differential voltage across VOSNS to GOSNS pin. The
conversion equation for VOUT is related with VOUT step (5 mV or 10 mV) which is defined by PROTOCOL_ID
bits in I2C (C2h) PROTOCOL_ID_SVID register.
The VOUT conversion equation for 5 mV step is:
VOUT = READ_VOUT × 0.00625 + 0.125
(4)
(5)
The VOUT conversion equation for 10 mV step is:
VOUT = READ_VOUT × 0.0125 + 0.250
Where
• VOUT is the sensed output voltage (VOSNS−GOSNS)
• READ_VOUT is the I2C (8Bh) READ_VOUT register value in decimal
The output current sense telemetry senses the average of low-side FET current from the start to the end of each
low-side FET on time which provides the average inductor current. To achieve high accuracy and wide report
range, the device automatically sets the current sense gain based on ICC_MAX setting in (C0h) ICC_MAX
register. When the ICC_MAX is equal or greater than 15 A, the current sense gain is set to a smaller value to
achieve wide report range. When the ICC_MAX is equal or less than 10 A, the current sense circuit uses a
higher gain to get a significant amplitude and achieve good accuracy. The change of gain setting does not affect
the positive overcurrent limit (OCL) threshold but affect the negative overcurrent (NOC) threshold. The IOUT
conversion equation is:
ICC_MAX
255
IOUT = READ_IOUT ×
(6)
Where
• IOUT is the DC output current flowing from the output capacitors to the load
• READ_IOUT is the I2C (8Ch) READ_IOUT register value in decimal
• ICC_MAX is a full-scale value selected in I2C (C0h) ICC_MAX register
IC Temperature Telemetry
The die temperature sense telemetry senses the controller die temperature. The power stage die implementes
its own over-temperature protection and power stage die temperature is not reported through temetry sub-
system. The IC Temperature conversion equation is:
TEMP = READ_TEMPERATURE_1 − 40
(7)
Where
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• TEMP is the controller die temperature
• READ_TEMPERATURE_1 is the I2C (8Dh) READ_TEMPERATURE_1 register value in decimal
7.3.20 I2C Interface General Description
The TPS544C26 device offers both I2C interface and SVID interface for programming and telemetry report. The
device supports a group of I2C registers which is listed in . The device also supports a subset of the SVID
registers listed in .
For I2C interface, the TPS544C26 device supports minimum 50 kHz and maximum 1 MHz operating frequency
range, with the support of the Standard-mode, Fast-mode, and Fast-mode Plus bus timing requirements.
The high threshold of I2C SCL and SDA pin is 0.585 V typical, and the low threshold of I2C SCL and SDA pin is
0.515 V typical.
The TPS544C26 device contains nonvolatile memory that is used to store user-accessible configurations. The
settings programmed into the device are not automatically saved into this nonvolatile memory. The (15h)
STORE_USER_ALL command must be used to commit the current I2C settings to nonvolatile memory as device
defaults. For example, after importing a group of settings from a user specific configuration file the (15h)
STORE_USER_ALL command must be used to save the settings into the nonvolatile memory. The settings that
are capable of being stored in nonvolatile memory are noted in their detailed descriptions.
备注
Per I2C Standard, the packet error checking (PEC) feature is not supported by TPS544C26. A
command with PEC can result in unexpected communication error.
7.3.20.1 Setting the I2C Address
The TPS544C26 device offers selectable 7-bit I2C address either through a resistor from the I2C_ADDR pin (pin
29) to AGND, or programmable by writing an 7-bit address value into the (A2h) I2C_ADDR register.
As the default configuration, a resistor from the I2C_ADDR pin (pin 29) to AGND sets the pre-configured 7-bit I2C
address (0x70 to 0x7F) in the memory map. Up to 16 different addresses can be set, allowing 16 devices with
unique addresses in a single system. TI recommends ±1% tolerance resistors with a typical temperature
coefficient of ±100 ppm/°C
As an alternative method, the I2C address of a TPS544C26 device can be programmed by writing an address
value into (A2h) I2C_ADDR register. This register supports the full range from 00h to 7Fh (7-bit, ‘0000000’ to
‘1111111’). And, an override bit has to be set to ‘1’so that TPS544C26 device ignores the pin 29 detection
and straightly go to (A2h) I2C_ADDR register for I2C address. This method allows much more flexibility on the
address selections. This override bit locates in (A0h) SYS_CFG_USER1 register bit[0].
For the programmed address to take effect, below actions have to be taken:
1. Write the desired I2C address value to bit[6:0] in the (A2h) I2C_ADDR register.
2. Set the OVRD_I2C_ADDR bit in the (A0h) SYS_CFG_USER1 register.
3. Store the new values to EEPROM by writing "1" to bit[0] in (15h) STORE_USER_ALL register. The whole
store process takes 150 ms to finish.
4. Wait sufficient time for the store action to finish. Power cycle the device. During the power-on, the address
programmed to the (A2h) I2C_ADDR register takes effect.
I2C_ADDR
AGND
图7-1. I2C Address Pin-strapping
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表7-16. I2C_ADDR pin resistor selected values
(A2h) I2C_ADDR (Bin)
(A2h) I2C_ADDR (Hex)
RADDR (kΩ)
SHORT
5.62
9.53
14
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
21
30.1
36.5
43.2
51.1
61.9
75
88.7
105
127
150
FLOAT
For example, using 9.53 kΩ selects 1110010b (72h) as the 7-bit I2C address. Then the 8-bit I2C address is
11100100b (E4h), which is the 7-bit address followed by the write bit 0b.
表7-17. I2C 8-bit Address
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
Bit 3
Bit 2
1
Bit 1
0
Bit 0
0
0
0
7 bits set by address pin resistor
Write bit
7.3.20.2 I2C Write Protection
The TPS544C26 device offers write protection feature through (B1h) REG_LOCK register. After power-on, the
user accessible registers with write access are by default under "write protected" state, meaning the response to
a write is NACK. The device always acknowledges a read command and responds the data byte accordantly.
Only after writing the correct passcodes (multiple writes in the right order) into this REG_LOCK register, the user
accessible registers are "unlocked" and the device acknowledges the next write commands. (B1h) REG_LOCK
shows more details.
7.3.20.3 I2C Registers With Special Handling
In most cases the effect of an I2C write to a register is immediate: Once the write is performed, the value
becomes available for use in the system. There are a few exceptions with special handling for preserving the
integrity of the system.
Prevent write when the SW switching is enabled
A write to the following list of registers is prevented and the system response is to NACK writes to these
registers when the SW switching is enabled. For example, before importing the user specific configuration,
disabling the SW switching is required to successfully import a new value to these registers.
• (16h) RESTORE_USER_ALL
• (60h) TON_DELAY
• (61h) TON_RISE
• (64h) TOFF_DELAY
• (65h) TOFF_FALL
• (BDh) EXT_CAPABILITY_VIDOMAX_H
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• (BEh) VIDO_MAX_L
When ON_OFF_CONFIG is set to Always On, the values from the NVM restore for these registers will be
NACKed and will never become effective. Even the NVM restore during power-on initialization is affected by this
kind of configuration.
Register update waits until the SW switching is disabled
When a write to one of these registers is accepted (ACKed), one or more bit-fields in this register are allowed to
take effect immediately only if the SW switching is disabled. If the SW switching is enabled, the previous value
for those bit-fields continues to be used by the system, and the new value for those bit-fields is kept ready inside
the IC but only become effective the next time when the SW switching is disabled. A readback attempt will be
accepted (ACKed) and return the most recent ACKed value.
• (A0h) SYS_CFG_USER1 register, FCCM bit
• (A0h) SYS_CFG_USER1 register, VOUT_CTRL field
• (A0h) SYS_CFG_USER1 register, EN_SOFT_STOP bit
• (A0h) SYS_CFG_USER1 register, VRRDY_DELAY field
• (A1h) SVID_ADDR
• (C2h) PROTOCOL_ID_SVID register, ALL_CALL_SEL field
• (A8h) I2C_OFFSET, but only when VOUT_CTRL field is set to “01b”
When ON_OFF_CONFIG is set to Always On, the values from the NVM restore can be kept in the staging area
and never become effective. Even the NVM restore during power-on initialization is affected by this kind of
configuration.
Register update waits for a power cycling or a manual restore
When a write to one of these register is accepted (ACKed), one or more bit-fields in the register are not allowed
to take effect at all. The new value takes effect only if the value is stored into NVM first and then retrieved from
NVM after the device is powered on.
• (A0h) SYS_CFG_USER1 register, OVRD_SVID_ADDR bit
• (A0h) SYS_CFG_USER1 register, OVRD_I2C_ADDR bit
• (A2h) I2C_ADDR register, I2C_ADDR filed
The sequence of events, for the contents of those fields to take effect is as follows:
1. The user writes the desired value to the register,
2. The user executes an NVM store command ((15h) STORE_USER_ALL),
3. The part is power-cycled.
7.4 Device Functional Modes
7.4.1 Forced Continuous-Conduction Mode
When the operation mode is set to FCCM, the controller operates in continuous conduction mode (CCM) during
light-load conditions. During CCM, the switching frequency maintained to an almost constant level over the entire
load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower
efficiency.
When FCCM is selected, the TPS544C26 device operates at CCM during the whole soft-start period as well as
the nominal operation.
7.4.2 Auto-Skip Eco-mode™ Light Load Operation
When the operation mode is set to DCM, the device automatically reduces the switching frequency at light-load
conditions to maintain high efficiency. This section describes the operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
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and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation
so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IOUT(LL) (for example: the threshold between
continuous- and discontinuous-conduction mode) is calculated as shown in below equation.
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
OUT LL
( )
2´L ´ f
SW
(8)
Where
• fSW is the switching frequency
TI recommends sing low ESR capacitors (such as ceramic capacitor) for skip-mode.
7.5 Programming
7.5.1 Supported I2C Registers
The Supported I2C and Default Values Table lists the implemented registers and also the default for the bit
behavior and register values.
表7-18. Supported I2C and Default Values
Register
address
Default Value
(Hex)
Register Name
OPERATION
R/W
NVM
Default Behavior
01h
02h
03h
15h
16h
33h
R/W
R/W
W
NO
YES
NO
00h
40h
N/A
N/A
N/A
01h
OPERATION OFF
ON_OFF_CONFIG
CLEAR_FAULTS
Turn ON/OFF by EN pin only
Clear all faults
STORE_USER_ALL
RESTORE_USER_ALL
FREQUENCY_SWITCH
VIN_ON
W
NO
Stores all current storable register settings into NVM
Restores all storable register settings from NVM
Switching frequency is set to 800 kHz
W
NO
R/W
YES
ON threshold is determined by both PVIN and VCC
conditions. Both PVIN > 2.55 V and VCC > 3.8 V conditions
have to be satisfied to enable the power conversion.
35h
36h
R/W
R/W
YES
YES
03h
07h
VIN_OFF
OFF threshold is determined by both PVIN and VCC
conditions. Either PVIN ≤2.3 V or VDRV ≤3.4 V disables
the power conversion.
40h
41h
42h
43h
44h
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
R/W
R/W
R/W
R/W
R/W
YES
YES
YES
YES
YES
02h
00h
01h
01h
02h
VOUT Tracking OV Fault threshold = +200 mV
Latch-off after a fault
VOUT Tracking OV Warning threshold = +150 mV
VOUT Tracking UV Warning threshold = −150 mV
VOUT Tracking UV Fault threshold = −200 mV
Latch-off after a fault, and the response delay before
disabling the power conversion is 64 µs
45h
R/W
YES
02h
46h
4Fh
50h
51h
55h
IOUT_OC_FAULT_LIMIT
OT_FAULT_LIMIT
R/W
R/W
R/W
R/W
R/W
YES
YES
YES
YES
YES
09h
07h
00h
06h
01h
Low-side valley current limiting threshold = 35 A
Programmable OT Fault threshold = 150 °C
Latch-off after a fault
OT_FAULT_RESPONSE
OT_WARN_LIMIT
Programmable OT Warning threshold = 125 °C
PVIN OV Fault threshold = 18.5 V
VIN_OV_FAULT_LIMIT
TON_DELAY
0.5 ms delay when a start condition is received (as
programmed by the ON_OFF_CONFIG register) until the
output voltage starts to rise
60h
61h
64h
R/W
R/W
R/W
YES
YES
YES
00h
00h
00h
TON_RISE
1 ms from when the output starts to rise until the output
voltage has entered the regulation band
TOFF_DELAY
0 ms from when a stop condition is received (as
programmed by the ON_OFF_CONFIG register) until the
unit starts the soft-stop operation
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表7-18. Supported I2C and Default Values (continued)
Register
address
Default Value
Register Name
R/W
NVM
Default Behavior
(Hex)
TOFF_FALL
0.5 ms from the end of the turn-off delay time until the
internal reference DAC is commanded to 0 mV
65h
R/W
YES
00h
6Bh
7Ah
7Bh
7Ch
7Dh
80h
88h
89h
8Bh
8Ch
8Dh
PIN_OP_WARN_LIMIT
STATUS_VOUT
STATUS_IOUT
R/W
R/W
R/W
R/W
R/W
R/W
R
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
03h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Maximum PIN (input power) threshold = 360 W
Current status
Current status
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_MFR_SPECIFIC
READ_VIN
Current status
Current status
Current status
Measured input voltage on pin 4 VINSENM
Measured input current over the external sensing resistor
Measured output voltage
READ_IIN
R
READ_VOUT
R
READ_IOUT
R
Measured output current
READ_TEMPERATURE_1
READ_PIN
R
Measured Controller die temperature
Calculated input power, the product of the measured input
voltage and input current
97h
R
NO
N/A
SYS_CFG_USER1
Operation mode under light load condition is DCM
VOUT is controlled by SVID bus only
Soft-stop feature is enabled
A0h
R/W
YES
10h
VR Ready delay = 0 ms
I2C address is set by pin 29 pin strap detection
I2C_ADDR
Bit[7] = 0b, reserved for TI usage
I2C address saved in NVM is 77h. However, after initial
power-on, the effective I2C address shown in this field is
determined by the resistor on pin 29
A2h
R/W
YES
N/A
A3h
A4h
SVID_ADDR
IMON_CAL
R/W
R/W
YES
YES
00h
78h
Device address for SVID communication is set to 00h
IMON gain calibration = 0%
IMON offset calibration = 0 A
IIN_CAL
IIN gain calibration = 0%
IIN offset calibration = 0 A
A5h
A6h
R/W
R/W
YES
YES
78h
VOUT_CMD
Default VOUT setting saved in VOUT_CMD is 1.1V. The
VOUT_CMD does not control VOUT unless VOUT_CTRL =
10b or 11b
ABh
VID_SETTING
After initial power-on, this register shows a value reflecting
the last commanded VOUT either from SVID bus or I2C bus
A7h
A8h
R
NO
N/A
00h
I2C_OFFSET
R/W
YES
I2C OFFSET = 0 mV
COMP1_MAIN
AC Gain = 2
A9h
R/W
YES
4Ah
AC Load Line = 7
COMP2_MAIN
Integration gain = 2
AAh
R/W
YES
19h
Integration time constant = 4.25 µs
Ramp Amplitude = 60 mV
COMP1_ALT
COMP2_ALT
This register is not activated in the TPS544C26 device and
affects nothing.
ABh
ACh
R/W
R/W
YES
YES
23h
A2h
This register is not activated in the TPS544C26 device and
affects nothing.
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表7-18. Supported I2C and Default Values (continued)
Register
address
Default Value
Register Name
R/W
NVM
Default Behavior
(Hex)
COMP3
Bit[7] = 0b, reserverd for TI usage
Force DCM during soft-start enable/disable bit = disabled
On-time during NOC (Negative OC) operation = longer
tON_NOC
ADh
R/W
YES
02h
LOUT (output inductor value) for current sensing circuit = 100
nH
DC Load Line = 0.75 mΩ
DVS_CFG
Dynamic voltage change fast slew rate configuration = 10
mV/µs
AFh
B0h
R/W
R/W
YES
YES
06h
00h
DVID_OFFSET
REG_LOCK
DVID Up positive DAC offset = 0 mV
DVID Down positive DAC offset = 0 mV
The user-accessible registers (not including B1h) are “write
protected”and by default. User can still read back from
registers
B1h
B3h
W
YES
YES
N/A
05h
PIN_SENSE_RES
IOUT_NOC_LIMIT
Input power sense resistor is 0.5 mΩ. This also sets the
Maximum IIN to 40 A with IIN_LSB = 0.15625 A
R/W
VOUT Fixed OV Fault threshold = 1.5 V
VOUT Fixed OV Fault enable/disable bit = enabled
Negative OC limit = −15 A when ICC_MAX ≥15 A or −7.5 A
when ICC_MAX < 10 A
B4h
R/W
YES
05h
B5h
B6h
BAh
BBh
BCh
USER_DATA_01
R/W
R/W
R/W
R/W
R
YES
YES
YES
YES
NO
00h
00h
N/A
N/A
FBh
Bit[7:4]: For user to store manufacturer specific information
Bit[7:5]: For user to store manufacturer specific information
A direct copy of the bits of SVID STATUS_1 register
A direct copy of the bits of SVID STATUS_2 register
A direct copy of the bits of SVID CAPABILITY register
USER_DATA_02
STATUS1_SVID
STATUS2_SVID
CAPABILITY
EXT_CAPABILITY_VIDOMAX_H
A direct copy of the bits of SVID VIDOMAX_H_CAPA
register
BDh
R/W
YES
04h
BEh
C0h
C1h
VIDOMAX_L
R/W
R/W
R/W
YES
YES
YES
B6h
05h
06h
9-bit VIDoMAX = 1.155 V
ICC_MAX
ICC_MAX = 30 A
TEMP_MAX
TEMP_MAX = 125 °C while controls SVID "ThermAlert" bit
PROTOCOL_ID_SVID
PROTOCOL_ID_SVID = 07h (VR13, VOUT step 5 mV)
Vboot = 1.1 V
C2h
R/W
YES
63h
Respond to SVID All-call address both 0Eh and 0Fh
VENDOR_ID
SVID VENDOR_ID = 22h. This vendor ID is assigned to
Texas Instruments by Intel, to identify the VR vendor.
C6h
R
NO
22h
C8h
C9h
PRODUCT_ID
R
R
NO
NO
13h
02h
TPS544C26 Product ID = 13h
PRODUCT_REV_ID
TPS544C26 current device revision = PG2.1
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7.5.2 Support of Intel SVID Interface
The TPS544C26 device supports Intel SVID interface (VR13 Mode). Details are described in this section.
The SVID address for a TPS544C26 device can be programmabled in (A3h) SVID_ADDR register, allowing
address value from 00h to 0Dh.
The TPS544C26 device supports VR13 Mode SVID registers and also VIDoMAX register. The table below
summarizes the SVID register initialization performed by TPS544C26 at each power-on. Any writeable register
can be changed by the SVID host after initialization. Refer to the Intel documentation for more detailed
description of the individual register functionality.
表7-19. SVID Register Support (VR13 Mode)
Register Address
00h
Register Name
R/W
Source or Behavior
VENDOR_ID
PROD_ID
R
R
R
R
R
R
R
R
R
R
R
22h
01h
Per I2C register (C8h) PRODUCT_ID
02h
PROD_REV
Per I2C register (C9h) PROD_REV_ID
05h
PROTOCOL_ID
CAPABILITY
VIDOMAX_H_CAPA
VIDOMAX_L
VIN_FULLSCALE_H
VIN_FULLSCALE_L
VOUT_FULLSCALE_H
VOUT_FULLSCALE_L
ALLCALL_ACT
STATUS1
Per I2C register (C2h) PROTOCOL_ID_SVID[7:6]
06h
FBh
09h
Per I2C register (BDh) EXT_CAPABILITY_VIDOMAX_H[7:0]
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
Per I2C register (BEh) VIDO_MAX_L[7:0]
06h
40h
0Ch
80h
R/W
R
Per I2C register (C2h) PROTOCOL_ID_SVID[1:0]
Current status
11h
STATUS2
R
Current status
12h
TEMPERATURE
IOUT_H
R
Current status
15h
R
Current status
16h
VOUT_H
R
Current status
17h
VR_TEMP
R
Current status
19h
IIN_H
R
Current status
1Ah
1Bh
1Ch
20h
VIN_H
R
Current status
PIN_H
R
Current status
STATUS2_LASTREAD
ICC_IN_MAX
ICC_MAX
R
Current status
R
FFh
21h
R
Per I2C register (C0h) ICC_MAX[2:0]
22h
TEMP_MAX
SR_FAST
R
Per I2C register (C1h) TEMP_MAX[2:0]
24h
R
Per I2C register (AFh) DVS_CFG[2:0]
25h
SR_SLOW
R
Programmed by SVID register (2Ah) SLOW_SR_SEL_HC
26h
VBOOT
R
Per I2C register (C2h) PROTOCOL_ID_SVID[5:2]
2Ah
2Bh
2Eh
30h
SLOW_SR_SEL_HC
PS4_EXIT_LAT
PIN_MAX
R/W
R
02h
85h
R
Per I2C register (6Bh) PIN_OP_WARN_LIMIT
VID_MAX
R/W
R
FFh
31h
VID_SETTING
PWR_STATE
OFFSET
Current status
32h
R
00h
00h
01h
00h
00h
00h
00h
33h
R/W
R/W
R/W
R/W
R/W
R/W
34h
MULTI_VR_CONFIG
WP0
3Ah
3Bh
3Ch
3Dh
WP1
WP2
WP3
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表7-19. SVID Register Support (VR13 Mode) (continued)
Register Address
Register Name
R/W
Source or Behavior
56h
DIGOUT_STATUS
R
Current status
The table below summarizes the SVID commands supported by TPS544C26.Refer to the Intel documentation
for more detailed description of the individual command functionality.
表7-20. Supported SVID Command
Command Code
Command
Supported by TPS544C26
01h
02h
03h
04h
05h
06h
07h
09h
SetVID_Fast
SetVID_Slow
SetVID_Decay
SetPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SetRegAddr
SetRegData
GetReg
SetWP
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7.6 Register Maps
7.6.1 (01h) OPERATION
CMD Address
Write Transaction:
Read Transaction:
Format:
01h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Back-up:
Updates:
On-the-fly
The OPERATION command is used to enable or disable power conversion.
Return to Supported I2C and Default Values.
图7-2. (01h) OPERATION Register Map
7
6
5
4
3
2
1
0
R/W
R
R
R
R
R
R
R
ON_OFF
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-21. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
ON_OFF
R/W
0b
Enable/disable power conversion. Note that there can be several other
requirements that must be satisfied before the power conversion can begin (for
example, input voltages above UVLO thresholds).
0b: Disable power conversion.
1b: Enable power conversion.
6:0
Reserved
R
0000000b Not used and always set to 0.
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7.6.2 (02h) ON_OFF_CONFIG
Register Address
Write Transaction:
Read Transaction:
Format:
02h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
The ON_OFF_CONFIG command configures the combination of enable pin input and serial bus commands
needed to enable/disable power conversion. This includes how the unit responds when power is applied to
PVIN.
Return to Supported I2C and Default Values.
图7-3. (02h) ON_OFF_CONFIG Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R
R
R
R
R
ON_OFF_CONFIG
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-22. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:5 ON_OFF_CONFIG
R/W
NVM
These bits determine the on-off mechanism as follow:
000b: Power conversion is always ON
001b: Turn power conversion ON/OFF by I2C Operation Command only
010b: Turn power conversion ON/OFF by EN pin only
011b: The power conversion is not turned ON until commanded by the EN pin and
OPERATION command. The power conversion can be turned OFF either
commanded by the EN pin or OPERATION command
100b to 111b: Reserved. The device always acknowledges a write with this value
but does not change the operation state.
4:0
Reserved
R
00000b
Not used and always set to 0.
Attempts to write ON_OFF_CONFIG to any value other than those explicitly listed above will be considered
invalid/unsupported data and cause the TPS544C26 to respond by flagging the appropriate status bits, and
notifying the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.
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7.6.3 (03h) CLEAR_FAULTS
CMD Address
Write Transaction:
Read Transaction:
Format:
03h
Send Byte
N/A
Data-less
No
NVM Back-up:
Updates:
On-the-fly
CLEAR_FAULTS is a command used to clear any fault bits that have been set. CLEAR_FAULTS is a write-only
command with no data. Writing a "1" into bit[0] of this command clears all bits in all status registers. The bit
clears itself after the write.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the
fault is still present when the bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
图7-4. (03h) CLEAR_FAULTS Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
CLEAR_FAULT
S
Reserved
LEGEND: R/W = Read/Write; R = Read only
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7.6.4 (15h) STORE_USER_ALL
CMD Address
Write Transaction:
Read Transaction:
Format:
15h
Send Byte
N/A
Data-less
NVM Back-up:
Updates:
No
Not recommended for on-the-fly-use, but not explicitly blocked
The STORE_USER_ALL command instructs the TPS544C26 device to copy the entire contents of the Operating
Memory to the matching locations in the non-volatile User Store Memory. Any items in Operating Memory that do
not have matching locations in the User Store Memory are ignored. Writing a "1" into bit[0] of this command
executes the store operation. The bit clears itself after the write.
User must wait for at least 150 msec from executing this command before power can be turned off to make sure
a successful write to NVM is executed. NVM store operation is not recommended while the output is enabled,
although the user is not explicitly prevented from doing so, as interruption can result in a corrupted NVM. I2C
commands issued during this time will be ignored. Following issuance of NVM store operations, TI recommends
disabling regulation and waiting a minimum of 125 ms before continuing.
Return to Supported I2C and Default Values.
图7-5. (15h) STORE_USER_ALL Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reserved
STORE
LEGEND: R/W = Read/Write; R = Read only
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7.6.5 (16h) RESTORE_USER_ALL
CMD Address
Write Transaction:
Read Transaction:
Format:
16h
Send Byte
N/A
Data-less
NVM Back-up:
Updates:
No
Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked
The RESTORE_USER_ALL command instructs the the TPS544C26 device to copy the entire contents of the
non-volatile User Store Memory to the matching locations in the Operating Memory. Any items in Operating
Memory that do not have matching locations in the User Store Memory are ignored (for example the STATUS
registers). This operation overwrite any value set through a pin detection after the last power-cycle, such as the
I2C address set through the I2C_ADDR pin.
Writing a "1" into bit[0] of this command executes the restore operation. When acknowledged, the I2C serial
interface is disabled while the restore takes place and all frames will be NACKed during that time. The bit clears
itself after the write.
备注
Using the RESTORE_USER_ALL command while the SW switching is enabled is not allowed,
meaning a NACK response is provided by the device. RESTORE_USER_ALL command can be
executed after the SW switching is disabled.
Return to Supported I2C and Default Values.
图7-6. (16h) RESTORE_USER_ALL Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reserved
RESTORE
LEGEND: R/W = Read/Write; R = Read only
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7.6.6 (33h) FREQUENCY_SWITCH
CMD Address
Write Transaction:
Read Transaction:
Format:
33h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
FREQUENCY_SWITCH sets the switching frequency of the active device.
Return to Supported I2C and Default Values.
图7-7. (33h) FREQUENCY_SWITCH Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
SEL_FSW
LEGEND: R/W = Read/Write; R = Read only
表7-23. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:2
Reserved
R
000000b Not used and always set to 0.
00b: switching frequency is set to 0.6 MHz
01b: switching frequency is set to 0.8 MHz
10b: switching frequency is set to 1.0 MHz
11b: switching frequency is set to 1.2 MHz
1:0
SEL_FSW
R/W
NVM
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7.6.7 (35h) VIN_ON
CMD Address
Write Transaction:
Read Transaction:
Format:
35h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VIN_ON command sets the value of the PVIN input voltage, in Volts, at which the unit starts power
conversion.
Return to Supported I2C and Default Values.
图7-8. (35h) VIN_ON Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
PVIN_ON
LEGEND: R/W = Read/Write; R = Read only
表7-24. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
Description
Reserved
PVIN_ON
000000b Not used and always set to 0.
R/W
NVM
00b: ON threshold is PVIN = 10 V.
01b: ON threshold is PVIN = 9 V
10b: ON threshold is PVIN = 8 V
11b: ON threshold is determined by both PVIN and VCC conditions. When this
option is selected, both PVIN > 2.55 V and VCC > 3.8 V conditions have to be
satisfied to enable the power conversion.
Note that the PVIN_UVF condition in (7Ch) STATUS_INPUT register is masked until the sensed input voltage
exceeds the VIN_ON threshold for the first time following a power-on reset. The EN pin toggles and NVM store
or restore operations do not reset this masking.
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7.6.8 (36h) VIN_OFF
CMD Address
Write Transaction:
Read Transaction:
Format:
36h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VIN_OFF command sets the value of the PVIN input voltage, in Volts, at which the unit must stop power
conversion. If the power conversion enable conditions as defined by (02h) ON_OFF_CONFIG are met and PVIN
is less than the selected VIN_OFF threshold, the power conversion turns off and the PVIN_UVF bit in (7Ch)
STATUS_INPUT is set.
Return to Supported I2C and Default Values.
图7-9. (36h) VIN_OFF Register Map
7
6
5
R
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
Reserved
PVIN_OFF
LEGEND: R/W = Read/Write; R = Read only
表7-25. Register Field Descriptions
Bit
7:3
2:0
Field
Access
R
Reset
00000b
NVM
Description
Reserved
PVIN_OFF
Not used and always set to 0.
R/W
000b: OFF threshold is PVIN = 4.2 V
001b: OFF threshold is PVIN = 9.5 V
010b: OFF threshold is PVIN = 8.5 V
011b: OFF threshold is PVIN = 7.5 V
100b: OFF threshold is PVIN = 6.5 V
101b: OFF threshold is PVIN = 5.5 V
110b: OFF threshold is PVIN = 4.2 V
111b: OFF threshold is determined by both PVIN and VDRV conditions. When this
option is selected, either PVIN ≤2.3 V or VDRV ≤3.4 V disables the power
conversion.
While it is possible to set (36h) VIN_OFF threshold greater than (35h) VIN_ON threshold, it is not advisable and
can produce rapid enabling and disabling of conversion and undesirable operation. Please set (35h) VIN_ON
threshold always greater than (36h) VIN_OFF threshold.
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7.6.9 (40h) VOUT_OV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
40h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage sensed at the (VOSNS − GOSNS)
pins that causes an output overvoltage fault. SEL_OVF bits set an overvoltage fault threshold relative to the
current VOUT setting that is commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD. The VOUT
Tracking OVF function is activated after the soft-start ramp completes.
Following an overvoltage fault condition, the device responds according to (41h) VOUT_OV_FAULT_RESP. Due
to the lack of an I2C alert pin, the TPS544C26 device does not have a way to notify the host.
Return to Supported I2C and Default Values.
图7-10. (40h) VOUT_OV_FAULT_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
SEL_OVF
LEGEND: R/W = Read/Write; R = Read only
表7-26. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
000000b Not used and always set to 0.
NVM Sets the overvoltage fault threshold.
Description
Reserved
SEL_OVF
R/W
00b: VOUT Tracking OVF threshold = +100 mV
01b: VOUT Tracking OVF threshold = +150 mV
10b: VOUT Tracking OVF threshold = +200 mV
11b: VOUT Tracking OVF threshold = +300 mV
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7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
41h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an
output overvoltage fault. Upon triggering the tracking overvoltage fault (a.k.a VOUT Tracking OVF), the
TPS544C26 device responds according to the RESTART bit in this register, and the following actions are taken:
• Set the OVF bit in the (7Ah) STATUS_VOUT register.
• Enter continuous Negative Overcurrent (NOC) operation immediately, and the delay from the VOUT Tracking
OVF detection circuit is minimized (less than 1 µs).
• Due to the lack of an I2C alert pin, the TPS544C26 device does not have a way to notify the host.
The selected Tracking OVF response in this VOUT_OV_FAULT_RESP register does not affect the response for
a Fixed OVF event.
Return to Supported I2C and Default Values.
图7-11. (41h) VOUT_OV_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
R
0
R
R
R
R
R/W
R
R
Reserved
RESTART
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-27. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
Reserved
R
0000b
Not used and always set to 0.
VOUT Tracking OVF response selection
0b: Latch-off after the fault. A VCC power cycle or EN toggle can restart the power
conversion.
3
RESTART
Reserved
R/W
R
NVM
000b
1b: Automatically restart after a delay of 56 ms, without limitation on the number of
restart attempts.
2:0
Not used and always set to 0.
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7.6.11 (42h) VOUT_OV_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
42h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage sensed at the (VOSNS − GOSNS)
pins that causes an output voltage high warning. This value is typically less than the output overvoltage fault
threshold. The SEL_OVW bits set an overvoltage warning threshold relative to the current VOUT setting that is
commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD.
When the sensed output voltage exceeds the VOUT Tracking OVW threshold, the OVW bit in the (7Ah)
STATUS_VOUT register is set. Due to the lack of an I2C alert pin, the TPS544C26 device does not have a way
to notify the host.
Return to Supported I2C and Default Values.
图7-12. (42h) VOUT_OV_WARN_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
SEL_OVW
LEGEND: R/W = Read/Write; R = Read only
表7-28. Register Field Descriptions
Bit
Field
Access
Reset
000000b Not used and always set to 0.
Sets the overvoltage warning threshold.
Description
7:2
Reserved
R
00b: VOUT Tracking OVW threshold = +100 mV
01b: VOUT Tracking OVW threshold = +150 mV
10b: VOUT Tracking OVW threshold = +200 mV
11b: VOUT Tracking OVW threshold = +300 mV
1:0
SEL_OVW
R/W
NVM
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7.6.12 (43h) VOUT_UV_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
43h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_UV_WARN_LIMIT command sets the value of the output voltage sensed at the (VOSNS − GOSNS)
pins that causes an output voltage low warning. This value is typically less negative than the output undervoltage
fault threshold. The SEL_UVW bits set an undervoltage warning threshold relative to the current VOUT setting
that is commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD.
When the sensed output voltage falls below the VOUT Tracking UVW threshold, the UVW bit in the (7Ah)
STATUS_VOUT register is set. Due to the lack of an I2C alert pin, the TPS544C26 device does not have a way
to notify the host.
Return to Supported I2C and Default Values.
图7-13. (43h) VOUT_UV_WARN_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
SEL_UVW
LEGEND: R/W = Read/Write; R = Read only
表7-29. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:2
Reserved
R
000000b Not used and always set to 0.
Sets the undervoltage warning threshold.
00b: VOUT Tracking UVW threshold = −100 mV
01b: VOUT Tracking UVW threshold = −150 mV
10b: VOUT Tracking UVW threshold = −200 mV
11b: VOUT Tracking UVW threshold = −300 mV
1:0
SEL_UVW
R/W
NVM
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7.6.13 (44h) VOUT_UV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
44h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage sensed at the (VOSNS − GOSNS)
pins that causes an output undervoltage fault. The SEL_UVF bits set an undervoltage fault threshold relative to
the current VOUT setting that is commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD. The
VOUT Tracking UVF function is activated after the soft-start ramp completes.
When the undervoltage fault condition is triggered, the device responds according to (45h)
VOUT_UV_FAULT_RESPONSE. Due to the lack of an I2C alert pin, the TPS544C26 device does not have a
way to notify the host.
Return to Supported I2C and Default Values.
图7-14. (44h) VOUT_UV_FAULT_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
SEL_UVF
LEGEND: R/W = Read/Write; R = Read only
表7-30. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
000000b Not used and always set to 0.
NVM Sets the undervoltage fault threshold.
Description
Reserved
SEL_UVF
R/W
00b: VOUT Tracking UVF threshold = −150 mV
01b: VOUT Tracking UVF threshold = −200 mV
10b: VOUT Tracking UVF threshold = −200 mV
11b: VOUT Tracking UVF threshold = −300 mV
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7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
45h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an
output undervoltage fault. Upon triggering the tracking undervoltage fault (a.k.a VOUT Tracking UVF), the
TPS544C26 device responds according to the RESTART bit in this register, and the following actions are taken:
• Set the UVF bit in the (7Ah) STATUS_VOUT register.
• Start the UVF Response Delay selected in this register. During the UVF Response Delay, if the output voltage
(VOSNS − GOSNS) rises above the UVF threshold, thus not qualified for a UVF event, the UVF response
delay timer resets to zero. When the VOUT drops below the UVF threshold again, the UVF response delay
timer re-starts from zero.
• Due to the lack of an I2C alert pin, the TPS544C26 device does not have a way to notify the host.
Return to Supported I2C and Default Values.
图7-15. (45h) VOUT_UV_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R
R/W
R/W
Reserved
RESTART
Reserved
RESPONSE_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-31. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
Reserved
R
0000b
Not used and always set to 0.
VOUT Tracking UVF response selection
0b: Latch-off after the fault. A VCC power cycle or EN toggle can restart the power
conversion.
3
2
RESTART
Reserved
R/W
R
NVM
0b
1b: Automatically restart after a delay of 56 ms, without limitation on the number of
restart attempts.
Not used and always set to 0.
VOUT Tracking UVF Response Delay selection
00b: UVF Response Delay = 2 µs
RESPONSE
_DELAY
00b: UVF Response Delay = 16 µs
00b: UVF Response Delay = 64 µs
00b: UVF Response Delay = 256 µs
1:0
R/W
NVM
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7.6.15 (46h) IOUT_OC_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
46h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM or Pin Detection
On-the-fly
NVM Backup:
Updates:
The IOUT_OC_FAULT_LIMIT command sets the value of the output current that causes the overcurrent detector
to indicate an overcurrent fault condition. The thresholds selected here are compared to the sensed low-side
valley current. See Overcurrent Limit and Low-side Current Sense for more details.
Return to Supported I2C and Default Values.
图7-16. (46h) IOUT_OC_FAULT_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only
表7-32. Register Field Descriptions
Bit
7:4
3:0
Field
Access
R
Reset
0000b
NVM
Description
Reserved
SEL_OCL
Not used and always set to 0.
R/W
These bits select the IOUT valley current limiting threshold.
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7.6.16 (4Fh) OT_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
4Fh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The OT_FAULT_LIMIT command sets the temperature of the unit, at which, it indicates an overtemperature fault
condition. The unit of this command is degrees Celsius. This feature utilizes a digital comparator that compares
the output of the IC TEMPERATURE telemetry to the fault threshold selected in this register.
The device response to an overtemperature event is described in (50h) OT_FAULT_RESPONSE.
Return to Supported I2C and Default Values.
图7-17. (4Fh) OT_FAULT_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R/W
R/W
R/W
Reserved
SEL_OTF
LEGEND: R/W = Read/Write; R = Read only
表7-33. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not used and always set to 0.
These bits select the OT fault threshold which is compared with the output of the IC
TEMP telemetry.
000b: OTF threshold = 115 °C
001b: OTF threshold = 120 °C
010b: OTF threshold = 125 °C
011b: OTF threshold = 130 °C
100b: OTF threshold = 135 °C
101b: OTF threshold = 140 °C
110b: OTF threshold = 145 °C
111b: OTF threshold = 150 °C
2:0
SEL_OTF
R/W
NVM
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7.6.17 (50h) OT_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
50h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The (50) OT_FAULT_RESPONSE command instructs the device on what action to take in response to an
overtemperature fault. Upon triggering the overtemperature fault, the device responds per the RESTART bit in
this register, and sets the OTF_PROG bit in the (7Dh) STATUS_TEMPERATURE register. Due to the lack of an
I2C alert pin, the device does not have a way to notify the host.
Return to Supported I2C and Default Values.
图7-18. (50h) OT_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
R
0
R
R
R
R
R/W
R
R
Reserved
RESTART
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-34. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
Reserved
R
0000b
Not used and always set to 0.
This bit selects the response to a programmable OT fault condition
0b: Latch-off after the fault. A VCC power cycle or EN toggle can restart the power
conversion.
3
RESTART
Reserved
R/W
R
NVM
000b
1b: Automatically restart after a delay of 56 ms, without limitation on the number of
restart attempts.
2:0
Not used and always set to 0.
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7.6.18 (51h) OT_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
51h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The OT_WARN_LIMIT command sets the temperature of the unit, at which, it indicates an overtemperature
warning alarm. The unit of this command is degrees Celsius. This feature utilizes a digital comparator that
compares the output of the IC TEMPERATURE telemetry to the warning threshold selected in this register.
Upon triggering the overtemperature fault, the device sets the OTW_PROG bit in the (7Dh)
STATUS_TEMPERATURE register. Due to the lack of an I2C alert pin, the TPS544C26 device does not have a
way to notify the host.
Return to Supported I2C and Default Values.
图7-19. (51h) OT_WARN_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R/W
R/W
R/W
Reserved
SEL_OTW
LEGEND: R/W = Read/Write; R = Read only
表7-35. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not used and always set to 0.
These bits select the OT warning threshold which is compared with the output of
the IC TEMP telemetry.
000b: OTW threshold = 85 °C
001b: OTW threshold = 95 °C
010b: OTW threshold = 100 °C
011b: OTW threshold = 105 °C
100b: OTW threshold = 110 °C
101b: OTW threshold = 115 °C
110b: OTW threshold = 125 °C
111b: OTW threshold = 135 °C
2:0
SEL_OTW
R/W
NVM
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7.6.19 (55h) VIN_OV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
55h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The VIN_OV_FAULT_LIMIT command sets the PVIN voltage, in volts, when a VIN_OV_FAULT is declared. The
response to a detected VIN_OV_FAULT is latch-off always. (55h) VIN_OV_FAULT_LIMIT is typically used to
stop switching in the event of excessive input voltage, which can result in over-stress damage to the power FETs
due to ringing on the SW node. Upon triggering the PVIN overvoltage fault, the device sets the PVIN_OVF bit in
the (7C) STATUS_INPUT register.
Due to the lack of an I2C alert pin, the device does not have a way to notify the host.
Return to Supported I2C and Default Values.
图7-20. (55h) VIN_OV_FAULT_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R/W
PVIN_OVF
LEGEND: R/W = Read/Write; R = Read only
表7-36. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:1
Reserved
R
0000000b Not used and always set to 0.
This bit selects the PVIN_OVF rising threshold. The falling threshold is always 13.5
V.
0
PVIN_OVF
R/W
NVM
0b: PVIN_OVF rising threshold = 16.5 V
1b: PVIN_OVF rising threshold = 18.5 V
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7.6.20 (60h) TON_DELAY
CMD Address
Write Transaction:
Read Transaction:
Format:
60h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received (as
programmed by the (02h) ON_OFF_CONFIG command) until the output voltage starts to rise.
Return to Supported I2C and Default Values.
图7-21. (60h) TON_DELAY Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
TON_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-37. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
Description
Reserved
000000b Not used and always set to 0.
These bits select the turn-on delay options before enabling the SW switching.
00b: TON_DELAY time = 0.5 ms
TON_DELA
Y
R/W
NVM
01b: TON_DELAY time = 1 ms
10b: TON_DELAY time = 1.5 ms
11b: TON_DELAY time = 2 ms
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7.6.21 (61h) TON_RISE
CMD Address
Write Transaction:
Read Transaction:
Format:
61h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM or Pin Detection
On-the-fly
NVM Backup:
Updates:
The TON_RISE command sets the time, in milliseconds, from when the output starts to rise until the voltage has
entered the regulation band, which effectively sets the slew rate of the reference DAC during the soft-start
period. Note that the soft-start time is equal to TON_RISE selection only when the output voltage is controlled by
SVID bus. The soft-start time varies from the TON_RISE selection when I2C_OFFSET is involved or (A6h)
VOUT_CMD is used for boot up. See section Startup and 表7-7 for more details.
Return to Supported I2C and Default Values.
图7-22. (61h) TON_RISE Register Map
7
6
5
R
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
Reserved
TON_RISE
LEGEND: R/W = Read/Write; R = Read only
表7-38. Register Field Descriptions
Bit
7:3
2:0
Field
Access
R
Reset
00000b
NVM
Description
Reserved
TON_RISE
Not used and always set to 0.
R/W
These bits select the soft-start time options.
000b: TON_RISE time = 1 ms
001b: TON_RISE time = 2 ms
010b: TON_RISE time = 4 ms
011b: TON_RISE time = 8 ms
100b to 111b: TON_RISE time = 16 ms
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7.6.22 (64h) TOFF_DELAY
CMD Address
Write Transaction:
Read Transaction:
Format:
64h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received (as
programmed by the (02h) ON_OFF_CONFIG command) until the device starts the soft-stop operation. When the
soft-stop feature is disabled through the EN_SOFT_STOP bit in (A0h) SYS_CFG_USER1 register, the
TOFF_DELAY time is automatically set to 0 ms, thus the device stops switching (tri-state power FETs)
immediately when a stop condition is received.
Return to Supported I2C and Default Values.
图7-23. (64h) TOFF_DELAY Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
TOFF_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-39. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
Description
Reserved
000000b Not used and always set to 0.
These bits select the turn-off delay options before starting soft-stop operation.
When soft-stop feature is disabled the TOFF_DELAY is automatically set to 0 ms.
00b: TOFF_DELAY time = 0 ms
TOFF_DEL
AY
R/W
NVM
01b: TOFF_DELAY time = 1 ms
10b: TOFF_DELAY time = 1.5 ms
11b: TOFF_DELAY time = 2 ms
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7.6.23 (65h) TOFF_FALL
CMD Address
Write Transaction:
Read Transaction:
Format:
65h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the
reference DAC is commanded to 0 mV. This command is used with the TPS544C26 device whose output can
sink enough current to cause the output voltage to decrease at a controlled rate, which effectively sets the slew
rate of the reference DAC during the soft-off period. The VOUT fall time is actually not equal to TOFF_FALL
value since the device stops SW switching once the output voltage is discharged to 200 mV, and the fall time is
more for setting the reference DAC slew rate. See Shutdown and 表7-8 for more details.
Return to Supported I2C and Default Values.
图7-24. (65h) TOFF_FALL Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
Reserved
TOFF_FALL
LEGEND: R/W = Read/Write; R = Read only
表7-40. Register Field Descriptions
Bit
7:2
1:0
Field
Access
R
Reset
Description
Reserved
TOFF_FALL
000000b Not used and always set to 0.
These bits select the soft-stop time option before disabling the SW switching and
tri-state the power FETs.
R/W
NVM
00b: TOFF_FALL time = 0.5 ms
01b: TOFF_FALL time = 1 ms
10b: TOFF_FALL time = 2 ms
11b: TOFF_FALL time = 4 ms
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7.6.24 (6Bh) PIN_OP_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
6Bh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The PIN_OP_WARN_LIMIT command sets the value of the input power, in watts, that causes a warning that the
input power is high. The PIN_MAX value which is the maximum input power threshold is always the same as
PIN_OP_WARN_LIMIT value. This feature utilizes a digital comparator that compares the output of the PIN
telemetry to the fault threshold selected in this register.
In response to the PIN_OP_WARN_LIMIT being exceeded, the device sets the PIN_OPW bit in the (7Ch)
STATUS_INPUT register.
Return to Supported I2C and Default Values.
图7-25. (6Bh) PIN_OP_WARN_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R/W
R/W
R/W
Reserved
PIN_OPW
LEGEND: R/W = Read/Write; R = Read only
表7-41. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not used and always set to 0.
These bits select the PIN_OPW and PIN_MAX thresholds.
000b: PIN_OPW = PIN_MAX = 510 W
001b: PIN_OPW = PIN_MAX = 480 W
010b: PIN_OPW = PIN_MAX = 420 W
011b: PIN_OPW = PIN_MAX = 360 W
100b: PIN_OPW = PIN_MAX = 300 W
101b: PIN_OPW = PIN_MAX = 240 W
110b: PIN_OPW = PIN_MAX = 180 W
111b: PIN_OPW = PIN_MAX = 120 W
2:0
PIN_OPW
R/W
NVM
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7.6.25 (7Ah) STATUS_VOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Ah
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The STATUS_VOUT command returns one data byte with contents as follows. All supported bits can be cleared
either by CLEAR_FAULTS, or individually by writing a "1" to the (7Ah) STATUS_VOUT register in their position. If
a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
图7-26. (7Ah) STATUS_VOUT Register Map
7
6
5
4
3
R
0
2
R
0
1
R
0
0
R
0
R/W
R/W
R/W
R/W
VOUT_OVF
VOUT_OVW
VOUT_UVW
VOUT_UVF
LEGEND: R/W = Read/Write; R = Read only
表7-42. Register Field Descriptions
Bit
Field
Access
Reset
Description
0b: Latched flag indicating a VOUT OV fault has not occurred.
7
VOUT_ OVF
R/W
0b
1b: Latched flag indicating either a VOUT Fixed OV fault or a VOUT Tracking OV
fault has occurred.
0b: Latched flag indicating a VOUT Tracking OV warn has not occurred.
VOUT_
OVW
6
5
R/W
R/W
0b
0b
1b: Latched flag indicating a VOUT Tracking OV warn has occurred.
0b: Latched flag indicating a VOUT Tracking UV warn has not occurred.
VOUT_
UVW
1b: Latched flag indicating a VOUT Tracking UV warn has occurred.
0b: Latched flag indicating a VOUT Tracking UV fault has not occurred.
4
VOUT_ UVF
R/W
R
0b
1b: Latched flag indicating a VOUT Tracking UV fault has occurred.
3:0
Not
0000b
Not supported and always set to 0.
supported
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7.6.26 (7Bh) STATUS_IOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Bh
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The STATUS_IOUT command returns one data byte with contents as follows. All supported bits can be cleared
either by CLEAR_FAULTS, or individually by writing a "1" to the (7Bh) STATUS_IOUT register in their position. If
a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
图7-27. (7Bh) STATUS_IOUT Register Map
7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
R/W
R/W
IOUT_OCL
IOUT_OCUV
LEGEND: R/W = Read/Write; R = Read only
表7-43. Register Field Descriptions
Bit
Field
Access
Reset
Description
0b: Latched flag indicating low-side valley OC limit has not occurred.
7
IOUT_ OCL
R
0b
1b: Latched flag indicating low-side valley OC limit has occurred.
0b: Latched flag indicating both low-side valley OC limit and VOUT Tracking UV
fault have not occurred.
IOUT_OCU
V
6
R/W
R
0b
1b: Latched flag indicating both low-side valley OC limit and VOUT Tracking UV
fault have occurred.
5:0
Not
000000b Not supported and always set to 0.
supported
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7.6.27 (7Ch) STATUS_INPUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Ch
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The STATUS_INPUT command returns one data byte with contents as follows. All supported bits can be cleared
either by CLEAR_FAULTS, or individually by writing a "1" to the (7Ch) STATUS_INPUT register in their position.
If a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Return to Supported I2C and Default Values.
图7-28. (7Ch) STATUS_INPUT Register Map
7
6
R
0
5
R
0
4
3
R
0
2
R
0
1
R
0
0
R/W
R/W
R/W
PVIN_OVF
PVIN_UVF
PIN_OPW
LEGEND: R/W = Read/Write; R = Read only
表7-44. Register Field Descriptions
Bit
7
Field
Access
R/W
R
Reset
Description
0b: Latched flag indicating a PVIN OV fault has not occurred.
PVIN_OVF
0b
1b: Latched flag indicating a PVIN OV fault has occurred.
6:5
Not
00b
Not supported and always set to 0.
supported
0b: Latched flag indicating a PVIN UV fault has not occurred.
4
PVIN_UVF
R/W
R
0b
1b: Latched flag indicating a PVIN UV fault has occurred.
3:1
Not
000b
Not supported and always set to 0.
supported
0b: Latched flag indicating a PIN OP event has not occurred.
0
PIN_ OPW
R/W
0b
1b: Latched flag indicating a PIN OP event has occurred.
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7.6.28 (7Dh) STATUS_TEMPERATURE
CMD Address
Write Transaction:
Read Transaction:
Format:
7Dh
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The STATUS_TEMPERATURE command returns one data byte with contents as follows. All supported bits can
be cleared either by CLEAR_FAULTS, or individually by writing a "1" to the (7Dh) STATUS_TEMPERATURE
register in their position. If a fault condition is still present when the corresponding bit is cleared, the fault bit is
immediately set again.
Return to Supported I2C and Default Values.
图7-29. (7Dh) STATUS_TEMPERATURE Register Map
7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
R/W
R/W
OTF_PROG
OTW_PROG
LEGEND: R/W = Read/Write; R = Read only
表7-45. Register Field Descriptions
Bit
Field
Access
Reset
Description
0b: Latched flag indicating an OT fault has not occurred.
1b: Latched flag indicating an OT fault has occurred on the Controller die.
7
OTF_PROG
R/W
0b
Note: A digital comparator on the Controller die is utilized to compare the output of
the IC TEMP telemetry to the fault threshold selected in (4Fh) OT_FAULT_LIMIT
register. This bit has no relationship with the overtemperature detection
implemented on the Power Stage (PS) die.
6
OTW_PRO
G
R/W
0b
0b: Latched flag indicating an OT warn has not occurred.
1b: Latched flag indicating an OT warn has occurred on the Controller die.
Note: A digital comparator on the Controller die is utilized to compare the output of
the IC TEMP telemetry to the warning threshold selected in (51h)
OT_WARN_LIMIT register. This bit has no relationship with the overtemperature
detection implemented on the Power Stage (PS) die.
5:0
Not
R
000000b Not supported and always set to 0.
supported
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7.6.29 (80h) STATUS_MFR_SPECIFIC
CMD Address
Write Transaction:
Read Transaction:
Format:
80h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The STATUS_MFR_SPECIFIC command returns one data byte with contents as follows. All supported bits,
except DCM bit, can be cleared either by CLEAR_FAULTS, or individually by writing a "1" to the (80h)
STATUS_MFR_SPECIFIC register in their position. If a fault condition is still present when the corresponding bit
is cleared, the fault bit is immediately set again.
Bit[7] DCM is a LIVE bit updated by the analog detection circuit, which continuously monitors the output of the
zero-cross comparator. During CCM operation, this bit shows a value of "0". Once the device enters DCM
operation this bit is set showing a value of "1".
Return to Supported I2C and Default Values.
图7-30. (80h) STATUS_MFR_SPECIFIC Register Map
7
6
5
4
3
2
1
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS_COMM_W RESTORE_ER
RN
PS_OTF_ANAL
OG
DCM
OTF_ANALOG
PS_FAULT
NOC
VDRV_UVF
R
LEGEND: R/W = Read/Write; R = Read only
表7-46. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
DCM
R/W
0b
A LIVE bit updated by the analog detection circuit, which continuously monitors the
output of the zero-cross comparator.
0b: Un-latched flag indicating the the device is under CCM operation.
1b: Un-latched flag indicating the the device is under DCM operation.
6
OTF_ANAL
OG
R/W
0b
0b: Latched flag indicating an OT fault has not occurred.
1b: Latched flag indicating an OT fault has occurred on the Controller die.
Note: An analog comparator on the Controller die is utilized to compare the output
of the IC temperature sensing circuit to a fixed threshold (166 °C typical). This bit
has no relationship with the overtemperature detection implemented on the Power
Stage (PS) die.
5
4
PS_FAULT
R/W
R/W
0b
0b
0b: Latched flag indicating no fault has occurred on Power Stage (PS) die.
1b: Latched flag indicating at least one fault has occurred on the PS die.
PS_COMM_
WRN
0b: Latched flag indicating no error has occurred for the communications between
the Controller and PS die.
1b: Latched flag indicating a communications error has occurred between the
Controller and PS die.
Note: A VCC reset (power cycle) is recommended when this bit is set.
3
RESTORE_
ERR
R/W
0b:
0b: Latched flag indicating no error has occurred during the initial restore from
NVM operation (copy the entire contents of the non-volatile User Store Memory to
the matching locations in the Operating Memory).
1b: Latched flag indicating an error has occurred during the initial restore from
NVM operation.
Note: The restore operation mentioned here refers to the one-time restore
operation during the initial power-on. This bit doesn't validate the
RESTORE_USER_ALL operation. A VCC reset (power cycle) is recommended
when this bit is set.
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表7-46. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
2
NOC
R/W
0b
0b: Latched flag indicating no NOC operation has occurred.
1b: Latched flag indicating at least one cycle of NOC operation has occurred.
1
0
PS_OTF_A
NALOG
R/W
0b
0b: Un-latched flag indicating an OT fault has not occurred.
1b: Un-latched flag indicating an OT fault has occurred on the Power Stage (PS)
die.
Note: An analog comparator on the Power Stage die is utilized to compare the
output of the IC temperature sensing circuit to a fixed threshold (166 °C typical).
This bit has no relationship with the overtemperature detection implemented on the
Controller die.
VDRV_UVF
R/W
0b
0b: Latched flag indicating a VDRV UV fault has not occurred.
1b: Latched flag indicating a VDRV UV fault has occurred.
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7.6.30 (88h) READ_VIN
CMD Address
Write Transaction:
Read Transaction:
Format:
88h
N/A
Read Byte
Unsigned Binary (1 byte)
NVM Backup:
Update Rate:
No
190 µs
8 V –16 V
Supported Range:
The READ_VIN command returns input voltage in Volts. See Telemetry for more details.
Return to Supported I2C and Default Values.
图7-31. (88h) READ_VIN Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_VIN
LEGEND: R/W = Read/Write; R = Read only
表7-47. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_
VIN_
R
Input
voltage
Input voltage (on pin 4 VINSENM) reading. See Telemetry for more details.
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7.6.31 (89h) READ_IIN
CMD Address
Write Transaction:
Read Transaction:
Format:
89h
N/A
Read Byte
Unsigned Binary (1 byte)
NVM Backup:
Update Rate:
No
95 µs
Supported Range:
0 A to 40 A (if PIN_SENSE_RES = 05h)
The READ_IIN command returns the measured input current in Amperes. See Telemetry for more details.
Return to Supported I2C and Default Values.
图7-32. (89h) READ_IIN Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_IIN
LEGEND: R/W = Read/Write; R = Read only
表7-48. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_IIN
R
Current
Status
Input current (over the external sensing resistor) reading. See Telemetry for more
details.
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7.6.32 (8Bh) READ_VOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
8Bh
N/A
Read Byte
Unsigned Binary (1 byte)
NVM Backup:
Update Rate:
No
190 µs
VOUT 5 mV step: up to 1.6 V
VOUT 10 mV step: up to 3.2 V
Supported Range
The READ_VOUT command returns the actual, measured output voltage (VOSNS−GOSNS) in Volts. See
Telemetry for more details.
Return to Supported I2C and Default Values.
图7-33. (8Bh) READ_VOUT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_VOUT
LEGEND: R/W = Read/Write; R = Read only
表7-49. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_
VOUT
R
Current
Status
Output voltage reading. See Telemetry for more details.
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7.6.33 (8Ch) READ_IOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
8Ch
N/A
Read Byte
Unsigned Binary (1 byte)
NVM Backup:
Update Rate:
No
95 µs
Supported Range:
0 A to 40 A (if ICC_MAX = 40 A)
The READ_IOUT command returns the measured output current in Amperes. See Telemetry for more details.
Return to Supported I2C and Default Values.
图7-34. (8Ch) READ_IOUT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_IOUT
LEGEND: R/W = Read/Write; R = Read only
表7-50. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_
IOUT
R
Current
Status
Output current reading. See Telemetry for more details.
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7.6.34 (8Dh) READ_TEMPERATURE_1
CMD Address
Write Transaction:
Read Transaction:
Format:
8Dh
N/A
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Update Rate:
190 µs
Supported Range:
–40°C to 150°C
The READ_TEMPERATURE_1 command returns the Controller die temperature in degrees Celsius. See
Telemetry for more details.
Return to Supported I2C and Default Values.
图7-35. (8Dh) READ_TEMPERATURE_1 Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_TEMPERATURE_1
LEGEND: R/W = Read/Write; R = Read only
表7-51. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_TEM
PERATURE
_1
R
Current
Status
Controller die temperture reading. See Telemetry for more details.
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7.6.35 (97h) READ_PIN
CMD Address
Write Transaction:
Read Transaction:
Format:
97h
N/A
Read Byte
Unsigned Binary (1 byte)
NVM Backup:
Update Rate:
No
95 µs
Supported Range:
0 W to 510 W (if PIN_OPW = 510 W)
The READ_PIN command returns the measured input power, in watts. See Telemetry for more details.
Return to Supported I2C and Default Values.
图7-36. (97h) READ_PIN Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_PIN
LEGEND: R/W = Read/Write; R = Read only
表7-52. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
READ_PIN
R
Current
Status
Input power reading. See Telemetry for more details.
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7.6.36 (A0h) SYS_CFG_USER1
Register Address
Write Transaction:
Read Transaction:
Format:
A0h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
On-the-fly. Note that many of the fields in this register either require the output to be disabled to
take effect or require (15h) STORE_USER_ALL then VCC reset.
Updates:
The SYS_CFG_USER1 command contains miscellaneous bits for the device configuration.
Return to Supported I2C and Default Values.
图7-37. (A0h) SYS_CFG_USER1 Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EN_SOFT_STO
P
OVRD_SVID_A OVRD_I2C_AD
DDR DR
FCCM
VOUT_CTRL
VRRDY_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-53. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
FCCM(1)
R/W
NVM
0b: Discontinuous conduction mode (DCM) operation at light loads.
1b: Forced continuous conduction mode (FCCM) operation at light loads.
6:5
VOUT_CTRL(1)
R/W
NVM
00b: Output voltage and offset are programmed through the SVID interface. Writes
to I2C register (A6h) VOUT_CMD are always accepted but do not change the
output voltage. Writes to (A8h) I2C_OFFST are always NACKed.
01b: Output voltage is programmed through the SVID interface and offset is
programmed through the I2C interface (A8h) I2C_OFFST. Writes to SVID (33h)
OFFSET register are always accepted but do not change the output voltage.
10b: Output voltage and offset are controlled via I2C register (A6h) VOUT_CMD
and (A8h) I2C_OFFST, respectively. Writes to SVID (33h) OFFSET register or
SetVID commands are always accepted but do not change the output voltage.
11b: Same as 10b.
4
EN_SOFT_STOP(1)
R/W
R/W
NVM
NVM
0b: The SW switching is turned off immediately (ignores TOFF_FALL (soft-stop)
and TOFF_DELAY is automatically set to 0 ms).
1b: The SW switching is turned off after going through TOFF_DELAY and
TOFF_FALL (soft-stop).
3:2 VRRDY_DELAY(1)
Program the rising edge delay time from soft start complete to VRRDY pin going
high:
00b: 0 ms
01b: 0.5 ms
10b: 1.0 ms
11b: 2.0 ms
1
0
OVRD_SVID_ADD
R(2)
R/W
R/W
NVM
NVM
This bit is reserved for future usage.
0b: I2C address is determined by pin-strapping on the I2C_ADDR pin.
1b: I2C address is determined by NVM backup.
OVRD_I2C_ADDR
(2)
(1) Writes are always accepted and the data is updated; however, in order for this bit to take effect, the device's swtiching must be
disabled, including the (02h) ON_OFF_CONFIG register cannot be set to "Always on" behavior.
(2) Writes are always accepted and the data is updated; however, in order for this bit to take effect, send a (15h) STORE_USER_ALL to
store the new value to NVM then reset the VCC.
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7.6.37 (A2h) I2C_ADDR
Register Address
Write Transaction:
Read Transaction:
Format:
A2h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Update the I2C_ADDR value, set the OVRD_I2C_ADDR bit, 节7.6.4 then VCC reset are all
Updates:
required for the device to respond to a new I2C address.
The I2C_ADDR command reads the I2C device address when the address is determined by pin-strapping. When
the OVRD_I2C_ADDR bit is set the device address is set by the value written into this register. Update the
I2C_ADDR value, set the OVRD_I2C_ADDR bit, execute (15h) STORE_USER_ALL then VCC reset are all
required for the device to respond to a new I2C address
Return to Supported I2C and Default Values.
图7-38. (A2h) I2C_ADDR Register Map
7
R
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
I2C_ADDR
LEGEND: R/W = Read/Write; R = Read only
表7-54. Register Field Descriptions
Bit
7
Field
Access
R
Reset
Description
Reserved
I2C_ADDR
0b
Reserved for TI usage.
6:0
R/W
NVM
These bits set the I2C address. By default, the address is set through the resistor
on the I2C_ADDR pin as described in Setting the I2C Address. The I2C address
can be changed through these bits together using the OVRD_I2C_ADDR bit. The
OVRD_I2C_ADDR bit must be set to "1", stored to NVM and the VCC resets
before the TPS544C26 will respond to the programmed new address.
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7.6.38 (A3h) SVID_ADDR
CMD Address
Write Transaction:
Read Transaction:
Format:
A3h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The SVID_ADDR command sets the SVID address for the device.
Return to Supported I2C and Default Values.
图7-39. (A3h) SVID_ADDR Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
Reserved
SVID_ADDR
LEGEND: R/W = Read/Write; R = Read only
表7-55. Register Field Descriptions
Bit
7:4
3:0
Field
Access
R
Reset
0000b
NVM
Description
Reserved
Not used and always set to 0.
SVID_ADD
R
R/W
0000b: SVID address = 00h
0001b: SVID address = 01h
0010b: SVID address = 02h
0011b: SVID address = 03h
0100b: SVID address = 04h
0101b: SVID address = 05h
0110b: SVID address = 06h
0111b: SVID address = 07h
1000b: SVID address = 08h
1001b: SVID address = 09h
1010b: SVID address = 0Ah
1011b: SVID address = 0Bh
1100b: SVID address = 0Ch
1101b: SVID address = 0Dh
1110b: Reserved
1111b: Reserved
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7.6.39 (A4h) IMON_CAL
CMD Address
Write Transaction:
Read Transaction:
Format:
A4h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
The IMON_CAL command contains 2 fields (Gain and Offset) for READ_IOUT (IMON) calibration.
Return to Supported I2C and Default Values.
图7-40. (A4h) IMON_CAL Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IMON_GAIN_CAL
IMON_OFS_CAL
LEGEND: R/W = Read/Write; R = Read only
表7-56. Register Field Descriptions
Bit
Field
Access
Reset
Description
These bits contains the READ_IOUT (IMON) gain calibration. This field gives
flexibility to change the gain of nominal reporting by −3.5% to +4%.
0000b: IMON Gain Adjustment = −3.5%
0001b: IMON Gain Adjustment = −3.0%
0010b: IMON Gain Adjustment = −2.5%
0011b: IMON Gain Adjustment = −2.0%
0100b: IMON Gain Adjustment = −1.5%
0101b: IMON Gain Adjustment = −1.0%
0110b: IMON Gain Adjustment = −0.5%
0111b: IMON Gain Adjustment = −0%
1000b: IMON Gain Adjustment = +0.5%
1001b: IMON Gain Adjustment = +1.0%
1010b: IMON Gain Adjustment = +1.5%
1011b: IMON Gain Adjustment = +2.0%
1100b: IMON Gain Adjustment = +2.5%
1101b: IMON Gain Adjustment = +3.0%
1110b: IMON Gain Adjustment = +3.5%
1111b: IMON Gain Adjustment = +4.0%
7:4 IMON_GAIN_CAL
R/W
NVM
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表7-56. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
These bits contains the READ_IOUT (IMON) offset calibration. This field gives
flexibility to change the nominal reporting by −2.0 A to 1.75 A. However, special
attention is needed when setting the offset adjustment to a negative value. The
calculation from the combination of ADC conversion and calibration register input is
not clamped at zero. When the calculated value of (ADC conversion result +
calibration offset value) goes negative, the final reporting value rolls over to a large
positive value (decreased from the maximum limit). For example, for a case of real
IOUT = 0.5 A, IMON offset adjutment = −1.0 A, ICC_MAX = 30 A, the final reporting
value is not clamped at 0 A, instread, the reporting value shows +29.5 A. TI
suggests using the calibration offset in a way that the calculated value from (ADC
conversion result + calibration offset value) never goes negative, especially at
minimum load case.
0000b - 0111b: Negative offset adjustment but NOT recommended to use if the
minimum load (IOUT) is 0 A. Contact TI for details in case of negative offset
adjustment needed.
3:0
IMON_OFS_CAL
R/W
NVM
1000b: IMON Offset Adjustment = 0 A
1001b: IMON Offset Adjustment = +0.25 A
1010b: IMON Offset Adjustment = +0.50 A
1011b: IMON Offset Adjustment = +0.75 A
1100b: IMON Offset Adjustment = +1.00 A
1101b: IMON Offset Adjustment = +1.25 A
1110b: IMON Offset Adjustment = +1.50 A
1111b: IMON Offset Adjustment = +1.75 A
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7.6.40 (A5h) IIN_CAL
CMD Address
Write Transaction:
Read Transaction:
Format:
A5h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
The IIN_CAL command contains 2 fields (Gain and Offset) for READ_IIN calibration.
Return to Supported I2C and Default Values.
图7-41. (A5h) IIN_CAL Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IIN_GAIN_CAL
IIN_OFS_CAL
LEGEND: R/W = Read/Write; R = Read only
表7-57. Register Field Descriptions
Bit
Field
Access
Reset
Description
These bits contains the READ_IIN gain calibration. This field gives flexibility to
change the gain of nominal reporting by −3.5% to +4%.
0000b: IIN Gain Adjustment = −3.5%
0001b: IIN Gain Adjustment = −3.0%
0010b: IIN Gain Adjustment = −2.5%
0011b: IIN Gain Adjustment = −2.0%
0100b: IIN Gain Adjustment = −1.5%
0101b: IIN Gain Adjustment = −1.0%
0110b: IIN Gain Adjustment = −0.5%
0111b: IIN Gain Adjustment = −0%
1000b: IIN Gain Adjustment = +0.5%
1001b: IIN Gain Adjustment = +1.0%
1010b: IIN Gain Adjustment = +1.5%
1011b: IIN Gain Adjustment = +2.0%
1100b: IIN Gain Adjustment = +2.5%
1101b: IIN Gain Adjustment = +3.0%
1110b: IIN Gain Adjustment = +3.5%
1111b: IIN Gain Adjustment = +4.0%
7:4
IIN_GAIN_CAL
R/W
NVM
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表7-57. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
These bits contains the READ_IIN offset calibration. This field gives flexibility to
change the nominal reporting by −2.0 A to 1.75 A. However, special attention is
needed when setting the offset adjustment to a negative value. The calculation
from the combination of ADC conversion and calibration register input is not
clamped at zero. When the calculated value of (ADC conversion result + calibration
offset value) goes negative, the final reporting value rolls over to a large positive
value (decreased from the maximum limit). For example, for a case of real IIN = 0.5
A, IIN offset adjutment = −1.0 A, IIN_MAX = 32 A, the final reporting value is not
clamped at 0 A, instread, the reporting value shows +31.5 A. TI suggests using the
calibration offset in a way that the calculated value from (ADC conversion result +
calibration offset value) never goes negative, especially at minimum IIN case.
0000b - 0111b: Negative offset adjustment but NOT recommended to use if the
minimum IIN is 0 A. Contact TI for details in case of negative offset adjustment
needed.
3:0
IIN_OFS_CAL
R/W
NVM
1000b: IIN Offset Adjustment = 0 A
1001b: IIN Offset Adjustment = +0.25 A
1010b: IIN Offset Adjustment = +0.50 A
1011b: IIN Offset Adjustment = +0.75 A
1100b: IIN Offset Adjustment = +1.00 A
1101b: IIN Offset Adjustment = +1.25 A
1110b: IIN Offset Adjustment = +1.50 A
1111b: IIN Offset Adjustment = +1.75 A
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7.6.41 (A6h) VOUT_CMD
Register Address
Write Transaction:
Read Transaction:
Format:
A6h
Write Byte
Read Byte
VID, either 5 mV/LSB or 10 mV/LSB
NVM Back-up:
Updates:
EEPROM
On-the-fly
If the VOUT_CTRL bits in (A0h) SYS_CFG_USER1 are set to 10b, VOUT_CMD causes the device to set its
output voltage to the commanded value. Output voltage changes due to VOUT_CMD occur at ¼ of the fast slew
rate which is selected in (AFh) DVS_CFG register.
The VOUT step (LSB) is either 5 mV/LSB or 10 mV/LSB which is determined by PROCOTOL_ID bits in (C2h)
PROTOCOL_ID_SVID register.
The device will NACK writes to VOUT_CMD during soft-start and soft-stop. The device will ACK writes to
VOUT_COMMAND after soft-start has completed. After soft-start has completed, writes to VOUT_CMD are also
allowed even if the output voltage is still transitioning to a previously programmed VOUT_CMD. The output
voltage will immediately begin transitioning to the newly programmed VOUT_CMD at the ¼ of the fast slew rate
which is selected in (AFh) DVS_CFG register. The device does not wait for the prior transition to completed.
Return to Supported I2C and Default Values.
图7-42. (A6h) VOUT_CMD Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VOUT_CMD
LEGEND: R/W = Read/Write; R = Read only
表7-58. Register Field Descriptions
Bit
Field
Access
Reset
Description
Sets the output voltage target via the I2C interface. See 表7-6 for the available
7:0
VOUT_CMD
R/W
NVM
values.
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7.6.42 (A7h) VID_SETTING
CMD Address
Write Transaction:
Read Transaction:
Format:
A7h
N/A
Read Byte
VID, either 5 mV/LSB or 10 mV/LSB
NVM Backup:
Update Rate:
No
190 µs
8 V –16 V
Supported Range:
The VID_SETTING command returns the last commanded VOUT level either from I2C or from SVID including
Vboot. The reading in this register is “in sync” with the SVID (31h) VID_SETTING register. This register does
not include any OFFSET contributions from either SVID or I2C space.
Return to Supported I2C and Default Values.
图7-43. (A7h) VID_SETTING Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VID_SETTING
LEGEND: R/W = Read/Write; R = Read only
表7-59. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
VID_SETTI
NG
R
Last
commanded
VOUT
These bits tells the last commanded VOUT (VID format).
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7.6.43 (A8h) I2C_OFFSET
Register Address
Write Transaction:
Read Transaction:
Format:
A8h
Write Byte
Read Byte
DIRECT
EEPROM
on-the-fly
NVM Back-up:
Updates:
The I2C_OFFSET is used to apply a fixed offset voltage to the output voltage command value. Output voltage
changes due to I2C_OFFSET occur at ¼ of the fast slew rate which is selected in (AFh) DVS_CFG register..
The usage of I2C_OFFSET depends on the value of VOUT_CTRL in (A0h) SYS_CFG_USER1 register. See 表
7-4 for more details.
When the PROTOCOL_ID bits in (C2h) PROTOCOL_ID_SVID is 01b or 10b (VOUT step = 5 mV), the
I2C_OFFSET adds offset to the output voltage with the 0.5 mV/LSB. With a signed implementation, the offset
can be programmed in a range of −64 mV to +63 mV.
When the PROTOCOL_ID bits in (C2h) PROTOCOL_ID_SVID is 00b or 11b (VOUT step = 10 mV), the
I2C_OFFSET adds offset to the output voltage with the 1.0 mV/LSB. With a signed implementation, the offset
can be programmed in a range of −128 mV to +127 mV.
Return to Supported I2C and Default Values.
图7-44. (A8h) I2C_OFFSET Register Map
7
6
5
4
3
2
1
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C_OFFSET
LEGEND: R/W = Read/Write; R = Read only
表7-60. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
I2C_OFFSET
R/W
NVM
Output voltage offset with Direct format.
VOUT step = 5 mV configuration: I2C OFFSET is 0.5 mV/LSB, with a range of −64
mV to +63 mV.
VOUT step = 10 mV configuration: I2C OFFSET is 1.0 mV/LSB, with a range of
−128 mV to +127 mV.
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7.6.44 (A9h) COMP1_MAIN
CMD Address
Write Transaction:
Read Transaction:
Format:
A9h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
The COMP1_MAIN command contains 2 fields (AC Gain and AC Load Line) for the control loop compensation.
See Loop Compensation for more details.
The AC_GAIN bits select the gain of the AC paths including the output voltage error and the load current step.
The AC Load Line (ACLL) bits set the AC response to an output voltage error.
Return to Supported I2C and Default Values.
图7-45. (A9h) COMP1_MAIN Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AC_GAIN
ACLL
LEGEND: R/W = Read/Write; R = Read only
表7-61. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
AC_GAIN
R/W
NVM
These bits determine the AC gain setting.
0000b: AC Gain = 0.3
0001b: AC Gain = 0.5
0010b: AC Gain = 1.0
0011b: AC Gain = 1.5
0100b: AC Gain = 2.0
0101b: AC Gain = 2.5
0110b: AC Gain = 3.0
0111b: AC Gain = 3.5
1000b: AC Gain = 4.0
1001b: AC Gain = 5.0
1010b: AC Gain = 6.0
1011b: AC Gain = 7.0
1100b to 1111b: Reserved. Do not set AC Gain to these values.
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表7-61. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
3:0
ACLL
R/W
NVM
These bits determine the AC Load Line (ACLL) setting.
0000b: ACLL = 0.5
0001b: ACLL = 1.0
0010b: ACLL = 1.5
0011b: ACLL = 2.0
0100b: ACLL = 2.5
0101b: ACLL = 3.0
0110b: ACLL = 3.5
0111b: ACLL = 4.0
1000b: ACLL = 5.0
1001b: ACLL = 6.0
1010b: ACLL = 7.0
1011b: ACLL = 9.0
1100b: ACLL = 10.0
1101b: ACLL = 12.0
1110b: ACLL = 13.0
1111b: ACLL = 15.0
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7.6.45 (AAh) COMP2_MAIN
CMD Address
Write Transaction:
Read Transaction:
Format:
AAh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
This COMP2_MAIN command contains 3 fields for configuring the internal integration circuit and the ramp
generation circuit. See Loop Compensation for more details.
The INT_GAIN bits select the gain of the integration stage.
The INT_TIME bits set the time constant of the integration stage which affects the settling and response time
following an output voltage error.
The RAMP bits select the amplitude of the internal-generated ramp.
Return to Supported I2C and Default Values.
图7-46. (AAh) COMP2_MAIN Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INT_GAIN
INT_TIME
RAMP
LEGEND: R/W = Read/Write; R = Read only
表7-62. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
INT_GAIN
R/W
NVM
These bits selects the gain of the integration stage.
00b: integration stage gain = 2
01b: integration stage gain = 1.5
10b: integration stage gain = 1
11b: integration stage gain = 0.5
5:3
INT_TIME
R/W
NVM
These bits set the time constant of the integration stage which affects the settling
and response time following an output voltage error.
000b: integration time constant = 0.25 µs
001b: integration time constant = 1.0 µs
010b: integration time constant = 3.0 µs
011b: integration time constant = 4.5 µs
100b: integration time constant = 6.25 µs
101b: integration time constant = 8.0 µs
110b: integration time constant = 10.0 µs
111b: integration time constant = 20.0 µs
2:0
RAMP
R/W
NVM
These bits select the amplitude of the internal-generated ramp.
000b: ramp amplitude = 40 mV
001b: ramp amplitude = 60 mV
010b: ramp amplitude = 80 mV
011b: ramp amplitude = 100 mV
100b: ramp amplitude = 120 mV
101b: ramp amplitude = 160 mV
110b: ramp amplitude = 200 mV
111b: ramp amplitude = 240 mV
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7.6.46 (ABh) COMP1_ALT
CMD Address
Write Transaction:
Read Transaction:
Format:
ABh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
The COMP1_ALT command contains 2 alternate fields (AC Gain and AC Load Line) for the control loop
compensation. This register is not activated in the TPS544C26 device and affects nothing.
Return to Supported I2C and Default Values.
图7-47. (ABh) COMP1_ALT Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AC_GAIN_ALT
ACLL_ALT
LEGEND: R/W = Read/Write; R = Read only
表7-63. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
AC_GAIN_ALT
R/W
NVM
These bits determine the alternate AC gain setting.
0000b: alternate AC Gain = 0.3
0001b: alternate AC Gain = 0.5
0010b: alternate AC Gain = 1.0
0011b: alternate AC Gain = 1.5
0100b: alternate AC Gain = 2.0
0101b: alternate AC Gain = 2.5
0110b: alternate AC Gain = 3.0
0111b: alternate AC Gain = 3.5
1000b: alternate AC Gain = 4.0
1001b: alternate AC Gain = 5.0
1010b: alternate AC Gain = 6.0
1011b: alternate AC Gain = 7.0
1100b to 1111b: Reserved. Do not set AC Gain to these values.
3:0
ACLL_ALT
R/W
NVM
These bits determine the alternate AC Load Line (ACLL) setting.
0000b: alternate ACLL = 0.5
0001b: alternate ACLL = 1.0
0010b: alternate ACLL = 1.5
0011b: alternate ACLL = 2.0
0100b: alternate ACLL = 2.5
0101b: alternate ACLL = 3.0
0110b: alternate ACLL = 3.5
0111b: alternate ACLL = 4.0
1000b: alternate ACLL = 5.0
1001b: alternate ACLL = 6.0
1010b: alternate ACLL = 7.0
1011b: alternate ACLL = 9.0
1100b: alternate ACLL = 10.0
1101b: alternate ACLL = 12.0
1110b: alternate ACLL = 13.0
1111b: alternate ACLL = 15.0
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7.6.47 (ACh) COMP2_ALT
CMD Address
Write Transaction:
Read Transaction:
Format:
ACh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
On-the-fly
This COMP2_ALT command contains 3 alternate fields for configuring the internal integration circuit and the
ramp generation circuit. This register is not activated in the TPS544C26 device and affects nothing.
Return to Supported I2C and Default Values.
图7-48. (ACh) COMP2_ALT Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INT_GAIN_ALT
INT_TIME_ALT
RAMP_ALT
LEGEND: R/W = Read/Write; R = Read only
表7-64. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
INT_GAIN_ALT
R/W
NVM
These bits selects the gain of the integration stage.
00b: alternate integration stage gain = 2
01b: alternate integration stage gain = 1.5
10b: alternate integration stage gain = 1
11b: alternate integration stage gain = 0.5
5:3
INT_TIME_ALT
R/W
NVM
These bits set the time constant of the integration stage which affects the settling
and response time following an output voltage error.
000b: alternate integration time constant = 0.25 µs
001b: alternate integration time constant = 1.0 µs
010b: alternate integration time constant = 3.0 µs
011b: alternate integration time constant = 4.5 µs
100b: alternate integration time constant = 6.25 µs
101b: alternate integration time constant = 8.0 µs
110b: alternate integration time constant = 10.0 µs
111b: alternate integration time constant = 20.0 µs
2:0
RAMP_ALT
R/W
NVM
These bits select the amplitude of the internal-generated ramp.
000b: alternate ramp amplitude = 40 mV
001b: alternate ramp amplitude = 60 mV
010b: alternate ramp amplitude = 80 mV
011b: alternate ramp amplitude = 100 mV
100b: alternate ramp amplitude = 120 mV
101b: alternate ramp amplitude = 160 mV
110b: alternate ramp amplitude = 200 mV
111b: alternate ramp amplitude = 240 mV
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7.6.48 (ADh) COMP3
CMD Address
Write Transaction:
Read Transaction:
Format:
ADh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The COMP3 command contains 4 fields for configuring the control loop.
The EN_SS_DCM bit sets the operation mode during the soft-start ramp. With value "1" on this bit, the device is
forced to under DCM operation during the soft-start ramp. This bit doesn't control the operation mode after the
soft-start ramp completes.
The SEL_NOC_TON bit selects the on-time reference for a NOC operation and thus determines the high-side
FET conduction time during a NOC operation period. The on-time option selected here can help to avoid two
undesired behaviors:
• For relatively low VOUT applications (such as VOUT = 1.1 V) using longer tON_NOC helps to prevent negative
current run-away behavior. A NOC run-away behavior occurs when the inductor current moves more
negatively during low-side FET conduction time than the movement during high-side conduction time. A NOC
run-away behavior can lead to excessive stress on low-side FET and raise the concern of FET reliability.
• For applications with an extra large inductor current ripple (≥10 A) and the NOC threshold is set to a less
negative value (for example NOC threshold = −7.5 A), the average current during the NOC operation is likely
not that negative. This leads to insufficient discharge on VOUT and thus the load is stressed under the
overvoltage condition for a longer period. To build sufficient negative current during the NOC operation, select
the shorter tON_NOC to reduce the positive inductor current movement during the high-side on-time. A design
example of this kind of case is VCCFA_EHV rail which can have the following configuration: PVIN = 12 V,
VOUT = 1.8 V, fSW = 1 MHz, LOUT = 150 nH, ICC_MAX = 10 A, and NOC threshold = −7.5 A. To have
sufficient discharge on VOUT, the design can either select the shorter tON_NOC or set ICC_MAX to 15 A so
that the NOC threshold is more negative (such as −15 A).
These SEL_LO_CS bits select the LOUT (output inductor value) for the current sensing circuit. The TPS544C26
IC utilizes the output inductor value entered here to build an accurate output from the current sense circuit.
Please choose a value closest to the inductor that is used in a BOM. For any inductor value higher than 400 nH,
set SEL_LO_CS to 11b. Selecting a value that is significantly different from the real inductor (for example, 400
nH used but 100 nH selected) can lead to an inaccurate current sense output which can cause unexpected
control loop behavior and also an inaccurate READ_IOUT telemetry report.
The DCLL bits determine the DC load line setting. Select a DCLL value per the requirement from the processor
or the load, otherwise, the load regulation can be out of expectation.
Return to Supported I2C and Default Values.
图7-49. (ADh) COMP3 Register Map
7
6
5
4
3
2
1
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SEL_NOC_TO
N
Reserved
EN_SS_DCM
SEL_LO_CS
DCLL
LEGEND: R/W = Read/Write; R = Read only
表7-65. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
Reserved
R
0b
Not used and always set to 0.
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表7-65. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
6
EN_SS_DC
M
R/W
NVM
0b: the operation during the soft-start ramp follows the configuration set by the
FCCM bit in (A0h) SYS_CFG_USER1 register.
1b: Forced DCM operation during the soft-start ramp
5
SEL_NOC_
TON
R/W
R/W
NVM
NVM
Select the on-time for NOC operation. See for more details
4:3
SEL_LO_C
S
These bits select the LOUT (output inductor value) for the current sensing circuit.
00b: LOUT = 100 nH
01b: LOUT = 200 nH
10b: LOUT = 300 nH
11b: LOUT = 400 nH
2:0
DCLL
R/W
NVM
These bits determine the DCLL setting.
000b: DCLL = 0 mΩ (VOUT maintains the regulation regardless of the load current)
001b: DCLL = 0.5 mΩ
010b: DCLL = 0.75 mΩ
011b: DCLL = 1.0 mΩ
100b: DCLL = 1.5 mΩ
101b: DCLL = 2.9 mΩ
110b: DCLL = 3.2 mΩ
111b: DCLL = 4.05 mΩ
表7-66. High-side On Time During a NOC Operation
PROTOCOL_ID in (C2h)
PROTOCOL_ID_SVID
SEL_NOC_TON
Option
tON_NOC (ns)
Use:
0.6 V
PVIN × f
1
Shorter tON_NOC
t
t
t
t
=
=
=
=
(9)
(10)
(11)
(12)
ON_NOC
ON_NOC
ON_NOC
ON_NOC
SW
PROTOCOL_ID = 01b or 10b (VOUT
step = 5 mV)
Use:
Use:
Use:
1.6 V
PVIN × f
0
1
0
Longer tON_NOC
Shorter tON_NOC
Longer tON_NOC
SW
SW
SW
1.2 V
PVIN × f
PROTOCOL_ID = 00b or 11b (VOUT
step = 10 mV)
3.2 V
PVIN × f
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7.6.49 (AFh) DVS_CFG
Register Address
Write Transaction:
Read Transaction:
Format:
AFh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Updates:
on-the-fly
The DVS_CFG sets the fast slew rate at which any output voltage changes per SVID SetVID-Fast command.
This commanded rate of change does not apply when the unit is commanded to turn on or to turn off. The unit is
mV/μs.
Return to Supported I2C and Default Values.
图7-50. (AFh) DVS_CFG Register Map
7
6
5
R
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
Reserved
DVS_CFG
LEGEND: R/W = Read/Write; R = Read only
表7-67. Register Field Descriptions
Bit
7:3
2:0
Field
Access
R
Reset
00000b
NVM
Description
Reserved
DVS_CFG
Not used and always set to 0.
R/W
These bits select the Dynamic Voltage Scale (DVS) fast slew rate. Upon
acknowledging a new value written into this register, the new slew rate value is
loaded into SVID (24h) SR_FAST register immediately. See below table for details.
表7-68. Dynamic Voltage Scale Fast Slew Rate Options
DVS Fast Slew Rate (mV/μs)
DVS_CFG
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV)
PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV)
000
001
010
011
100
101
110
111
1.34
1.43
2.50
2.67
5.00
5.56
10.00
12.50
2.67
2.86
5.00
5.34
10.00
11.12
20.00
25.00
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7.6.50 (B0h) DVID_OFFSET
CMD Address
Write Transaction:
Read Transaction:
Format:
B0h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The DVID_OFFSET command contains 2 fields for configuring the DAC offset during a DVID transition. This
Vout-referred offset is added only during a DVID transition (for example per SetVID or SetWP command).
DVID_OFS_UP is used to compensate for delays in the feedback compensation network and reach the target
value faster for DVID up scenario, and DVID_OFS_DOWN is implemented to prevent the output from ringing
below the target for DVID down scenario. Note that:
• The offsets are used only when the selected DVID slew rate is Fast or Slow.
• The offsets are not used when the selected DVID slew rate is Decay nor for (A6h) VOUT_CMD changes via
I2C.
• The offsets are not used during soft-start nor during soft-stop period.
Return to Supported I2C and Default Values.
图7-51. (B0h) DVID_OFFSET Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
Reserved
DVID_OFS_DOWN
DVID_OFS_UP
LEGEND: R/W = Read/Write; R = Read only
表7-69. Register Field Descriptions
Bit
7:4
3:2
Field
Access
R
Reset
0000b
NVM
Description
Reserved
Not used and always set to 0.
DVID_OFS_
DOWN
R/W
This positive offset is effectively a threshold: When the new VID target is lower than
the current VOUT, the DAC starts counting down from its current value using the
selected slew rate, and continues until the DAC reaches VID target +
DVID_OFS_DOWN. At that point, the VOUT transition slew rate changes to ¼ of
the selected slew rate until the actual VID target is reached.
00b: DVID_OFS_DOWN = 0 mV
01b: DVID_OFS_DOWN = 5 mV
10b: DVID_OFS_DOWN = 10 mV
11b: DVID_OFS_DOWN = 20 mV
1:0
DVID_OFS_
UP
R/W
NVM
This positive DAC offset is to be added when the new VID target is higher than the
current VOUT. DVID_OFS_UP is added immediately to the current DAC count as
the first step toward the new target, and as soon as the DAC count reaches the
VID target, the DAC stops the ramp, and DVID_OFS_UP is no longer applied.
00b: DVID_OFS_UP = 0 mV
01b: DVID_OFS_UP = 5 mV
10b: DVID_OFS_UP = 10 mV
11b: DVID_OFS_UP = 20 mV
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7.6.51 (B1h) REG_LOCK
CMD Address
Write Transaction:
Read Transaction:
Format:
B1h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
NVM Backup:
Updates:
On-the-fly
The REG_LOCK command controls writing to the TPS544C26 device. The intent of this command is to provide
protection against accidental changes. This command does NOT provide protection against deliberate or
malicious changes to a configuration or operation of the device.
After power-on, the user accessible registers with write access are by default under "write protected" state,
meaning the response to a write is NACK. The device always acknowledges a read command and responds the
data byte accordantly. Only after writing the correct passcodes (multiple writes in the right order) into this
REG_LOCK register, the user accessible registers are "unlocked" and the device acknowledges the next write
commands. For a device under "unlock" state, the writable registers turn to "write protected" state again if one
more write is sent to (B1h) REG_LOCK register, no matter with the correct passcode or wrong one. The user has
to go through the complete passcode write combination to unlock the write protection again.
For a device under "unlock" state, VCC power cycling resets the device and the user accessible registers with
write access are now under "write protected" state. A RESTORE_USER_ALL command does not change the
state.
The expected response for a write into this REG_LOCK register is always NACK, no matter with a correct
passcode or a wrong value. For security considerations, the passcodes are not listed in this datasheet. Please
contact TI for more details.
All user accessible registers with write access are protected by this mechanism except below ones:
• (03h) CLEAR_FAULTS
• (7Ah) STATUS_VOUT
• (7Bh) STATUS_IOUT
• (7Ch) STATUS_INPUT
• (7Dh) STATUS_TEMPERATURE
• (80h) STATUS_MFR
• (A2h) I2C_ADDR, bit[7] - this bit is reserved for TI usage and always under write protection
• (B1h) REG_LOCK
Return to Supported I2C and Default Values.
图7-52. (B1h) REG_LOCK Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Passcode
LEGEND: R/W = Read/Write; R = Read only
表7-70. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
Passcode
W
00000000b Write the passcodes to unlock the write protection.
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7.6.52 (B3h) PIN_SENSE_RES
CMD Address
Write Transaction:
Read Transaction:
Format:
B3h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The PIN_SENSE_RES command selects the external input current/power sense resistor value and related
configurations. The supported sensing resistor value ranges from 0.25 mΩ to 4 mΩ.
Return to Supported I2C and Default Values.
图7-53. (B3h) PIN_SENSE_RES Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R/W
R/W
R/W
Reserved
PIN_SENSE_RES
LEGEND: R/W = Read/Write; R = Read only
表7-71. Register Field Descriptions
Bit
7:3
2:0
Field
Access
R
Reset
00000b
NVM
Description
Reserved
Not used and always set to 0.
PIN_SENSE
_RES
R/W
These bits select the external sensing resistor used for input current/power
measurement. See below table for more details.
表7-72. Input Current/Power Sense Resistor Value and IIN_MAX
RSENSE used in a BOM
(mΩ)
PIN_SENSE_RES
Internal Gain (V/V)
IIN_MAX (A)
IIN LSB (A)
0.0625
000
001
010
011
100
101
110
111
4
3
12.5
12.5
25
16
21.3
16
0.0833
0.0625
0.15625
0.125
2
1
20
40
1
25
32
0.5
0.5
0.25
40
40
0.15625
0.125
50
32
50
64
0.250
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7.6.53 (B4h) IOUT_NOC_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
B4h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The IOUT_NOC_LIMIT command contains 3 fields for configuring the VOUT Fixed OVF and Neagive
Overcurrent (NOC) limit selection.
The SEL_FIX_OVF bit sets the value of the output voltage measured at the (VOSNS − GOSNS) pins that
causes an output overvoltage fault. The Fixed OVF function sets a constant overvoltage threshold that has no
relationship to the current VOUT setting. The VOUT Fixed OVF is active as soon as the TPS544C26 device
completes its power-on reset, even if the output conversion is disabled.
Following a Fixed OVF condition, the device always latches OFF high-side MOSFET and latches ON low-side
MOSFET. The response setting in (41h) VOUT_OV_FAULT_RESP register does not affect the response for a
Fixed OVF condition.
The VOUT Fixed OVF feature can be disabled through the EN_FIX_OVF bit.
The NOC threshold which scales with ICC_MAX setting (see (C0h) ICC_MAX) is selected by SEL_NOC field.
Return to Supported I2C and Default Values.
图7-54. (B4h) IOUT_NOC_LIMIT Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
Reserved
SEL_FIX_OVF EN_FIX_OVF
SEL_NOC
LEGEND: R/W = Read/Write; R = Read only
表7-73. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
Reserved
R
0000b
Not used and always set to 0.
SEL_FIX_O
VF
3
2
R/W
R/W
R/W
NVM
NVM
NVM
Select the VOUT Fixed OVF thresholds. See details on 表7-74.
EN_FIX_OV
F
0b: Enable the VOUT Fixed OVF
1b: Disable the VOUT Fixed OVF
SEL_NOC
Select the Negative Overcurrent limits which scale with ICC_MAX setting. See
details on 表7-75.
1:0
表7-74. VOUT Fixed OV Fault Thresholds
PROTOCOL_ID in (C2h)
PROTOCOL_ID_SVID
SEL_FIX_OVF[1] in (B4h)
VOUT Fixed OVF threshold (V)
IOUT_NOC_LIMIT
PROTOCOL_ID = 01b or 10b (VOUT step =
5 mV)
0
1
0
1
1.5
1.8
2.4
3.0
PROTOCOL_ID = 01b or 10b (VOUT step =
5 mV)
PROTOCOL_ID = 00b or 11b (VOUT step =
10 mV)
PROTOCOL_ID = 00b or 11b (VOUT step =
10 mV)
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表7-75. Negative Overcurrent Limits
Negative Overcurrent Limits (A)
SEL_NOC[1:0]
ICC_MAX ≥15 A
ICC_MAX ≤10 A
00
01
10
11
−20
−15
−12
−10
−10
−7.5
−6
−5
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7.6.54 (B5h) USER_DATA_01
CMD Address
Write Transaction:
Read Transaction:
Format:
B5h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The USER_DATA_01 command provides memory for users to store manufacturer specific information. User
chooses the format and data value.
Return to Supported I2C and Default Values.
图7-55. (B5h) USER_DATA_01 Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R
R
R
R
USER_DATA_01
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-76. Register Field Descriptions
Bit
7:4
3:0
Field
Access
Reset
Description
USER_DAT
A_01
R
R
NVM
User to store manufacturer specific information
Not used and always set to 0.
Reserved
0000b
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7.6.55 (B6h) USER_DATA_02
CMD Address
Write Transaction:
Read Transaction:
Format:
B6h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The USER_DATA_02 command provides memory for users to store manufacturer specific information. User
chooses the format and data value.
Return to Supported I2C and Default Values.
图7-56. (B6h) USER_DATA_02 Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R
R
R
R
R
USER_DATA_02
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-77. Register Field Descriptions
Bit
7:5
4:0
Field
Access
R/W
R
Reset
Description
USER_DAT
A_02
NVM
User to store manufacturer specific information
Not used and always set to 0.
Reserved
00000b
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7.6.56 (BAh) STATUS1_SVID
CMD Address
Write Transaction:
Read Transaction:
Format:
BAh
N/A
Read Byte
Unsigned Binary (1 byte)
The STATUS1_SVID command contains direct copies of the bits of SVID (10h) STATUS_1 register. When a bit
in the SVID (10h) STATUS_1 register is cleared via the SVID bus, the corresponding bit in I2C (BAh)
STATUS1_SVID register also get cleared. There is no separate clear mechanism for the bits in BAh register via
the I2C bus.
Return to Supported I2C and Default Values.
图7-57. (BAh) STATUS1_SVID Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_STATUS
2
Reserved
VID_DAC_High
IccMaxAlert
ThermAlert
VR_Settled
LEGEND: R/W = Read/Write; R = Read only
表7-78. Register Field Descriptions
Bit
7
Field
Access
Reset
Description
READ_STA
TUS2
Current
status
R
R
R
Defined by Intel. Refer to Intel document for details.
Not supported and always set to 0.
Defined by Intel. Refer to Intel document for details.
6:4
3
Reserved
000b
VID_DAC_H
igh
Current
status
Current
status
2
1
IccMaxAlert
ThermAlert
R
R
Defined by Intel. Refer to Intel document for details.
Defined by Intel. Refer to Intel document for details.
Current
status
0
VR_Settled
R
Current
status
Defined by Intel. Refer to Intel document for details.
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7.6.57 (BBh) STATUS2_SVID
CMD Address
Write Transaction:
Read Transaction:
Format:
BBh
N/A
Read Byte
Unsigned Binary (1 byte)
The STATUS2_SVID command contains direct copies of the bits of SVID (11h) STATUS_2 register. When a bit in
the SVID (11h) STATUS_2 register is cleared via the SVID bus, the corresponding bit in I2C (BBh)
STATUS2_SVID register also get cleared. There is no separate clear mechanism for the bits in BBh register via
the I2C bus.
Return to Supported I2C and Default Values.
图7-58. (BBh) STATUS2_SVID Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
SVID_OCL_LA
TCH
Reserved
SVID_frame_err SVID_parity_err
LEGEND: R/W = Read/Write; R = Read only
表7-79. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not supported and always set to 0.
SVID_OCL_
LATCH
Current
status
2
1
R
R
Defined by Intel. Refer to Intel document for details.
Defined by Intel. Refer to Intel document for details.
SVID_frame
_err
Current
status
0
SVID_parity
_err
R
Current
status
Defined by Intel. Refer to Intel document for details.
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7.6.58 (BCh) CAPABILITY
CMD Address
Write Transaction:
Read Transaction:
Format:
BCh
N/A
Read Byte
Unsigned Binary (1 byte)
The CAPABILITY command contains direct copies of the bits of SVID (06h) CAPABILITY register, which
indicates telemetry capabilities of the part. This register is read-only.
Return to Supported I2C and Default Values.
图7-59. (BCh) CAPABILITY Register Map
7
R
6
R
5
4
3
2
1
R
0
R
R
R
R
R
IOUT
TEMP
PIN
VIN
IIN
POUT
VOUT
VR13+
LEGEND: R/W = Read/Write; R = Read only
表7-80. Register Field Descriptions
Bit
7
Field
IOUT
TEMP
PIN
Access
Reset
Description
R
R
R
R
R
R
R
R
1b
1b: IOUT telemetry is supported
1b: TEMP telemetry is supported
1b: PIN telemetry is supported
1b: VIN telemetry is supported
1b: IIN telemetry is supported
0b: POUT telemetry is NOT supported
1b: VOUT telemetry is supported
6
1b
5
1b
4
VIN
1b
3
IIN
1b
2
POUT
VOUT
VR13+
0b
1
1b
0
1b
1b: The output current telemetry is supported in the VR13+ format
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7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
CMD Address
Write Transaction:
Read Transaction:
Format:
BDh
Write Byte
Read Byte
Unsigned Binary (1 byte)
Bit[7:1]: No
Bit[0]: Yes
NVM Backup:
Updates:
Bit[0] only: On-the-fly when the power conversion is disabled. A write is not allowed (NACK
response) when the power conversion is enabled.
The EXT_CAPABILITY_VIDOMAX_H command contains direct copies of the bits of SVID (09h)
VIDOMAX_H_CAPA register except bit[0]. The lowest bit (bit[0]) is MSB of 9-bit VIDo_MAX value and the user
can read and write into this bit. See more details in (BEh) VIDO_MAX_L register. The rest 7 bits in this register
indicates the extended capabilities of the part. These 7 bits are read-only.
Return to Supported I2C and Default Values.
图7-60. (BDh) EXT_CAPABILITY_VIDOMAX_H Register Map
7
R
6
R
5
4
3
2
1
R
0
R
R
R
R
R/W
PsysWarn
IMON_CAL
DFDS
DFDV
HI_PRES
IccInMax
Reserved
VIDo_MAX[8]
LEGEND: R/W = Read/Write; R = Read only
表7-81. Register Field Descriptions
Bit
7
Field
PsysWarn
IMON_CAL
DFDS
Access
Reset
Description
R
R
0b
0b: PsysWarn is NOT supported
0b: SVID IMON_CAL is NOT supported
0b: DFDS function is NOT supported
0b: DFDV function is NOT supported
0b: HI_PRES telemetry is NOT supported
1b: IccInMax is supported for IIN telemetry
Not used and always set to 0.
6
0b
5
R
0b
4
DFDV
R
0b
3
HI_PRES
IccInMax
Reserved
R
0b
2
R
0b
1
R
0b
0
VIDo_MAX[
8]
R/W
NVM
MSB of 9-bit VIDo_MAX value. See more details in (BEh) VIDO_MAX_L register.
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7.6.60 (BEh) VIDOMAX_L
Register Address
Write Transaction:
Read Transaction:
Format:
BEh
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
On-the-fly when the power conversion is disabled. A write is not allowed (NACK response) when
the power conversion is enabled.
Updates:
The VIDOMAX_L command together with the bit[0] in (BDh) EXT_CAPABILITY_VIDOMAX_H forms a 9-bit
register to set the maximum value of (VID+Offset) allowed via SVID. Setting the 9-bit VIDo_MAX register to 17E
(hex) value reaches the maximum possible (VID+Offset) value with 8-bit register for each (VID unsigned, offset
signed).
Exceeding VIDo_MAX with (VID + offset) causes a REJ (Reject) response for individual rail SVID requests and a
NACK response for all-call SVID requests.
When a write to this register is attempted, the VIDOMAX_L value combined with VIDo_MAX[8] value (bit[0] in
(BDh) EXT_CAPABILITY_VIDOMAX_H register) must satisfy a range check:
• If the combined value is not greater than 0, the write is NACKed.
• If the combined value is greater than 0, then the write is ACKed.
Further, VIDo_MAX bit in (BDh) EXT_CAPABILITY_VIDOMAX_H register does not take effect when updated. It
only takes effect when the VIDOMAX_L register is written with a value (can be the same value as the current
one) and also the combined value satisfies the range check. When attempting to write a new VIDo_MAX value, it
is recommended to write in the following order: write into the (BDh) EXT_CAPABILITY_VIDOMAX_H register
first, and then write into the VIDOMAX_L register. To illustrate, a few examples are listed below:
• Example #1: Firstly, a value is written into (BDh) EXT_CAPABILITY_VIDOMAX_H register and is
acknowledged. Secondly, another write command is sent to (BEh) VIDOMAX_L register and this write is
acknowledged too.
– Result: The 9-bit VIDo_MAX register is updated and takes effect.
• Example #2: A value is written into (BEh) VIDOMAX_L register and is acknowledged. No write command is
sent to (BDh) EXT_CAPABILITY_VIDOMAX_H register.
– Result: The 9-bit VIDo_MAX register is updated in the lower 8-bit (in (BEh) VIDOMAX_L register) and the
new value takes effect.
• Example #3: Firstly, a value is written into (BEh) VIDOMAX_L register and is acknowledged. Secondly,
another write command is sent to (BDh) EXT_CAPABILITY_VIDOMAX_H register to update VIDo_MAX bit
with a new value and this write is acknowledged too.
– Result: The 9-bit VIDo_MAX register is updated but the VIDo_MAX bit in (BDh)
EXT_CAPABILITY_VIDOMAX_H register does not take effect.
Note: (BDh) EXT_CAPABILITY_VIDOMAX_H and (BEh) VIDOMAX_L registers acknowledges a write only when
the power conversion is disabled. A write is not allowed (NACK response) when the power conversion is
enabled.
Return to Supported I2C and Default Values.
图7-61. (A6h) VOUT_CMD Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VIDOMAX_L
LEGEND: R/W = Read/Write; R = Read only
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表7-82. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
VIDOMAX_L
R/W
NVM
These bits sets the lower 8-bit value for the 9-bit VIDoMAX register.
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7.6.61 (C0h) ICC_MAX
CMD Address
Write Transaction:
Read Transaction:
Format:
C0h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The ICC_MAX command sets the effective maximum output current that the device reports through the IOUT
telemetry sub-system. ICC_MAX setting is not a fault threshold. Upon acknowledging a new value written into
this register, the new ICC_MAX value is loaded into SVID (21h) ICC_MAX register immediately.
Return to Supported I2C and Default Values.
图7-62. (C0h) ICC_MAX Register Map
7
6
5
R
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
Reserved
ICC_MAX
LEGEND: R/W = Read/Write; R = Read only
表7-83. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not used and always set to 0.
These bits configures the ICC_MAX setting.
000b: ICC_MAX = 6 A (not recommended)
001b: ICC_MAX = 10 A (not recommended)
010b: ICC_MAX = 15 A (recommend using 15 A setting for a design with maximum
load less than 10 A)
011b: ICC_MAX = 20 A
100b: ICC_MAX = 25 A
101b: ICC_MAX = 30 A
110b: ICC_MAX = 35 A
111b: ICC_MAX = 40 A
2:0
ICC_MAX
R/W
NVM
Note: ICC_MAX = 6 A or 10 A option is not recommended to use. Instread, using
the 15 A option for a design with 10A or less load is recommended.
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7.6.62 (C1h) TEMP_MAX
CMD Address
Write Transaction:
Read Transaction:
Format:
C1h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Backup:
Updates:
On-the-fly
The TEMP_MAX command provides a default value for SVID (22h) TEMP_MAX register. The TEMP_MAX
setting is not a fault threshold. Upon acknowledging a new value written into this register, the new TEMP_MAX
value is loaded into SVID (22h) TEMP_MAX register immediately.
Return to Supported I2C and Default Values.
图7-63. (C1h) TEMP_MAX Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R/W
R/W
R/W
Reserved
TEMP_MAX
LEGEND: R/W = Read/Write; R = Read only
表7-84. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:3
Reserved
R
00000b
Not used and always set to 0.
These bits configures the TEMP_MAX setting.
000b: TEMP_MAX = 95 °C
001b: TEMP_MAX = 100 °C
010b: TEMP_MAX = 105 °C
011b: TEMP_MAX = 110 °C
100b: TEMP_MAX = 115 °C
101b: TEMP_MAX = 120 °C
110b: TEMP_MAX = 125 °C
111b: TEMP_MAX = 130 °C
2:0
TEMP_MAX
R/W
NVM
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7.6.63 (C2h) PROTOCOL_ID_SVID
CMD Address
Write Transaction:
Read Transaction:
Format:
C2h
Write Byte
Read Byte
Unsigned Binary (1 byte)
EEPROM
NVM Back-up:
Vboot: on-the-fly.
Updates:
PROTOCOL_ID and ALL_CALL_SEL: field value update will wait until the power conversion is
disabled.
This PROTOCOL_ID_SVID command contains 3 fields for configuring the SVID Protocol ID, Vboot (boot up
voltage), and All-call address selection.
The PROTOCOL_ID bits set the Protocol ID for SVID communication. The setting also programs an internal
precision resistor divider thus determines the VOUT scaling (mV/LSB) of the device.
The Vboot bits program the initial output voltage at start-up when the output voltage is controlled by SVID
interface (e.g. VOUT_CTRL = 00b or 01b).
The ALL_CALL_SEL bits set the All-call address for SVID communication.
Return to Supported I2C and Default Values.
图7-64. (C2h) PROTOCOL_ID_SVID Register Map
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PROTOCOL_ID
Vboot
ALL_CALL_SEL
LEGEND: R/W = Read/Write; R = Read only
表7-85. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
PROTOCOL_ID
R/W
NVM
These bits set the Protocol ID for SVID communication. The setting also programs
an internal precision resistor divider thus determines the VOUT scaling (mV/LSB)
of the device.
00b: SVID PROTOCOL ID = 04h (VR13, 10 mV). And VOUT_CMD step = 10
mV/LSB
01b: SVID PROTOCOL ID = 07h (VR13, 5 mV). And VOUT_CMD step = 5
mV/LSB
10b: SVID PROTOCOL ID = 09h (VR14, 5 mV). And VOUT_CMD step = 5
mV/LSB
11b: SVID PROTOCOL ID = 0Ah (VR14, 10 mV). And VOUT_CMD step = 10
mV/LSB
The function selected in this field is loaded into SVID register (05h)
PROTOCOL_ID as well. In order for this field to take effect, the power conversion
must be disabled.
Note: The TPS544C26 device is VR13 compliant and no support to VR14.
5:2
Vboot
R/W
NVM
These bits program the initial output voltage at start-up. See 表7-86 for the
available settings. The Vboot and Protocol ID selections have to align based on the
listed options on 表7-86 no matter the VOUT adjustment is controlled by SVID
interface or I2C interface. Otherwise, an error check will NACK the write attempt.
For example, a write attempt with C2h = 011111xxb (Vboot = 1.8 V and Protocol ID
= 5 mV) will be NACKed, while a write attempt with C2h = 011000xxb (Vboot =
1.1V and Protocol ID = 5mV) will be ACKed.
The function selected in this field is loaded into SVID register (26h) VBOOT as
well, in VID format.
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表7-85. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
1:0
ALL_CALL_SEL
R/W
NVM
These bits set the All-call address for SVID communication.
00b: Not support All-call address, will reject both 0Eh and 0Fh address
01b: Respond to All-call address 0Fh only
10b: Respond to All-call address 0Eh only
11b: Respond to All-call address both 0Eh and 0Fh
The function selected in this field is loaded into SVID register (0Fh) ALLCALL_ACT
as well. In order for this field to take effect, the power conversion must be disabled.
表7-86. Vboot settings
Vboot
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
VID code(1) (Hex)
Vboot (V)
PROTOCOL_ID
00h
65h
6Fh
79h
83h
8Dh
97h
A1h
ABh
AFh
C9h
DDh
FBh
6Fh
79h
83h
0
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.20
1.25
1.35
1.50
1.60
1.70
1.80
Must set PROTOCOL_ID = 01b
or 10b (VOUT step = 5 mV)
Must set PROTOCOL_ID = 00b
or 11b (VOUT step = 10 mV)
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7.6.64 (C6h) VENDOR_ID
CMD Address
Write Transaction:
Read Transaction:
Format:
C6h
N/A
Read Byte
Unsigned Binary (1 byte)
The VENDOR_ID command reads an unique identity of the IC vendor. This vendor ID value is assigned to Texas
Instruments by Intel. The Vendor ID value is loaded into SVID (00h) VENDOR_ID register during the initial
power-on.
Return to Supported I2C and Default Values.
图7-65. (C6h) VENDOR_ID Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VENDOR_ID
LEGEND: R/W = Read/Write; R = Read only
表7-87. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
VENDOR_I
D
R
00100010b A Vendor ID to identify the IC vendor.
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7.6.65 (C8h) PRODUCT_ID
CMD Address
Write Transaction:
Read Transaction:
Format:
C8h
N/A
Read Byte
Unsigned Binary (1 byte)
The PRODUCT_ID command reads an unique identity of the IC. This unique product ID is chosen by Texas
Instruments for TPS544C26 device. The product ID value is loaded into SVID (01h) PRODUCT_ID register
during the initial power-on.
Return to Supported I2C and Default Values.
图7-66. (C8h) PRODUCT_ID Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
PRODUCT_ID
LEGEND: R/W = Read/Write; R = Read only
表7-88. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
PRODUCT_
ID
R
00010011b A product ID to identify the TPS544C26 device.
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7.6.66 (C9h) PRODUCT_REV_ID
CMD Address
Write Transaction:
Read Transaction:
Format:
C9h
N/A
Read Byte
Unsigned Binary (1 byte)
The PRODUCT_REV_ID command reads the IC's revision. This product revision ID is assigned by Texas
Instruments and this value is loaded into SVID (02h) PRODUCT_REV register during the initial power-on.
Return to Supported I2C and Default Values.
图7-67. (C9h) PRODUCT_REV_ID Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
PRODUCT_REV_ID
LEGEND: R/W = Read/Write; R = Read only
表7-89. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
PRODUCT_
REV_ID
R
00000010b These bits read the TPS544C26 device's revision.
00000010b: PG2.1 production unit (current revision)
00000001b: PG2.0 engineering samples (previous revision)
00000000b: PG1.0 engineering samples (previous revision)
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS544C26 device is a highly-integrated, synchronous, step-down DC/DC converter. The TPS544C26 has
a simple design procedure where programmable parameters can be configured by I2C and stored to nonvolatile
memory (NVM) to minimize external component count.
8.2 Typical Application
8.2.1 Application
This design describes a 1.1-V, 35-A application for a VCCD_HV rail in an Intel Server platform.
图8-1. VCCD_HV 1.1 V Output Application
8.2.2 Design Requirements
This design uses the parameters listed in 表8-1.
表8-1. Design Parameters
PARAMETER
VALUE
10.8 V –13.2 V
1.1 V
Input Voltage
Output Voltage
Output Current
Switching Frequency
I2C Address
35 A
800 kHz
71h
SVID Address
00h
8.2.3 Detailed Design Procedure
This design example leverages the requirements for the VCCD_HV rail in an Intel Server platform. The default
settings for this device are optimal for this application. The following steps illustrate how to select key
components.
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8.2.3.1 Inductor Selection
The inductor must be selected such that the transient performance and ripple requirements are balanced for a
particular design. In general, a smaller inductance increases loop bandwidth leading to better transient response
at the expense of higher current and voltage ripple. In this example, a 120-nH, 0.228-mΩ inductor is used.
8.2.3.2 Input Capacitor Selection
Input capacitors must be selected to provide reduction in input voltage ripple and high-frequency bypassing,
which in return will reduce switching stress on the power stage MOSFETs internal to the device. In this example,
a 0.1-µF, 25-V, 0402 must be placed as close as possible to pin 20 of the device on the same layer as the IC on
the PCB. In addition, 6x 10-µF ceramic capacitors are used and a 270-µF bulk capacitor is used on the input.
8.2.3.3 Output Capacitor Selection
To meet the output voltage ripple and load transient requirements in the Intel specification, use a 1-µF and 2 x
47-µF ceramic capacitors local to the output of the inductor. Additionally, use 6 x 47-µF on the top-side of the
CPU socket cavity combined with 4 x 22-µF capacitors on the bottom-side of the CPU socket cavity.
8.2.3.4 VCC/VRDV Bypass Capacitor
Use a minimum of 2.2-µF to 4.7-µF, 10-V rated capacitor for bypassing of the VCC/VDRV pin. This bypass
capcitor must refer to PGND to minimize the length of high-frequency driving current path.
8.2.3.5 BOOT Capacitor Selection
Use a minimum of a 0.1-µF capacitor connected from Phase (pin 25) to Boot (pin 26). An optional serires boot
resistor of 0-Ω or 2.2-Ω can be added.
8.2.3.6 RSENSE Selection
In this application, a 0.5-Ω resistor is selected to sense the input current (IIN) on a 12 V bus for DDR5 DIMMs.
The sensed input current and the sensed input voltage on pin 4 VINSENM are used to calculate the total input
power. The input power information can be read through telemetry registers and used for power management.
8.2.3.7 VINSENP and VINSENN Capacitor Selection
Use a 100-pF ceramic capacitor referenced to PGND on both the VINSENP (pin 3) and VINSENN (pin 4). The
decoupling capacitors minimizes the impact from switching noise on the 12 bus and thus help the device to
achieve high accuracy on IIN reporting.
8.2.3.8 VRRDY Pullup Resistor Selection
The VRRDY output is an open-drain output and must be pulled up externally through a pullup resistor. Place a
pull-up resistor, within a 1-kΩ to 100-kΩ range, at the VRRDY pin (pin 2). In this example, VRRDY is pulled up to
VCC/VDRV with a 10-kΩ resitor.
8.2.3.9 I2C Address Resistor Selection
Refer to 表7-16 for the list of I2C addresses selectable by an external resistor. A resistor between the I2C_ADDR
(pin 29) and AGND sets the preconfigured I2C address in the memory map. In this application, the 5.62-kΩ
resistor selects an I2C address of 71h.
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8.2.4 Application Curves
100
90
80
70
60
50
40
30
20
10
0
9
8
7
6
5
4
3
2
1
0
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
VOUT = 1.1 V
PVIN = 12 V
VOUT = 1.1 V
图8-2. Efficiency, FCCM, Internal LDO
图8-3. Power Dissipation, FCCM, Internal LDO
100
90
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
1
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30 35
Load Current (A)
Load Current (A)
PVIN = 12 V
VOUT = 1.1 V
PVIN = 12 V
VOUT = 1.1 V
图8-4. Efficiency, FCCM, External 5-V Bias
图8-5. Power Dissipation, FCCM, External 5-V Bias
100
90
80
70
60
50
40
7
6
5
4
3
30
2
600 kHz
800 kHz
600 kHz
20
800 kHz
1.0 MHz
1.2 MHz
1.0 MHz
1.2 MHz
1
10
0
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30 35
Load Current (A)
Load Current (A)
PVIN = 12 V
VOUT = 1.1 V
备注
VOUT = 1.1 V
PVIN = 12 V
图8-7. Power Dissipation, DCM, External 5-V Bias
图8-6. Efficiency, DCM, External 5-V Bias
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1.11
1.105
1.1
1.12
1.11
1.1
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
1.095
1.09
1.09
1.08
1.07
1.06
1.085
1.08
1.075
1.07
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
PVIN = 12 V
DC Load Line (DCLL) = 0.75
DC Load Line (DCLL) = 0.75
mΩ
mΩ
图8-8. Load Regulation, FCCM, Internal LDO
图8-9. Load Regulation, FCCM, External 5-V Bias
1.12
1.12
600 kHz
800 kHz
1.0 MHz
1.2 MHz
600 kHz
800 kHz
1.0 MHz
1.2 MHz
1.11
1.1
1.11
1.1
1.09
1.08
1.07
1.06
1.09
1.08
1.07
1.06
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Load Current (A)
Load Current (A)
PVIN = 12 V
PVIN = 12 V
DC Load Line (DCLL) = 0.75
DC Load Line (DCLL) = 0.75
mΩ
mΩ
图8-10. Load Regulation, DCM, Internal VCC LDO 图8-11. Load Regulation, DCM, External 5-V Bias
图8-12. ENABLE Start-Up Waveform
图8-13. ENABLE Shutdown Waveform
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图8-14. Output Voltage Ripple, 600 kHz FCCM, 35- 图8-15. Output Voltage Ripple, 800 kHz FCCM, 35-
A Load
A Load
图8-16. Output Voltage Ripple, FCCM, No load
图8-17. Output Voltage Ripple, DCM, No load
图8-18. Output Voltage Ripple, DCM, 500-mA Load
图8-19. Output Voltage Ripple, DCM, 1-A Load
8.3 Power Supply Recommendations
The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when the
VCC/VDRV pin is powered by an external bias ranging from 4.75 V to 5.3 V. Both input supplies (PVIN and VCC
bias) must be well regulated. Proper bypassing of input supplies (PVIN and VCC/VDRV) is also critical for noise
performance, as are PCB layout and grounding scheme. See the recommendations in Layout Guidelines.
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8.4 Layout
8.4.1 Layout Guidelines
Layout is critical for good power-supply design. Layout example shows the recommended PCB-layout
configuration. A list of PCB layout considerations using the device is listed as follows:
• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side
of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid
ground inner plane.
• PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or
0805 ceramic capacitors, TI highly recommends a 0.1-µF 0402 ceramic capacitor with 25 V / X7R rating on
PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. The 25-V rating is
recommended but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.
• When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is
introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad
(formed by pin 20 to pin 24) and at least 9 times PGND vias on the thermal pad (underneath of the IC) is
important to minimize the extra impedance for the bottom layer bypass capacitors.
• Except the PGND vias underneath the thermal pad, at least 4 PGND vias are required to be placed as close
as possible to the PGND pin 7 to pin 10. At least 2 PGND vias are required to be placed as close as possible
to the PGND pin 19. Thisaction minimizes PGND bounces and also lowers thermal resistance.
• Place the VCC/VDRV-to-PGND decoupling capacitor as close as possible to the device. TI recommends
a2.2-µF/6.3-V/X7R/0603 or 4.7-µF/6.3-V/X6S/0603 ceramic capacitor. The voltage rating of this bypass
capacitor must be at least 6.3 V but no more than 10 V to lower ESR and ESL. The recommended capacitor
size is 0603 to minimize the capacitance drop due to DC bias effect. Ensure the VCC/VDRV to PGND
decoupling loop is the smallest and ensure the routing trace is wide enough to lower impedance.
• For remote sensing, the connections from the VOSNS/GOSNS pins to the remote location must be a pair of
PCB traces with at least 12 mil trace width, and must implement Kelvin sensing across a high bypass
capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be connected to
GOSNS pin. The VOUT connection of the remote sensing signal must be connected to the VOSNS pin. To
maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from
any noise sources such as inductor and SW nodes, or high frequency clock lines. And TI recommends to
shield the pair of remote sensing lines with ground planes above and below.
• For single-end sensing, connect the VOSNS pin to a high-frequency local bypass capacitor of 0.1 μF or
higher, and short GOSNS to AGND with shortest trace.
• To minimize the impact from switching noise and achieve high accuracy on the input power monitoring
feature, a PGND referenced bypass capacitor is required for each of VINSENP and VINSENM pins, with at
least 100-pF volume and at least 25-V rating. These bypass capacitors must be placed close to VINSENP or
VINSENM pin accordingly.
• In a case that the input power feature is not used, follow below connection for pin 3 VINSENP and pin 4
VINSENM so that the device can report the input voltage level on PVIN node:
1. Short pin 3 VINSENP to pin 4 VINSENM,
2. Place a 0.1 µF ceramic bypass capacitor on pin 4 VINSENM referring to AGND,
3. Connect pin 4 VINSENM to PVIN node of TPS544C26 device.
• The AGND pin 32 must be connected to a solid PGND plane. TI recommends to place two AGND vias close
to pin 32 to route AGND from top layer to bottom layer, and then connect the AGND trace to the PGND vias
(underneath IC) through either a net-tie or a 0 Ω resistor on the bottom layer.
• Connecting a resistor from pin 29 (I2C_ADDR) to AGND sets I2C address. It is required not to have any
capacitor on pin 29. A capacitor on pin 29 likely leads to a wrong detection result for I2C address.
• Pin 6 (DNC) is a Do-Not-Connect pin. Pin 6 can be shorted to pin 37, which is an NC pin (No internal
Connection). Do not connect pin 6 to any other net including ground.
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8.4.2 Layout Example
8/20
0402
0402
GOSNS_Local
8/20
GOSNS_Remote
SVID Bus
8/20
8/20
8/20
8/20
8/20
0402
0402
VOSNS_Remote
VOSNS_Local
8/20
0402
8/20
8/20
8/20
I2C Clock
I2C Data
CAT_FAULT#
Signal
8/20
0402
AGND
8/20
8/20
8/20
8/20
0402
VRRDY Singal
VRRDY
Pullup
source
CAT_FAULT#
Pullup Source
8/20
Enable
0402
0402
0402
8/20
I2C_SDA
VRRDY
CAT_FAULT#
EN
8/20
8/20
8/20
8/20
0402
8/20
PVIN Bypass capacitors:
8/20
8/20
1x 0402 capacitors on top layer;
2x 0805 capacitors on top layer;
2x 0805 capacitors on bo om layer
VINSENP
VINSENM
VCC/VDRV
DNC
BOOT
PHASE
PVIN
PGND
8/20
8/20
8/20
0402
8/20
8/20
8/20
8/20
8/20
8/20
NC
PVIN
8/20
8/20
8/20
PGND
PVIN
8/20
PGND
PVIN
8/20
PGND
PVIN
PGND
PGND
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8 / 2 0
8 / 2 0
08
08
GOSNS_Local
VOSNS_Local
8 / 2 0
8 / 2 0
8 / 2 0
8 / 2 0
8 / 2 0
8 / 2 0
VOUT
VOUT Bypass capacitors:
Place ceramic capacitors on top
layer; Bulk capacitors are op onal
and can be placed on bo om layer
图8-20. Layout Recommendation
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8.4.2.1 Thermal Performance on TPS544C26EVM
Below are thermal results captured on the TPS544C26EVM with PVIN = 12 V, VOUT = 1.1 V conditions.
图8-21. Thermal Characteristics, 600 kHz FCCM,
图8-22. Thermal Characteristics, 600 kHz FCCM,
Internal LDO, 35 A Load
External 5-V Bias, 35-A Load
图8-23. Thermal Characteristics, 800 kHz FCCM,
图8-24. Thermal Characteristics, 800 kHz FCCM,
Internal LDO, 35-A Load
External 5-V Bias, 35-A Load
图8-25. Thermal Characteristics, 1.2-MHz FCCM,
图8-26. Thermal Characteristics, 1.2-MHz FCCM,
Internal LDO, 35-A Load
External 5-V Bias, 35-A Load
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
D-CAP+™ and TI E2E™ are trademarks of Texas Instruments.
Intel® is a registered trademark of Intel.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
WQFN-
FCRLF
TPS544C26RXXR
RXX
37
3000
330.0
12.0
5.25
6.3
1.0
8.0
12.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
WQFN-FCRLF
Package Drawing Pins
RXX 37
SPQ
Length (mm) Width (mm)
355.0 338.0
Height (mm)
TPS544C26RXXR
3000
35.0
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS544C26RXXR
ACTIVE WQFN-FCRLF
RXX
37
3000 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
544C26
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RXX 37
5 x 6, 0.5 mm pitch
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228557/A
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PACKAGE OUTLINE
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
A
RXX0037B
5.1
4.9
B
6.1
5.9
PIN 1 INDEX AREA
0.7
0.6
C
SEATING PLANE
0.01
0.00
0.08
(0.2)
C
0.45
0.35
(0.20) TYP
(0.25) TYP
11
18
19
20
2.34±0.1
10
6X (2.07)
2.089±0.1
1.839±0.1
6X (1.5)
(1.405)
0.5
0.4
(1.375)
(0.975)
2X (1)
4X (0.925)
0.625±0.1
(0.612)
(0.3)
7
(0.952)
(0.543)
(0.526)
3X (0.028)
6
2X (0.5)
0.15±0.1
0.000 PKG ℄
2X 4.5
0.3
0.2
37
24
25
0.306±0.1
0.626±0.1
0.325±0.1
3X (0.5)
(0.668)
2X (1)
2X (1.075)
(1.438)
2X (1.522)
2X (1.582)
2X NO METAL
40X (Ø 0.15) NO METAL
2.25±0.1
28
1
PIN 1 ID
(OPTIONAL)
36
29
0.45
18X
0.3
0.2
37X
0.35
0.1
C
A
B
0.05
C
32X 0.5
2X 3.5
4228540/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RXX0037B
29
36
10X (R0.1)
(2.9)
(0.05) MIN
ALL AROUND
TYP
(R 0.05) TYP
28
(2.25)
1
(1.938)
18X (0.6)
(0.938)
25
(0.363)
(0.325)
(0.626)
(0.306)
24
37
0.000 PKG ℄
2X (4.5)
(0.15)
6
(0.45)
(0.625)
7
(0.635)
(0.767)
(Ø0.2) TYP
(1.483)
20
(1.839)
(2.089)
(2.34)
19
10
(2.6)
(2.8)
(3.2)
11
18
37X (0.25)
32X (0.5)
2X (3.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228540/C 10/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RXX0037B
3X (1)
37X (0.25)
18X (0.6)
36
29
(2.9)
(R 0.05) TYP
28
1
(1.438)
(1.47)
2X (1.318)
2X (1.71)
25
24
37
2X (4.5)
(0.84)
0.000 PKG ℄
(0.155)
(0.187)
6
7
(1.47)
10X (0.45)
2X (0.96)
(1.347)
2X (1.547)
2X (1.55)
20
(1.2)
2X (1.05)
(2.09)
10
19
(2.6)
(2.8)
(3.2)
18
11
(1.17)
32X (0.5)
2X (3.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SOLDER COVERAGE BY AREA UNDER PACKAGE :
THERMAL PAD CONNECTED TO PINS 7-10 &19: 80%
THERMAL PAD CONNECTED TO PINS 20-24: 86%
SCALE: 15X
4228540/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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