TPS54561DPRR [TI]
具有软启动和 Eco-mode™ 的 4.5V 至 60V 输入 5A 降压直流/直流转换器 | DPR | 10 | -40 to 125;
| 型号： | TPS54561DPRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有软启动和 Eco-mode™ 的 4.5V 至 60V 输入 5A 降压直流/直流转换器 | DPR | 10 | -40 to 125 开关 软启动 光电二极管 转换器 |
| 文件： | 总54页 (文件大小：2965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54561
ZHCSBY9G –JULY 2013 –REVISED JUNE 2021
TPS54561 具有软启动和Eco-mode™ 的4.5V 至60V 输入、5A 降压直流/直流转
换器
1 特性
3 说明
• 在轻负载条件下使用脉冲跳跃Eco-mode™ 实现高
效率
• 87mΩ高侧MOSFET
• 152μA 工作静态电流和
2μA 关断电流
• 100kHz 至2.5MHz 可调开关频率
• 与外部时钟同步
TPS54561 是一款具有集成式高侧 MOSFET 的 60V、
5A、降压稳压器。按照ISO 7637 标准，此器件能够耐
受的负载突降脉冲高达 65V。它采用电流模式控制，
可实现简单的外部补偿和灵活的组件选择。一个低纹波
脉冲跳跃模式将无负载时的电源电流减小至 152μA。
当使能引脚被拉至低电平时，关断电源电流被减少至
2μA。
• 轻负载条件下使用集成型BOOT 再充电FET 实现
低压降
• 可调UVLO 电压和迟滞
• UV 和OV 电源正常输出
• 可调节软启动和时序
欠压闭锁在内部设定为 4.3V，但可用使能引脚上的一
个外部电阻分压器将之提高。输出电压启动斜坡由软启
动引脚控制，该引脚还可被配置用来控制时序/跟踪。
开漏电源正常信号表示输出处于其标称电压的 93% 至
106% 之间。
• 0.8V 1% 内部电压基准
• 带有散热焊盘的10 引脚WSON 封装
• –40°C 至150°C TJ 工作范围
• 利用TPS54561 并借助WEBENCH® Power
Designer 创建定制设计方案
宽可调开关频率范围可针对效率或者外部组件尺寸进行
优化。逐周期电流限制、频率折返和热关断在过载条件
下保护内部和外部组件。
TPS54561 采用10 引脚4mm × 4mm WSON 封装。
2 应用
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS54561
• 工业自动化和电机控制
WSON (10)
4.00mm × 4.00mm
• 汽车配件：GPS（请参阅SLVA412）、娱乐
• USB 专用充电端口和电池充电器（请参阅
SLVA464）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 12V、24V 和48V 工业、汽车及通信用电源系统
100
VIN
36 V to 12 V
PWRGD
VIN
95
TPS54561
90
85
BOOT
EN
12 V to 3.3 V
80
RT/CLK
SS/TR
VOUT
12 V to 5 V
SW
75
70
VOUT = 12 V, fsw = 620kHz,
VOUT = 5 V and 3.3 V, f sw = 400 kHz
65
60
COMP
FB
0
1
2
3
4
5
C024
IO - Output Current (A)
GND
效率和负载电流间的关系
Copyright © 2017, Texas Instruments Incorporated
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSBO1
TPS54561
ZHCSBY9G –JULY 2013 –REVISED JUNE 2021
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Table of Contents
8 Application and Implementation..................................29
8.1 Application Information............................................. 29
8.2 Typical Applications.................................................. 29
9 Power Supply Recommendations................................43
10 Layout...........................................................................44
10.1 Layout Guidelines................................................... 44
10.2 Layout Example...................................................... 44
10.3 Estimated Circuit Area............................................ 44
11 Device and Documentation Support..........................45
11.1 Device Support........................................................45
11.2 Documentation Support.......................................... 45
11.3 接收文档更新通知................................................... 45
11.4 支持资源..................................................................45
11.5 Trademarks............................................................. 45
11.6 Electrostatic Discharge Caution..............................45
11.7 Glossary..................................................................46
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Switching Characteristics............................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................28
Information.................................................................... 46
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision F (January 2017) to Revision G (June 2021)
Page
• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1
• Added VIN - SW 5-ns and 10-ns transient .........................................................................................................4
• Changed SW - GND 5-ns and 10-ns transient max values to 67 V ...................................................................4
Changes from Revision E (February 2016) to Revision F (January 2017)
Page
• 向特性、详细设计过程和器件支持部分添加了WEBENCH 信息...................................................................... 1
• Changed 方程式10 and 方程式11 ..................................................................................................................20
• Changed 方程式30 ......................................................................................................................................... 30
• Changed From: "power pad" To: "thermal pad" in the Layout Guidelines section............................................ 44
Changes from Revision C (November 2013) to Revision D (February 2016)
Page
• 添加了ESD 等级表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器
件和文档支持部分以及机械、封装和可订购信息部分。................................................................................... 1
Changes from Revision B (November 2013) to Revision C (November 2013)
Page
• 将器件状态从“产品预发布”更改为“量产”....................................................................................................1
Changes from Revision A (October 2013) to Revision B (November 2013)
Page
• 将特性列表项中的“PowerPAD”更改为“散热焊盘”..................................................................................... 1
• 删除了说明部分对PowerPAD 的引用................................................................................................................1
• Deleted ORDERING INFORMATION table before DEVICE INFORMATION section........................................ 3
Changes from Revision * (July 2013) to Revision A (October 2013)
Page
• 更改了效率和负载电流间的关系图，将fSW = 630KhZ 更改为fSW = 620kHz..................................................... 1
• Added the APPLICATION INFORMATION section...........................................................................................30
• Added the Power Dissipation Estimate section................................................................................................ 36
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5 Pin Configuration and Functions
1
2
3
4
5
10
9
BOOT
PWRGD
SW
VIN
8
EN
GND
COMP
FB
7
SS/TR
RT/CLK
6
图5-1. DPR Package 10-Pin WSON Top View
表5-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
BOOT
1
O
VIN
EN
2
3
I
I
Input supply voltage with 4.5-V to 60-V operating range.
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See 节7.3.7.
Soft-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
SS/TR
4
5
I
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal
amplifier is re-enabled and the operating mode returns to resistor frequency programming.
RT/CLK
FB
6
7
I
Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
COMP
O
GND
SW
8
9
Ground
–
I
The source of the internal high-side power MOSFET and switching node of the converter.
Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal
shutdown, dropout, over-voltage or EN shut down
PWRGD
10
11
O
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Thermal Pad
–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
-7
MAX
65
67
67
8.4
8
UNIT
VIN
VIN - SW, 5-ns Transient
VIN - SW, 10-ns Transient
EN
-2
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–7
BOOT–SW
FB
3
COMP
3
Voltage
V
PWRGD
SS/TR
6
3
RT/CLK
3.6
67
67
65
150
150
SW - GND, 5-ns Transient
SW - GND, 10-ns Transient
SW
–2
–0.6
–40
–65
Operating junction temperature, TJ
Storage temperature range, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
60
UNIT
V
Supply input voltage, VVIN
Output voltage, VO
4.5
0.8
0
58.8
5
V
Output current, IO
A
Operating junction temperature, TJ
-40
150
°C
6.4 Thermal Information
TPS54561
THERMAL METRIC(1) (2)
DPR (WSON)
10 PINS
35.1
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
Junction-to-case(top) thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.1
Junction-to-board thermal resistance
12.3
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TPS54561
THERMAL METRIC(1) (2)
DPR (WSON)
10 PINS
0.3
UNIT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
°C/W
°C/W
°C/W
ψJT
12.5
ψJB
RθJC(bot)
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See 节8.2.1.2.12 for more information.
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
4.1
60
V
V
Internal undervoltage lockout
threshold
Rising
4.3
4.48
Internal undervoltage lockout
threshold hysteresis
325
2.25
152
mV
Shutdown supply current
4.5
EN = 0 V, 25°C, 4.5 V ≤VIN ≤60 V
μA
Operating: nonswitching supply
current
FB = 0.9 V, TA = 25°C
200
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
No voltage hysteresis, rising and falling
Enable threshold +50 mV
1.1
1.2
–4.6
–1.2
–3.4
540
1.3
V
Input current
μA
-1.8
-4.5
Enable threshold –50 mV
–0.58
–2.2
Hysteresis current
Enable to COMP active
VOLTAGE REFERENCE
Voltage reference
μA
VIN = 12 V, TA = 25°C
µs
0.792
0.8
87
0.808
185
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM)
350
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
VFB = 0.8 V
μMhos
Error amplifier transconductance (gM)
during soft-start
77
μMhos
Error amplifier dc gain
10,000
2500
±30
V/V
kHz
μA
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current
transconductance
17
A/V
CURRENT LIMIT
All VIN and temperatures, Open Loop(1)
All temperatures, VIN = 12 V, Open Loop(1)
VIN = 12 V, TA = 25°C, Open Loop(1)
6.3
6.3
7.1
7.5
7.5
7.5
60
8.8
8.3
7.9
Current limit threshold
A
Current limit threshold delay
THERMAL SHUTDOWN
Thermal shutdown
ns
176
12
°C
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
1.55
1.2
2
V
V
RT/CLK low threshold
0.5
SOFT START AND TRACKING (SS/TR PIN)
Charge current
VSS/TR = 0.4 V
VSS/TR = 0.4 V
98% nominal
1.7
42
µA
mV
V
SS/TR-to-FB matching
SS/TR-to-reference crossover
SS/TR discharge current (overload)
SS/TR discharge voltage
1.16
354
54
FB = 0 V, VSS/TR = 0.4 V
FB = 0 V
µA
mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low
FB threshold for PWRGD high
FB falling
FB rising
90
93
%
%
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TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
FB threshold for PWRGD low
FB threshold for PWRGD high
Hysteresis
TEST CONDITIONS
MIN
TYP
108
106
2.5
10
MAX
UNIT
%
FB rising
FB falling
FB falling
%
%
Output high leakage
VPWRGD = 5.5 V, TA = 25°C
nA
On resistance
IPWRGD = 3 mA, VFB < 0.79 V
VPWRGD < 0.5 V, IPWRGD = 100 µA
45
Ω
Minimum VIN for defined output
0.9
2
V
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
6.6 Timing Requirements
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum CLK input pulse width
15
55
ns
ns
RT/CLK falling edge to SW rising edge delay –Measured at 500 kHz with
RT resistor in series
6.7 Switching Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW
Switching frequency
450
100
500
550
kHz
kHz
RT = 200 kΩ
Switching frequency range using RT
mode
2500
Switching frequency range using
CLK mode
160
2300
kHz
PLL lock in time
Measured at 500 kHz
78
μs
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6.8 Typical Characteristics
0.25
0.2
0.15
0.1
0.05
0
0.814
0.809
0.804
0.799
0.794
0.789
0.784
BOOT-SW = 3 V
BOOT-SW = 6 V
VIN=12V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C001
C002
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
图6-1. ON Resistance vs Junction Temperature 图6-2. Voltage Reference vs Junction Temperature
9
8.5
8
9
8.5
8
7.5
7
7.5
7
-40 °C
25 °C
6.5
6
6.5
6
V=12V
IN
150 °C
0
25
50
75
100
125
150
0
10
20
30
40
50
60
œ50
œ25
C003
C004
TJ œ Junction Temperature (°C)
VI - Input Voltage (V)
图6-3. Switch Current Limit vs Junction
图6-4. Switch Current Limit vs Input Voltage
Temperature
550
540
530
520
510
500
490
480
470
460
500
450
400
350
300
250
200
150
100
RT = 200 kꢀ, VIN = 12 V
450
0
25
50
75
100
125
150
200
300
400
500
600
700
800
900 1000
œ50
œ25
C005
C006
TJ œ Junction Temperature (°C)
RT/CLK - Resistance (kꢀ)
图6-5. Switching Frequency vs Junction
图6-6. Switching Frequency vs RT/CLK Resistance
Temperature
Low Frequency Range
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2500
500
450
400
350
300
250
200
2000
1500
1000
500
VIN = 12 V
0
0
50
100
150
200
0
25
50
75
100
125
150
œ50
œ25
C007
C008
RT/CLK - Resistance (kꢀ)
TJ œ Junction Temperature (°C)
图6-7. Switching Frequency vs RT/CLK Resistance
图6-8. EA Transconductance vs Junction
High Frequency Range
Temperature
120
110
100
90
1.3
1.27
1.24
1.21
1.18
80
70
60
50
40
30
VIN = 12 V
VIN = 12 V
20
1.15
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C009
C010
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
图6-9. EA Transconductance During Soft-Start vs 图6-10. EN Pin Voltage vs Junction Temperature
Junction Temperature
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
œ4.7
œ4.9
œ5.1
œ5.3
œ5.5
œ0.5
œ0.7
œ0.9
œ1.1
œ1.3
œ1.5
œ1.7
œ1.9
œ2.1
œ2.3
œ2.5
VIN = 12 V, IEN = Threshold + 50 mV
VIN = 12 V, IEN = Threshold - 50 mV
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C011
C012
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
图6-11. EN Pin Current vs Junction Temperature
图6-12. EN Pin Current vs Junction Temperature
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œ2.5
œ2.7
œ2.9
œ3.1
œ3.3
œ3.5
œ3.7
œ3.9
œ4.1
œ4.3
œ4.5
100.0
75.0
50.0
25.0
0.0
V
Falling
SENSE
VIN = 12 V
VSENSERising
0.6 0.7
0
25
50
75
100
125
150
0.0
0.1
0.2
0.3
0.4
0.5
0.8
œ50
œ25
C013
C014
TJ œ Junction Temperature (°C)
VSENSE (V)
图6-13. EN Pin Current Hysteresis vs Junction
图6-14. Switching Frequency vs FB
Temperature
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0.5
0
VIN = 12 V
TJ = 25 °C
0
0
25
50
75
100
125
150
0
10
20
30
40
50
60
œ50
œ25
C015
C016
TJ œ Junction Temperature (°C)
VIN - Input Voltage (°C)
图6-15. Shutdown Supply Current vs Junction
图6-16. Shutdown Supply Current vs Input Voltage
Temperature
(VIN)
210
190
170
150
130
110
90
210
190
170
150
130
110
90
VIN = 12 V
TJ = 25 °C
70
70
0
25
50
75
100
125
150
0
10
20
30
40
50
60
œ50
œ25
C017
C018
TJ œ Junction Temperature (°C)
VIN - Input Voltage (°C)
图6-17. VIN Supply Current vs Junction
图6-18. VIN Supply Current vs Input Voltage
Temperature
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2.6
2.5
2.4
2.3
2.2
2.1
2
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
BOOT-PH UVLO Falling
BOOT-PH UVLO Rising
UVLO Start Switching
UVLO Stop Switching
1.9
1.8
0
25
50
75
100
125
150
0
25
50
75
100
125
150
œ50
œ25
œ50
œ25
C019
C020
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
图6-19. BOOT-SW UVLO vs Junction Temperature
图6-20. Input Voltage UVLO vs Junction
Temperature
80
70
60
50
40
30
20
10
110
FB
108
106
FB Falling
104
102
100
98
96
94
92
90
88
VIN = 12 V
FB Rising
VIN = 12 V
FB Falling
25
0
0
25
50
75
100
125
150
0
50
75
100
125
150
œ50
œ25
œ50
œ25
C021
C022
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
图6-21. PWRGD ON Resistance vs Junction
图6-22. PWRGD Threshold vs Junction
Temperature
Temperature
900
60
55
50
45
40
35
30
25
VIN = 12 V, 25 °C
800
700
600
500
400
300
200
100
0
VIN = 12 V, FB = 0.4 V
20
0
100
200
300
400
500
600
700
800
0
25
50
75
100
125
150
œ50
œ25
C024
C025
SS/TR (mV)
TJ œ Junction Temperature (°C)
图6-23. SS/TR to FB Offset vs FB
图6-24. SS/TR to FB Offset vs Temperature
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5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
Start
Stop
Dropout
Voltage
Dropout
Voltage
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
C026
Output Current (A)
图6-25. 5-V Start and Stop Voltage (see )
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7 Detailed Description
7.1 Overview
The TPS54561 is a 60-V, 5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. The
device implements constant frequency, current mode control which reduces output capacitance and simplifies
external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either
efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted
using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL)
connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external clock
signal.
The TPS54561 has a default input start-up voltage of 4.3 V typical. The EN pin can be used to adjust the input
voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current source
enables operation when the EN pin is floating. The operating current is 152 μA under no load condition when
not switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩhigh side MOSFET supports high efficiency power supply designs capable of delivering 5
A of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is supplied by
a bootstrap capacitor connected from the BOOT to SW pins. The TPS54561 reduces the external component
count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a UVLO
circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset threshold. An
automatic BOOT capacitor recharge circuit allows the TPS54561 to operate at high duty cycles approaching
100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The
minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be connected to the pin to adjust the soft start time. A resistor
divider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an over-
temperature fault, UVLO fault or a disabled condition. When the overload condition is removed, the soft start
circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency foldback
circuit reduces the switching frequency during start up and overcurrent fault conditions to help maintain control of
the inductor current.
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7.2 Functional Block Diagram
PWRGD
EN
VDD
Shutdown
UV
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Boot
UVLO
Current
Sense
Skip
Error
Amplifier
PWM
Comparator
FB
BOOT
SS/TR
Logic
Shutdown
Slope
Compensation
S
SW
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
With PLL
RT/CLK
GND
Thermal Pad
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54561 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an
error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
at the COMP pin controls the high side power switch current. When the high side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will
increase and decrease as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54561 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
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7.3.3 Pulse Skip Eco-mode
The TPS54561 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since
the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling
output voltage by increasing the COMP pin voltage. The high side MOSFET is enabled and switching resumes
when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the
regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at
light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54561 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 152-
μA input quiescent current. The circuit in 图 8-1 enters Eco-mode at 25-mA output current and with no external
load has an average input current of 280 µA.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54561 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high
side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54561 will
operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1V. When the voltage from
BOOT to SW drops below 2.1 V, the high side MOSFET is turned off and an integrated low side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output
voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
The start and stop voltage for a typical 5-V output application is shown in 图 6-25 where the input voltage is
plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. 方程式 1 can be
used to calculate the minimum input voltage for this condition.
VOmax = Dmax × (VVINmin –IOmax × RDS(on) + Vd) –Vd –IOmax × Rdc
(1)
Where:
• Dmax ≥0.9
• Vd = Forward Drop of the Catch Diode
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• Rdc = DC resistance of output inductor
• RDS(on) = 1 / (-0.3 × VB2SW2 + 3.577 × VB2SW - 4.246)
• VB2SW = VBOOT + Vd
• VBOOT = (1.41 × VVIN - 0.554 - Vd × fsw - 1.847 × 103 × IB2SW) / (1.41 + fsw)
• fsw = Operating frequency in MHz
• IB2SW = 100 × 10-6 A
spacer
7.3.5 Error Amplifier
The TPS54561 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-
start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. Using 1% tolerance or better divider resistors is recommended.
Select the low side resistor RLS for the desired divider current and use 方程式 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator
will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
Vout - 0.8V
æ
ö
RHS = RLS
´
ç
÷
0.8 V
è
ø
(2)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54561 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54561 is disabled when the VIN pin voltage falls below 4 V or when the EN
pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables
operation of the TPS54561 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in 图 7-1 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4-
μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use 方
程式 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use 方程式 4 to calculate RUVLO2 for the
desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN pin is clamped internally with a 5.8-V zener diode that will sink up to 150 μA.
V
- V
STOP
START
R
=
UVLO1
I
HYS
(3)
V
ENA
R
=
UVLO2
V
- V
ENA
START
+ I
1
R
UVLO1
(4)
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VIN
TPS54561
TPS54561
i1 ihys
VIN
R
R
UVLO1
UVLO1
10 kW
EN
EN
Node
5.8 V
VEN
R
R
UVLO2
UVLO2
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
图7-2. Internal EN Pin Clamp
图7-1. Adjustable Undervoltage Lockout (UVLO)
7.3.8 Soft Start/Tracking Pin (SS/TR)
The TPS54561 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as
the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a soft start time. The TPS54561 has an internal pull-up current source of 1.7 μA that
charges the external soft start capacitor. The calculations for the soft start time (10% to 90%) are shown in 方程
式 5. The voltage reference (VREF) is 0.8 V and the soft start current (ISS) is 1.7 μA. The soft start capacitor
should remain lower than 0.47 μF and greater than 0.47 nF.
Tss(ms) ´ Iss(mA)
Css(nF) =
Vref (V) ´ 0.8
(5)
At power up, the TPS54561 will not start switching until the soft start pin is discharged to less than 54 mV to
ensure a proper power up, see 图7-3.
Also, during normal operation, the TPS54561 will stop switching and the SS/TR must be discharged to 54 mV,
when the VIN UVLO is exceeded, EN pin pulled below 1.2 V, or a thermal shutdown event occurs.
The FB voltage will follow the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see 图 6-23).
The SS/TR voltage will ramp linearly until clamped at 2.7 V typically as shown in 图7-3.
图7-3. Operation of SS/TR Pin when Starting
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7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of
another device. The sequential method is illustrated in 图 7-4 using two TPS54561 devices. The power good is
Connected to the EN pin on the TPS54561 which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will provide a
1-ms start up delay. 图7-5 shows the results of 图7-4.
TPS54561
PWRGD
TPS54561
EN
EN
SS/TR
SS /TR
PWRGD
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图7-4. Schematic for Sequential Start-Up
Sequence
图7-5. Sequential Startup using EN and PWRGD
TPS54561
3
4
6
EN
SS/TR
PWRGD
TPS54561
3
4
6
EN
图7-7. Ratio-Metric Startup using Coupled SS/TR
SS/TR
pins
PWRGD
Copyright © 2017, Texas Instruments Incorporated
图7-6. Schematic for Ratio-Metric Start-Up
Sequence
图 7-6 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator
outputs will ramp up and reach regulation at the same time. When calculating the soft start time the pull up
current source must be doubled in 方程式5. 图7-7 shows the results of 图7-6.
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TPS54561
EN
VOUT 1
SS/TR
PWRGD
TPS54561
VOUT 2
EN
R1
R2
SS/TR
PWRGD
R3
R4
Copyright © 2017, Texas Instruments Incorporated
图7-8. Schematic for Ratio-Metric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in 图 7-8 to the output of the power supply that needs to be tracked or another voltage
reference source. Using 方程式 6 and 方程式 7, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. 方程式8 is the voltage difference between Vout1 and Vout2 at
the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
FB offset (VSSOFFSET) in the soft start circuit and the offset created by the pullup current source (Iss) and tracking
resistors, the VSSOFFSET and ISS are included as variables in the equations.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in 方程式 6 through 方程式 8 for deltaV. 方程式 8 will result in a
positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
Since the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors ensures that the device will restart after a fault. The calculated R1 value
from 方程式6 must be greater than the value calculated in 方程式9 to ensure the device recovers from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSOFFSET becomes larger
as the soft start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.5 V for a complete handoff to the internal voltage reference.
Vout2 + deltaV
VREF
Vssoffset
Iss
R1 =
´
(6)
VREF ´ R1
Vout2 + deltaV - VREF
R2 =
(7)
(8)
(9)
deltaV = Vout1 - Vout2
R1 > 2800 ´ Vout1 - 180 ´ deltaV
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图7-9. Ratio-Metric Startup with Tracking
图7-10. Ratio-Metric Startup with Tracking
Resistors
Resistors
图7-11. Simultaneous Startup with Tracking Resistor
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54561 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use 方程式 10 or 方程式 11 or the curves in 图 6-5 and 图 6-6. To reduce the solution size one would
typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum
input voltage and minimum controllable on time should be considered. The minimum controllable on time is
typically 135 ns which limits the maximum operating frequency in applications with high input to output step
down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more detailed
discussion of the maximum switching frequency is provided in the next section.
101756
f sw (kHz)1.008
RT (kW) =
(10)
92417
RT (kW)0.991
f sw (kHz) =
(11)
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7.3.11 Maximum Switching Frequency
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54561
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls
from 0.8 V to 0 V. The TPS54561 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current may exceed
the peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. 方程式 13 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
方程式 12 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
æ
ç
ö
÷
IO ´Rdc + VOUT + Vd
1
fSW maxskip
=
´
(
)
ç
÷
tON
VIN -IO ´RDS on + Vd
( )
è
ø
(12)
(13)
æ
ö
ICL ´Rdc + VOUT sc + Vd
fDIV
( )
ç
÷
fSW(shift)
=
´
ç
÷
tON
VIN -ICL ´RDS on + Vd
( )
è
ø
IO
Output current
ICL
Current limit
Rdc
VIN
VOUT
Inductor resistance
Maximum input voltage
Output voltage
VOUT(SC)
Vd
RDS(on)
tON
Output voltage during short
Diode voltage drop
Switch on resistance
Controllable on time
Frequency divide equals (1, 2, 4, or 8)
ƒDIV
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7.3.12 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in 图
7-12. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V and have a
pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of
the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should
be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when the
synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected
in parallel with an ac coupling capacitor to a termination resistor (that is, 50 Ω) as shown in 图 7-12. The two
resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum
of the resistance should set the switching frequency close to the external CLK frequency. AC coupling the
synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold the TPS54561 switches from the RT resistor free-
running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency
can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor
mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then
increase or decrease to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. 图 7-13, 图 7-14, and 图 7-15 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
TPS54561
PLL
TPS54561
PLL
RT/CLK
RT
RT/CLK
RT
Hi-Z
Clock
Source
Clock
Source
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图7-12. Synchronizing to a System Clock
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图7-14. Plot of Synchronizing in DCM
图7-13. Plot of Synchronizing in CCM
图7-15. Plot of Synchronizing in Eco-mode
7.3.13 Accurate Current Limit Operation
The TPS54561 implements peak current mode control in which the COMP pin voltage controls the peak current
of the high side MOSFET. A signal proportional to the high side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is
turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the
peak switch current limit. The TPS54561 provides an accurate current limit threshold with a typical current limit
delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in 图7-16.
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Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = V /L x tCLdelay
IN
tCLdelay
tON
图7-16. Current Limit Delay
7.3.14 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩto a voltage source that is
5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull-up
voltage source when the PWRGD pin is asserted low. A lower pull-up resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but
with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input
voltage approaches 3 V.
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. Also, PWRGD is pulled low, if UVLO or thermal shutdown are asserted or the EN pin pulled
low.
7.3.15 Overvoltage Protection
The TPS54561 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable
time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit
threshold. When the overload condition is removed, the regulator output rises and the error amplifier output
transitions to the normal operating level. In some applications, the power supply output voltage can increase
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high side MOSFET resumes normal operation.
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7.3.16 Thermal Shutdown
The TPS54561 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by discharging the SS/TR pin.
7.3.17 Small Signal Model for Loop Response
图 7-17 shows a simplified equivalent model for the TPS54561 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor
Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV ac voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model
is only valid for continuous conduction mode (CCM) operation.
SW
V
O
Power Stage
gm 17 A/V
ps
a
b
R
R1
ESR
R
COMP
L
c
FB
C
OUT
0.8 V
CO
RO
R3
C1
gm
ea
C2
R2
350 mA/V
Copyright © 2016, Texas Instruments Incorporated
图7-17. Small Signal Model for Loop Response
7.3.18 Simple Small Signal Model for Peak Current Mode Control
图 7-18 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54561 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in 方
程式 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch
current and the change in COMP pin voltage (node c in 图 7-17) is the power stage transconductance, gmPS
.
The gmPS for the TPS54561 is 17 A/V. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in 方程式15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively.
This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with
the load current (see 方程式 16). The combined effect is highlighted by the dashed line in the right half of 图
7-18. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
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electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see 方程式17).
V
O
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
图7-18. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
ç
è
ö
÷
ø
s
1+
1+
2p´ fZ
VOUT
= Adc ´
VC
æ
ç
è
ö
÷
ø
s
2p´ fP
(14)
(15)
Adc = gmps ´ RL
1
f
=
P
C
´R ´ 2p
L
OUT
(16)
(17)
1
f
=
Z
C
´R
´ 2p
OUT
ESR
7.3.19 Small Signal Model for Frequency Compensation
The TPS54561 uses a transconductance amplifier for the error amplifier and supports three of the commonly-
used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in 图
7-19. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output
capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. 方程式 18 and 方程式 19 relate the frequency response of the amplifier to the small signal
model in 图 7-19. The open-loop gain and bandwidth are modeled using the RO and CO shown in 图 7-19. See
the application section for a design example using a Type 2A network with a low ESR output capacitor.
方程式 18 through 方程式 27 are provided as a reference. An alternative is to use WEBENCH software tools to
create a design based on the power supply requirements.
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V
O
R1
FB
Type 2A
Type 2B
Type 1
gm
ea
R
COMP
Vref
C2
R3
C1
R3
R2
C2
C
O
O
C1
Copyright © 2016, Texas Instruments Incorporated
图7-19. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
图7-20. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
Ro =
(18)
(19)
gmea
CO
=
2p ´ BW (Hz)
æ
ç
è
ö
÷
ø
s
1+
2p´ fZ1
EA = A0´
æ
ç
è
ö æ
ö
÷
ø
s
s
1+
´ 1+
÷ ç
2p´ fP1
2p´ fP2
ø è
(20)
(21)
(22)
R2
A0 = gmea ´ Ro ´
R1 + R2
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
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1
P1=
2p´Ro´ C1
(23)
1
Z1=
2p´R3´ C1
(24)
(25)
1
P2 =
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
(26)
(27)
1
P2 =
type 1
2p ´ RO ´ (C2 + CO
)
7.4 Device Functional Modes
The TPS54561 is designed to operate with input voltages above 4.5 V. When the VIN voltage is above the 4.3 V
typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device is active. If the
VIN voltage falls below the typical 4-V UVLO turn off threshold the device stops switching. If the EN voltage falls
below the 1.2-V threshold the device stops switching and enters a shutdown mode with low supply current of 2
µA typical.
The TPS54561 will operate in CCM when the output current is enough to keep the inductor current above 0 A at
the end of each switching period. As a non-synchronous converter it will enter DCM at low output currents when
the inductor current falls to 0 A before the end of a switching period. At very low output current the COMP
voltage will drop to the pulse skipping threshold and the device operates in a pulse-skipping Eco-mode. In this
mode the high-side MOSFET does not switch every switching period. This operating mode reduces power loss
while keeping the output voltage regulated. For more information on Eco-mode see 节7.3.3.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54561 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 5 A.
Example applications are: 12-V, 24-V, and 48-V industrial, automotive and communication power systems. Use
the following design procedure to select component values for the TPS54561 device. The Excel® spreadsheet
(SLVC452) located on the product page can help on all calculations. Alternatively, use the WEBENCH software
to generate a complete design. The WEBENCH software uses an interactive design procedure and accesses a
comprehensive database of components when generating a design.
8.2 Typical Applications
8.2.1 Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
PWRGD
PWRGD PULL UP
TP9
R8
7 V to 60 V
C11
U1
TP10
1.00k
2
1
2
3
5
4
7
10
VIN
VIN
PWRGD
BOOT
SW
C4
TP1
TP2
1
9
6
8
GND
L1
EN
+
5 V @ 5 A
R1
442k
C10
2.2µF
C3
2.2µF
C1
2.2µF
C2
2.2µF
0.1µF
DNP
1
2
J2
VOUT
GND
RT/CLK
SS/TR
COMP
TP5
TP6
TP4
TP7
TP8
7447798720
7.2µH
SS/TR
C13
FB
FB
R3
243k
R7
49.9
J1
GND
PAD
D1
PDS760-13
+
C12
GND
C9 DNP
47µF
C6
47µF
C7
47µF
R4
16.9k
TPS54561DPR
GND
0.01µF
C8
47pF
2
1
GND
GND
R5
53.6k
C5
4700pF
J4
R2
90.9k
2
1
EN
GND
FB
GND
GND
J3
R6
10.2k
TP3
GND
GND
SS/TR
GND
2
1
SS/TR
GND
J5
Copyright © 2017, Texas Instruments Incorporated
图8-1. 5-V Output TPS54561 Design Example
8.2.1.1 Design Requirements
图 8-1 illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet (SLVC452)
located on the product page. This example is designed to the following known parameters:
表8-1. Design Parameters
PARAMETER
Output Voltage
VALUE
5 V
ΔVOUT = 4 %
5 A
Transient response 1.25 A to 3.75 A load step
Maximum output current
Input voltage
12 V nom. 7 V to 60 V
0.5% of VOUT
6.5 V
Output voltage ripple
Start input voltage (rising VIN)
Stop input voltage (falling VIN)
5 V
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
方程式 12 and 方程式 13 should be used to calculate the upper limit of the switching frequency for the regulator.
Choose the lower value result from the two equations. Switching frequencies higher than these values results in
pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54561. For this example, the output voltage is 5 V and
the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 708 kHz to avoid pulse
skipping from 方程式 12. To ensure overcurrent runaway is not a concern during short circuits use 方程式 13 to
determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage of
60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch resistance of 87 mΩ, a current
limit value of 6 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 855 kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use 方程式 10 or the curve in 图
6-6. The switching frequency is set by resistor R3 shown in 图 8-1. For 400-kHz operation, the closest standard
value resistor is 243 kΩ.
1
5 A x 11 mW + 5 V + 0.7 V
60 V - 5 A x 87 mW + 0.7 V
æ
ö
fSW(maxskip)
=
´
= 708 kHz
ç
÷
135 ns
è
ø
(28)
(29)
(30)
8
6 A x 11 mW + 0.1 V + 0.7 V
60 V - 6 A x 87 mW + 0.7 V
æ
ö
fSW(shift)
=
´
= 855 kHz
ç
÷
135 ns
è
ø
101756
400 (kHz)1.008
RT (kW) =
= 242 kW
8.2.1.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use 方程式31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
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or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 7.6 μH. The nearest standard
value is 7.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from 方程式 33 and 方程式 34. For this design, the
RMS inductor current is 5 A and the peak inductor current is 5.8 A. The chosen inductor is a WE 7447798720,
which has a saturation current rating of 7.9 A and an RMS current rating of 6 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54561 which is nominally 7.5 A.
V
- VOUT
IN max
(
VOUT
)
60 V - 5 V
5 A x 0.3
5 V
LO min
=
´
=
´
= 7.6 mH
(
)
IOUT ´KIND
V
´ fSW
60 V ´ 400 kHz
IN max
(
)
(31)
(32)
spacer
V
OUT ´(V
- VOUT )
IN max
(
)
5 V x (60 V - 5 V)
IRIPPLE
=
=
= 1.591 A
V
´LO ´ fSW
60 V x 7.2 mH x 400 kHz
IN max
(
)
spacer
2
æ
ö
2
V
´ V
- V
OUT
(
OUT
)
æ
ç
ç
è
ö
÷
÷
ø
IN max
(
5 V ´ 60 V - 5 V
)
(
)
1
ç
ç
÷
1
2
2
I
=
I
(
+
´
=
5 A
+
´
= 5 A
)
( )
OUT
÷
L rms
(
)
12
V
´L ´ f
12
60 V ´ 7.2 mH ´ 400 kHz
O
SW
IN max
(
)
ç
÷
è
ø
(33)
spacer
IRIPPLE
1.591 A
2
IL peak = IOUT
+
= 5 A +
= 5.797 A
(
)
2
(34)
8.2.1.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
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supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. 方程
式 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw is
the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,
ΔIOUT is 3.75 A - 1.25 A = 2.5 A and ΔVOUT = 0.04 × 5 = 0.2 V. Using these numbers gives a minimum
capacitance of 62.5 μF. This value does not take the ESR of the output capacitor into account in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic
and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator cannot sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in 图 8-6. The excess energy absorbed in the output capacitor will increase the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. 方程式 36
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and Vi is the initial voltage. For this example, the worst case load step will be from 3.75 A to
1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is 4
% of the output voltage. This makes Vf = 1.04 × 5 = 5.2. Vi is the initial capacitor voltage which is the nominal
output voltage of 5 V. Using these numbers in 方程式36 yields a minimum capacitance of
44.1 μF.
方程式 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is
the inductor ripple current. 方程式37 yields 19.9 μF.
方程式 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. 方程式38 indicates the ESR should be less than 15.7 mΩ.
The most stringent criteria for the output capacitor is 62.5 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 3 x
47 μF, 10-V ceramic capacitors with 5 mΩof ESR will be used. The derated capacitance is 87.4 µF, well above
the minimum required capacitance of 62.5 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. 方程式 39 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, 方程式39 yields 459 mA.
2´ DI
2 ´ 2.5 A
OUT
C
>
=
= 62.5 mF
OUT
f
´ DV
400 kHz x 0.2 V
SW
OUT
(35)
2
(OH ) (OL )
2
3.75 A2 -1.25 A2
I
-
I
(
)
(
)
= 44.1 mF
COUT > LO
x
= 7.2 mH x
2
2
5.2 V2 - 5 V2
V
-
V
I
( ) ( )
(
)
f
(
)
(36)
(37)
1
1
1
1
C
>
´
=
x
= 19.9 mF
OUT
8´ f
8 x 400 kHz
25 mV
1.591 A
æ
ç
è
ö
÷
ø
æ
ö
V
SW
ORIPPLE
ç
è
÷
ø
I
RIPPLE
V
25 mV
ORIPPLE
R
<
=
= 15.7 mW
ESR
I
1.591 A
RIPPLE
(38)
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V
´ V
(
IN max
(
- V
OUT
OUT
)
=
IN max
(
5 V ´ 60 V - 5 V
)
(
)
12 ´ 60 V ´ 7.2 mH ´ 400 kHz
I
=
= 459 mA
COUT(rms)
12 ´ V
´L ´ f
O
SW
)
(39)
8.2.1.2.5 Catch Diode
The TPS54561 requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum
of 60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54561.
For the example design, the PDS760 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the PDS760 is 0.52 V at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. 方程式 40 is used
to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The PDS760 diode has a junction capacitance of 180 pF. Using 方程式 40, the total loss in the diode at the
nominal input voltage is 1.65 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
)
(V
- V
) ´ I
´ Vf d
C ´ f
´ V + Vf d
(
OUT
OUT
IN max
(
)
j
SW
IN
P =
+
=
D
V
2
IN max
(
)
2
12 V - 5 V ´ 5 A x 0.52 V
(
)
12 V
180 pF x 400 kHz x (12 V + 0.52 V)
+
= 1.65 W
2
(40)
8.2.1.2.6 Input Capacitor
The TPS54561 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54561. The input ripple current can be calculated using 方程式41.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V,
50 V or 100 V. For this example, four 2.2 μF, 100 V capacitors in parallel are used. 表 8-2 shows several
choices of high voltage capacitors.
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The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 方程式 42. Using the design example values, IOUT = 5 A, CIN = 8.8 μF, ƒsw = 400 kHz, yields
an input voltage ripple of 355 mV and a rms input ripple current of 2.26 A.
V
- V
OUT
)
= 5 A
(
IN min
(
7 V - 5 V
)
V
(
)
5 V
7 V
OUT
I
= I
x
x
´
= 2.26 A
OUT
CI rms
(
)
V
V
7 V
IN min
(
IN min
(
)
)
(41)
(42)
I
´ 0.25
5 A ´ 0.25
8.8 mF ´ 400 kHz
OUT
DV
=
=
= 355 mV
表8-2. Capacitor Types
IN
C
´ f
IN
SW
VENDOR
EIA Size
VOLTAGE
100 V
50 V
DIALECTRIC
COMMENTS
VALUE (μF)
1 to 2.2
1 to 4.7
1
1210
GRM32 series
Murata
100 V
50 V
1206
2220
2225
1812
1210
1210
1812
GRM31 series
VJ X7R series
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
50 V
100 V
50 V
Vishay
TDK
100 V
100 V
50 V
X7R
C series C4532
C series C3225
100 V
50 V
50 V
100 V
50 V
AVX
X7R dielectric series
1 to 4.7
1 to 2.2
100 V
8.2.1.2.7 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54561 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. 方程式 43 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the effective output capacitance of 87 µF up to 5 V with an
average current of 1 A requires a 0.3 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using 方程式 5. For the
example circuit, the slow start time is not too critical since the output capacitor value is 3 x 47 μF which does
not require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value of
3.5 ms which requires a 9.3-nF slow start capacitor calculated by 方程式 44. For this design, the next larger
standard value of 10 nF is used.
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Cout ´ Vout ´ 0.8
tss >
Issavg
(43)
(44)
Tss(ms) ´ Iss(μA)
Vref (V) ´ 0.8
3.5 ms ´ 1.7 μA
Css(nF) =
=
= 9.3 nF
(0.8 V x 0.8)
8.2.1.2.8 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A
ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or
higher voltage rating.
8.2.1.2.9 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54561. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin
and ground connected to the EN pin. 方程式 3 and 方程式 4 calculate the resistance values necessary. For the
example application, a 442 kΩ between VIN and EN (RUVLO1) and a 90.9 kΩ between EN and ground (RUVLO2
)
are required to produce the 6.5 V and 5 V start and stop voltages.
(45)
V
1.2 V
6.5 V - 1.2 V
442 kW
ENA
R
=
=
= 90.9 kW
UVLO2
V
- V
ENA
START
+1.2 mA
+ I
1
R
UVLO1
(46)
8.2.1.2.10 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩwas selected for R6.
Using 方程式 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
VOUT - 0.8 V
0.8 V
5 V - 0.8 V
0.8 V
æ
ö
RHS = RLS
x
= 10.2 kW x
= 53.5 kW
ç
÷
è
ø
(47)
8.2.1.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using 方程式48 and 方程式
49. For COUT, use a derated value of 87.4 μF. Use equations 方程式 50 and 方程式 51 to estimate a starting
point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1821 Hz and ƒz(mod) is 1100 kHz. 方程
式 49 is the geometric mean of the modulator pole and the ESR zero and 方程式 51 is the mean of modulator
pole and half of the switching frequency. 方程式 50 yields 44.6 kHz and 方程式 51 gives 19.1 kHz. Use the
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geometric mean value of 方程式 50 and 方程式 51 for an initial crossover frequency. For this example, after lab
measurement, the crossover frequency target was increased to 30 kHz for an improved transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT max
(
)
5 A
fP mod
=
=
2´ p´ VOUT ´ COUT 2 ´ p ´ 5 V ´ 87.4 mF
= 1821 Hz
(
)
(48)
1
1
f
=
=
= 1100 kHz
Z mod
(
)
2´ p´R
´ C
2 ´ p ´ 1.67 mW ´ 87.4 mF
ESR
OUT
(49)
(50)
f
=
f
f
=
1821 Hz x 1100 kHz = 44.6 kHz
co1
p(mod) x z(mod)
f
400 kHz
SW
f
=
f
=
1821 Hz x
= 19.1 kHz
co2
p(mod) x
2
2
(51)
To determine the compensation resistor, R4, use 方程式 52. Assume the power stage transconductance, gmps,
is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5 V, 0.8 V,
and 350 μA/V, respectively. R4 is calculated to be 16.8 kΩand a standard value of 16.9 kΩis selected. Use 方
程式 53 to set the compensation zero to the modulator pole frequency. 方程式 53 yields 5172 pF for
compensating capacitor C5. 4700 pF is used for this design.
æ
ç
è
ö
÷
ø
æ 2´ p´ f ´ C
ö
÷
ø
V
OUT
æ
ç
è
ö
÷
ø
2´ p´ 29.2 kHz ´ 87.4 mF
17 A / V
5V
æ
ö
co
OUT
R4 =
C5 =
x
=
x
= 16.8 kW
ç
ç
÷
gmps
V
x gmea
0.8 V x 350 mA / V
è
ø
è
REF
(52)
1
1
=
= 5172 pF
2´ p´R4 x f
2´ p´16.9 kW x 1821 Hz
p(mod)
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from 方程式 54 and 方程式 55 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x R
ESR
87.4 mF x 1.67 mW
16.9 kW
OUT
C8 =
=
= 8.64 pF
R4
(54)
(55)
1
1
C8 =
=
= 47.1 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
8.2.1.2.12 Power Dissipation Estimate
The following formulas show how to estimate the TPS54561 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD
)
and supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design
example.
æ
ç
è
ö
÷
ø
V
5 V
2
2
OUT
P
= I
(
´R
´
= 5 A ´ 87 mW ´
= 0.958 W
)
COND
OUT
DS on
( )
V
12 V
IN
(56)
spacer
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P
= V ´ f
´I
´ t
= 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
rise
SW
IN
SW
OUT
(57)
(58)
(59)
spacer
P
= V ´ Q ´ f
= 12 V ´ 3nC´ 400 kHz = 0.014 W
SW
GD
IN
G
spacer
P
= V ´ I = 12 V ´ 146 mA = 0.0018 W
IN Q
Q
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
P
= P
+ P
+ P + P = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W
TOT
COND
SW GD Q
(60)
(61)
For given TA,
T = T + R ´P
TOT
J
A
TH
For given TJMAX = 150°C
TA max = TJ max - RTH ´PTOT
(
)
(
)
(62)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance from junction to ambient for a given PCB layout (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
8.2.1.2.13 Safe Operating Area
The safe operating area (SOA) of a typical design is shown in 图 8-2, through 图 8-5 for 3.3-V, 5-V and 12-V
outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at
which the internal components and external components are at or below the manufacturer’s maximum
operating temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz.
copper, similar to the EVM. Careful attention must be paid to the other components chosen for the design,
especially the catch diode. In most applications the thermal performance will be limited by the catch diode. When
operating with high duty cycles, higher input voltage or at higher switching frequency the TPS54561's thermal
performance can become the limiting factor.
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90
80
70
60
90
80
70
60
50
40
30
20
50
6 V
8 V
12 V
40
24 V
12 V
24 V
36 V
48 V
60 V
36 V
48 V
30
60 V
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C047
C048
IOUT (Amps)
IOUT (Amps)
图8-3. 5-V Output with 400-kHz Switching
图8-2. 3.3-V Output with 400-kHz Switching
Frequency
Frequency
90
80
70
60
90
80
70
60
50
50
400 LFM
18 V
40
40
30
20
200 LFM
100 LFM
Nat Conv
24 V
36 V
30
48 V
60 V
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C048
C048
IOUT (Amps)
IOUT (Amps)
VIN = 36 V
VO = 12 V
fsw = 800 kHz
图8-4. 12-V Output with 800-kHz Switching
Frequency
图8-5. Air Flow Conditions
8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 410 mA. The power supply enters Eco-mode when the output current is lower than 25 mA. The input
current draw is 280 μA with no load.
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8.2.1.3 Application Curves
Measurements are taken with standard EVM using a 12-V input, 5-V output, and 5-A load unless otherwise
noted.
VIN
IOUT
VOUT œ5V offset
VOUT œ5V offset
Time = 4 ms/div
Time = 100 ms/div
图8-7. Line Transient (8 V to 40 V)
图8-6. Load Transient
EN
VIN
SS/TR
VOUT
EN
VOUT
PGOOD
Time = 2 ms/div
Time = 2 ms/div
图8-9. Start-up With EN
图8-8. Start-up With VIN
SW
SW
IL
IL
VOUT œ AC Coupled
VOUT œ AC Coupled
Time = 4 ms/div
Time = 4 ms/div
图8-11. Output Ripple DCM
图8-10. Output Ripple CCM
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SW
SW
IL
IL
VOUT œ AC Coupled
VIN œ AC Coupled
Time = 1 ms/div
Time = 4 ms/div
图8-12. Output Ripple PSM
图8-13. Input Ripple CCM
SW
IL
SW
IL
VOUT
VIN œ AC Coupled
Time = 4 ms/div
Time = 40 ms/div
图8-14. Input Ripple DCM
图8-15. Low Dropout Operation
I
= 100 mA
I
= 1 A
OUT
EN Floating
OUT
EN Floating
V
V
V
V
IN
IN
OUT
OUT
Time = 40 ms/div
Time = 40 ms/div
图8-16. Low Dropout Operation
图8-17. Low Dropout Operation
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100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5 V, fsw = 400 kHz
VOUT = 5 V, fsw = 400 kHz
VIN = 24 V
VIN = 7 V
VIN = 7 V
VIN = 12 V
VIN = 12 V
VIN =24V
VIN = 60 V
VIN = 36 V
VIN = 48 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
60
0
0.001
1
2
3
4
5
0.01
0.10
1.00
C024
C024
IO - Output Current (A)
IO - Output Current (A)
图8-18. Efficiency vs Load Current
图8-19. Light Load Efficiency
100
100
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
60
VIN = 6 V
VIN = 12 V
VIN =24V
VIN =36V
VOUT = 3.3 V, fsw = 400 kHz
VIN = 6 V
VIN =12V
VIN = 24V
VIN = 48 V
VOUT = 3.3 V, fsw = 400 kHz
VIN = 60 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
6
0.001
0
1
2
3
4
5
0.01
0.10
1.00
C024
C024
IO - Output Current (A)
IO - Output Current (A)
图8-20. Efficiency vs Load Current
图8-21. Light Load Efficiency
100
60
40
180
95
90
85
80
75
70
65
60
Phase
120
60
Gain
20
0
0
VIN = 18 V
VIN = 24 V
œ20
œ40
œ60
œ60
œ120
œ180
VIN = 36 V
V
= 48 V
IN
V
= 60 V
IN
VIN = 12 V, VOUT = 5 V, IOUT = 5 A, fSW = 400 kHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
10
100
1k
10k
100k
C024
IO - Output Current (A)
C053
Frequency (Hz)
VOUT = 12 V
fsw = 800 kHz
图8-23. Overall Loop Frequency Response
图8-22. Efficiency vs Output Current
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0.10
0.08
0.10
0.08
0.06
0.06
0.04
0.04
0.02
0.02
0.00
0.00
œ0.02
œ0.04
œ0.06
œ0.02
œ0.04
œ0.06
œ0.08
œ0.10
œ0.08
VOUT = 5 V, IOUT = 2.5 A, fsw = 400 kHz
5 10 15 20 25 30 35 40 45 50 55 60
VIN = 12 V, VOUT = 5 V, fsw = 400 kHz
œ0.10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C024
C024
IO - Output Current (A)
VI - Input Voltage (V)
图8-24. Regulation vs Load Current
图8-25. Regulation vs Input Voltage
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8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
VIN
+
Cin
Cboot
Lo
SW
GND
BOOT
VIN
Cd
R1
R2
+
GND
Co
TPS54561
FB
VOUT
EN
COMP
SS/TR
Rcomp
RT/CLK
Czero Cpole
Css
RT
Copyright © 2017, Texas Instruments Incorporated
图8-26. TPS54561 Inverting Power Supply From Application Note
8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
VOPOS
+
Copos
VIN
+
Cin
Cboot
SW
GND
BOOT
VIN
GND
Lo
Cd
R1
R2
+
Coneg
TPS54561
VONEG
FB
EN
SS/TR
COMP
RT/CLK
Rcomp
Czero Cpole
Css
RT
Copyright © 2017, Texas Instruments Incorporated
图8-27. TPS54561 Split Rail Power Supply Based on the Application Note
9 Power Supply Recommendations
The design of the device is for operation from an power supply range between 4.5 V and 60 V. Good regulation
of this power supply is essential. If the power supply is more distant than a few inches from the TPS54561
converter, the circuit may require additional bulk capacitance besides the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 µF is a typical choice.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See 图 10-1 for a PCB layout
example. The GND pin should be tied directly to the thermal pad under the IC.
The thermal pad should be connected to internal PCB ground planes using multiple vias directly under the IC.
The SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW
connection is the switching node, the catch diode and output inductor should be located close to the SW pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full
rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to
noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of
trace. The additional external components can be placed approximately as shown. It may be possible to obtain
acceptable performance with alternate PCB layouts, however this layout has been shown to produce good
results and is meant as a guideline.
10.2 Layout Example
VOUT
Output
Capacitor
Output
Inductor
Topside
Ground
Route Boot Capacitor
Catch
Area
Trace on another layer to
provide wide path for
topside ground
Diode
Input
Bypass
Capacitor
BOOT
VIN
PWRGD
VIN
SW
EN
GND
UVLO
SS/TR
COMP
FB
Adjust
Resistors
RT/CLK
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Soft-Start
Capacitor
Frequency
Set Resistor
图10-1. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of 图8-1 the estimated printed circuit board area is 1.025 in2 (661 mm2).
This area does not include test points or connectors.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the TPS54560, TPS54561, and TPS54561-Q1 family Excel design tool, see SLVC452.
11.1.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
• Evaluation Module for the TPS54561 Step-Down Converter, SLVU993
• Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511, SLVA464
• Creating GSM /GPRS Power Supply from TPS54260, SLVA412)
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
Eco-mode™ and TI E2E™ are trademarks of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation.
WEBENCH® are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54561DPRR
TPS54561DPRT
ACTIVE
WSON
WSON
DPR
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS
54561
ACTIVE
DPR
NIPDAU
TPS
54561
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2021
OTHER QUALIFIED VERSIONS OF TPS54561 :
Automotive : TPS54561-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54561DPRR
TPS54561DPRT
WSON
WSON
DPR
DPR
10
10
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54561DPRR
TPS54561DPRT
WSON
WSON
DPR
DPR
10
10
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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