TPS54680PWP [TI]
3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FOR SEQUENCING; 3 V至6 V的输入， 6 -A输出跟踪同步降压型PWM具有集成FET SWITCHER （ SWIFT ）进行测序
| 型号： | TPS54680PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FOR SEQUENCING |
| 文件： | 总18页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Size
6,4 mm X 9,7 mm
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK
PWM SWITCHER WITH INTEGRATED FETs (SWIFT ) FOR SEQUENCING
FEATURES
DESCRIPTION
D
Power Up/Down Tracking For Sequencing
As a member of the SWIFT family of dc/dc regulators,
the TPS54680 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Using the TRACKIN pin
with other regulators, simultaneous power up and down
are easily implemented. Included on the substrate with
the listed features are a true, high performance, voltage
error amplifier that enables maximum performance and
flexibility in choosing the output filter L and C
components; an under-voltage-lockout circuit to
prevent start-up until the input voltage reaches 3 V; an
internally or externally set slow-start circuit to limit
inrush currents; and a power good output useful for
processor/logic reset.
D
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
or Sink Current
D
Wide PWM Frequency:
Fixed 350 kHz or Adjustable 280 kHz to
700 kHz
D
D
D
Power Good and Enable
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
D
D
Low-Voltage, High-Density Distributed Power
Systems
The TPS54680 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors Requiring Sequencing
D
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
STARTUP TIMING
I/O Supply
I/O
V
= 5 V
I
Input
Core Supply
f
= 700 kHz
s
VIN
PH
CORE
TPS54680
BOOT
PGND
TRACKIN
VSENSE
AGND COMP
VBIAS
PWRGD(I/O)
PWRGD(CORE)
t – Time – 500 µs/div
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of TexasInstruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
(1)
–40°C to 85°C
0.9 V to 3.3 V
Plastic HTSSOP (PWP)
TPS54680PWP
(1)
ThePWPpackageisalsoavailabletapedandreeled. AddanRsuffix to the device type(i.e.,TPS54680PWPR).Seetheapplicationsectionof
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)
TPS54680
–0.3 V to 7 V
–0.3 V to 6 V
–0.3 V to 4V
–0.3 V to 17 V
–0.3 V to 7 V
–0.6 V to 10 V
UNIT
VIN, ENA
RT
Input voltage range, V
V
I
VSENSE, TRACKIN
BOOT
VBIAS, COMP, PWRGD
Output voltage range, V
V
O
PH
PH
InternallyLimited
Source current, I
O
COMP, VBIAS
PH
6
12
mA
A
COMP
6
Sink current, I
S
mA
ENA, PWRGD
AGND to PGND
10
Voltagedifferential
Operating virtual junction temperature range, T
±0.3
V
–40 to 125
–65 to 150
300
°C
°C
°C
J
Storagetemperature,T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Inputvoltage, V
3
6
V
I
Operatingjunctiontemperature, T
–40
125
°C
J
DISSIPATION RATINGS(1)(2)
THERMALIMPEDANCE
JUNCTION-TO-AMBIENT
T
= 25°C
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING POWER RATING POWER RATING
(3)
28 Pin PWP with solder
18.2 °C/W
40.5 °C/W
5.49 W
3.02 W
1.36 W
2.20 W
0.99 W
28 Pin PWP without solder
2.48 W
(1)
(2)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
(3)
2
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS
overoperating free-air temperature range unless otherwise noted
PARAMETER
SUPPLY VOLTAGE, VIN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range, VIN
3.0
6.0
V
f = 350 kHz, RT open,
PH pin open
s
11
15.8
I
Quiescentcurrent
mA
(Q)
f = 500 kHz, RT = 100 kΩ, PH pin open
16
1
23.5
1.4
s
Shutdown, ENA = 0 V
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
2.80
0.16
2.5
3.0
V
V
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.70
0.14
V
(1)
Rising and falling edge deglitch, UVLO
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I
= 0
2.70
2.80
2.90
100
V
(VBIAS)
(2)
µA
CUMULATIVE REFERENCE
V
ref
Accuracy
0.882 0.891
0.900
V
REGULATION
I
L
I
L
I
L
I
L
= 3 A, f = 350 kHz, T = 85°C
0.04
0.04
0.03
0.03
s
J
(1)(3)
Lineregulation
%/V
%/A
= 3 A, f = 550 kHz, T = 85°C
s
J
= 0 A to 6 A, f = 350 kHz, T = 85°C
s
J
(1)(3)
Loadregulation
= 0 A to 6 A, f = 550 kHz, T = 85°C
s
J
OSCILLATOR
Internallyset—freerunningfrequency
RT open
280
252
460
663
350
280
500
700
0.75
1
420
308
540
762
kHz
kHz
RT = 180 kΩ (1% resistor to AGND)
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)
Externally set—free running frequency range
(1)
Ramp valley
(1)
Rampamplitude(peak-to-peak)
V
V
(1)
Minimumcontrollableontime
Maximum duty cycle
200
ns
90%
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 9
3
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
overoperating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
(1)
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND
90
3
110
5
dB
(1)
Parallel 10 kΩ, 160 pF COMP to AGND
MHz
Error amplifier common mode input voltage
range
(1)
Powered by internal LDO
0
VBIAS
250
V
Input bias current, VSENSE
VSENSE = V
ref
60
nA
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/µs
PWM COMPARATOR
PWMcomparatorpropagationdelaytime,
PWM comparator input to PH pin (excluding
deadtime)
(1)
10-mVoverdrive
70
85
ns
ENABLE
Enable threshold voltage, ENA
Enable hysteresis voltage, ENA
0.82
1.20
0.03
2.5
1.40
V
V
(1)
Falling edge deglitch, ENA
µs
µA
Leakage current, ENA
V = 5.5 V
I
1
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
VSENSEfalling
90
3
%V
%V
ref
(1)
(1)
ref
Power good falling edge deglitch
35
µs
Output saturation voltage, PWRGD
Leakage current, PWRGD
I
= 2.5 mA
0.18
0.3
1
V
(sink)
V = 5.5 V
µA
I
CURRENT LIMIT
(1)
(1)
V = 3 V Outputshorted
7.2
10
10
12
I
Current limit trip point
A
V = 6 V Outputshorted
I
Current limit leading edge blanking time
Current limit total response time
100
200
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
°C
°C
Thermalshutdownhysteresis
OUTPUT POWER MOSFETS
(4)
(4)
V = 6 V
26
36
47
65
I
r
Power MOSFET switches
mΩ
DS(on)
V = 3 V
I
TRACKIN
Input offset, TRACKIN
V
= TRACKIN = 1.25 V
–1.5
1.5
mV
V
SENSE
See Note 1
Input voltage range, TRACKIN
Specified by design
0
V
ref
(1)
(2)
(3)
(4)
Static resistive loads only
Specified by the circuit used in Figure 9
MatchedMOSFETs low-side r
DS(on)
production tested, high-side r specified by design
DS(on)
4
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TPS54680
SLVS429 – OCTOBER 2002
PWP PACKAGE
(TOP VIEW)
1
28
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
ENA
TRACKIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
2
27
26
25
24
23
22
21
20
19
18
17
16
15
3
4
5
6
7
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
8
9
10
11
12
13
14
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor.
ConnectPowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
ENA
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
27
Enableinput. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and
places device in low quiescent current state.
PGND
15–19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
totheinputandoutputsupplyreturns,andnegativeterminalsoftheinputandoutputcapacitors.Asinglepointconnection
to AGND is recommended.
PH
6–14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
RT
4
Power good open drain output. High when VSENSE ≥ 90% V , otherwise PWRGD is low.
ref
28
26
25
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
External reference input. High impedance input to internal reference/multiplexer and error amplifier circuits.
TRACKIN
VBIAS
Internal biasregulatoroutput.Suppliesregulatedvoltagetointernalcircuitry. BypassVBIASpintoAGNDpinwithahigh
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20–24 Input supplyforthepowerMOSFETswitchesandinternalbiasregulator. Bypass VIN pins to PGND pins close to device
packagewith a high quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
Enable
Comparator
REG
Falling
Edge
Deglitch
SHUTDOWN
ENA
VIN
ILIM
1.2 V
VIN
Comparator
Thermal
Shutdown
150°C
Hysteresis: 0.03 V
Leading
Edge
2.5 µs
Blanking
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.95 V
sense Fet
Deglitch
Hysteresis: 0.16 V
30 mΩ
I/O
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
Core
PH
TRACKIN
Multiplexer
Reference
+
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
–
Error
Amplifier
PWM
Comparator
VIN
25 ns Adaptive
Dead Time
30 mΩ
PGND
OSC
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 V
ref
Hysteresis: 0.03 Vref
TPS54680
SHUTDOWN
35 µs
VSENSE
COMP
RT
ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS397 AND SLVS400)
DEVICE
TPS54611
TPS54612
TPS54613
OUTPUT VOLTAGE
DEVICE
TPS54614
TPS54615
TPS54616
OUTPUT VOLTAGE
DEVICE
TPS54672
TPS54610
OUTPUT VOLTAGE
Activeterminal
Adjustable
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
RELATED DC/DC PRODUCTS
D
D
D
D
UCC3585—dc/dc controller
TPS56300—dc/dc controller
TPS759xx—7.5-A low dropout regulator
PT6440 series—6-A plugin modules
6
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
TYPICAL CHARACTERISTICS
INTERNALLY SET
DRAIN-SOURCE
DRAIN-SOURCE
OSCILLATOR FREQUENCY
vs
ON-STATE RESISTANCE
vs
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
60
50
40
750
650
550
60
VIN = 3.3 V
VIN = 5 V
I
= 6 A
O
50
I
= 6 A
O
40
30
20
30
20
450
350
250
10
0
10
0
–40
0
25
85
125
–40
0
25
85
125
–40
0
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 1
Figure 2
Figure 3
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
DEVICE POWER LOSSES AT T = 125°C
J
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
vs
LOAD CURRENT
JUNCTION TEMPERATURE
5
0.895
0.893
0.891
0.889
800
700
600
T
= 125°C
= 700 kHz
J
4.5
4
f
s
RT = 68 k
RT = 100 k
RT = 180 k
V
= 3.3 V
I
3.5
3
2.5
2
500
400
300
200
1.5
1
V
I
= 5 V
0.887
0.885
0.5
0
0
1
2
3
4
5
6
7
8
–40
0
25
85
125
–40
0
25
85
125
I
– Load Current – A
L
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 6
Figure 4
Figure 5
OUTPUT VOLTAGE REGULATION
ERROR AMPLIFIER
OPEN LOOP RESPONSE
vs
INPUT VOLTAGE
0
140
120
0.895
0.893
0.891
0.889
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
L
A
T
= 85°C,
= 3 A
A
–20
–40
–60
–80
I
O
100
80
60
40
20
Phase
f
= 550 kHz
s
–100
–120
–140
–160
–180
–200
Gain
0.887
0.885
0
–20
1
10 100 1 k 10 k 100 k 1 M 10 M
3
3.5
4
4.5
5
5.5
6
f – Frequency – Hz
V – Input Voltage – V
I
Figure 7
Figure 8
7
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54680 application. The TPS54680 (U1) can provide
greater than 6 A of output current at a nominal output
voltage of 1.8 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated
circuit package must be soldered to the printed-circuit
board. To provide power up tracking, the enable of the I/O
supply should be used. If the I/O enable is not used to
power up, then devices with similar undervoltage lockout
thresholds need to be implemented to ensure power up
tracking. To ensure power down tracking, the enable pin
should be used.
TPS54610
I/O Power Supply
VOUT_I/O
R1
10 kΩ
U1
R2
28
1
2
3
4
5
6
7
RT
AGND
R3
R4
10 kΩ
27
26
25
24
23
22
21
20
19
18
17
16
15
71.5 kΩ
ENA
VSENSE
R5
C1
10 kΩ
TRACKIN COMP
10 kΩ
R7
VBIAS
VIN
PWRGD
BOOT
PH
470 pF
C4
C3
C2
R6
301 Ω
470 pF
C5
VIN
1 µF
9.76 kΩ
R8
12 pF
0.047 µF
VIN
VIN
VIN
PH
8
9.76 kΩ
PH
9
PH
10
11
12
PGND
PGND
PGND
PGND
PGND
PH
VOUT_CORE
VIN
L1
0.65 µH
PH
R9
2.2 Ω
PH
C7
10 µF
C9
C10
22 µF 22 µF
C6
10 µF
C8
22 µF
13
14
PH
PH
C11
PwrPad
3300 pF
Analog and Power Grounds are Tied at
the Power Pad Under the Package of IC
Figure 9. Application Circuit
at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form the
loopcompensation network for the circuit. For this design,
a Type 3 topology is used.
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional designinformationisavailable
at www.ti.com.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is selected
byleavingRTopen.Connectinga180 kΩ to68kΩresistor
betweenRT(pin28) and analog ground can be used to set
the switching frequency to 280 kHz to 700 kHz. To
calculate the RT resistor, use the equation below:
INPUT FILTER
The input voltage is a nominal 5 Vdc. The input filter C6 is
a 10-µF ceramic capacitor (Taiyo Yuden). C7 also a 10-µF
ceramic capacitor (Taiyo Yuden) provides high frequency
decoupling of the TPS54680 from the input supply and
must be located as close as possible to the device. Ripple
current is carried in both C6 and C7, and the return path to
PGND must avoid the current circulating in the output
capacitors C8, C9, and C10.
500 kHz
Switching Frequency
R +
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and 3
x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0227. The
capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R3 and R8 sets the output voltage for the circuit
8
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TPS54680
SLVS429 – OCTOBER 2002
GROUNDING AND POWERPAD LAYOUT
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
The TPS54680 has two internal grounds (analog and
power).Inside the TPS54680, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directlyto AGND. Noise injected between the two grounds
can degrade the performance of the TPS54680,
particularly at higher output currents. However, ground
noiseonananaloggroundplanecanalsocauseproblems
with some of the control and bias signals. Therefore,
separate analog and power ground planes are
recommended. These two planes must tie together
directlyattheICtoreducenoisebetweenthetwogrounds.
The only components that must tie directly to the power
groundplane are the input capacitor, the output capacitor,
theinputvoltagedecouplingcapacitor, andthePGNDpins
of the TPS54680. The layout of the TPS54680 evaluation
module is representative of a recommended layout for a
4-layer board. Documentation for the TPS54680
evaluationmodule can be found on the TexasInstruments
web site under the TPS54680 product folder. See the
TPS54680 EVM user’s guide.
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3-inchby3-inchplaneof1ouncecopperisrecommended,
thoughnotmandatory,dependingonambienttemperature
andairflow. Most applicationshavelargerareasofinternal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available must be used when 6 A or greater
operationis desired. Connection from theexposedareaof
the PowerPAD to the analog ground plane layer must be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias must be in the
PowerPAD areawithfouradditionalviaslocatedunderthe
device package. The size of the vias under the package,
butnot in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyondthetwelverecommended
that enhance thermal performance must be included in
areas not under the device package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mil
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
Minimum Recommended Top
Side Analog Ground Area
0.0400
Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD
9
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
PERFORMANCE GRAPHS
EFFICIENCY
vs
LOAD REGULATION
vs
LINE REGULATION
vs
OUTPUT CURRENT
OUTPUT CURRENT
INPUT VOLTAGE
0.20
0.15
0.10
0.05
95
0.20
0.15
T
A
= 25°C,
V
= 0.9 V
F
V
= 700 kHz,
= 1.8 V
O
S
O
V
= 1.8 V
O
90
85
80
75
70
V
= 1.2 V
O
0.10
I
= 6 A
O
V
= 1.8 V
O
0.05
0
V
= 1.2 V
O
0
V
= 0.9 V
I
= 0 A
O
O
–0.05
–0.05
–0.10
T
A
= 25°C,
–0.10
V
= 3.3 V,
V
F
= 3.3 V,
I
I
65
60
F
S
= 700 kHz,
–0.15
–0.20
= 700 kHz,
–0.15
–0.20
S
V
= 0.9 V, 1.2 V and 1.8 V
V
= 0.9 V, 1.8 V and 2.5 V
O
O
3
3.5
4
4.5
5
5.5
6
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
I
– Output Current – A
I
– Output Current – A
O
V – Input Voltage – V
I
O
Figure 11
Figure 13
Figure 12
AMBIENTTEMPERATURE
vs
LOAD CURRENT
OUTPUT AND INPUT RIPPLE
LOOP RESPONSE
125
115
105
95
180
150
120
90
60
T
J
= 125°C
50
f
= 700 kHz
s
40
30
20
10
V
= 5 V
Phase
I
60
85
30
(1)
Safe Operating Area
75
Gain
0
0
–10
–30
65
V
= 3.3 V
I
–20
–60
55
–30
–40
–50
–90
45
V
I
f
= 5 V,
= 0 A,
= 700 kHz
I
O
S
–120
35
–150
–180
25
–60
0
1
2
3
4
5
6
7
8
t – Time – 1 µs/div
100
1 k
10 k
100 k
1 M
I
– Output Current – A
f – Frequency – Hz
O
Figure 14
Figure 16
Figure 15
STARTUP TIMING
LOAD TRANSIENT RESPONSE
POWER DOWN TIMING
I/O
I/O
V
f
= 5 V
= 700 kHz
I
s
V
V
= 5 V,
I
= 1.8 V
O
CORE
CORE
PWRGD(I/O)
PWRGD(I/O)
PWRGD(CORE)
PWRGD(CORE)
t – Time – 500 µs/div
t – Time –20 µs/div
t – Time –20 µs/div
Figure 19
Figure 17
Figure 18
(1)
10
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
Figure 20 shows the schematic diagram for a power
supply tracking design using a TPS2034 high side power
switch and a TPS54680 device. The TPS2034 power
switch ensures the I/O voltage is not applied to the load
before U1 has enough bias voltage to operate and
generate the core voltage.
TPS2034
Distribution Switch
VOUT_I/O
R1
10 kΩ
U1
R2
28
1
2
3
4
5
6
7
RT
AGND
R3
R4
10 kΩ
27
26
25
24
23
22
21
20
19
18
17
16
15
71.5 kΩ
ENA
VSENSE
R5
C1
10 kΩ
TRACKIN COMP
10 kΩ
R7
VBIAS
VIN
PWRGD
BOOT
PH
470 pF
C4
C3
C2
R6
301 Ω
470 pF
C5
VIN
1 µF
9.76 kΩ
R8
12 pF
0.047 µF
VIN
VIN
VIN
PH
8
9.76 kΩ
PH
9
PH
10
11
12
PGND
PGND
PGND
PGND
PGND
PH
VOUT_CORE
VIN
L1
0.65 µH
PH
R9
2.2 Ω
PH
C7
10 µF
C9
C10
22 µF 22 µF
C6
10 µF
C8
22 µF
13
14
PH
PH
C11
PwrPad
3300 pF
Analog and Power Grounds are Tied at
the Power Pad Under the Package of IC
Figure 20. 3.3-V Small Size, High Frequency Design
11
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
LOAD TRANSIENT RESPONSE
V
V
= 3.3 V,
I
= 1.8 V
O
t – Time –20 µs/div
Figure 21
EFFICIENCY
LOAD REGULATION
vs
LINE REGULATION
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
INPUT VOLTAGE
100
95
0.20
0.15
0.20
0.15
0.10
0.05
V
T
= 1.8 V,
25°C,
= 700 kHz
O
A
V
V
T
A
= 5 V,
I
= 1.8 V,
= 25°C,
O
V
= 1.8 V
O
90
F
S
0.10
0.05
0
F
S
= 700 kHz
85
80
I
= 6 A
O
V
= 0.9 V
O
75
70
0
I
= 0 A
V
= 1.2 V
O
O
–0.05
–0.05
65
60
–0.10
–0.15
–0.20
–0.10
–0.15
–0.20
V
= 5 V,
= 25°C,
= 700 kHz
I
T
A
55
50
F
S
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
0
1
2
3
4
5
6
7
8
4
4.5
5
5.5
6
I
– Output Current – A
I
– Output Current – A
O
O
V – Input Voltage – V
I
Figure 22
Figure 24
Figure 23
AMBIENTTEMPERATURE
vs
LOAD CURRENT
LOOP RESPONSE
OUTPUT AND INPUT RIPPLE
125
115
105
95
180
150
120
90
60
50
T
J
= 125°C
f
= 700 kHz
s
40
30
20
10
Phase
V = 5 V
I
60
85
30
(1)
Safe Operating Area
Gain
75
0
0
–10
–30
65
V
= 3.3 V
I
–20
–60
55
–30
–40
–50
–90
V
I
f
= 3.3 V,
= 0 A,
= 700 kHz
I
O
S
45
–120
35
–150
–180
25
–60
0
1
2
3
4
5
6
7
8
100
1 k
10 k
100 k
1 M
t – Time – 1 µs/div
I
– Output Current – A
f – Frequency – Hz
O
Figure 25
Figure 27
Figure 26
12
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
SLOW-START TIMING
SLOW-START TIMING
4.0 ms/div
4.0 ms/div
Figure 28
Figure 29
13
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
DETAILED DESCRIPTION
VOLTAGE REFERENCE
The voltage reference system produces a precise V
ref
UNDERVOLTAGE LOCK OUT (UVLO)
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54680, since it cancels
offset errors in the scale and error amplifier circuits.
The TPS54680 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
thresholdvoltageof2.95V.OncetheUVLOstartthreshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
risingandfallingedgedeglitchcircuitreducethelikelihood
of shutting the device down due to noise on VIN.
OSCILLATOR AND PWM RAMP
The oscillator frequency is set internally to 350 kHz. If a
different frequency of operation is required for the
application, the oscillator frequency can be externally
adjusted from 280 to 700 kHz by connecting a resistor
between the RT pin and AGND. The switching frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
TRACKIN/INTERNAL SLOW-START
The internal slow-start circuit provides start-up slope
control of the output voltage. The nominal internal
slow-start rate is 25 V/ms. When the voltage on TRACKIN
rises faster than the internal slope or is present when
deviceoperationisenabled, theoutputrisesattheinternal
rate. If the reference voltage on TRACKIN rises more
slowly, then the output rises at about the same rate as
TRACKIN.
(2)
100 kW
Switching Frequency +
500 [kHz]
R
SWITCHING FREQUENCY
350 kHz, internally set
RT PIN
Float
R = 180 kΩ to 68 kΩ
Externally set 280 kHz to 700 kHz
Once the voltage on the TRACKIN pin is greater than the
internal reference of 0.891 V, the multiplexer switches the
noninverting node to the high precision reference.
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54680 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type
compensation can be employed using external
compensation components.
ENABLE (ENA)
The enable pin, ENA, provides a digital control enable or
disable (shut down) for the TPS54680. An input voltage of
1.4VorgreaterensuresthattheTPS54680isenabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
2 or type 3
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWMlatch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimumduration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommendedbecause their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
Externalloading on VBIAS is allowed, with the cautionthat
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latchisneverreset, andthehigh-sideFETremainsonuntil
14
www.ti.com
TPS54680
SLVS429 – OCTOBER 2002
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operatesatitsmaximumdutycycleuntiltheoutputvoltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54680 is capable of sinking current continuously
until the output reaches the regulation set-point.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reachingthecurrentlimitthreshold. A100-nsleadingedge
blanking circuit prevents the current limit from false
tripping. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the output
filter. Load protection during current sink operation is
provided by thermal shutdown.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-sideFETturnsontodecreasetheenergyintheoutput
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
THERMAL SHUTDOWN
Thedeviceusesthethermalshutdowntoturnoffthepower
MOSFETs and disable the controller if the junction
temperatureexceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
startingupbycontrolofthesoft-startcircuit,heatingupdue
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
doesnotturnonuntilthevoltageatthegateofthelow-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or ENA is low, or a thermal
shutdown occurs. When VIN ≥ UVLO threshold, ENA ≥
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
enable threshold, and VSENSE > 90% of V , the open
ref
drain output of the PWRGD pin is high. A hysteresis
voltageequalto3%ofV anda35µsfallingedgedeglitch
ref
circuit prevent tripping of the power good comparator due
to high frequency noise.
15
TPS54680
SLVS429 – OCTOBER 2002
www.ti.com
MECHANICAL DATA
PWP (R-PDSO-G**)
POWERPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
M
0,65
20
0,10
11
ThermalPad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
SeatingPlane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of TexasInstruments.
16
THERMAL PAD MECHANICAL DATA
PWP (R-PDSO-G28)
PowerPAD™ PLASTIC SMALL-OUTLINE
www.ti.com
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Copyright 2002, Texas Instruments Incorporated
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