TPS546D24SRVFR [TI]
具有增强安全性的 2.95V 至 16V、可堆叠 40A 同步 SWIFT™ 降压 PMBus® 转换器 | RVF | 40 | -40 to 150;型号: | TPS546D24SRVFR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有增强安全性的 2.95V 至 16V、可堆叠 40A 同步 SWIFT™ 降压 PMBus® 转换器 | RVF | 40 | -40 to 150 转换器 |
文件: | 总181页 (文件大小:5003K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS546D24S
ZHCSQY3 –MARCH 2023
TPS546D24S 具有PMBus® 和扩展写保护功能且最多可堆叠4 个的2.95V 至
16V、40A SWIFT™ 同步降压转换器
1 特性
3 说明
• 集成扩展安全功能
• 支持双电源:2.95V 至16V PVIN;2.95V 至18V
AVIN(4VIN VDD5 开关电压)
TPS546D24S 是一款高度集成的非隔离式直流/直流转
换器,它通过添加制造商特定的 PMBus 命令以及扩展
写保护和密钥,在 TPS546D24A 的基础上进行了扩
展。与标准写保护命令相比,此功能能够以更高的分辨
率限制写入功能,从而提高了安全性,有助于防止恶意
访问 PMBus。TPS546D24S 具有较高的工作频率和
40A 的电流输出,并采用 7mm × 5mm 封装。可将两
个、三个和四个 TPS546D24S 器件互连,在单个输出
上提供最高 160A 的电流。该器件可通过 VDD5 引
脚,利用 5V 的外部电源对内部的 5V LDO 进行过驱
动,从而提高效率并降低转换器的功耗。
• 集成4.5mΩ/0.9mΩ MOSFET
• 具有可选内部补偿的平均电流模式控制
• 可堆叠2 个、3 个、4 个,电流共享高达160A,每
个输出可支持单个地址
• 通过引脚搭接的可选输出电压范围为0.5V 至
5.5V,使用PMBus VOUT_COMMAND 的电压范
围为0.25V 至5.5V
• 广泛的PMBus 命令集,可遥测VOUT、IOUT 和内部
裸片温度
• 通过内部反馈分压器实现差分遥感,可检测到小于
1% 的VOUT 误差,TJ 为–40°C 至+150°C
• 通过PMBus 实现AVS 和裕量调节
• 采用MSEL 引脚,引脚编程PMBus 默认值
• 12 种介于225kHz 和1.5MHz 之间的可选开关频率
(8 个引脚搭接选项)
TPS546D24S 使用专有的固定频率电流模式控制,具
有输入前馈和可选的内部补偿元件,可在各种输出电容
下更大限度减小尺寸和提高稳定性。
PMBus® 接口具有 1MHz 时钟支持,为转换器配置提
供了便捷且标准化的数字接口,并且实现了对输出电
压、输出电流和内部裸片温度等关键参数的监控。对故
障状况的响应可设置为重新启动、锁存或忽略,具体取
决于系统要求。堆叠器件之间的反向通道通信使得所有
TPS546D24S 转换器能够为单个输出轨供电,共享一
个地址,从而简化系统软件/固件设计。也可通过 BOM
选择在不进行 PMBus 通信的情况下,配置输出电压、
开关频率、软启动时间和过流故障限制等关键参数,以
支持无程序加电。
• 频率同步输入/同步输出
• 支持预偏置输出
• 7mm × 5mm × 1.5mm、40 引脚QFN
• 与TPS546D24A 直接兼容
• 使用TPS546D24S 并借助WEBENCH® Power
Designer 创建定制设计方案
2 应用
封装信息
封装(1)
• 数据中心交换机、机架式服务器
• 有源天线系统、远程射频和基带单元
• 自动化测试设备、CT、PET 和MRI
• ASIC、SoC、FPGA、DSP 内核和I/O 电压
VIN
封装尺寸(标称值)
器件型号
RVF(LQFN-CLIP,
40)
TPS546D24S
7.00mm × 5.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
BP1V5
DRTN
VOSNS
GOSNS/FLWR
BOOT
MSEL1
MSEL2
ADRSEL
VSEL
VOUT
TPS546D24S
SW
VDD5
PGND
AGND
To Loop Followers
To PMBus
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSF26
TPS546D24S
ZHCSQY3 –MARCH 2023
www.ti.com.cn
Table of Contents
7.6 Register Maps...........................................................47
8 Application and Implementation................................155
8.1 Application Information........................................... 155
8.2 Typical Application.................................................. 155
8.3 Two-Phase Application........................................... 165
8.4 Four-Phase Application...........................................169
8.5 Power Supply Recommendations...........................170
8.6 Layout..................................................................... 170
9 Device and Documentation Support..........................173
9.1 Device Support....................................................... 173
9.2 Documentation Support.......................................... 173
9.3 接收文档更新通知................................................... 173
9.4 支持资源..................................................................173
9.5 Trademarks.............................................................173
9.6 静电放电警告.......................................................... 174
9.7 术语表..................................................................... 174
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Typical Characteristics..............................................15
7 Detailed Description......................................................19
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................35
7.5 Programming............................................................ 36
Information.................................................................. 175
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2023
*
Initial Release
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5 Pin Configuration and Functions
PGD/RST_B
PMB_DATA
PMB_CLK
BP1V5
DRTN
1
32
31
30
29
28
27
26
25
24
23
22
21
MSEL1
ADRSEL
VSEL
2
3
4
MSEL2
VDD5
EN/UVLO
AVIN
5
SMB_ALRT
BOOT
6
Thermal
Pad
7
SW
8
PVIN
SW
9
PVIN
SW
10
11
12
PVIN
SW
PVIN
SW
PVIN
Not to scale
图5-1. 40-Pin LQFN-CLIP with Exposed Thermal Pad RVF Package (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Open-drain power good or (21h) VOUT_COMMAND RESET#. As determined by user-programmable
RESET# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS). The default pin function is an open-drain
power-good indicator. When configured as RESET#, an internal pullup can be enabled or disabled by the
PULLUP# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS).
1
PGD/RST_B
I/O
2
3
PMB_DATA
PMB_CLK
I/O PMBus DATA pin. See Current PMBus Specifications.
I
PMBus CLK pin. See Current PMBus Specifications.
Output of the 1.5-V internal regulator. This regulator powers the digital circuitry and must be bypassed
with a minimum of 1 µF to DRTN with an X5R or better ceramic capacitor rated for a minimum of 6 V.
BP1V5 is not designed to power external circuit.
4
BP1V5
O
Digital bypass return for bypass capacitor for BP1V5. Internally connected to AGND. Do not connect to
PGND or AGND.
5
6
DRTN
—
SMB_ALRT
O
SMBus alert pin. See SMBus specification.
Bootstrap pin for the internal flying high side driver. Connect a typical 100-nF X5R or better ceramic
capacitor rated for a minimum of 10 V from this pin to SW. To reduce the voltage spike at SW, an optional
BOOT resistor of up to 8 Ωcan be placed in series with the BOOT capacitor to slow down turn-on of the
high-side FET.
7
BOOT
I
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
8
NAME
9
Switched power output of the device. Connect the output averaging filter and bootstrap to this group of
pins.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SW
I/O
PGND
Power stage ground return. These pins are internally connected to the thermal pad.
—
Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. PVIN to
PGND must be bypassed with X5R or better ceramic capacitors rated for at least 1.5x the maximum
PVIN voltage. In addition, a minimum of one 0402 2.2-nF - 10-nF X7R or better ceramic capacitance
rated for at least 1.5x the maximum PVIN voltage must placed as close to the PVIN and PGND pins or
under the PVIN pins to reduce the high-frequency bypass impedance.
PVIN
AVIN
I
I
Input power to the controller. Bypass with a minimum 1-µF X5R or better ceramic capacitor rated for at
least 1.5x the maximum AVIN voltage to AGND. If AVIN is connected to the same input as PVIN or
VDD5, a minimum 10-µs R-C filter between PVIN or VDD5 and AVIN is recommended to reduce
switching noise on AVIN.
26
Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to
program input voltage UVLO.
27
28
EN/UVLO
VDD5
I
Output of the 5-V internal regulator. This regulator powers the driver stage of the controller and must be
bypassed with a minimum of 4.7-µF X5R or better ceramic capacitor rated for a minimum of 10 V to
PGND at the thermal pad. Low impedance bypassing of this pin to PGND is critical.
O
Connect this pin to a resistor divider between BP1V5 and AGND for different options of soft-start time,
overcurrent fault limit,and multiphase information. See Programming MSEL2 or Programming MSEL2 for
a Loop Follower Device (GOSNS Tied to BP1V5) for a loop follower device (GOSNS tied to BP1V5) if
GOSNS is tied to BP1V5.
29
MSEL2
I
Connect this pin to a resistor divider between BP1V5 and AGND for different options of internal voltage
feedback divider and default output voltage. See Programming VSEL.
30
31
32
VSEL
ADRSEL
MSEL1
I
I
I
Connect this pin to a resistor divider between BP1V5 and AGND for different options of PMBus
addresses and frequency sync (including determination of SYNC pin as SYNCIN or SYNCOUT
function).See Programming ADRSEL.
Connect this pin to a resistor divider between BP1V5and AGND for different options of switching
frequency and internal compensation parameters. See Programming MSEL1.
The positive input of the remote sense amplifier. For a stand-alone device or the loop controller device in
a multi-phase configuration, connect VOSNS pin to the output voltage at the load. For the loop follower
device in a multi-phase configuration, the remote sense amplifier is not required for output voltage
sensing or regulation and this pin can be left floating. If used to monitor another voltage with the Phased
READ_VOUT command, VOSNS must be maintained between 0 V and 0.75 V with a <1-kΩresistor
divider due to the internal resistance to GOSNS, which is connected to BP1V5.
33
34
VOSNS
I
I
The negative input of the remote sense amplifier for loop controller device or must be pulled up high to
indicate loop follower. For a standalone device or the loop controller device in a multi-phase
configuration, connect the GOSNS pin to the ground at the load. For the loop follower device in a multi-
phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device a loop follower.
GOSNS/FLWR
Voltage sharing signal for multi-phase operation. For standalone device, the VSHARE pin must be left
floating. VSHARE can by bypassed to AGND with up to 50 pF of capacitance.
35
36
VSHARE
NC
I/O
-
Not internally connected. Connect to PGND at the thermal pad.
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PIN
表5-1. Pin Functions (continued)
I/O
DESCRIPTION
NO.
NAME
37
AGND
-
Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board.
For frequency synchronization, can be programmed as SYNC IN or SYNC OUT pin by ADRSEL pin or
38
SYNC
I/O the (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) PMBus Command. The SYNC pin can be left floating
when not used.
39
40
BCX_CLK
BCX_DAT
I/O Clock for back-channel communications between stacked devices
I/O Data for back-channel communications between stacked devices
Package thermal pad, internally connected to PGND. The thermal pad must have adequate solder
coverage for proper operation.
Thermal pad
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–1
MAX UNIT
Input voltage
Input voltage
Input voltage
PVIN
16
19
V
V
PVIN, < 2-ms transient
24
V
PVIN –SW (PVIN to SW differential)
AVIN
20
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
BOOT
35
V
5.5
V
BOOT –SW (BOOT to SW differential)
EN/UVLO, VOSNS, SYNC, VSEL, MSEL1, MSEL2, ADRSEL
VSHARE, GOSNS/FLWR
Input voltage
5.5
V
1.98
5.5
V
PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT
SW
V
Output voltage
Output voltage
19.5
19.5
5.5
V
SW < 10-ns transient
V
–5
VDD5, SMB_ALRT, PGD/RST_B
BP1V5
V
–0.3
–0.3
–40
–55
Output voltage
1.65
150
150
V
TJ operating junction temperature
Tstg Storage temperature
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.95
2.95
NOM
12
MAX
18
UNIT
V
VAVIN
VPVIN
VSW(peak)
TJ
Controller input voltage
Power stage input voltage
12
16
V
Peak Switch Node Voltage with respect to PGND
Junction temperature
18
V
150
°C
–40
6.4 Thermal Information
TPS546X24S
PQFN (RVF)
40 PINS
28.9
THERMAL METRIC(1)
UNIT
RθJA
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance JEDEC
Junction-to-ambient thermal resistance EVM(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
8.1
18.9
4.1
Junction-to-top characterization parameter
1.3
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English Data Sheet: SLUSF26
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6.4 Thermal Information (continued)
TPS546X24S
THERMAL METRIC(1)
PQFN (RVF)
40 PINS
4.1
UNIT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
ψJB
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) EVM thermal resistance measured on TPS546D24SEVM-2PH. 8-layer, 2-oz Cu per layer evaluation board.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY
VAVIN
Input supply voltage range
Power stage voltage range
Input operating current
2.95
2.95
16
V
VPVIN
16
IAVIN
Converter not switching
12.5
2.5
17 mA
AVIN UVLO
Analog input voltage UVLO
for power on reset (PMBus
communication)
enable threshold
2.7
V
VAVINuvlo
Analog input voltage UVLO
for disable
2.09
2.3
V
Analog input voltage UVLO
hysteresis
250
mV
Delay from AVIN UVLO to
tdelay(uvlo_PMBus) PMBus ready to
communicate
AVIN = 3 V
8
ms
PVIN UVLO
Factory default setting
Programmable range
Resolution
2.75
0.25
2.5
2.75
–5%
2.5
15.75
5%
V
VIN_ON
Power input turn on voltage
Accuracy
Factory default setting
Programmable range
Resolution
15.5
5%
V
VIN_OFF
Power input turnoff voltage
0.25
Accuracy
–5%
ENABLE AND UVLO
EN/UVLO Voltage rising
1.05
1.1
V
threshold
VENuvlo
EN/UVLO Voltage falling
threshold
0.9
4.5
VENhys
IENhys
EN/UVLO Voltage hysteresis No external resistors on EN/UVLO
EN/UVLO hysteresis current VEN/UVLO = 1.1 V
70
5.5
mV
6.5 uA
-5 nA
EN/UVLO hysteresis current VEN/UVLO = 0.9 V
-100
REMOTE SENSE AMPLIFIER
Remote sense input
impedance
VOSNS –
GOSNS = 1V
ZRSA
VOSNS to GOSNS
85
130
165
kΏ
GOSNS input range for
regulation accuracy (1)
VOSNS –GOSNS = 1V, VOUT_SCALE_LOOP ≤
0.5
VIRNG(GOSNS)
0.05
V
–0.05
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MAX UNIT
6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VOSNS input range for
regulation accuracy (1)
VIRNG(VOSNS)
5.5
V
GOSNS = AGND, VOUT_SCALE_LOOP ≤0.5
–0.1
REFERENCE VOLTAGE AND ERROR AMPLIFIER
Default setting
0.4
V
V
V
V
V
V
V
V
V
V
V
V
VREF
Reference voltage(1)
Reference voltage range(1)
Reference voltage resolution(1)
VOUT = 1000 mV
0.25
0.75
2 –12
0.992
0.492
1.490
0.994
0.494
1.492
0.995
0.495
1.493
1.008
0.508
1.510
1.006
0.506
1.508
1.005
0.505
1.507
–40°C ≤TJ ≤150°C(2)
0°C ≤TJ ≤125°C(2)
0°C ≤TJ ≤85°C(2)
VOUT = 500 mV
VOUT = 1500 mV
VOUT = 1000 mV
VOUT = 500 mV
VOUT = 1500 mV
VOUT = 1000 mV
VOUT = 500 mV
VOUT = 1500 mV
VOUT(ACC)
Output voltage accuracy
Progrmmable error amplifier
transonductance
25
200
µS
MHz
kΩ
GmEA
Resolution(1)
Four settings: 25 uS, 50 uS, 100 uS, 200 uS
25
8
Unloaded Bandwidth(1)
Programmable parallel
resistor range
5
1.25
6.25
315
18.75
RpEA
CintEA
CpEA
Resolution(1)
5
1.25
6.25
Programmable integrator
capacitor range
pF
pF
Resolution(1)
Programmable parallel
capacitor range
193.75
pF
Resolution(1)
CURRENT GM AMPLIFIER
Progrmmable current error
25
200
amplifier transonductance
µS
MHz
kΩ
GmBUF
Resolution(1)
Four settings: 25 µS, 50 µS, 100 µS, 200 µS
25
17
Unloaded bandwidth(1)
Programmable parallel
resistor range
5
800
315
1600
RpBUF
RintBUF
CintBUF
Resolution(1)
5
800
Programmable integrator
resistor range(1)
kΩ
pF
pF
Resolution(1)
Programmable integrator
capacitor range
0.3125
3.125
4.6875
96.875
Resolution(1)
0.3125
3.125
Programmable parallel
capacitor range
CpBUF
Resolution(1)
OSCILLATOR
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
225
500
TYP
MAX UNIT
Adjustment range(2)
Switching frequency(2)
1500
kHz
600
fSW
550
SYNCHRONIZATION
VIH(sync) High-level input voltage
VIL(sync)
1.35
V
Low-level input voltage
0.8
Sync input minimum pulse
width
tpw(sync)
fsw = 225 kHz to 1500 kHz
200
20
ns
%
SYNC pin frequency range
from FREQUENCY_SWITCH
frequency(1)
ΔfSYNC
–20
VDD5
–0.85V
VOH(sync)
VOL(sync)
tPLL
Sync output high voltage
Sync output low voltage
PLL lock time
VDD5
0.4
V
V
100-μA load
2.4-mA load
Fsw = 550 kHz, SYNC clock frequency 495 kHz -
605 kHz(1)
65
μs
Degre
e
fsw < 1.1 MHz
9
PhaseErr
Phase interleaving error(5)
23
ns
fsw ≥1.1 MHz
RESET
VIH(reset)
VIL(reset)
High-level input voltage(1)
Low-level input voltage
1.35
25
V
0.8
200
55
Minimum RESET_B pulse
width
tpw(reset)
ns
kΩ
V
Rpullup(reset)
Vpullup(reset)
Internal pull-up resistance
Internal Pull-up Voltage
VRESET = 0.8V
RESET# = 1
RESET# = 1
34
VDD5 -
0.5
IRESET = 10 μA
VDD5 REGULATOR
Regulator output voltage
Default, IVDD5 = 10 mA
4.5
3.9
4.7
4.9
5.3
V
V
VVDD5
Programmable range(1)
Resolution
200
130
mV
VVDD5(do)
IVDD5SC
Regulator dropout voltage
285 mV
mA
VAVIN –VVDD5, VAVIN = 4.5 V, IVDD5 = 25 mA
Regulator short-circuit
current(1)
VAVIN = 4.5 V
100
Enable voltage on VDD5 for
pin-strapping
VVDD5ON(IF)
VVDD5OFF(IF)
VVDD5ON(SW)
VVDD5OFF(SW)
VVDD5UV(hyst)
2.62
2.48
2.85
V
V
Disable voltage on VDD5 for
pin-strapping
2.25
Switching enable voltage
upon VDD5
4.05
V
Switching disable voltage
upon VDD5
3.10
400
V
Regulator UVLO voltage
hysteresis
mV
BOOTSTRAP
VBOOT(drop)
Bootstrap voltage drop
IBOOT = 20 mA, VDD5 = 4.5 V
225 mV
BP1V5 REGULATOR
VBP1V5
1.5-V regulator output voltage
1.42
1.5
1.58
V
V
AVIN ≥4.5 V, IBP1V5 = 5 mA
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.5-V regulator short-circuit
current(1)
IBP1V5SC
PWM
30
mA
Minimum controllable pulse
width(1)
tON(min)
20
ns
ns
tOFF(min)
PWM Minimum off-time(1)
Soft-start time
400
3
500
SOFT START
Factory default setting
Programmable range(1) (3)
0
–10%
0
31.75 ms
15%
tON_RISE
Resolution
0.25
0
Accuracy, TON_RISE = 3 ms
Factory default setting(4)
Programmable range(1) (4)
Resolution
127.5 ms
15%
Upper limit on the time to
power up the output
tON_MAX_FLT_LT
0.5
0
Accuracy(1)
–10%
0
Factory default setting
Programmable range(1)
Resolution
127.5 ms
15%
tON_DELAY
SOFT STOP
tOFF_FALL
Turn-on delay
0.5
Accuracy(1)
–10%
Factory default setting(3)
Programmable range(1)
0.5
0.25
0
(3)
0
–10%
0
31.75 ms
15%
Soft-stop time
Turn-off delay
Resolution
Accuracy, TOFF_FALL = 1 ms
Factory default setting
Programmable range(1)
Resolution
127.5 ms
15%
tOFF_DELAY
0.5
Accuracy(1)
–10%
POWER INPUT OVERVOLTAGE/UNDERVOLTAGE
Factory default
20
Power Input overvoltage fault
limit
VPVINOVF
Programmable range
Resolution
6
20
V
V
1
Factory default
Programmable range
Resolution
2.5
Power Input undervoltage
warning limit
VPVINUVW
2.5
15.75
0.25
POWER STAGE
VBOOT - VSW = 4.5 V, TJ = 25°C
VBOOT - VSW = 3 V, TJ = 25°C
VVDD5 = 4.5 V, TJ = 25°C
VVDD5 = 3 V, TJ = 25°C
4.5
8.0
0.9
1.4
mΩ
mΩ
mΩ
mΩ
High-side power device on-
resistance
RHS
Low-side power device on-
resistance
RLS
SW internal pull-down
resistance
Rswpd
3
30
35
kΩ
Weak high-side gate drive
triggering threshold upon
PVIN rising
Vwkdr(on)
14.75
V
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English Data Sheet: SLUSF26
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Weak high-side gate drive
recovering threshold upon
PVIN falling
Vwkdr(off)
14.35
V
Power stage driver dead-time
tDEAD(LtoH)
from Low-side off to High-side VVDD5 = 4.5 V, TJ = 25°C(1)
on
6
6
ns
ns
Power stage driver dead-time
tDEAD(HtoL)
from High-side off to Low-side VVDD5 = 4.5 V, TJ = 25°C(1)
on
CURRENT SHARING
Output current sharing
accuracy of two devices
defined as the ratio of the
current difference between
two devices to the sum of the
two
OUT ≥20 A per device(5)
–10%
10%
I
ISHARE(acc)
Output current sharing
accuracy of two devices
defined as the current
difference between each
device and the average of all
devices
IOUT < 20 A per device(5)
2
A
–2
Current Share Ratio between
TPS546B24S and
ISHARE(ratio)
IOUT(B24S + D24S) = 30A(5)
0.5
TPS546D24S
VSHARE fault trip threshold
0.1
0.2
VVSHARE
V
VSHARE fault release
threshold
LOW-SIDE CURRENT LIMIT PROTECTION
Off time between restart
7 ×
tON_RISE
Factory default setting
attempts(1)
tOFF(OC)
ms
1 ×
tON_RISE
7 ×
tON_RISE
Range
Factory default setting
Programmable range
Resolution
52
IO_OC_FLT_L Output current overcurrent
8
62
MT
fault threshold
2
–20
40
A
Negative output current
overcurrent protection
threshold
INEGOC
Factory default setting
Programmable range
Resolution
IO_OC_WRN_L Output current overcurrent
8
62
A
A
MT
warning threshold
2
IOUT = 20 A
4
8
–2
–4
Output current overcurrent
fault error
IOC(acc)
IOUT = 40 A(5)
HIGH-SIDE SHORT CIRCUIT PROTECTION
Ratio of High-side short-
circuit protection fault
threshold over Low-side
(VBOOT –VSW) = 4.5V, TJ = 25°C(5)
105%
150%
100
200%
IHSOC
overcurrent limit
High-side current sense
blanking time
ns
POWER GOOD (PGOOD) AND OVERVOLTAGE/UNDERVOLTAGE WARNING
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MAX UNIT
6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
RPGD
PGD pulldown resistance
IPGD = 5 mA
VPGD = 5 V
30
50
Ω
Output high open drain
leakage current into PGD pin
IPGD(OH)
15 µA
PGD pin output low level
voltage at no supply voltage
VPGD(OL)
0.8
V
VAVIN = 0, IPGD = 80 μA
Overvoltage warning
threshold (PGD threshold on
VOSNS rising)
106%
103%
110%
114%
116%
VOVW
Factory default, at VOUT_COMMAND (VOC) = 1 V
Range
Resolution
1%
Undervoltage warning
threshold (PGD threshold on
VOSNS falling)
86%
84%
90%
94%
97%
VUVW
Factory default, at VOUT_COMMAND (VOC) = 1 V
Range
VOC
Resolution
1%
PGD release threshold on
VOSNS rising and
undervoltage warning de-
assertion threshold
VPGD(rise)
Factory default, at VOUT_COMMAND (VOC) = 1 V
Factory default, at VOUT_COMMAND (VOC) = 1 V
95%
PGD threshold on VOSNS
falling and overvoltage
warning de-assertion
threshold
VPGD(fall)
105%
115%
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE FAULT PROTECTION
Factory default, at
VOUT_COMMAN
D (VOC) = 1 V
Factory default, at
VOUT_COMMAND (VOC) = 1 V
Overvoltage fault threshold
Range
111%
105%
119%
140%
Factory default, at
VOUT_COMMAN
D (VOC) = 1 V
Factory default, at
VOUT_COMMAND (VOC) = 1 V
VOVF
Factory default, at
VOUT_COMMAN
D (VOC) = 1 V
Factory default, at
VOUT_COMMAND (VOC) = 1 V
Resolution
2.5%
85%
VOC
Factory default, at
Undervoltage fault threshold VOUT_COMMAN
D (VOC) = 1 V
Factory default, at
VOUT_COMMAND = 1.00 V
81%
60%
89%
95%
Factory default, at
VOUT_COMMAN
D = 1.00 V
Factory default, at
VOUT_COMMAND = 1.00 V
VUVF
Range
Factory default, at
VOUT_COMMAN
D = 1.00 V
Factory default, at
VOUT_COMMAND = 1.00 V
Resolution
2.5%
1.2
Factory default, at
VOUT_COMMAN
D (VOC) = 1 V
Fixed overvoltage fault
threshold
Factory default, at
VOUT_COMMAND = 1.00 V
1.15
1.25
VOVF(fix)OFF
V
Factory default, at
VOUT_COMMAN
D = 1.00 V
Factory default, at
VOUT_COMMAND = 1.00 V
Recovery threshold(1)
0.4
OUTPUT VOLTAGE TRIMMING
Default Resolution of VOUT_COMMAND, Trim and
Margin, VOUT_SCALE_LOOP = 0.5
1.90
2–12
1.95
2.00 mV
2 –5
VOUTRES
Programmable range(1)
V
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Factory default setting
1
mV/µs
VOUT_TRAN_
RT
Programmable range(1)
Accuracy
0.063
15.933
Output voltage transition rate
10%
–10%
Factory default setting
Programmable range, 4 discrete settings
Factory default setting
0.5
0.8
Feedback loop scaling
factor(1)
VOUT_SCL_LP
0.125
1
V
V
VOUT_SCALE_LOOP = 1 (5)
0.25
0.25
0.25
0.75
1.5
3
Output voltage programmable
values
VOUT_SCALE_LOOP = 0.5
VOUT_CMD
Programmable
range
VOUT_SCALE_LOOP = 0.25(5)
VOUT_SCALE_LOOP =
0.125(5)
0.25
6
TEMPERATURE SENSE AND THERMAL SHUTDOWN
Bandgap thermal shutdown
TSD
150
170
150
temperature(1)
Bandgap thermal shutdown
THYST
25
hysteresis(1)
Factory default setting
Internal overtemperature fault
limit(1)
OT_FLT_LMT
Programmable range
0
0
160
°C
Resolution
1
Factory default setting
Programmable range
Resolution
125
Internal overtemperature
warning limit(1)
OT_WRN_LMT
TOT(hys)
160
25
1
Internal overtemperature
fault, warning hysteresis(1)
Factory default setting
250 mV < VOUT < 6 V
MEASUREMENT SYSTEM
Output voltage measurement
MVOUT(rng)
MVOUT(acc)
MVOUT(lsb)
MIOUT(rng)
MIOUT(acc)
MIOUT(acc)
MIOUT(acc)
MIOUT(acc)
MIOUT(acc)
MIOUT(lsb)
MPVIN(rng)
MPVIN(acc)
0
6
V
range(1)
Output voltage measurement
accuracy
2%
–2%
Output voltage measurement
bit resolution(1)
244
µV
A
Output current measurement
range(1)
60
1.8
3
–10
–1.8
–3
Output current measurement
accuracy(5)
0
0
A
I
OUT ≤10 A, TJ = 25°C
Output current measurement
accuracy(5)
A
IOUT = 20A, -40°C ≤TJ ≤150°C
IOUT = 40A, -40°C ≤TJ ≤150°C
IOUT = 20A, 0°C ≤TJ ≤85°C
IOUT = 40A, 0°C ≤TJ ≤85°C
Output current measurement
accuracy(5)
0
4
A
–4
Output current measurement
accuracy(5)
0
2.5
3
A
–2.5
–3
Output current measurement
accuracy(5)
0
A
Output current measurement
bit resolution(1)
2–6
A
Input voltage measurement
range(1)
0
20
3
V
Input voltage measurement
accuracy
4 V< PVIN < 20 V
%
–3
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage measurement
bit resolution(1)
MPVIN(lsb)
MTSNS(acc)
MTSNS(lsb)
2–6
V
Internal temperature sense
accuracy(5)
3
–40°C ≤TJ ≤150°C
–3
°C
Internal temperature sense bit
resolution(1)
0.25
PMBUS INTERFACE + BCX
High-level input voltage on
VIH(PMBUS)
PMB_CLK, PMB_DATA,
BCX_CLK, BCX_DAT
1.35
V
Low-level input voltage on
PMB_CLK, PMB_DATA,
BCX_CLK, BCX_DAT
VIL(PMBUS)
0.8
Input high level current into
PMB_CLK, PMB_DATA
IlH(PMBUS)
IIL(PMBUS)
10
10
–10
–10
μA
μA
Input low level current into
PMB_CLK, PMB_DATA
Output low level votlage on
PMB_DATA, SMB_ALRT,
BCX_DAT
VAVIN > 4.5 V, input current to PMB_DATA,
SMB_ALRT, BCX_DAT = 20 mA
VOL(PMBUS)
0.4
10
V
Output high level open drain
leakage current into
IOH(PMBUS)
Voltage on PMB_DATA, SMB_ALRT = 5.5 V
μA
PMB_DATA, SMB_ALRT
Output low level open drain
sinking current on
PMB_DATA, SMB_ALRT,
BCX_DAT
Voltage on PMB_DATA, SMB_ALRT, BCX_DAT =
0.4 V
IOL(PMBUS)
20
10
mA
PMBus operating frequency
range
fPMBUS_CLK
GOSNS = AGND
Vpin = 0.1V to 1.35V
–40°C to 150°C
1000 kHz
PMBUS_CLK &
CPMBUS
PMBUS_DATA pin input
5
pF
capactiance(1)
Number of NVM writeable
cycles(1)
NWR_NVM
1000
cycle
ms
Maximum Allowable Clock
Stretch(1)
tCLK_STCH(max)
6
(1) Specified by design. Not production tested.
(2) The parameter covers 2.95 V to 18 V of AVIN.
(3) The setting of TON_RISE and TOFF_FALL of 0 ms means the unit to bring its output voltage to the programmed regulation value of
down to 0 as quickly as possible, which results in an effective TON_RISE and TOFF_FALL time of 0.5 ms (fastest time supported).
(4) The setting of TON_MAX_FAULT_LIMIT and TOFF_MAX_WARN_LIMIT of 0 means disabling TON_MAX_FAULT and
TOFF_MAX_WARN response and reporting completely.
(5) Not production tested. Specified by correlation. AVIN = PVIN = 12 V, VOUT = 1 V fsw = 325kHz L = 320nH
Copyright © 2023 Texas Instruments Incorporated
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6.6 Typical Characteristics
VPIN = VAVIN = 12 V, TA = 25°C, fsw = 325 kHz (unless otherwise specified). Safe operating area curves were measured using
a Texas Instruments evaluation module (EVM).
105
100
95
90
85
80
75
70
65
60
55
50
105
100
95
90
85
80
75
70
65
60
55
50
Nat conv
100 LFM
200 LFM
400 LFM
Nat conv
100 LFM
200 LFM
400 LFM
10
15
20
25
Phase Current (A)
30
35
40
45
50
10
15
20
25
Phase Current (A)
30
35
40
45
50
D001
D002
VIN = 5 V
fSW = 325 kHz
VOUT = 1 V
L = 300 nH
VIN = 5 V
VOUT = 1 V
L = 300 nH
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
fSW = 550 kHz
图6-1. TPS546D24S Safe Operating Area
图6-2. TPS546D24S Safe Operating Area
105
105
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
Nat conv
100 LFM
200 LFM
400 LFM
Nat conv
100 LFM
200 LFM
400 LFM
10
15
20
25
Phase Current (A)
30
35
40
45
50
10
15
20
25
Phase Current (A)
30
35
40
45
50
D003
D004
VIN = 12 V
VOUT = 1 V
L = 300 nH
VIN = 12 V
VOUT = 1 V
L = 300 nH
Snubber = 1 nF + 1Ω
RBOOT = 0 Ω
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
fSW = 325 kHz
fSW = 550 kHz
图6-3. TPS546D24S Safe Operating Area
图6-4. TPS546D24S Safe Operating Area
105
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
100
95
90
85
80
75
70
65
60
55
50
45
40
35
Nat conv
100 LFM
200 LFM
400 LFM
Nat conv
100 LFM
200 LFM
400 LFM
10
15
20
25
Phase Current (A)
30
35
40
45
50
10
15
20
25
Phase Current (A)
30
35
40
45
50
D005
D006
VIN = 12 V
VOUT = 3.3 V
L = 300nH
VIN = 12 V
VOUT = 3.3 V
L = 300 nH
Snubber = 1 nF + 1Ω
RBOOT = 0 Ω
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
fSW = 325 kHz
fSW = 550 kHz
图6-5. TPS546D24S Safe Operating Area
图6-6. TPS546D24S Safe Operating Area
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6.6 Typical Characteristics (continued)
VPIN = VAVIN = 12 V, TA = 25°C, fsw = 325 kHz (unless otherwise specified). Safe operating area curves were measured using
a Texas Instruments evaluation module (EVM).
110
100
90
110
100
90
80
70
60
50
40
30
20
80
70
60
50
Nat conv
100 LFM
200 LFM
400 LFM
Nat conv
100 LFM
200 LFM
400 LFM
40
30
10
15
20
25
Phase Current (A)
30
35
40
45
50
10
15
20
25
Phase Current (A)
30
35
40
45
50
D007
D008
VIN = 12 V
VOUT = 5 V
L = 300 nH
VIN = 12 V
VOUT = 5 V
L = 300 nH
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
fSW = 325 kHz
fSW = 550 kHz
图6-7. TPS546D24S Safe Operating Area
图6-8. TPS546D24S Safe Operating Area
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
0.8V
1.0V
1.2V
3.3V
0.8V
1.0V
1.2V
3.3V
0
5
10
15
Load Current (A)
20
25
30
35
40
0
5
10
15
Load Current (A)
20
25
30
35
40
D009
D010
VIN = 5 V
fSW = 325 kHz
L = 300 nH
VIN = 5 V
fSW = 550 kHz
L = 300 nH
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
Snubber = 1 nF + 1 Ω
RDCR = 0.15 mΩ
RDCR = 0.15 mΩ RBOOT = 0 Ω
图6-9. TPS546D24S Efficiency vs Output Current
图6-10. TPS546D24S Efficiency vs Output Current
100
95
90
85
80
100
95
90
85
80
75
75
0.8V
1.0V
1.2V
3.3V
5.0V
0.8V
1.0V
1.2V
3.3V
5.0V
70
70
65
60
65
60
0
5
10
15
Load Current (A)
20
25
30
35
40
0
5
10
15
Load Current (A)
20
25
30
35
40
D011
D012
VIN = 12 V
L = 300 nH
VIN = 12 V
L = 300 nH
Snubber = 1 nF + 1
Ω
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
fSW = 325 kHz
RDCR = 0.15 mΩ
fSW = 550 kHz
RDCR = 0.15 mΩ
RBOOT = 0 Ω
图6-11. TPS546D24S Efficiency vs Output Current
图6-12. TPS546D24S Efficiency vs Output Current
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6.6 Typical Characteristics (continued)
VPIN = VAVIN = 12 V, TA = 25°C, fsw = 325 kHz (unless otherwise specified). Safe operating area curves were measured using
a Texas Instruments evaluation module (EVM).
9
1.65
8.5
1.55
8
1.45
7.5
1.35
1.25
1.15
1.05
0.95
0.85
7
6.5
6
5.5
5
Vgate
3.0V
4.5V
Vgate = 3.0V
Vgate = 4.5V
4.5
4
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D013
D014
图6-13. Low-Side MOSFET On-Resistance (RDS(on)
)
图6-14. High-Side MOSFET On-Resistance (RDS(on)
)
vs Junction Temperature
vs Junction Temperature
1.003
1.002
1.001
1
700
650
600
550
500
450
400
350
300
0.999
0.998
325kHz
550kHz
250
200
VOUT = 1.00V
0.997
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D015
D016
VOUT_COMMAND = 1 V
图6-15. Output Voltage vs Junction Temperature
图6-16. Switching Frequency
vs Junction Temperature
13.8
13.6
13.4
13.2
13
4.75
4.725
4.7
12.8
12.6
12.4
12.2
12
4.675
11.8
4.65
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D017
D018
IVDD5 = 10 mA
VPVIN = VAVIN= 12 V
图6-17. Non-Switching Input Current (IAVIN
)
图6-18. VDD5 Voltage vs Junction Temperature
vs Junction Temperature
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6.6 Typical Characteristics (continued)
VPIN = VAVIN = 12 V, TA = 25°C, fsw = 325 kHz (unless otherwise specified). Safe operating area curves were measured using
a Texas Instruments evaluation module (EVM).
1.55
1.525
1.5
2.9
2.85
2.8
2.75
2.7
1.475
2.65
1.45
2.6
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D023
D019
IBP1V5 = 2 mA
VPVIN = VAVIN= 12 V
(35h) VIN_ON = 2.75 V
图6-19. BP1V5 Voltage vs Junction Temperature
图6-20. Turnon Voltage vs Junction Temperature
2.65
1.1
2.6
2.55
2.5
1.05
1
2.45
2.4
0.95
ON
OFF
2.35
-40 -20
0.9
-40 -20
0
20
40
60
80 100 120 140 160
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D020
D021
图6-22. EN/UVLO Thresholds vs Junction Temperature
(36h) VIN_OFF = 2.5 V
图6-21. Turnoff Voltage vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS546D24S uses a fixed-frequency, proprietary current-mode control. The switching frequency can be
selected from pre-set values through pin-strapping and PMBus programming. The output voltage is sensed
through a true differential remote sense amplifier and internal resistor divider, then compared to an internal
voltage reference by an error amplifier. An internal oscillator initiates the turn-on of the high-side power switch.
The error amplifier output is buffered and shared through VSHARE among stacked devices. This shared voltage
is compared to the sensed switch node current to drive a linear voltage ramp modulator with input voltage,
output voltage, and switching frequency feedforward to regulate the average switch-node current. As a
synchronous buck converter, the device normally works in continuous conduction mode (CCM) under all load
conditions. The compensation components are integrated into the TPS546D24S devices, and programmable
through the PMBus command (B1h) USER_DATA_01 (COMPENSATION_CONFIG) or with the external pin
MSEL1 to select pre-set values based on switching frequency and output LC filters.
7.2 Functional Block Diagram
SYNC
MSEL2
BP1V5
VDD5
EN/UVLO AVIN PVIN
Auto-detection/
PMBus
SYNC
_IN
Linear
Regulators
Decoder
(SS, OC, Phase
Count)
SYNC_
OUT
UVLO
PLL
BOOT
BP1V8
To
Infrastructure
Oscillator
PVIN
Driver
Control
PWM
Decoder
(Fsw, Comp)
SW
MSEL1
VSEL
Anti-Cross-
Conduction
On-Time
Generator
VDD5
MSEL2/PMBus
Pre-Bias
Decoder
(Vref, Divider
Ratio)
Soft-Start
DAC
PGND
Output Current
Sensing
IMON
AGND
To Infrastructure and
Selectable Divider Ratio
R1
VSHARE
Error Amplifier with
Internal Compensation
VOSNS
+
Fault
Management
VMON and
R2
VOUT/UV/OV
Detection
OV/UV
TMON
ADC, PMBus Interface, Back Channel
Interface, Memory
GOSNS/FLWR
RESET Vout
Die Temp
Sensing
Decoder
(Addr, PH Pos,
Det SYNC in/out)
Follower
Detection
PGD/RST_B
SMB_ALRT
PMB_DATA BCX_CLK
BCX_DAT
DRTN
PMB_CLK
ADRSEL
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7.3 Feature Description
7.3.1 Average Current-Mode Control
The TPS546D24S device uses an average current-mode control architecture with independently programmable
current error integration and voltage error integration loops. This architecture provides similar performance to
peak current-mode control without restricting the minimum on-time or minimum-off time control, allowing the gain
selection of the current loop to effectively set the slope compensation. For help selecting compensation values,
customers can use the TPS546x24S Compensation and Pin-Strap Resistor Calculator design tool.
Voltage Feed Forward and Frequency Se ng
Voltage Feed Forward
Remote Sense with Internal
Resistor Divider
Switching Frequency
Voltage Regula on Error Ampli er w/
Internal Type-II Compensator
VO_SNS
High-Bandwidth Average
Unity Gain
Current Mode Control
Ampli er w/ Internal
Compensa on
Remote
Sense Amp
Voltage Error
Amp
Sensed
GMV
+
VOUT
ꢀ VOUT err
-
S
R
Q
Q
Icntrl
GMI
PWM
+
ꢀ IL err
+
+
-
Vcntrl
RVV
VREF
GND_SNS
RVI
TON
Generator
I_SNS
Current Error
Amp
CPI
Start
CZV
CPV
CZI
High-Frequency, Low Ji er
On-Time Modulator
Common Internal Ground for Regula on
PLL Synchronizable
PWM_CLK_EDGE
VSHARE
Regula on and Current Share Loop for
Stackability
图7-1. Average Current Mode Control Block Diagram
7.3.1.1 On-Time Modulator
The input voltage feedforward modulator converts the integrated current error signal, ILerr, into an inductor on-
time that provides a controlled volt-second balance across the inductor over each full switching period that
simplifies the current error integration loop design. The modulator produces a full-cycle averaged small signal
Vcntrl to dIL/dt transfer function given by 方程式1:
dIL
VIN
dt
dVcntrl Vramp
1
L
5.5
L
=
ì
=
(1)
Thus the inductor current modulator gain is given by 方程式2:
dIL
VIN
1
5.5
ƒ =
( )
ì
=
dVcntrl
Vramp L ì ƒ L ì ƒ
(2)
This natural integration 1/f function allows the current loop to be compensated by the mid-band gain of the error
current integrator.
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7.3.1.2 Current Error Integrator
The current error integrator adjusts the modulator control voltage to match the sensed inductor current, Isns, to
the current voltage at the VSHARE pin. The integrator is tuned through the GMI, RVI, CZI, CPI, and CZI_MUL
parameters in (B1h) USER_DATA_01 (COMPENSATION_CONFIG). Thanks to the natural integration of the 1/f
function of the current control gain, the bandwidth of the current control loop can be adjusted with the mid-band
gain of the integrator, GMI × RVI.
The current loop crossover occurs at the frequency when the full loop gain is equal to 1 according to 方程式3:
VPVIN
1
ILOOP ƒ ì
( )
ìCSA ì
= 1
V
1.7 ì pì ƒ ìL
ramp
(3)
Solving for the mid-band gain of the current loop, you find 方程式4:
V
1.7
ramp
ILOOPMB = GMIìRVI =
ì
ìL ì pì ƒcoi
VPVIN CSA
(4)
While Nyquist Theorem suggests that a bandwidth of ½ fSW is possible, inductor tolerances and phase delays in
the current sense, modulator, and H-bridge power FETs make fSW/4 a more practical target, which simplifies the
target current loop midband gain to achieve a current loop bandwidth of fSW/4 to 方程式5:
V
ƒsw
1.7
1.7ìp
4ì5.5ì6.155ì10-3
ramp
ILOOPMB = GMIìRVI =
ì
ìLìpì
=
ìLìƒsw = 39.4ìLìƒsw
VPVIN CSA
4
(5)
An integrator from DC to the low-frequency zero, RVI × CZI, compensates for the valley voltage of the modulator
ramp and the nominal offset of the output voltage. A high-frequency filter pole, RVI × CPI between half the
switching frequency and the switching frequency reduces high-frequency noise from VSHARE and minimizes
pulse-width jitter.
To avoid loop interactions, the integrating zero frequency must be below the voltage loop cross-over frequency,
while the high-frequency pole must be between ½ the switching frequency and the switching frequency to limit
high-frequency noise and jitter in the current loop without imposing additional phase loss in the voltage loop.
The closed loop average current mode control allows the current sense amplifier, on-time modulator, H-bridge
power FETs, and inductor to operate as a transconductance amplifier with forward gain of 1/CSA or 162.5 A/V
with a bandwidth equal to Fcoi.
7.3.1.3 Voltage Error Integrator
The voltage error integrator regulates the output voltage by adjusting the current control voltage, VSHARE,
similar to any current mode control architecture. A transconductance amplifier compares the sense feedback
voltage to a programmed reference voltage to set the current control voltage VSHARE to maintain the desired
output voltage. While a regulated current source feeding an output capacitance provides a natural, stable
integrator, mid-band gain is often desired to improve the loop bandwidth and transient response.
With a transconductance set by the current sense gain, the voltage loop cross-over occurs when the full loop
gain equal 1 according to 方程式6.
1
VOUT _SCALE_LOOPì VLOOP ƒ ì
( )
ì ZOUT ƒ = 1
( )
CSA
(6)
To prevent the current integration loop bandwdith from negatively impacting the phase margin of the voltage
loop, the voltage loop must have a target bandwidth of Fcoi / 2.5. With a current mode loop of fSW/4, the voltage
loop mid-band gain must be 方程式7:
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1
CSA
VLOOPMB = GMV ì RVV =
ì
f
VOUT _SCALE_LOOP
’
≈
SW
ZOUT
∆
÷
◊
10
«
(7)
An integrator pole is necessary to maintain accurate DC regulation, and the zero-frequency set by RVV × CZV
must be set below the lowest cross-over frequency with the largest output capacitor intended to be supported at
the output, but not more than 1/2 the target voltage loop crossover frequency fcov
.
A high frequency noise pole, intended to keep switching noise out of the current loop must also be employed,
with a high-frequency pole set by RVV × CPV must be set between fsw/4 and fsw.
For pin programmed options of compensation components, see 表7-9.
For PMBus programming of compensation values, see (B1h) USER_DATA_01 (COMPENSATION_CONFIG).
7.3.2 Linear Regulators
The TPS546D24S devices have three internal linear regulators receiving power from AVIN and providing
suitable bias (1.5 V, 1.8 V, and 5 V) for the internal circuitry of the device. External bypass pins for VDD5 and
BP1V5 must be bypassed to their respective grounds for the converter to function properly. BP1V5 requires a
minimum of 1 μF of capacitance connected to DRTN. VDD5 requires a minimum 4.7 μF of capacitance
connected to PGND. After AVIN, 1.5-V, 1.8-V, and 5-V reach their respective UVLOs, the device initiates a
power-on reset, after which the device can be communicated with through PMBus for configuration and users
can store defaults to the NVM.
The VDD5 has internally fixed undervoltage lockout of 3.9 V (typical) to enable power-stage conversion. The
VDD5 regulator can also be fed by external supply to reduce internal power dissipation and improve efficiency by
eliminating the loss in the internal LDO, or to allow operation with AVIN less than 4 V. The external supply must
be higher voltage than the LDO regulation voltage programmed by (B5h) USER_DATA_05
(POWER_STAGE_CONFIG).
Place bypass capacitors as close as possible to the device pins, with a minimum return loop back to their
respective ground. Keep the return loop away from fast switching voltage and the main current path — see the
layout for details. Poor bypassing can degrade the performance of the regulator.
The use of the internal regulators to power other circuits is not recommended because the loads placed on the
regulators can adversely affect operation of the controller.
7.3.3 AVIN and PVIN Pins
The device allows for a variety of applications by using the AVIN and PVIN pins together or separately. The AVIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the switching power stage. When connected to a single supply, the input voltage for AVIN and PVIN can range
from 4 V to 16 V. If the PVIN is connected to separate supply from AVIN, the PVIN voltage can be 2.95 V to 16 V,
and AVIN has to meet 4-V minimum and 18-V maximum to drive the control and driver. If AVIN is connected to
the same supply as PVIN or VDD5, TI recommends a minimum 10-µs R-C filter with a 1-Ωto 10-Ωresistor and
AVIN bypass capacitor between AVIN and PVIN to reduce PVIN switching noise on the AVIN input.
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2.95 V œ 16 V
PVIN
VDD5
PGND
4.25 V œ 18 V
AVIN
AGND
图7-2. TPS546D24S Separate PVIN and AVIN Connections
2.95 V œ 16 V
PVIN
VDD5
PGND
4 V œ 5.25 V
AVIN
AGND
图7-3. TPS546D24S Separate PVIN and AVIN Connections with VDD5
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2.95 V œ 16 V
PVIN
4.75 V œ 5.25 V
VDD5
PGND
2.95 V œ 18 V
or PVIN
AVIN
AGND
图7-4. TPS546D24S Separate PVIN, AVIN, and VDD5 Connections
7.3.4 Input Undervoltage Lockout (UVLO)
The TPS546D24S provides four independent UVLO functions for the broadest range of flexibility in start-up
control. While only the fixed AVIN UVLO is required to enable PMBus connectivity as well as VOUT and
TEMPERATURE monitoring, all four UVLO functions must be met before switching can be enabled.
7.3.4.1 Fixed AVIN UVLO
The TPS546D24S has internally fixed UVLO of 2.5 V (typical) on AVIN to enable the digital core and initiate
power on reset, including pin detection. The off-threshold on AVIN is 2.3 V (typical).
7.3.4.2 Fixed VDD5 UVLO
The TPS546D24S has an internally fixed UVLO of 3.9 V (typical) on VDD5 to enable drivers and output voltage
conversion. The off-threshold on VDD5 is 3.5 V.
7.3.4.3 Programmable PVIN UVLO
Two PMBus commands ((35h) VIN_ON and (36h) VIN_OFF) allow the user to set PVIN voltage turn-on and turn-
off thresholds independently, with 0.25-V resolution from 2.75 V to 15.75 V (6-bit) for (35h) VIN_ON and from 2.5
V to 15.5 V (6-bit) for (36h) VIN_OFF.
备注
If (36h) VIN_OFF is programmed higher than (35h) VIN_ON, the TPS546D24S rapidly switches
between enabled and disabled while PVIN remains below (36h) VIN_OFF. Propagation delays
between enable and disable can result in the converter starting (61h) TON_RISE and (65h)
TOFF_FALL in such conditions.
7.3.4.4 EN/UVLO Pin
The TPS546D24S also offers a precise threshold and hysteresis current source on the EN/UVLO pin so that it
can be used to program an additional UVLO to any external voltage greater than 1.05 V (typ.), including AVIN,
PVIN, or VDD5. For an added level of flexibility, the EN/UVLO pin can be disabled or its logic inverted through
the PMBUS Command (02h) ON_OFF_CONFIG, which allows the pin to be connected to AGND to ensure the
output is not enabled until PMBus programming has been completed.
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PVIN
Ihys
EN/UVLO
CNTRL
AGND
图7-5. TPS546D24S UVLO Voltage Divider
7.3.5 Start-Up and Shutdown
The start-up and shutdown of the device is controlled by several PMBus programmable values including:
• (01h) OPERATION
• (02h) ON_OFF_CONFIG
• (60h) TON_DELAY
• (61h) TON_RISE
• (64h) TOFF_DELAY
• (65h) TOFF_FALL
With the default (02h) ON_OFF_CONFIG settings, the timing is as shown in 图 7-6. See the Supported PMBus
Commands for full details on the implementation.
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CNTRL
VDD5_OK
PVIN_OK
VOUT
TON_DELAY
TON_RISE
TOFF_DELAY
TOFF_FALL
图7-6. TPS546D24S Start-up and Shutdown
备注
The TPS546D24S requires time between the AVIN and VDD5 reaching their UVLO levels for pin-
detection and PMBus Communication and valid sensing of EN/UVLO and PVIN_OK. After AVIN and
VDD5 exceed their lower UVLO thresholds (2.9-V typ.), the TPS546D24S starts its power-on-reset,
self-calibration, and pin-detection. This time delay, tdelay(uvlo_PMBus) (8 ms typical) must be complete
before PVIN_OK or EN/UVLO sensing is enabled.
If VDD5PS_ON, PVIN_OK, and EN/UVLO are above their thresholds before the end of tdelay(uvlo_PMBus)
,
(60h) TON_DELAY starts after tdelay(uvlo_PMBus) completes.
If VDD5PS_ON, PVIN_OK, or EN/UVLO are below their thresholds when tdelay(uvlo_PMBus) completes,
(60h) TON_DELAY starts when VDD5_OK, PVIN_OK, and EN/UVLO are all above their thresholds.
7.3.6 Differential Sense Amplifier and Feedback Divider
The TPS546D24S includes a fully integrated, internal, precision feedback divider and remote sense. Using both
the selectable feedback divider and precision adjustable reference, output voltages up to 6.0 V can be obtained.
The feedback divider can be programmed to divider ratios of 1:1, 1:2, 1:4, or 1:8 using the (29h)
VOUT_SCALE_LOOP command.
The recommended operating range of (21h) VOUT_COMMAND is dependent upon the feedback divider ratio
configured (29h) VOUT_SCALE_LOOP as follows:
表7-1. (29h) VOUT_SCALE_LOOP and (21h)
VOUT_COMMAND Recommended Range
RECOMMENDED VOUT
VOUT_SCALE_LOOP
RANGE (V)
1
0.25 to 0.75
0.5 to 1.5
1 to 3
0.5
0.25
0.125
2 to 6
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Setting (21h) VOUT_COMMAND lower than the recommended range can negatively affect VOUT regulation
accuracy while setting (21h) VOUT_COMMAND above the recommended range can limit the actual output
voltage achieved.
备注
If the regulation output voltage is limited by the recommended range of the current (29h)
VOUT_SCALE_LOOP value, VOUT can be below the intended (43h) VOUT_UV_WARN_LIMIT or
(44h) VOUT_UV_FAULT_LIMIT without triggering their respective warning or faults due to the limited
range of the reference voltage.
7.3.7 Set Output Voltage and Adaptive Voltage Scaling (AVS)
The initial output voltage can be set by the VSEL pin at AVIN power up. As part of power-on reset (POR), the
VSEL pin senses both the resistance from the VSEL pin to AGND and the divider ratio of the VSEL pin between
B1V5 and AGND. These values program (29h) VOUT_SCALE_LOOP, (21h) VOUT_COMMAND, (2Bh)
VOUT_MIN, and (24h) VOUT_MAX and select the appropriate settings for the internal feedback divider and
precision adjustable reference voltage. After the TPS546D24S completes its POR and enables PMBus
communication, these initial values can be changed through PMBus communication.
• (20h) VOUT_MODE
• (21h) VOUT_COMMAND
• (29h) VOUT_SCALE_LOOP
• (22h) VOUT_TRIM
• (25h) VOUT_MARGIN_HIGH
• (26h) VOUT_MARGIN_LOW
• (01h) OPERATION
• (02h) ON_OFF_CONFIG
The output voltage can be programmed through PMBus and its value is related to the following registers:
• (24h) VOUT_MAX
• (2Bh) VOUT_MIN
• (40h) VOUT_OV_FAULT_LIMIT
• (42h) VOUT_OV_WARN_LIMIT
• (43h) VOUT_UV_WARN_LIMIT
• (44h) VOUT_UV_FAULT_LIMIT
The TPS546D24S defaults to the relative format for the following, but can be changed to use absolute format
through the PMBus command (20h) VOUT_MODE:
• (25h) VOUT_MARGIN_HIGH
• (26h) VOUT_MARGIN_LOW
• (40h) VOUT_OV_FAULT_LIMIT
• (42h) VOUT_OV_WARN_LIMIT
• (43h) VOUT_UV_WARN_LIMIT
• (44h) VOUT_UV_FAULT_LIMIT
Refer to the detailed description of (20h) VOUT_MODE for details.
7.3.7.1 Reset Output Voltage
The (21h) VOUT_COMMAND value and the corresponding output voltage can be reset to the last selected
power-on reset value set by VSEL or EEPROM as selected in the (EEh) MFR_SPECIFIC_30
(PIN_DETECT_OVERRIDE) command when the PGD/RST_B pin function is set to RESET# in the (EDh)
MFR_SPECIFIC_29 (MISC_OPTIONS) PMBus command. To reset (21h) VOUT_COMMAND to its last Power-
On Reset value, when the RESET# optional function is enabled, assert the PGD/RST_B pin low externally.
While RESET# is asserted low, (21h) VOUT_COMMAND values received through PMBus is ACKed but no
change in (21h) VOUT_COMMAND is made. When RESET# is selected in (EDh) MFR_SPECIFIC_29
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(MISC_OPTIONS), an internal pullup on the PGD/RST_B pin can be selected by the PULLUP# bit in the same
PMBus command to eliminate the need for an external pullup with the RESET# function.
PGD/
RST_B
Boot VOUT (VSEL or NVM)
Pre-AVS VOUT
VOUT
Slew Rate set by
VOUT_TRANSITION_RATE
AVS by
VOUT_COMMAND
RST_B Response Delay
图7-7. TPS546D24S Output Voltage Reset
7.3.7.2 Soft Start
To control the inrush current needed to charge the output capacitor bank during start-up, the TPS546D24S
implements a soft-start time programmed by the (61h) TON_RISE command. When the device is enabled, the
reference voltage ramps from 0 V to the final level defined by the following at a slew rate defined by the (61h)
TON_RISE command:
• (21h) VOUT_COMMAND
• (29h) VOUT_SCALE_LOOP
• (22h) VOUT_TRIM
• (25h) VOUT_MARGIN_HIGH
• (26h) VOUT_MARGIN_LOW
• (01h) OPERATION
The TPS546D24S devices support several soft-start times from 0 ms to 31.75 ms in 250-µs steps (7 bits)
selected by the (61h) TON_RISE command. The tON_RISE time is selectable by pin-strapping through the MSEL2
pin (eight options), PMBus programming, or both.
During soft start, when the PWM pulse width is shorter than the minimum controllable on-time, pulse skipping
can be seen and the output can show larger ripple voltage than normal operation.
7.3.8 Prebiased Output Start-Up
The TPS546D24S limits current from being discharged from a pre-biased output voltage during start-up by
preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side
FET. After the increasing reference voltage exceeds VOSNS voltage and high-side SW pulses start, the
TPS546D24S limits the synchronous rectification during each SW period with a narrow on-time. The maximum
low-side MOSFET on-time slowly increases on a cycle-by-cycle basis until 128 switch periods have elapsed and
the synchronous rectifier runs fully complementary to the high-side MOSFET. This limits the sinking of current
from a pre-biased output, and ensures the output voltage start-up and ramp-to regulation sequences are
monotonically increasing.
In the event of a pre-biased output voltage greater than (40h) VOUT_OV_FAULT_LIMIT, the TPS546D24S
responds as soon as it completes POR and VDD5 is greater than its own 3.9-V UVLO, even if conversion is
disabled by EN/UVLO or the PMBus (01h) OPERATION command.
7.3.9 Soft Stop and (65h) TOFF_FALL Command
When enabled by (02h) ON_OFF_CONFIG or (01h) OPERATION, the TPS546D24S implements (65h)
TOFF_FALL command to force a controlled decrease of the output voltage from regulation to 0. There can be
negative inductor current forced during the (65h) TOFF_FALL time to discharge the output voltage. The setting
of (65h) TOFF_FALL of 0 ms means the unit to bring its output voltage down to 0 as quickly as possible, which
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results in an effective (65h) TOFF_FALL time of 0.5 ms. When disabled in the (02h) ON_OFF_CONFIG for the
turnoff controlled by EN/UVLO pin or bit 6 of (01h) OPERATION if the regulator is turned off by (01h)
OPERATION command, both high-side and low-side FET drivers are turned off immediately and the output
voltage slew rate is controlled by the discharge from the external load.
This feature is disabled for EN/UVLO in (02h) ON_OFF_CONFIG by default.
7.3.10 Power Good (PGOOD)
When conversion is enabled and tON_RISE complete, if the output voltage remains between (43h)
VOUT_UV_WARN_LIMIT and (42h) VOUT_OV_WARN_LIMIT, the PGOOD open-drain output is released and
allowed to rise to an externally supplied logic level. Upon any fault condition with a shutdown response, the
PGOOD open-drain output is asserted, forcing PGOOD low by default. See 表 7-4 for the possible sources to
pull down the PGOOD pin.
The PGOOD signal can be connected to the EN/UVLO pin of another device to provide additional controlled
turnon and turnoff sequencing.
7.3.11 Set Switching Frequency
An internal oscillator generates a 225-kHz to 1.5-MHz clock for PWM switching with 16 discrete programmable
options. The switching frequency is selectable by pin-strapping through the resistor divider of MSEL1 (8 options),
PMBus programming (16 options), or both, using the (33h) FREQUENCY_SWITCH command, listed in 表7-2.
表7-2. Oscillator fSW Options
AVAILABLE fSW OPTIONS (kHz)
fSW PIN-STRAPPING OPTIONS (kHz)
225
275
325
375
450
550
650
750
900
1100
1300
1500
275
325
450
550
650
900
1100
1500
7.3.12 Frequency Synchronization
The oscillator can be synchronized to external clock (SYNC IN) or output a clock to synchronize other devices
(SYNC out) on the SYNC pin. To support phase shifted clock for both multi-rail interleaving and multi-phase
operation, the internal oscillator can be phase-shifted from the SYNC pin by 0, 90, 120, 180, 240, or 270
degrees for 1, 2, 3, or 4 phase operation. The SYNC IN or SYNC OUT function, and phase position of single
phase or stand-alone devices can be selected by pin-strapping through resistor divider on at the ADRSEL pin, or
by the resistor from the MSEL2 pin to AGND for multi-phase loop follower devices.
In single output multi-phase stack configurations, the SYNC phase offset is programmed along with device count
and phase position using the MSEL2 pin. Loop follower devices in multi-phase stacks are always configured as
SYNC_IN while the loop controller device can be configured for auto-detect, SYNC_IN, or SYNC_OUT through
the resistor divider on the ADRSEL pin.
表7-3. Pin Programmed Phase Positions through ADRSEL Resistor Divider (Single Phase Stand-Alone)
RDIV CODE
Open (no resistor to BP1V5)
0, 1
PHASE POSITION (DEGREE)
SYNC IN, OUT
Auto-detect in, out
In
0
0
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表7-3. Pin Programmed Phase Positions through ADRSEL Resistor Divider (Single Phase Stand-Alone)
(continued)
RDIV CODE
2, 3
PHASE POSITION (DEGREE)
SYNC IN, OUT
90
120
180
240
270
0
In
In
4, 5
6, 7
In
8, 9
In
10,11
12, 13
14, 15
In
Out
Out
180
After initial power up and pin detection, if SYNC IN/OUT is set as auto-detection configuration, the TPS546D24S
senses the SYNC pin to determine if there is any external SYNC clock. Switching or a consistent pullup on the
SYNC pin sets the device for SYNC_IN while a consistent pulldown on SYNC sets the device for SYNC_OUT.
The TPS546D24S devices programmed to be loop followers are always programmed to be SYNC IN.
When configured for SYNC_IN, if SYNC input pulses are missed for two cycles, or the oscillator frequency drops
below 50% of the free-running switching frequency, the device determines that SYNC clock is lost. If the
TPS546D24S is part of a multi-phase stack, the converter shuts down and remains disabled until a SYNC signal
is reestablished to prevent damage due to the loss of synchronization. Single phase stand-alone devices
continues to operate at approximately 50% of the nominal frequency.
7.3.13 Loop Follower Detection
The GOSNS/FLWR pin voltage is detected at power up. When it is pulled high to BP1V5, the device is
recognized as loop follower. When the GOSNS/FLWR pin is connected to the Output Ground, the TPS546D24S
is configured as a loop controller.
7.3.14 Current Sensing and Sharing
Both high-side and low-side FET use a SenseFET architecture for current sensing to achieve accurate and
temperature compensated current monitoring. This SenseFET architecture uses the parasitic resistance of the
FETs to achieve lossless current sense with no external components.
When multiple (2×, 3×, or 4×) devices operate in multi-phase application, all devices share the same internal
control voltage through VSHARE pin. The sensed current in each phase is regulated by the VSHARE voltage by
internal transconductance amplifier, to achieve loop compensation and current balancing between different
phases. The amplifier output voltage is compared with an internal PWM ramp to generate the PWM pulse.
7.3.15 Telemetry
The telemetry sub-system in the controller core supports direct measurements of input voltage, output voltage,
output current, and die temperature. The ADC supports internal rolling window averaging with rolling windows up
to 16 previous measurements for accurate measurements of these key system parameters. Each ADC
conversion requires less than 500 µs, allowing each telemetry value to be updated within 2 ms.
The current sense telemetry, which senses the low-side FET current at the start and end of each low-side FET
on-time and averages the two measurements to monitor the average inductor current over-report current if the
inductor current is non-linear during the low-side FET on-time, such as when the inductor is operating above its
saturation current.
7.3.16 Overcurrent Protection
Both low-side overcurrent (OC) and high-side short circuit protection are implemented.
The low-side overcurrent fault and warning thresholds are programmed through PMBus and sensed across
cycle-by-cycle average current through the low-side MOSFET and compared to the set warning or fault threshold
while High-side pulses are terminated on a cycle-by-cycle basis, if the peak current through the high-side
MOSFET exceeds the 1.5× the programmed low-side threshold.
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When either a low-side overcurrent or high-side short circuit threshold is exceeded during a switching cycle, an
OCP fault counter is incremented. If no overcurrent condition is detected in a switching cycle, the counter is
decremented. If the counter exceeds the delay selected by the (47h) IOUT_OC_FAULT_RESPONSE PMBus
value (default = 3) overcurrent fault condition is declared and the output shuts down. Restart and timing is also
defined as part of (47h) IOUT_OC_FAULT_RESPONSE.
The output OC fault thresholds and fault response are set through PMBUS. The OC fault response can be set to
shutdown, restart, or ignore.
7.3.17 Overvoltage/Undervoltage Protection
The voltage on VOSNS pin is monitored to provide output voltage overvoltage (OV) and undervoltage (UV)
protection. When VOSNS voltage is higher than OV fault threshold, OV fault is declared and the low-side FET is
turned on to discharge the output voltage and eliminate the OV condition. The low-side FET remains on until the
VOSNS voltage is discharged to 200 mV divided by the internal feedback divider as programmed by (29h)
VOUT_SCALE_LOOP. After the output voltage is discharged, the output is disabled and the converter times out
and restarts according to the (41h) VOUT_OV_FAULT_RESPONSE PMBus command. When VOSNS voltage is
lower than UV fault threshold, UV fault is declared. After an initial delay programmed by the (45h)
VOUT_UV_FAULT_RESPONSE PMBus command, the output is disabled and the converter times out and
restarts according to the (45h) VOUT_UV_FAULT_RESPONSE PMBus command.
The output UV/OV fault thresholds and fault response are set through PMBUS. The UV/OV fault response can
be set to shutdown, restart, or continue operating without interruption.
7.3.18 Overtemperature Management
There are two schemes of overtemperature protections in the TPS546D24S device:
1. On-chip die temperature sensor for monitoring and overtemperature protection (OTP)
2. The bandgap based thermal shutdown (TSD) protection. TSD provides OT fail-safe protection in the event of
a failure of the temperature telemetry system, but can be disabled through (50h) OT_FAULT_RESPONSE
for high temperature testing
The overtemperature protection (OTP) threshold is set through PMBus and compares the (8Dh)
READ_TEMPERATURE_1 telemetry to the (51h) OT_WARN_LIMIT and (4Fh) OT_FAULT_LIMIT. The
overtemperature (OT) fault response can be set to shutdown, restart, or continue operating without interruption.
7.3.19 Fault Management
For the response on OC fault, OT fault, and thermal shutdown for multi-phase stack, the shutdown response has
the highest priority, followed by restart response. Continue operating without interruption response has the
lowest priority.
When multiple faults occur in rapid succession, the first fault to occur to masking the second fault is possible. If
the first fault to be detected is configured to continue operating without interruption, and the second fault is
configured to shutdown and restart, the second fault shuts down but can fail to restart as programmed.
表7-4. Fault Protection Summary
FAULT OR
WARNING
FAULT RESPONSE
ACTIVE DURING
PROGRAMMING
FET BEHAVIOR
SMB_ALRT
MASKABLE
PGOOD LOGIC
SETTING
tON_RISE
Shutdown
Restart
Ignore
Both FETs off
Low
(4Fh)
OT_FAULT_LIMIT
Internal OT fault
Internal OT warning
TSD
Both FETs off, restart
Yes
Yes
Yes
Y
Y
FETS still controlled by PWM
High
Shutdown or restart
on Fault
(51h)
OT_WARN_LIMIT
FETS still controlled by PWM
Y
Y
Y
Y
High
Ignore fault
Shutdown
Restart
Both FETs off
Low
Threshold fixed
internally
Both FETs off, restart
High
Ignore
FETS still controlled by PWM
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表7-4. Fault Protection Summary (continued)
FAULT OR
WARNING
FAULT RESPONSE
ACTIVE DURING
PROGRAMMING
FET BEHAVIOR
SMB_ALRT
MASKABLE
PGOOD LOGIC
SETTING
tON_RISE
Shutdown
3 PWM counts, then both FETs off
(46h)
IOUT_OC_FAULT_LI
MIT
Low
High
High
3 PWM counts, then both FETs
off, restart after [DELAY]*tON_RISE
Low Side OC fault
Restart
Ignore
Yes
Y
Y
FETS still controlled by PWM
Shutdown or restart
on Fault
(4Ah)
IOUT_OC_WARN_LI
MIT
Low Side OC
warning
FETS still controlled by PWM
Yes
Yes
Y
Y
Y
Y
Ignore fault
Enable
Negative OC fault
(lower priority than
OVF)
Turn off LS FET
Low
N/A
Disable
FETS still controlled by PWM
High
3 cycles of pulse-by-pulse current
limiting followed by both FETs off
Shutdown
(46h)
IOUT_OC_FAULT_LI
MIT
Low
3 cycles of pulse-by-pulse current
limiting followed by both FETs off,
restart after [DELAY]*tON_RISE
High side OC fault
Yes
Y
Y
Restart
Ignore
FETS still controlled by PWM
High
LS FET latched ON or turned on
till VOUTreaches 200 mV/
VOUT_SCALE_LOOP; HS FET
OFF
Shutdown
Restart
(40h)
VOUT_OV_FAULT_L
IMIT
Low
High
Low
LS FET latched ON or turned on
till VOUTreaches 200 mV/
VOUT_SCALE_LOOP; HS FET
OFF, restart after [DELAY] *
tON_RISE
Vout OV fault
No
Y
Y
Ignore
FETS still controlled by PWM
LS FET latched ON or turned on
till VOUTreaches 200 mV/
VOUT_SCALE_LOOP; HS FET
OFF
Shutdown
(40h)
VOUT_OV_FAULT_L
IMIT
LS FET latched ON or turned on
till VOUTreaches 200 mV/
VOUT_SCALE_LOOP; HS FET
OFF, restart after
VOUT OVF fix
Yes
Y
Y
Restart
Ignore
[DELAY]*tON_RISE
FETS still controlled by PWM
FETS still controlled by PWM
Both FETs off
High
High
Shutdown or restart
on Fault
(42h)
VOUT_OV_WARN_L
IMIT
Vout OV warning
Vout UV fault
No
No
No
Y
Y
Y
Y
Y
Y
Ignore Fault
Shutdown
(44h)
VOUT_UV_FAULT_L
IMIT
Low
High
Low
Both FETs off , restart after
[DELAY]*tON_RISE
Restart
Ignore
FETS still controlled by PWM
FETS still controlled by PWM
Both FETs off
Shutdown or restart
on Fault
(43h)
VOUT_UV_WARN_L
IMIT
Vout UV warning
Ignore fault
Shutdown
(62h)
TON_MAX_FAULT_L
IMIT
Low
Both FETs off, restart after
[DELAY]*tON_RISE
tON MAX rault
PVin UVLO
Restart
Ignore
Yes
Yes
Y
Y
Y
Y
FETS still controlled by PWM
Both FETs off
High
Low
(35h) VIN_ON, (36h)
VIN_OFF
Shutdown
Shutdown
Restart
Ignore
Both FETs off
(55h)
VIN_OV_FAULT_LIM
IT
Low
PVIN OV FAULT
BCX_fault
Both FETs off, restart
Yes
Yes
Y
Y
Y
Y
FETS still controlled by PWM
FETS still controlled by PWM
High
High
N/A
N/A
N/A
N/A
VSEL
MSEL1
MSEL2
ADRSEL
Pin_Strap_NonConv
erge
No (active before
Both FETs off, pull low VSHARE
N
N
N/A
N/A
Low
tON_RISE
)
SYNC_Fault
Loop controller or
stand-alone device
Yes
High
Low
FETS still controlled by PWM
Loop follower device
Both FETs off, pull low VSHARE
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表7-4. Fault Protection Summary (continued)
FAULT OR
WARNING
FAULT RESPONSE
ACTIVE DURING
PROGRAMMING
FET BEHAVIOR
SMB_ALRT
MASKABLE
N/A
PGOOD LOGIC
SETTING
tON_RISE
SYNC_High/Low
N/A
Loop controller or
stand-alone device
Yes
N
High
Low
FETS still controlled by PWM
Loop follower device
Both FETs off, pull low VSHARE
7.3.20 Back-Channel Communication
To allow multiple devices with a shared output to communicate through a single PMBus address and single
PMBus loop follower, the TPS546D24S uses a back-channel communication implemented through BCX_CLK
and BCX_DAT pins. During POR, all of the devices connected to VSHARE must also be connected to BCX_CLK
and BCX_DAT and have appropriate (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) settings. Any programming
error among the devices of a stack results in a POR fault and prevent enabling of conversion.
During POR, the loop controller reads the programmed values from the loop followers to ensure all expected
loop followers are present and correctly phase-shifted. Then, the loop controller loads critical operating
parameters such as the following to the loop follower devices to ensure correct operation of the STACK:
• (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
• (33h) FREQUENCY_SWITCH
• (61h) TON_RISE
• (21h) VOUT_COMMAND
During operation, the loop controller device receives and responds to all PMBus communication, and loop
follower devices do not need to be connected to the PMBus. If the loop controller receives commands that
require updates to the PMBus registers of the loop follower, the loop controller relays these commands to the
loop followers. Additionally, the loop controller periodically polls loop follower devices for status and telemetry
information to maintain an accurate record of the telemetry and STATUS information for the full stack of devices.
Most PMBus communication must be directed to all phases by leaving the (04h) PHASE PMBus command at its
Power On Reset default value of FFh. If a specific device must be communicated with, the (04h) PHASE
command can be changed to address a specific device within the stack, as set by the order value of the (37h)
INTERLEAVE command programmed during POR.
When commands are directed to individual loop followers, write commands are queued by the loop controller to
be sent to the loop followers through the BCX if other BCX communication is in progress. Queued write
commands are written to the loop followers in the order the loop controller receives them. To avoid unnecessary
delays on the PMBus and excessive clock stretching, read transactions targeting individual loop followers are not
queued, and are processed as soon as the BCX bus is available. As a result, it is possible for a read command
targeting an individual loop follower immediately following a write command can be processed before the
preceding write command. To ensure accurate read-back, users must allow a minimum of 4 ms between writing
a value to an individual loop follower and reading that same value back from the same loop follower.
7.3.21 Switching Node (SW)
The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the
highside gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally
traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the
output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency (> 100
MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the
input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the
pin.
In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND
can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber
network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the
SW pin exceeds the limit, then include snubber components.
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7.3.22 PMBus General Description
Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power
Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The TPS546D24S device
supports both the 100-kHz, 400-kHz, and 1-MHz bus timing requirements.
The TPS546D24S uses clock stretching during PMBus communication, but only stretches the clock during
specific bits of the transaction.
• The TPS546D24S does not stretch the clock during the address byte of any transaction.
• The TPS546D24S can stretch the clock between bit 0 of the command byte and its ACK response.
• The TPS546D24S stretches the clock after bit 0 of the read address of a read transaction.
• The TPS546D24S stretches the clock between bit 0 of the last byte of data and its ACK response
• The TPS546D24S can stretch the clock between bit 1 and bit zero of every fourth byte of data for blocks with
more than four bytes of data.
Communication over the PMBus interface can either support the packet error checking (PEC) scheme or not. If
the loop controller supplies clock (CLK) pulses for the PEC byte, PEC is used. If the CLK pulses are not present
before a STOP, the PEC is not used. If PEC is always used, consider enabling Require PEC in (EDh)
MFR_SPECIFIC_29 (MISC_OPTIONS) to configure the TPS546D24S to reject any write transaction that does
not include CLK pulses for a PEC byte.
The device supports a subset of the commands in the PMBus 1.3 Power Management Protocol Specification.
See Supported PMBus Commands for more information
The TPS546D24S also supports the SMB_ALERT response protocol. The SMB_ALERT response protocol is a
mechanism by which the TPS546D24S can alert the bus loop controller that it has experienced an alert and has
important information for the host. The host must process this event and simultaneously accesses all loop
followers on the bus that support the protocol through the alert response address. All loop followers that are
asserting SMB_ALERT must acknowledge this request with their PMBus Address. The host performs a modified
receive byte operation to get the address of the loop follower. At this point, the loop controller can use the
PMBus status commands to query the loop follower that caused the alert. For more information on the SMBus
alert response protocol, see the system management bus (SMBus) specification. Persistent faults associated
with status registers other than (7Eh) STATUS_CML reassert SMB_ALERT after responding to the host alert
response address.
The TPS546D24S contains non-volatile memory that is used to store configuration settings and scale factors.
The settings programmed into the device are not automatically saved into this non-volatile memory. The (15h)
STORE_USER_ALL command must be used to commit the current PMBus settings to non-volatile memory as
device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed
descriptions.
All pin programmable values can be committed to non-volatile memory. The POR default selection between pin
programmable values and non-volatile memory can be selected by the manufacturer specific (EEh)
MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) command.
7.3.23 PMBus Address
The PMBus specification requires that each device connected to the PMBus have a unique address on the bus.
The TPS546D24S PMBus address is determined by the value of the resistor connected between ADRSEL and
AGND and is programmable over the range from 0x10 –0x2F, providing 32 unique PMBus addresses.
7.3.24 PMBus Connections
The TPS546D24S supports the 100-kHz, 400-kHz, and 1-MHz bus speeds. Connection for the PMBus interface
must follow the high power DC specifications given in section 3.1.3 in the SMBus specification V2.0 for the 400-
kHz bus speed or the low power DC specifications in section 3.1.2. The complete SMBus specification is
available from the SMBus web site, smiforum.org
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The PMBus interface pins: PMB_CLK, PMB_DATA, and SMB_ALRT require external pullup resistors to a 1.8-V
to 5.5-V termination. Pullup resistors must be sized to meet the minimize rise-time required for the desired
PMBus clock speed but must not source more current than the lowest rated CLK, DATA, or SMB_ALRT pin on
the bus when the bus voltage is forced to 0.4 V. The TPS546D24S supports a minimum of 20 mA of sink current
on PMB_CLK, PMB_DATA, and SMB_ALRT.
7.4 Device Functional Modes
7.4.1 Programming Mode
The TPS546D24S devices can operate in programming mode when AVIN and VDD5 are powered above their
lower UVLO but VDD5 and PVIN are not powered above their UVLO to enable conversion. In programing mode,
the TPS546D24S accepts and responds to PMBus commands but does not enable switching or conversion.
While PMBus commands can be accepted and processed with VDD5 lower than 3 V, NVM programming through
the (15h) STORE_USER_ALL command must not be used when VDD5 is less than 3 V.
Programming mode allows the TPS546D24S to complete POR and to be configured through PMBus from a 3.3-
V supply without PVIN present.
7.4.2 Standalone, Loop Controller, Loop Follower Mode Pin Connections
The TPS546D24S can be programmed as a standalone device (Single Output, Single Phase) loop controller
device of a single-output multi-phase stack of devices, or a loop follower device to a loop controller of a mult-
phase stack. The details of the recommended pin connects for each configuration is given in 表7-5.
表7-5. Standalone, Loop Controller, Loop Follower Pin Connections
PIN
STANDALONE
LOOP CONTROLLER
LOOP FOLLOWER
GOSNS
Ground at Output Regulation Point
Ground at Output Regulation Point
BP1V5
Float or connect to divider for other
voltage to be monitored
VOSNS
Vout at Output Regulation Point
Vout at Output Regulation Point
Enable/Control or Resistor Divider
from PVIN
Enable/Control or Resistor Divider
from PVIN
Connect to EN/UVLO of the loop
controller
EN/UVLO
MSEL1
Programming MSEL1
Programming MSEL1
Short to PGND (Thermal Pad)
Programming MSEL2 for a Loop
Follower Device (GOSNS Tied to
BP1V5)
MSEL2
Programming MSEL2
Programming MSEL2
VSEL
Programming VSEL
Programming VSEL
Short to PGND (Thermal Pad)
Short to PGND (Thermal Pad)
ADRSEL
Programming ADRSEL
Programming ADRSEL
Float or Bypass to AGND with
capacitor
Connect to VSHARE of the loop
follower
Connect to VSHARE of the loop
controller
VSHARE
SYNC
Float or External Sync
External Sync or loop follower SYNC Connect to SYNC of the loop controller
Connect to System PMBus or PGND
(Thermal Pad) if not used
Connect to System PMBus or PGND
Short to PGND (Thermal Pad)
(Thermal Pad) if not used
PMB_CLK
Connect to System PMBus or PGND
(Thermal Pad) if not used
Connect to System PMBus or PGND
Short to PGND (Thermal Pad)
(Thermal Pad) if not used
PMB_DATA
SMB_ALRT
BCX_CLK
Connect to System PMBus or PGND
(Thermal Pad) if not used
Connect to System PMBus or PGND
Short to PGND (Thermal Pad)
(Thermal Pad) if not used
Connect to BCX_CLK of the loop
Short to PGND (Thermal Pad)
Short to PGND (Thermal Pad)
Connect to loop followers BCX_CLK
controller
Connect to BCX_DAT of the loop
BCX_DAT
Connect to loop followers BCX_DAT
controller
Connect to System PGD or RESET#
or PGND (Thermal Pad) if not used
Connect to System PGD or RESET#
Short to PGND (Thermal Pad)
PGOOD/RST_B
or PGND (Thermal Pad) if not used
7.4.3 Continuous Conduction Mode
The TPS546D24S devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the
output current. During soft start, some of the low-side MOSFET on-times are limited to prevent excessive current
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sinking in the event the device is started with a prebiased output. After the first PWM pulse, and with each
successive PWM pulse, this limit is increased to allow more low-side FET on-time and transition to CCM. After
this transition has completed, the low-side MOSFET and the high-side MOSFET on-times are fully
complementary.
7.4.4 Operation With CNTL Signal (EN/UVLO)
According to the value in the (02h) ON_OFF_CONFIG register, the TPS546D24S devices can be commanded to
use the EN/UVLO pin to enable or disable regulation, regardless of the state of the (01h) OPERATION
command. The EN/UVLO pin can be configured as either active high or active low (inverted) logic. To use EN/
UVLO pin as a programmable UVLO, the polarity set by (02h) ON_OFF_CONFIG must be positive logic.
7.4.5 Operation with (01h) OPERATION Control
According to the value in the (02h) ON_OFF_CONFIG register, the TPS546D24S devices can be commanded to
use the (01h) OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.
7.4.6 Operation with CNTL and (01h) OPERATION Control
According to the value in the (02h) ON_OFF_CONFIG command, the TPS546D24S devices can be commanded
to require both a CNTRL signal from the EN/UVLO pin, and the (01h) OPERATION command to enable or
disable regulation.
7.5 Programming
7.5.1 Supported PMBus Commands
The commands listed in 表 7-6 are implemented as described to conform to the PMBus 1.3 specification. 表 7-6
also lists the default for the bit behavior and register values.
表7-6. Supported PMBus Commands and Default Values
CMD CODE (HEX)
COMMAND NAME (PMBus 1.3 SPEC)
DEFAULT VALUE
01h
02h
03h
04h
10h
15h
16h
19h
1Bh
20h
21h
22h
24h
25h
26h
27h
29h
2Bh
33h
35h
36h
37h
38h
OPERATION
04h
ON_OFF_CONFIG
CLEAR_FAULTS
PHASE
17h
n/a
FFh
WRITE_PROTECT
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
00h
n/a
n/a
D0h
SMBALERT_MASK
VOUT_MODE
n/a
97h
VOUT_COMMAND
VOUT_TRIM
019Ah
0000h
0C00h
021Ah
01E6h
E010h
C840h
0100h
01C2h
F00Bh
F00Ah
0020h
C880h
VOUT_MAX
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_TRANSITION_RATE
VOUT_SCALE_LOOP
VOUT_MIN
FREQUENCY_SWITCH
VIN_ON
VIN_OFF
INTERLEAVE
IOUT_CAL_GAIN
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表7-6. Supported PMBus Commands and Default Values (continued)
CMD CODE (HEX)
COMMAND NAME (PMBus 1.3 SPEC)
IOUT_CAL_OFFSET
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_LIMIT
IOUT_OC_FAULT_RESPONSE
IOUT_OC_WARN_LIMIT
OT_FAULT_LIMIT
DEFAULT VALUE
39h
E000h
024Dh
BDh
40h
41h
42h
022Eh
01CCh
01B2h
BEh
43h
44h
45h
46h
F0D0h
FFh
47h
4Ah
4Fh
50h
F0A0h
0096h
BCh
OT_FAULT_RESPONSE
OT_WARN_LIMIT
51h
007Dh
0015
55h
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_UV_WARN_LIMIT
TON_DELAY
56h
3Ch
58h
F00Ah
F800h
F00Ch
F800h
3Bh
60h
61h
TON_RISE
62h
TON_MAX_FAULIT_LIMIT
TON_MAX_FAULT_RESPONSE
TOFF_DELAY
63h
64h
F800h
F002h
00h
65h
TOFF_FALL
78h
STATUS_BYTE
79h
STATUS_WORD
00h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
80h
STATUS_VOUT
00h
STATUS_IOUT
00h
STATUS_INPUT
00h
STATUS_TEMPERATURE
STATUS_CML
00h
00h
STATUS_OTHER
00h
STATUS_MFR_SPECIFIC
READ_VIN
00h
88h
n/a
8Bh
8Ch
8Dh
98h
READ_VOUT
n/a
READ_IOUT
n/a
READ_TEMPERATURE_1
PMBUS_REVISION
n/a
33h
99h
MFR_ID
00 00 00h
00 00 00h
00 00 00h
00 00 00h
54 49 54 6D 24 62h
41 00h
22 18 C2 1D 06h
70h
9Ah
9Bh
9Eh
ADh
AEh
B1h
B5h
D0h
MFR_MODEL
MFR_REVISION
MFR_SERIAL
IC_DEVICE_ID
IC_DEVICE_REV
USER_DATA_01 (COMPENSATION_CONFIG)
USER_DATA_05 (POWER_STAGE_CONFIG)
MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
03 03 03 03 03 00h
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表7-6. Supported PMBus Commands and Default Values (continued)
CMD CODE (HEX)
COMMAND NAME (PMBus 1.3 SPEC)
DEFAULT VALUE
DAh
DBh
E4h
ECh
EDh
EEh
EFh
F0h
F1h
FAh
FBh
FCh
FDh
MFR_SPECIFIC_10 (READ_ALL)
n/a
n/a
MFR_SPECIFIC_11 (STATUS_ALL)
MFR_SPECIFIC_20 (SYNC_CONFIG)
MFR_SPECIFIC_28 (STACK_CONFIG)
MFR_SPECIFIC_29 (MISC_OPTIONS)
MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
MFR_SPECIFIC_31 (DEVICE_ADDRESS)
MFR_SPECIFIC_32 (NVM_CHECKSUM)
MFR_SPECIFIC_33 (SIMULATE FAULTS)
MFR_SPECIFIC_42 (PASSKEY)
F0h
0000h
0000h
1F2Fh
24h
E9E0h
0000h
0000h
MFR_SPECIFIC_43 (EXT_WRITE_PROTECT)
MFR_SPECIFIC_44 (FUSION_ID0)
0000h
02C0h
54 49 4C 4F 43 4Bh
MFR_SPECIFIC_45 (FUSION_ID1)
7.5.2 Pin Strapping
The TPS546D24S provides four IC pins that allow the initial PMBus programming value on critical PMBus
commands to be selected by the resistors connected to that pin without requiring PMBus communication.
Whether a specific PMBus command is initialized to the value selected by the detected resistance or stored
NVM memory is determined by the commands bit in the PIN_DETECT_OVERRIDE PMBus Command. The four
pins and the commands they program for a loop controller or Stand-alone device (GOSNS connected to Ground)
are provided in 表7-7.
Each pin can be programmed in one of four ways:
• Pin shorted to AGND with less than 20 Ω
• Pin floating or tied to BP1V5 with more than 1 MΩ
• Pin bypassed to AGND through a resistor according to R2G code only (16 Resistor Options)
• Pin bypassed to AGND through a resistor according to R2G code and to BP1V5 according to Divider Code
(16 Resistor x 16 Resistor Divider Options)
Due to the flexibility of programming options with up to 274 configurations per pin, it is recommended that
designers consider using one of the available design tools, such as TPS546x24S Compensation and Pin-Strap
Resistor Calculator to assist with proper programming resistor selection.
表7-7. TPS546D24S Pin Programming Summary
PIN
RESISTORS
PMBus REGISTERS
MSEL1
MSEL2
Resistor to AGND
COMPENSATION_CONFIG
Resistor Divider
Resistor to AGND
Resistor Divider
Both
COMPENSATION_CONFIG, FREQUENCY_SWITCH
IOUT_OC_WARN_LIMIT, IOUT_OC_FAULT_LIMIT, STACK_CONFIG
TON_RISE
VSEL
VOUT_COMMAND, VOUT_SCALE_LOOP, VOUT_MAX, VOUT_MIN
DEVICE_ADDRESS
ADRSEL
Resistor to AGND
Resistor Divider
DEVICE_ADDRESS, SYNC_CONFIG, INTERLEAVE
备注
Resistor divider values of "none" can be implemented with no resistor to BP1V5 or use a 1-MΩ
resistor to BP1V5 for improved reliability and noise immunity.
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Loop follower with GOSNS tied to BP1V5 only use the resistor from MSEL2 to AGND to program the following:
• (4Ah) IOUT_OC_WARN_LIMIT
• (46h) IOUT_OC_FAULT_LIMIT
• (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
• (37h) INTERLEAVE
The loop follower receives all other pin programmed values from the loop controller over BCX as part of the
power-on reset function.
备注
The high precision Pin-Detection programming which provides 8-bit resolution for each pin in the
TPS546D24S can be sensitive to PCB contamination from flux, moisture, and debris. As such, users
must consider committing Pin Programmed values to User Non-Volatile memory and disable future
use of Pin Strapped values as part of the product flow. The programming sequence to commit Pin
Programmed PMBus register values to NVM and disable future use of Pin Strapped programming is:
• Select MSEL1, MSEL2, VSEL and ADRSEL programming resistors to program the desired PMBus
register values.
• Power AVIN and VDD5 above their UVLOs to initiate pin detection and enable PMBus
communication.
• Update any PMBus register values not programmed to their final value by Pin Detection.
• Write the value 0000h using the Write Word protocol to (EEh) MFR_SPECIFIC_30
(PIN_DETECT_OVERRIDE).
• Send the command code 15h using the Send Byte protocol to initialize a (15h)
STORE_USER_ALL function.
• Allow a minimum 100 ms for the device to complete a burn of NVM User Store. Loss of AVIN or
VDD5 power during this 100 ms can compromise the integrity of the NVM. Failure to complete the
NVM burn can result in a corruption of NVM and a POR fault on subsequent power on resets.
7.5.2.1 Programming MSEL1
The
MSEL1
pin
programs
(B1h)
USER_DATA_01
(COMPENSATION_CONFIG)
and
(33h)
FREQUENCY_SWITCH. The resistor divider ratio for MSEL1 selects the nominal switching frequency using 表
7-8:
表7-8. MSEL1 Divider Code for Programming
RESISTOR
DIVIDER
CODE
COMPENSATION_CONFIG (CONFIG #)
FREQUENCY_SWITCH VALUE (kHz)
None (No
Resistor to
BP1V5)
7 - 25 (Select Values)
550
0
1
2
3
4
5
6
7
8
9
0-15
16-31
0-15
275
325
450
550
650
16-31
0-15
16-31
0-15
16-31
0-15
16-31
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表7-8. MSEL1 Divider Code for Programming (continued)
RESISTOR
DIVIDER
CODE
COMPENSATION_CONFIG (CONFIG #)
FREQUENCY_SWITCH VALUE (kHz)
10
11
12
13
14
15
0-15
16-31
0-15
900
1100
1500
16-31
0-15
16-31
The resistor to ground for MSEL1 selects the (B1h) USER_DATA_01 (COMPENSATION_CONFIG) values to
program the following voltage loop and current loop gains. For options other than the EEPROM code (MSEL1
shorted to AGND or MSEL1 to AGND resistor code 0), the Current and Voltage loop zero and pole frequencies
are scaled with the programmed switching frequency. The current loop pole frequency is located at
approximately the switching frequency, while the current loop zero is located at approximately 1/20 the switching
frequency. The voltage loop pole is located at approximately ½ the switching frequency and the voltage loop
zero is located at approximately 1/100 the switching frequency.
表7-9. MSEL1 Resistor to AGND Code with no Divider Programming
COMPENSATION (NO DIVIDER)
COMPENSATION (EVEN DIVIDER)
COMPENSATION (ODD DIVIDER)
RESISTOR
CODE
I LOOP
GAIN
V LOOP
GAIN
I LOOP
GAIN
V LOOP
GAIN
I LOOP
GAIN
V LOOP
GAIN
CONFIG #
CONFIG #
CONFIG #
Short
Float
0
3
2
2
N/A
N/A
0
N/A
N/A
N/A
N/A
16
17
18
19
20
21
22
23
24
25
26
27
28
20
30
31
N/A
N/A
5
N/A
N/A
0.5
1
EEPROM
EEPROM
EEPROM
N/A
N/A
7
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
EEPROM
EEPROM
1
8
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
0.5
1
5
2
9
2
5
2
3
10
12
13
14
15
17
18
19
20
22
23
24
25
3
2
5
4
4
4
4
5
8
5
5
8
6
0.5
1
6
6
0.5
1
6
7
7
6
2
8
8
2
6
4
9
9
4
6
8
10
11
12
13
14
15
10
11
12
13
14
15
8
7
0.5
1
0.5
1
7
7
2
2
7
4
4
7
8
8
10
2
With both the resistor to ground code and the resistor divider code, use the look-up table to select the
appropriate resistors.
7.5.2.2 Programming MSEL2
The resistor divider on MSEL2 pin programs the (61h) TON_RISE value to select the soft-start time used by the
TPS546D24S.
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表7-10. MSEL2 Divider Code for Programming
RESISTOR DIVIDER CODE
TON_RISE VALUE (ms)
None (No Resistor to BP1V5)
Short to AGND
3
Float
0
1
2
3
4
5
6
7
0.5
1
3
5
7
10
20
31.75
The resistor to ground for MSEL2 selects the (4Ah) IOUT_OC_WARN_LIMIT, (46h) IOUT_OC_FAULT_LIMIT,
and (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) values using 表7-11.
表7-11. MSEL2 Resistor to AGND Code for IOUT_OC_WARN/FAULT_LIMIT and
STACK Programming
RESISTOR TO
AGND CODE
STACK_CONFIG(NUMBER OF
LOOP FOLLWOERS / # OF
PHASES)
OC_WARN (A) / OC_FAULT (A)
Short
0000h (0 loop followers, Stand-
alone)
40/52
40/52
Float
0
0001h (1 loop follower, 2-phase)
0000h (0 loop followers, Stand-
alone)
1
2
3
4
0001h (1 loop follower, 2-phase)
0002h (2 loop followers, 3-phase)
0003h (3 loop followers, 4-phase)
40/52
30/39
20/26
10/14
0000h (0 loop followers, Stand-
alone)
5
6
7
8
0001h (1 loop follower, 2-phase)
0002h (2 loop followers, 3-phase)
0003h (3 loop followers, 4-phase)
0000h (0 loop followers, Stand-
alone)
9
0001h (1 loop follower, 2-phase)
0002h (2 loop followers, 3-phase)
0003h (3 loop followers, 4-phase)
10
11
12
0000h (0 loop followers, Stand-
alone)
13
14
15
0001h (1 loop follower, 2-phase)
0002h (2 loop followers, 3-phase)
0003h (3 loop followers, 4-phase)
7.5.2.3 Programming VSEL
The resistor divider ratio for VSEL programs the (21h) VOUT_COMMAND range, (29h) VOUT_SCALE_LOOP
divider, (2Bh) VOUT_MIN, and (24h) VOUT_MAX levels according to the following tables.
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Select the resistor divider code that contains the desired nominal boot voltage within the range of VOUT between
minimum VOUT and maximum VOUT. For voltages from 0.5 V to 1.25 V, a single resistor to ground or a resistor
divider can be used.
表7-12. VSEL Resistor Divider Code for Programming
NOMINAL BOOT VOLTAGE RANGE
RESISTOR DIVIDER
CODE
MINIMUM VOUT
MAXIMUM VOUT
RESOLUTION
EEPROM (0.8V)
EEPROM (0.8V)
N/A
Float
None
0
0.5
0.6
0.75
0.9
1.05
1.2
1.5
1.8
2.1
2.4
3.0
3.6
4.2
3.6
4.2
4.8
5.4
1.25
0.75
0.9
1.05
1.2
1.5
1.8
2.1
2.4
3.0
3.6
4.2
4.8
4.2
4.8
5.4
6.0
0.050
0.010
0.010
0.010
0.010
0.020
0.020
0.020
0.020
0.040
0.040
0.040
0.040
0.040
0.040
0.040
0.040
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
With the resistor divider code selected for the range of VOUT, select the bottom resistor code with the (21h)
VOUT_COMMAND Offset and (21h) VOUT_COMMAND step from Programming VSEL.
表7-13. VSEL Resistor to AGND Code for Programming
RESISTOR DIVIDER VOUT_SCALE
VOUT_MIN
VOUT_MAX
VOUT_COMMAND
VOUT_COMMAND STEP (V)
CODE
_LOOP
OFFSET (V)
0.5
EEPROM (0.5)
EEPROM (1.5)
EEPROM
(0.80)
1.0
Short to AGND
N/A
Float
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
1.5
1.5
1.5
1.5
1.5
1.5
3
N/A
None
0
0.50
0.6
0.050
0.010
0.010
0.010
0.010
0.020
0.020
0.020
0.020
0.040
0.040
0.040
0.040
0.040
0.5
1
0.5
0.75
0.9
2
0.5
3
0.5
1.05
1.2
4
0.25
0.25
0.25
0.25
0.125
0.125
0.125
0.125
0.125
5
1
3
1.5
6
1
3
1.8
7
1
3
2.1
8
2
6
2.4
9
2
6
3.0
10
11
12
2
6
3.6
2
6
4.2
2
6
3.6
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表7-13. VSEL Resistor to AGND Code for Programming (continued)
RESISTOR DIVIDER VOUT_SCALE
VOUT_MIN
VOUT_MAX
VOUT_COMMAND
VOUT_COMMAND STEP (V)
CODE
_LOOP
0.125
0.125
0.125
OFFSET (V)
13
2
2
2
6
6
6
4.2
4.8
5.4
0.040
0.040
0.040
14
15
To calculate the resistor to AGND code, subtract the (21h) VOUT_COMMAND offset from the target output
voltage and divide by the (21h) VOUT_COMMAND step.
VOUT - VOUT_COMMAND(Offset)
Code =
VOUT _COMMAND(Step)
(8)
7.5.2.4 Programming ADRSEL
The resistor divider for the ADRSEL pin selects the range of PMBus Addresses and SYNC direction for the
TPS546D24S. For Stand Alone devices with only one device supporting a single output voltage, the ADRSEL
divider also selects the Phase Shift between SYNC and the switch node.
表7-14. ADRSEL Resistor Divider Code for and SYNC_IN Programming
RESISTOR DIVIDER
CODE
DEVICE_ADDRESS
SYNC IN / SYNC OUT
STACK_CONFIG = 0x0000 (STAND-ALONE
ONLY)
Range
0x7F (127d)
EEPROM (0x24h / 36d)
16d - 31d
PHASE SHIFT
INTERLEAVE
0x0020
0x0020
0x0020
0x0040
0x0040
0x0041
0x0041
0x0031
0x0031
0x0042
0x0042
0x0032
0x0032
0x0043
0x0043
0x0020
0x0020
0x0042
0x0042
—
—
Short to AGND
Auto Detect
Auto Detect
Auto detect
Sync in
0
Float
None
0
0
0
16d - 31d
0
1
32d - 47d
Sync in
0
2
16d - 31d
Sync in
90
3
32d - 47d
Sync in
90
4
16d - 31d
Sync in
120
120
180
180
240
240
270
270
0
5
32d - 47d
Sync in
6
16d - 31d
Sync in
7
32d - 47d
Sync in
8
16d - 31d
Sync in
9
32d - 47d
Sync in
10
11
12
13
14
15
16d - 31d
Sync in
32d - 47d
Sync in
16d - 31d
Sync out
Sync out
Sync out
Sync out
32d - 47d
0
16d - 31d
180
180
32d - 47d
The resistor to AGND for ADRSEL programs the device PMBus loop follower address according to 表7-15:
表7-15. ADRSEL Resistor to AGND Code for Programming
RESISTOR TO AGND CODE
DEVICE ADDRESS (16-31
RANGE)
DEVICE ADDRESS (32-47
RANGE)
0
1
2
0x10h (16d)
0x11h (17d)
0x12h (18d)
0x20h (32d)
0x21h (33d)
0x22h (34d)
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表7-15. ADRSEL Resistor to AGND Code for Programming (continued)
RESISTOR TO AGND CODE
DEVICE ADDRESS (16-31
RANGE)
DEVICE ADDRESS (32-47
RANGE)
3
4
0x13h (19d)
0x14h (20d)
0x15h (21d)
0x16h (22d)
0x17h (23d)
0x18h (24d)
0x19h (25d)
0x1Ah (26d)
0x1Bh (27d)
0x1Ch (28d)
0x1Dh (29d)
0x1Eh (30d)
0x1Fh (31d)
0x23h (35d)
0x24h (36d)
0x25h (37d)
0x26h (38d)
0x27h (39d)
0x48h (72d)
0x29h (41d)
0x2Ah (42d)
0x2Bh (43d)
0x2Ch (44d)
0x2Dh (45d)
0x2Eh (46d)
0x2Fh (47d)
5
6
7
8
9
10
11
12
13
14
15
备注
When a TPS546D24S device is configured as the loop controller of a multi-phase stack, the device
always occupies the zero-degree position in (37h) INTERLEAVE, but the ADRSEL resistor divider can
still be used to select Auto Detect, Forced SYNC_IN, and Forced SYNC_OUT. When the loop
controller of a multi-phase stack is configured for SYNC_IN, all devices of the stack remain disabled
until a valid external SYNC signal is provided.
7.5.2.5 Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5)
Configuring a TPS546D24S device as a loop follower disables all pinstraps except MSEL2, which programs
(37h)
INTERLEAVE
for
stacking
and
(ECh)
MFR_SPECIFIC_28
(STACK_CONFIG),
(4Ah)
IOUT_OC_WARN_LIMIT, and (46h) IOUT_OC_FAULT_LIMIT with a single resistor to AGND. Note that the loop
controller is always device 0.
表7-16. Loop Follower MSEL2 Resistor to AGND Code for and Programming
RESISTOR TO AGND
CODE
DEVICE NUMBER, NUMBER OF
PHASES
IOUT_OC_WARN_LIMIT (A) /
IOUT_OC_FAULT_LIMIT (A)
Short
Float
6
Device 1, 2-phase
Device 1, 2-phase
Device 1, 2-phase
Device1, 2-phase
Device 1, 3-phase
Device 1, 3-phase
Device 2, 3-phase
Device 2, 3-phase
Device 1, 4-phase
Device 1, 4-phase
Device 2, 4-phase
Device 2, 4-phase
Device 3, 4-phase
Device 3, 4-phase
40/52
30/39
40/52
30/39
40/52
30/39
40/52
30/39
40/52
30/39
40/52
30/39
40/52
30/39
7
4
5
8
9
2
3
14
15
10
11
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备注
During the power-on sequence, device 0 (stack loop controller) reads back phase information from all
connected loop followers, if any loop follower phase response does not match the (ECh)
MFR_SPECIFIC_28 (STACK_CONFIG) results of the loop controller, the converter sets the POR fault
bit in (80h) STATUS_MFR_SPECIFIC but does not allow conversion. After all connected devices
respond to Device 0, Device 0 passes remaining pin-strap information to the loop followers to ensure
matched programming during operation. Adding an additional phase requires adjusting the MSEL2
resistors on the loop controller device and the MSEL2 resistor to ground on all other loop follower
devices.
7.5.2.6 Pin-Strapping Resistor Configuration
表 7-17 and 表 7-18 provide the bottom resistor (pin to AGND) values in ohms, and the top resistor (pin to
BP1V5) values in ohms. Select the column with the desired R2G code in the top row and the row with the
desired resistor divider code in the left most column. The Pin-to-AGND resistor value is the resistor value in the
highlighted row in the first column under the desired R2G code. The Pin-to-BP1V5 resistor value, if used, is the
resistor value in the row starting with the desired divider code in the left most column under the desired R2G
code and resistor.
表7-17. Pin-Strapping Resistor (Ω) Table for R2G Codes 0-7
R2G code
0
1
2
3
4
5
6
7
4640
5620
6810
8250
10000
12100
14700
17800
Rbot →
Divider Code
Resistor to BP1V5 Value (Ω)
(↓)
0
1
21500
15400
11500
9090
7150
5620
4640
3830
3160
2610
2050
1620
1270
953
26100
18700
14000
11000
8660
6810
5620
4640
3830
3160
2490
1960
1540
1150
866
31600
22600
16900
13300
10500
8250
6810
5620
4640
3830
3010
2370
1870
1400
1050
750
38300
27400
20500
16200
12700
10000
8250
6810
5620
4640
3650
2870
2260
1690
1270
909
46400
33200
24900
19600
15400
12100
10000
8250
56200
40200
30100
23700
18700
14700
12100
10000
8250
68100
48700
36500
28700
22600
17800
14700
12100
10000
8250
82500
59000
44200
34800
27400
21500
17800
14700
12100
10000
7870
2
3
4
5
6
7
8
6810
9
5620
6810
10
11
12
13
14
15
4420
5360
6490
3480
4220
5110
6190
2740
3320
4020
4870
2050
2490
3010
3650
715
1540
1870
2260
2740
511
619
1100
1330
1620
1960
表7-18. Pin-Strapping Resistor (Ω) Table for R2G Codes 8-15
R2G code
8
9
10
11
12
13
14
15
21500
26100
31600
38300
46400
56200
68100
82500
Rbot →
Divider Code
Resistor to BP1V5 Value (Ω)
(↓)
0
1
2
3
100000
71500
53600
42200
121000
86600
64900
51100
147000
105000
78700
61900
178000
127000
95300
75000
215000
154000
115000
90900
261000
187000
140000
110000
316000
226000
169000
133000
402000
274000
205000
162000
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表7-18. Pin-Strapping Resistor (Ω) Table for R2G Codes 8-15 (continued)
4
5
33200
26100
21500
17800
14700
12100
9530
40200
31600
26100
21500
17800
14700
11500
9090
48700
38300
31600
26100
21500
17800
14000
11000
8660
59000
46400
38300
31600
26100
21500
16900
13300
10500
7870
71500
56200
46400
38300
31600
26100
20500
16200
12700
9530
86600
68100
56200
46400
38300
31600
24900
19600
15400
11500
8660
105000
82500
68100
56200
46400
38300
30100
23700
18700
14000
10500
7500
127000
100000
82500
68100
56200
46400
26500
28700
22600
16900
12700
9090
6
7
8
9
10
11
12
13
14
15
7500
5900
7150
4420
5360
6490
3320
4020
4870
5900
7150
2370
2870
3480
4220
5110
6190
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7.6 Register Maps
7.6.1 Conventions for Documenting Block Commands
According to the SMBus specification, block commands are transmitted across the PMBus interface in
ascending order. The description below shows the convention this document follows for documenting block
commands.
This document follows the convention for byte ordering of block commands:
When block values are listed as register map tables, they are listed in byte order from top to bottom starting with
Byte N and ending with Byte 0.
• Byte 0 (first byte sent) corresponds to bits 7:0.
• Byte 1 (second byte sent) corresponds to bits 15:8.
• Byte 2 (third byte sent) corresponds to bits 23:16.
• …and so on
When block values are listed as text in hexadecimal, they are listed in byte order, from left to right, starting with
Byte 0 and ending with Byte N with a space between each byte of the value. In block 54 49 54 6D 24 41h, the
byte order is:
• Byte 0, bits 7:0, = 54h
• Byte 1, bits 15:8, = 49h
• Byte 2, bits 23:16, = 6Dh
• Byte 3, bits 31:24, = 24h
• Byte 4, bits 39:32, = 41h
图7-8. Block Command Byte Ordering
47
46
45
44
43
42
41
40
RW
RW
RW
RW
RW
RW
RW
RW
Byte N
Byte …
Byte 3
Byte 2
Byte 1
Byte 0
39
38
37
36
35
34
33
32
RW
RW
RW
RW
RW
RW
RW
RW
31
30
29
28
27
26
25
24
RW
RW
RW
RW
RW
RW
RW
RW
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
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7.6.2 (01h) OPERATION
CMD Address
Write Transaction:
Read Transaction:
Format:
01h
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
No
On-the-fly
The (01h) OPERATION command is used to enable or disable power conversion, in conjunction input from the
enable pins, according to the configuration of the (02h) ON_OFF_CONFIG command. It is also used to set the
output voltage to the upper or lower MARGIN levels, and select soft-stop.
图7-9. (01h) OPERATION Register Map
7
6
5
4
3
2
1
0
R
0
RW
RW
RW
RW
RW
RW
RW
ON_OFF
SOFT_OFF
MARGIN
TRANSITION
LEGEND: R/W = Read/Write; R = Read only
表7-19. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
ON_ OFF
RW
0b
Enable/disable power conversion when the (02h) ON_OFF_CONFIG command is
configured to require input from the CMD bit for output control. Note that there can
be several other requirements that must be satisfied before the power conversion
can begin (for example, input voltages above UVLO thresholds, enable pins high if
required by (02h) ON_OFF_CONFIG and so forth).
0b: Disable power conversion.
1b: Enable power conversion and enable Ignore Faults on MARGIN.
6
SOFT_ OFF
RW
RW
0b
This bit controls the turnoff profile when (02h) ON_OFF_CONFIG is configured to
require input from the CMD bit for output voltage control and OPERATION bit 7
transitions from 1b to 0b is ignored when bit 7 is 1b.
0b: Immediate Off. Power conversion stops immediately and the power stage is
forced to a high-Z state.
1b: Soft Off. Power conversion continues for the TOFF_ DELAY time, then the
output voltage is ramped down to 0 V at a slew rate according to TOFF_ FALL.
After the output voltage reaches 0 V, power conversions stops.
5:2
MARGIN
0000b
Sets the margin state.
0000b, 0001b, 0010b: Margin OFF. Output voltage target is (21h)
VOUT_COMMAND, OV/UV faults behave normally per their respective fault
response settings 0.
0101b: Margin Low (Ignore Fault if bit 7 is 1b). Output voltage target is
VOUT_MARGIN_LOW. OV/UV faults are ignored and do not trigger shut-down or
STATUS updates.
0110b: Margin Low (Act on Fault). Output voltage target is (26h)
VOUT_MARGIN_LOW. OV/UV faults trigger per their respective fault response
settings.
1001b: Margin High (Ignore Fault). Output voltage target is VOUT_MARGIN_HIGH.
OV/UV trigger are ignored and do not trigger shut-down or STATUS update.
1010b: Margin High (Act on Fault). Output voltage target is (25h)
VOUT_MARGIN_HIGH. OV/UV trigger per their respective fault response settings.
Other: Invalid/Unsupported data
1
0
TRANSITIO
N
R
R
0b
0b
Not used and always set to 0.
Reserved
Not used and always set to 0.
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Attempts to write (01h) OPERATION to any value other than those listed above will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits, and notifying
the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.
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7.6.3 (02h) ON_OFF_CONFIG
CMD Address
Write Transaction:
Read Transaction:
Format:
02h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The (02h) ON_OFF_CONFIG command configures the combination of enable pin input and serial bus
commands needed to enable/disable power conversion. This includes how the unit responds when power is
applied to PVIN.
图7-10. (02h) ON_OFF_CONFIG Register Map
7
R
0
6
R
0
5
R
0
4
3
2
1
0
RW
PU
RW
CMD
RW
CP
RW
RW
POLARITY
DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-20. Register Field Descriptions
Bit
7:5
4
Field
Reserved
PU
Access
R
Reset
000b
NVM
Description
Not used and always set to 0.
RW
0b: Unit starts power conversion any time the input power is present regardless of
the state of the CONTROL pin.
1b: Act on CONTROL. (01h) OPERATION command to start/stop power
conversion, or both.
3
2
CMD
CP
RW
RW
NVM
NVM
0b: Ignore (01h) OPERATION Command to start/stop power conversion.
1b: Act on (01h) OPERATION Command (and CONTROL pin if configured by CP)
to start/stop power conversion.
0b: Ignore CONTROL pin to start/stop power conversion. The UVLO function of the
EN/UVLO pin is not active when CONTROL pin is ignored.
1b: Act on CONTROL pin (and (01h) OPERATION Command if configured by bit
[3]) to start/stop power conversion.
1
0
POLARITY
DELAY
RW
RW
NVM
NVM
0b: CONTROL pin has active low polarity. The UVLO function of the EN/UVLO pin
cannot be used when CONTROL has active load polarity.
1b: CONTROL pin has active high polarity.
0b: When power conversion is commanded OFF by the CONTROL pin (must be
configured to respect the CONTROL pin as above), continue regulating for the
(64h) TOFF_DELAY time, then ramp the output voltage to 0 V, in the time defined
by (65h) TOFF_FALL.
1b: When power conversion is commanded OFF by the CONTROL pin (must be
configured to respect the CONTROL pin as above), stop power conversion
immediately.
For the purposes of (02h) ON_OFF_CONFIG, the device pin EN/UVLO is the CONTROL pin.
Attempts to write (02h) ON_OFF_CONFIG to any value other than those explicitly listed above will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits, and notifying the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.
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7.6.4 (03h) CLEAR_FAULTS
CMD Address
Write Transaction:
Read Transaction:
Format:
03h
Send Byte
N/A
Data-less
Yes
Phased:
NVM Back-up:
Updates:
No
On-the-fly
CLEAR_FAULTS is a phased command used to clear any fault bits that have been set. This command
simultaneously clears all bits in all status registers of the selected phase, or all phases if PHASE = FFh. At the
same time, the device releases its SMB_ALERT# signal output if SMB_ALERT# is asserted. CLEAR_FAULTS is
a write-only command with no data.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the
fault is still present when the bit is cleared, the fault bit is immediately set again and the host is notified by the
usual means.
If the device responds to an Alert Response Address (ARA) from the host, it will clear SMB_ALERT# but not the
offending status bit or bits (as it has successfully notified the host and then expects the host to handle the
interrupt appropriately). The original fault and any from other sources that occur between the initial assertion of
SMB_ALERT# and the successful response of the device to the ARA are cleared (through CLEAR_FAULTS,
OFF-ON toggle, or power reset) before any of these sources are allowed to re-trigger SMB_ALERT#. However,
fault sources which only become active post-ARA trigger SMB_ALERT#.
图7-11. (03h) CLEAR_FAULTS Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
CLEAR_FAULTS
LEGEND: R/W = Read/Write; R = Read only
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7.6.5 (04h) PHASE
CMD Address
Write Transaction:
Read Transaction:
Format:
04h
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
No
On-the-fly
The PHASE command provides the ability to configure, control, and monitor individual phases. Each PHASE
contains the Operating Memory and User Store and Default Store for each phase output. The phase selected by
the PHASE command will be used for all subsequent phase-dependent commands. The phase configuration
needs to be established before any phase-dependent command can be successfully executed.
In the TPS546D24S, each PHASE is a separate device. The loop and PMBus loop controller device, GOSNS/
FLWR connected to ground, will always be PHASE = 00h. loop follower devices, GOSNS/FLWR connected to
BP1V5, have their phase assignment defined by their phase position, as defined by INTERLEAVE or MSEL2
图7-12. (04h) PHASE Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
PHASE
LEGEND: R/W = Read/Write; R = Read only
表7-21. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
PHASE
RW
FFh
00h: All commands address Phase 1.
01h: All commands address Phase 2.
02h: All commands address Phase 3.
03h: All commands address Phase 4.
04h-FEh: Unsupported/Invalid data
FFh: Commands are addressed to all phases as a single entity. See the following
text for more information.
The range of valid data for PHASE also depends on the phase configuration. Attempts to write (04h) PHASE to
a value not supported by the current phase configuration will be considered invalid/unsupported data and cause
the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the
PMBus 1.3.1 Part II specification, section 10.9.3.
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7.6.6 (10h) WRITE_PROTECT
CMD Address
Write Transaction:
Read Transaction:
Format:
10h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The WRITE_PROTECT command controls writing to the PMBus device. The intent of this command is to
provide protection against accidental changes; it has one data byte that is described below. This command does
NOT provide protection against deliberate or malicious changes to a configuration or operation of the device. All
supported commands can have their parameters read, regardless of the WRITE_PROTECT settings.
图7-13. (10h) WRITE_PROTECT Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
WRITE_PROTECT
LEGEND: R/W = Read/Write; R = Read only
表7-22. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:0
WRITE_
RW
NVM
00h: Enable writes to all commands.
PROTECT
20h: Disables all write access except to the WRITE_ PROTECT, OPERATION,
ON_ OFF_ CONFIG, STORE_USER_ALL, and VOUT_ COMMAND commands.
40h: Disables all WRITES except to the WRITE_ PROTECT, OPERATION, and
STORE_USER_ALL commands.
80h: Disables all WRITES except to the WRITE_ PROTECT and
STORE_USER_ALL commands.
Other: Invalid/Unsupported data
Attempts to write (10h) WRITE_PROTECT to any invalid value as specified above will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits, and notifying
the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.
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7.6.7 (15h) STORE_USER_ALL
CMD Address
Write Transaction:
Read Transaction:
Format:
15h
Send Byte
N/A
Data-less
Phased:
No, PHASE = FFh only
NVM Back-up:
Updates:
No
Not recommended for on-the-fly-use, but not explicitly blocked
The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the Operating
Memory to the matching locations in the non-volatile User Store memory. Any items in Operating Memory that do
not have matching locations in the User Store are ignored.
NVM Store operations are not recommended while the output voltages are in regulation, although the user is not
explicitly prevented from doing so, as interruption can result in a corrupted NVM. PMBus commands issued
during this time can cause long clock stretch times, or simply be ignored. TI recommends disabling regulation,
and waiting a minimum of 100 ms before continuing, following issuance of NVM store operations.
To prevent storing mismatched register values to NVM, STORE_USER_ALL must not be used unless PHASE =
FFh.
图7-14. (15h) STORE_USER_ALL Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
STORE_USER_ALL
LEGEND: R/W = Read/Write; R = Read only
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7.6.8 (16h) RESTORE_USER_ALL
CMD Address
Write Transaction:
Read Transaction:
Format:
16h
Send Byte
N/A
Data-less
Phased:
No, PHASE = FFh only
NVM Back-up:
Updates:
No
Disables Regulation during RESTORE
The RESTORE_USER_ALL command instructs the PMBus device to disable operation and copy the entire
contents of the non-volatile User Store memory to the matching locations in the Operating Memory, then
Overwrite Operating Memory of any commands selected in PIN_DETECT_OVERRIDE with their last read pin-
detected values. The values in the Operating Memory are overwritten by the value retrieved from the User Store
and Pin Detection. Any items in User Store that do not have matching locations in the Operating Memory are
ignored.
To prevent storing mismatched register values to NVM, RESTORE_USER_ALL must not be used unless PHASE
= FFh.
图7-15. (16h) RESTORE_USER_ALL Register Map
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
RESTORE_USER_ALL
LEGEND: R/W = Read/Write; R = Read only
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7.6.9 (19h) CAPABILITY
CMD Address
Write Transaction:
Read Transaction:
Format:
19h
N/A
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
No
N/A
This command provides a way for the host to determine the capabilities of this PMBus device. This command is
read-only and has one data byte formatted as below.
图7-16. (19h) CAPABILITY Register Map
7
R
6
5
4
3
2
1
R
0
0
R
0
R
R
R
R
R
PEC
SPEED
ALERT
FORMAT
AVSBUS
LEGEND: R/W = Read/Write; R = Read only
表7-23. Register Field Descriptions
Bit
7
Field
PEC
Access
Reset
Description
R
R
R
1b
1b: Packet Error Checking is supported.
10b: Maximum supported bus speed is 1 MHz.
6:5
4
SPEED
ALERT
10b
1b
1b: The device has an SMB_ALERT# pin and supports the SMBus Alert Response
Protocol.
3
2
FORMAT
AVSBUS
Reserved
R
R
R
0b
0b
0b: Numeric format is LINEAR or DIRECT.
0b: AVSBus is NOT supported.
1:0
00b
Reserved and always set to 0.
Attempts to write (19h) CAPABILITY to any value will be considered invalid/unsupported data and cause the
TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the PMBus
1.3.1 Part II specification, section 10.9.3.
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7.6.10 (1Bh) SMBALERT_MASK
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh
Write Word
Block-Write/Block-Read Process Call
Write: Unsigned Binary (2 bytes)Read: Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
The SMBALERT_MASK command can be used to prevent a warning or fault condition from asserting the
SMBALERT# signal. Setting a MASK bit does not prevent the associated bit in the STATUS_CMD from being
set, but prevents the associated bit in the STATUS_CMD from asserting SMB_ALERT#. See Reference [3] for
more information on the command format. The following register descriptions describe the individual mask bits
available.
SMBALERT_MASK Write Transaction = Write Word. CMD = 1Bh, Low =STATUS_CMD, High=MASK
SMBALERT_MASK Read Transaction = Block-Write/Block-Read Process Call. Write 1 byte block with
STATUS_CMD, read 1 byte block.
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7.6.11 (1Bh) SMBALERT_MASK_VOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Ah)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
SMBALERT_MASK bits for the STATUS_VOUT command
图7-17. (1Bh) SMBALERT_MASK_VOUT Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
R
R
mVOUT_MINM
AX
mVOUT_OVF mVOUT_OVW mVOUT_UVW mVOUT_UVF
LEGEND: R/W = Read/Write; R = Read only
mTON_MAX
0
0
表7-24. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
mVOUT_
OVF
RW
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
6
5
mVOUT_
OVW
RW
RW
RW
RW
RW
R
NVM
NVM
NVM
NVM
NVM
00b
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
mVOUT_
UVW
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
4
mVOUT_
UVF
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
3
mVOUT_
MINMAX
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
2
mTON_
MAX
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
1:0
Not
Not supported and always set to 00b.
supported
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7.6.12 (1Bh) SMBALERT_MASK_IOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Bh)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
SMBALERT_MASK bits for STATUS_IOUT
图7-18. (1Bh) SMBALERT_MASK_IOUT Register Map
7
6
R
0
5
4
3
R
0
2
R
0
1
R
0
0
R
0
RW
RW
R
mIOUT_OCF
mIOUT_OCW
mIOUT_UCF
LEGEND: R/W = Read/Write; R = Read only
表7-25. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
mIOUT_
OCF
RW
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
6
5
Not
supported
R
0b
NVM
NVM
0b
Not supported
mIOUT_
OCW
RW
RW
R
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
4
mIOUT_UC
F
1b: SMBALERT can NOT assert due to this condition.
3
Not
supported
Not supported
Not supported
2:0
Not
RW
0b
supported
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7.6.13 (1Bh) SMBALERT_MASK_INPUT
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Ch)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
SMBALERT_MASK bits for STATUS_INPUT
图7-19. (1Bh) SMBALERT_MASK_INPUT Register Map
7
6
5
4
R
0
3
2
R
0
1
R
0
0
R
0
R
0
R
0
R
0
RW
mLOW_VIN
LEGEND: R/W = Read/Write; R = Read only
表7-26. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
Not
R
0b
Not supported
supported
6
5
4
3
2
1
0
Not
supported
R
R
0b
0b
Not supported
Not supported
Not supported
Not
supported
Not
supported
R
0b
mLOW_ VIN
RW
R
NVM
0b
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
Not
supported
Not supported
Not supported
Not supported
Not
supported
R
0b
Not
R
0b
supported
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7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Dh)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
SMBALERT_MASK bits for STATUS_TEMPERATURE
图7-20. (1Bh) SMBALERT_MASK_TEMPERATURE Register Map
7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
RW
RW
mOTF
mOTW
LEGEND: R/W = Read/Write; R = Read only
表7-27. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
mOTF
RW
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
6
mOTW
RW
R
NVM
0d
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
5:0
Not
Not supported and always set to 000000b.
supported
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7.6.15 (1Bh) SMBALERT_MASK_CML
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Eh)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
No, Only PHASE = FFh is supported
EEPROM
Phased:
NVM Back-up:
Updates:
On-the-fly
SMBALERT_MASK bits for STATUS_CML
图7-21. (1Bh) SMBALERT_MASK_CML Register Map
7
6
5
4
3
2
R
0
1
0
R
0
RW
RW
RW
RW
R
RW
mIVC
mIVD
mPEC
mMEM
0
mCOMM
LEGEND: R/W = Read/Write; R = Read only
表7-28. Register Field Descriptions
Bit
Field
mIVC
Access
Reset
Description
7
6
RW
NVM
NVM
NVM
NVM
00b
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
mIVD
mPEC
mMEM
RW
RW
RW
R
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
5
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
4
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
3:2
1
Not
supported
Not supported
mCOMM
RW
R
NVM
0b
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
0
Not
Not supported
supported
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7.6.16 (1Bh) SMBALERT_MASK_OTHER
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 7Fh)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
SMBALERT_MASK bits for STATUS_OTHER
图7-22. (1Bh) SMBALERT_MASK_OTHER Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
mFIRST_
TO_ALERT
0
0
0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only
表7-29. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:1
Not
R
0h
Not supported
supported
0
mFIRST_
TO_ ALERT
R
1b
The FIRST_ TO_ ALERT bit does not in itself generate SMBALERT assertion,
hence this bit is hard-coded to 1b (source is masked).
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7.6.17 (1Bh) SMBALERT_MASK_MFR
CMD Address
Write Transaction:
Read Transaction:
Format:
1Bh (with CMD byte = 80h)
Write Word
Block-Write/Block-Read Process Call
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
SMBALERT_MASK bits for STATUS_MFR
图7-23. (1Bh) SMBALERT_MASK_MFR Register Map
7
6
5
R
0
4
R
0
3
2
1
0
R
0
RW
RW
RW
RW
RW
mPOR
mSELF
mRESET
mBCX
mSYNC
LEGEND: R/W = Read/Write; R = Read only
表7-30. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
mPOR
RW
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
6
mSELF
RW
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
Due to variations in AVIN UVLO, unmasking this bit can result in SMBALERT being
asserted on power up.
5
4
3
2
1
Not
supported
R
0b
Not supported
Not
supported
R
0b
Not supported
mRESET
RW
RW
RW
NVM
NVM
NVM
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
mBCX
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
mSYNC
0b: SMBALERT can assert due to this condition.
1b: SMBALERT can NOT assert due to this condition.
When the loop controller device of a multi-phase stack is programmed for Auto
Detect SYNC, unmasking this bit can result in a momentary assertion of
SMBALERT when the multi-phase stack is enabled.
0
Not
R
0b
Not supported
supported
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7.6.18 (20h) VOUT_MODE
CMD Address
Write Transaction:
Read Transaction:
Format:
20h
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
EEPROM
Conversion Disabled: on-the-fly, Conversion Enabled: Read Only
The data byte for the VOUT_MODE command is one byte that consists of a three bit Mode and a five bit
Parameter as shown in 图 7-24. The three bit Mode sets whether the device uses the ULINEAR16, Half-
precision IEEE 754 floating point, or VID or DIRECT modes for output voltage related commands. The five bit
Parameter provides more information about the selected mode, such as the ULINEAR16 Exponent or which
manufacturer's VID codes are being used.
图7-24. (20h) VOUT_MODE Register Map
7
6
5
4
3
2
1
0
RW
REL
R
R
RW
RW
RW
RW
RW
MODE
PARAMETER
LEGEND: R/W = Read/Write; R = Read only
表7-31. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
REL
RW
NVM
0b: Absolute Data Format
1b: Relative Data Format
6:5
4:0
MODE
R
00b
00b: Linear Format (ULINEAR16, SLINEAR16)
Other: Unsuported/Invalid
PARAMETE
R
RW
NVM
MODE = 00b (Linear Format): Specifies the exponent “N”to use with output
voltage related commands, in two’s complement format. Supported exponent
values in the linear mode range from -4 (62.5 mV/LSB) to -12 (0.244 mV/LSB).
Refer to the following text for more information.
Changing VOUT_MODE
Changing VOUT_MODE will force an update to the values of many VOUT related commands to conform to the
updated VOUT_MODE value including Relative versus Absolute mode and the linear Exponent value. When
programming VOUT_MODE in conjunction with other VOUT related commands, VOUT related commands will
be interpreted with the current VOUT_MODE value and converted if VOUT_MODE is later changed.
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7.6.19 (21h) VOUT_COMMAND
CMD Address
Write Transaction:
Read Transaction:
Format:
21h
Write Word
Read Word
ULINEAR16, Absolute Only per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM or Pin Detection
on-the-fly
VOUT_COMMAND causes the device to set its output voltage to the commanded value with two data bytes.
Output voltage changes due to VOUT_COMMAND occur at the rate specified by VOUT_TRANSITION_RATE.
When PGD/RST_B is configured as a RESET# pin in MISC_OPTIONS, assertion of the PGD/RST_B pin causes
the output voltage to return to the VBOOT value, and causes the VOUT_COMMAND value to be updated
accordingly.
图7-25. (21h) VOUT_COMMAND Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_COMMAND (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_COMMAND (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-32. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
RW
NVM
Sets the output voltage target via the PMBus interface.
COMMAND
At power up, the reset value of VOUT_COMMAND is derived from either pin-detection on the VSEL pin, or from
the NVM, depending on the VOUT_COMMAND bit in PIN_DETECT_OVERRIDE.
When the VOUT_COMMAND bit in PIN_DETECT_OVERRIDE = 0b, the default value of VOUT_COMMAND is
restored from NVM at Power On Reset or RESTORE_USER_ALL.
When the VOUT_COMMAND bit in PIN_DETECT_OVERRIDE = 1b, the default value of VOUT_COMMAND is
derived from pin-detection on the VSEL pin, at Power-On Reset or RESTORE_USER_ALL.
This default value, whether derived from pin detection, or NVM becomes the “default” output voltage (also
referred to as “VBOOT”), and is stored in RAM separately from the current value of VOUT_COMMAND.
BOOT Voltage Behavior
The RESET_FLT bit in MISC_OPTIONS selects the VOUT_COMMAND behavior following a fault-related
shutdown. When RESET_FLT = 0b, the device will retain the current value of VOUT_COMMAND during
HICCUP after a fault. When RESET_FLT = 1b, VOUT_COMMAND will reset to the last detected VSEL voltage
or the NVM STORED value for VOUT_COMMAND as selected by the VOUT_COMMAND bit in
MISC_OPTIONS.
Data Validity
Writes to VOUT_COMMAND for which the resulting value, including any offset from VOUT_TRIM is greater than
the current VOUT_MAX, or less than the current VOUT_MIN, causes the reference DAC to move to the value
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specified by VOUT_MIN or VOUT_MAX respectively, and causes the VOUT_MAX_MIN_WARNING fault
condition, setting the appropriate bits in STATUS_WORD, STATUS_VOUT and notifying the host per the PMBus
1.3.1 Part II specification, section 10.2.
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7.6.20 (22h) VOUT_TRIM
CMD Address
Write Transaction:
Read Transaction:
Format:
22h
Write Word
Read Word
SLINEAR16, Absolute Only per (20h) VOUT_MODE.
Phased:
No
NVM Back-up:
Updates:
EEPROM
on-the-fly
VOUT_TRIM is used to apply a fixed offset voltage to the output voltage command value. Output voltage
changes due to VOUT_TRIM occur at the rate specified by (27h) VOUT_TRANSITION_RATE.
图7-26. (22h) VOUT_TRIM Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_TRIM (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_TRIM (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-33. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
TRIM
RW
See Below
Output voltage offset. SLINEAR16 (two’s complement) format
Limited NVM Back-up
Only 8 bits of NVM backup are provided for this command. While the VOUT_TRIM command follows the (20h)
VOUT_MODE exponent, NVM back-up is stored with an exponent -12 and stored values will be limited to +127
to -128 with an exponent -12 irrespective of (20h) VOUT_MODE.
Data Validity
Referring to the data validity table in (21h) VOUT_COMMAND (reproduced below), the output voltage value
(including any offset from VOUT_TRIM, VOUT_COMMAND, VOUT_MARGIN, …) can not exceed the values
supported by the DAC hardware.
Programming a (21h) VOUT_COMMAND + (22h) VOUT_TRIM value greater than the maximum value
supported by the DAC hardware but less than (24h) VOUT_MAX will result in the regulated output voltage
clamping at the maximum value supported by the DAC hardware without setting the VOUT_MAX_MIN bit in
(7Ah) STATUS_VOUT.
表7-34. VOUT_COMMAND/VOUT_MARGIN + VOUT_TRIM data validity (Linear Format)
VOUT_SCALE_LOOP
INTERNAL DIVIDER
VALID VOUT_COMMAND /MARGIN +
VOUT_TRIM VALUES
1.0
0.5
None
1:1
0.000V to 0.700 V
0.000 V to 1.400 V
0.000 V to 2.800 V
0.000 V to 6.000 V
0.25
0.125
1:3
1:7
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The minimum and maximum valid data values for VOUT_TRIM follow the description in (21h)
VOUT_COMMAND. Attempts to write VOUT_TRIM to any value outside those specified as valid, will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits, and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Writes to VOUT_TRIM for which the resulting output voltage is greater than the current (24h) VOUT_MAX, or
less than the current (2Bh) VOUT_MIN, cause the reference DAC to move to the value specified by (2Bh)
VOUT_MIN or (24h) VOUT_MAX, respectively, and cause the VOUT_MAX_MIN_WARNING fault condition,
setting the appropriate bits in (79h) STATUS_WORD, (7Ah) STATUS_VOUT and notifying the host per the
PMBus 1.3.1 Part II specification, section 10.2.
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7.6.21 (24h) VOUT_MAX
CMD Address
Write Transaction:
Read Transaction:
Format:
24h
Write Word
Read Word
ULINEAR16, Absolute Only per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM or Pin Detection
On-the-fly
The VOUT_MAX command sets an upper limit on the output voltage the unit and can command regardless of
any other commands or combinations. The intent of this command is to provide a safeguard against a user
accidentally setting the output voltage to a possibly destructive level.
图7-27. (24h) VOUT_MAX Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MAX (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MAX (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-35. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
MAX
RW
NVM
Maximum output voltage. ULINEAR16 absolute per the setting of VOUT_ MODE.
Refer to the following description for data validity.
While conversion is enabled, any output voltage change (including VOUT_COMMAND, VOUT_TRIM, margin
operations) that causes the new target voltage to be greater than the current value of VOUT_MAX will cause the
VOUT_MAX_MIN_WARNING fault condition. This result causes the TPS546D24S to:
• Set to the output voltage to current value of VOUT_MAX, at the slew rate defined by
VOUT_TRANSITION_RATE.
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_MIN_MAX warning bit in STATUS_VOUT.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
Although the scenario is uncommon, note that the same response results if the user attempted to program
VOUT_MAX less than the current output voltage target.
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7.6.22 (25h) VOUT_MARGIN_HIGH
CMD Address
Write Transaction:
Read Transaction:
Format:
25h
Write Word
Read Word
ULINEAR16, per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when
the OPERATION command is set to “Margin High”. Output voltage transitions during margin operation occur
at the slew rate defined by VOUT_TRANSITION_RATE.
When the MARGIN bits in the OPERATION command indicate “Margin High,”the output voltage is updated to
the value of VOUT_MARGIN_HIGH + VOUT_TRIM.
图7-28. (25h) VOUT_MARGIN_HIGH Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGH (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGH (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-36. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
MARGH
RW
NVM
Margin High output voltage. ULINEAR16 relative or absolute per the setting of
VOUT_ MODE
The minimum and maximum valid data values for VOUT_MARGIN_HIGH follow the description in
VOUT_COMMAND. That is, the total combined output voltage, including VOUT_MARGIN_HIGH and
VOUT_TRIM, follow the values allowed by the current VOUT_MAX setting.
Attempts to write (25h) VOUT_MARGIN_HIGH to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.23 (26h) VOUT_MARGIN_LOW
CMD Address
Write Transaction:
Read Transaction:
Format:
26h
Write Word
Read Word
ULINEAR16, per VOUT_MODE
Phased:
No
NVM Back-up:
EEPROM
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when
the OPERATION command is set to “Margin Low”. Output voltage transitions during margin operation occur
at the slew rate defined by VOUT_TRANSITION_RATE.
When the MARGIN bits in the OPERATION command indicate “Margin Low,” the output voltage is updated to
the value of VOUT_MARGIN_LOW + VOUT_TRIM.
图7-29. (26h) VOUT_MARGIN_LOW Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGIN_LOW (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGIN_LOW (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-37. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
MARGL
RW
NVM
Margin Low output voltage. ULINEAR16 relative or absolute per the setting of
VOUT_ MODE
The minimum and maximum valid data values for VOUT_MARGIN_LOW follow the description in
VOUT_COMMAND. Attempts to write (26h) VOUT_MARGIN_LOW to any value outside those specified as valid
will be considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate
status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.24 (27h) VOUT_TRANSITION_RATE
CMD Address
Write Transaction:
Read Transaction:
Format:
27h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_TRANSITION_RATE sets the slew rate at which any output voltage changes during normal power
conversion occur. This commanded rate of change does not apply when the unit is commanded to turn on or to
turn off. The units are mV/μs.
图7-30. (27h) VOUT_TRANSITION_RATE Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOTR_EXP
VOTR_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOTR_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-38. Register Field Descriptions
Bit
Field
Reset
Description
Access
RW
15:11
10:0
VOTR_ EXP
11100b
NVM
Linear format two’s complement exponent. Exponent = -4, LSB = 0.0625 mV/μs
Linear format two’s complement mantissa
VOTR_
MAN
RW
Per the TPS546D24S product specification, the following slew rates are supported (see the table below). Note
that every binary value between the minimum and maximum values is writeable and readable, but that the actual
output voltage slew rate is set to the nearest supported value.
VOUT_TRANSITION RATE can be programmed from 0.067 mV/µs to 15.933 mV/µs.
Attempts to write (27h) VOUT_TRANSITION_RATE to any value outside those specified as valid will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.25 (29h) VOUT_SCALE_LOOP
CMD Address
Write Transaction:
Read Transaction:
Format:
29h
Write Word
Read Word
SLINEAR11 per CAPABILITY
No
Phased:
Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. To update hardware
after write while enabled, store to NVM with STORE_USER_ALL and RESTORE_USER_ALL or
cycle AVIN below UVLO.
Updates:
NVM Back-up:
EEPROM or Pin Detection
VOUT_SCALE_LOOP allows PMBus devices to map between the commanded voltage and the voltage at the
control circuit input. In the TPS546D24S, VOUT_SCALE_LOOP also programs an internal precision resistor
divider so no external divider is required.
图7-31. (29h) VOUT_SCALE_LOOP Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOSL_EXP
VOSL_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOSL_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-39. Register Field Descriptions
Bit
Field
Access
RW
Reset
11001b
NVM
Description
15:11
10:0
VOSL_ EXP
Linear format two’s complement exponent
Linear format two’s complement mantissa
RW
VOSL_
MAN
Data Validity
Every binary value between the minimum and maximum supported values is writeable and readable. However,
not every combination is supported in hardware. Refer to 表7-40:
表7-40. Accepted Values
VOUT_SCALE_LOOP (DECODED)
Less than or equal to 0.125
0.125 < VOSL ≤0.25
INTERNAL DIVIDER SCALING FACTOR
0.125
0.25
0.5
0.25 < VOSL ≤0.5
Greater than 0.5
1.0
Attempts to write (29h) VOUT_SCALE_LOOP to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
If a (29h) VOUT_SCALE_LOOP value other than a supported Internal Divider Scaling Factor is programmed into
(29h) VOUT_SCALE_LOOP, (21h) VOUT_COMMAND to VREF scale factors are calculated based on the actual
(29h) VOUT_SCALE_LOOP value. (29h) VOUT_SCALE_LOOP values other than supported Internal Divider
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Scaling Factors can produce a mismatch between (21h) VOUT_COMMAND and the actual commanded output
voltage.
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7.6.26 (2Bh) VOUT_MIN
CMD Address
Write Transaction:
Read Transaction:
Format:
2Bh
Write Word
Read Word
ULINEAR16,Absolute Only per VOUT_MODE
Phased:
No
Updates:
on-the-fly
NVM Back-up:
EEPROM or Pin Detection
The VOUT_MIN command sets a lower limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally
setting the output voltage to a level which will render the load inoperable.
图7-32. (2Bh) VOUT_MIN Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MIN (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MIN (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-41. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_ MIN
RW
NVM
Minimum output voltage. ULINEAR16 absolute per the setting of VOUT_ MODE.
During power conversion, any output voltage change (including VOUT_COMMAND, VOUT_TRIM, margin
operations) that causes the new target voltage to be less than the current value of VOUT_MIN will cause the
VOUT_MAX_MIN_WARNING fault condition. These results cause the TPS546D24S to:
• Set to the output voltage to current value of VOUT_MIN at the slew rate defined by
VOUT_TRANSITION_RATE.
• Set the NONE OF THE ABOVE in the STATUS_BYTE.
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_MIN_MAX warning bit in STATUS_VOUT.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
Although the scenario is uncommon, note that the same response results if the user attempted to program
VOUT_MAX greater than the current output voltage target.
Data Validity
The minimum and maximum valid data values for VOUT_MIN follow those of VOUT_MAX. Attempts to write
(2Bh) VOUT_MIN to any value outside those specified as valid will be considered invalid/unsupported data and
cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the
PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.27 (33h) FREQUENCY_SWITCH
CMD Address
Write Transaction:
Read Transaction:
Format:
33h
Write Word
Read Word
SLINEAR11, per CAPABILITY
No
Phased:
Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. To update hardware
after write while enabled, store to NVM with STORE_USER_ALL and RESTORE_USER_ALL or
cycle AVIN below UVLO.
Updates:
NVM Back-up:
EEPROM or Pin Detection
FREQUENCY_SWITCH sets the switching frequency of the active channel in kHz.
图7-33. (33h) FREQUENCY_SWITCH Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
FSW_EXP
FSW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
FSW_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-42. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
FSW_ EXP
RW
NVM
Linear format two’s complement exponent
On reset, FSW_EXP is auto-generated based on the switching frequency stored in
NVM.
10:0
FSW_ MAN
RW
NVM
Linear format two’s complement mantissa. Refer to 表7-43.
表7-43. Supported Switching Frequency Settings
FREQUENCY_SWITCH (Decoded)
Effective Switching Frequency (kHz)
Less than 250 kHz
225
275
325
375
450
550
650
750
900
1100
1300
1500
251 ≤FSW < 300 kHz
301 ≤FSW < 350 kHz
351 ≤FSW < 410 kHz
411 ≤FSW < 500 kHz
501 ≤FSW < 600 kHz
601 ≤FSW < 700 kHz
701 ≤FSW < 820 kHz
821 ≤FSW < 1000 kHz
1001 ≤FSW < 1200 kHz
1201 ≤FSW < 1400 kHz
1401 ≤FSW < 1650 kHz
FREQUENCY_SWITCH values greater than 1100 kHz can require higher VDD5 current than can be provided by
the internal AVIN to VDD5 linear regulator. Programming FREQUENCY_SWITCH to a value greater than 1100
kHz without an external source to VDD5 can result in repeated start-up and shut-down attempt.
FRQUENCY_SWITCH values greater than 1100 kHz are not recommended for Stacked Multi-phase operation.
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7.6.28 (35h) VIN_ON
CMD Address
Write Transaction:
Read Transaction:
Format:
35h
Write Word
Read Word
SLINEAR11, per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
VIN_ON command sets the value of the input voltage, in Volts, at which the unit must start power conversion.
图7-34. (35h) VIN_ON Register Map
15
14
13
RW
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
VON_EXP
VON_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VON_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-44. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
VON_ EXP
RW
11110b
Linear format two’s complement exponent, -2
10:0
VON_ MAN
RW
NVM
Linear format two’s complement mantissa. Refer to the following text for more
information.
Attempts to write (35h) VIN_ON to any value outside those specified as valid will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying
the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
(35h) VIN_ON and (36h) VIN_OFF have limited hardware range and resolution as well as limited NVM
allocation. While the command will accept any binary value within the valid range, values not exactly represented
by the hardware resolution will be rounded down to the next lower supported threshold for implementation or
upon restore from NVM during Power-On Reset or (16h) RESTORE_USER_ALL. (35h) VIN_ON hardware
supports all values from 2.50 V to 18.25 in 0.25-V steps.
Note that the LOW_VIN fault condition is masked until the sensed input voltage exceeds the VIN_ON threshold
for the first time following a power-on reset. Control/Enable pin toggles and EEPROM store/restore operations
do not reset this masking.
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7.6.29 (36h) VIN_OFF
CMD Address
Write Transaction:
Read Transaction:
Format:
36h
Write Word
Read Word
SLINEAR11, per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
(36h) VIN_OFF command sets the value of the PVIN input voltage, in Volts, at which the unit must stop power
conversion. If the Power Conversion Enable conditions as defined by (02h) ON_OFF_CONFIG are met and
PVIN is less than (36h) VIN_OFF, the output off due to low VIN bit in (7Ch) STATUS_INPUT is set.
图7-35. (36h) VIN_OFF Register Map
15
14
13
RW
12
11
10
9
8
RW
RW
RW
R
RW
RW
RW
VOFF_EXP
VOFF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOFF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-45. Register Field Descriptions
Bit
Field
Access
RW
Reset
11110b
NVM
Description
Linear format two’s complement exponent
Linear format two’s complement mantissa. Refer to the following text.
15:11
10:0
VOFF_ EXP
VOFF_
MAN
RW
Attempts to write (36h) VIN_OFF to any value outside those specified as valid will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying
the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
(35h) VIN_ON and (36h) VIN_OFF have limited hardware range and resolution as well as limited NVM
allocation. While the command will accept any binary value within the valid range, values not exactly represented
by the hardware resolution will be rounded down to the next lower supported threshold for implementation or
upon restoration from NVM during Power-On Reset or (16h) RESTORE_USER_ALL. (36h) VIN_OFF hardware
supports all values from 2.25 V to 18.25 in 0.25-V steps.
While it is possible to set (36h) VIN_OFF equal to or greater than (35h) VIN_ON, it is not advisable and can
produce rapid enabling and disabling of conversion and undesirable operation.
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7.6.30 (37h) INTERLEAVE
CMD Address
Write Transaction:
Read Transaction:
Format:
37h
Write Word (Single Phase Only)
Read Word
Four Hexadecimal values
No, Read only in Multi-phase stack
On-th-fly
Phased:
Updates:
NVM Back-up:
EEPROM or Pin Detection
INTERLEAVE sets the phase delay between the external SYNC (IN or OUT) and the internal PMW oscillator.
图7-36. (37h) INTERLEAVE Register Map
15
R
14
R
13
12
11
10
9
8
R
R
RW
RW
RW
RW
Not Used
GROUPID
ORDER
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
NUM_GROUP
LEGEND: R/W = Read/Write; R = Read only
表7-46. Register Field Descriptions
Bit
15:12
11:8
7:4
Field
Access
R
Reset
Description
Not Used
GROUPID
0h
Not used, set to b'0000.
Group ID Number. Set to 0h to Fh.
RW
NVM
NVM
NUM_GRO
UP
RW
Number in Group, sets the number of phases positions and the phase shift for
each value of ORDER. Set to value 1h to 4h.
3:0
ORDER
RW
NVM
Order within the group. Each value of ORDER adds a phase shift equal to 360° /
NUM_GROUP. Set to value 0h to NUM_GROUP - 1.
表7-47. Supported INTERLEAVE Settings
Number in Group
Order
Phase Position (°)
1
2
2
3
3
3
4
4
4
4
0
0
1
0
1
2
0
1
2
3
0
0
180
0
120
240
0
90
180
270
The (37h) INTERLEAVE command is used to arrange multiple devices sharing a common SYNC signal in time.
The phase delay added to each device is equal to 360° / Number in Group × Order. To prevent misaligning the
phases of a multi-phase stack, (37h) INTERLEAVE is read only when the TPS546D24S is configured as part of
a multi-phase stack. The Read/Write status of the (37h) INTERLEAVE command is set based on the state of the
(ECh) MFR_SPECIFIC_28 (STACK_CONFIG) command at power-on and is not updated if (ECh)
MFR_SPECIFIC_28 (STACK_CONFIG) is later changed. If (37h) INTERLEAVE will be used to program the
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phase position of a stand-alone device, the TPS546D24S must be configured as a stand-alone device at power-
on to ensure write capability of the (37h) INTERLEAVE command.
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7.6.31 (38h) IOUT_CAL_GAIN
CMD Address
Write Transaction:
Read Transaction:
Format:
38h
Write Word
Read Word
SLINEAR11, per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
(38h) IOUT_CAL_GAIN is used to trim the gain of the output current reported by the READ_IOUT command.
The value is a unitless gain factor applied to the internally sensed current measurement. It defaults to a value of
1.
图7-37. (38h) IOUT_CAL_GAIN Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
IOCG_EXP
IOCG_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOCG_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-48. Register Field Descriptions
Bit
Field
Access
RW
Reset
11001b
NVM
Description
15:11
10:0
IOCG_ EXP
IOCG_ MAN
Linear format, two’s complement exponent
Linear format, two’s complement mantissa
RW
Attempts to write (38h) IOUT_CAL_GAIN to any value outside those specified as valid will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying
the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The (38h) IOUT_CAL_GAIN command is implemented using the TPS546D24S internal telemetry system. As a
result, the value of this command can be programmed with very high resolution using the linear format. However,
the TPS546D24S provides only limited NVM-backed options for this command. Following a power-cycle or NVM
Store/Restore operation, the value will be rounded to the nearest 1/64 with a maximum supported value of 1.984
(1 63/64).
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7.6.32 (39h) IOUT_CAL_OFFSET
CMD Address
Write Transaction:
Read Transaction:
Format:
39h
Write Word
Read Word
SLINEAR11, per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT command. Each PHASE in a
stack can apply an independent IOUT_CAL_OFFSET value. The effective IOUT_CAL_OFFSET value for a
stack is equal to the sum of the IOUT_CAL_OFFSET values from all devices in the stack.
图7-38. (39h) IOUT_CAL_OFFSET Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
IOCOS_EXP
IOCOS_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOCOS_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-49. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
IOCOS_
EXP
RW
11100b
Linear format, two’s complement exponent
Linear format, two’s complement mantissa
10:0
IOCOS_
MAN
RW
NVM
(39h) IOUT_CAL_OFFSET has a programmable range from -8A to +7.9375A for each phase. Attempts to write
(39h) IOUT_CAL_OFFSET to any value outside those specified as valid will be considered invalid/unsupported
data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host
according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The (39h) IOUT_CAL_OFFSET command is implemented using the TPS546D24S internal telemetry system. As
a result, the value of this command can be programmed with very high resolution using the linear format.
However, the TPS546D24S only provides limited NVM-backed options for this command. Following a power-
cycle or NVM Store/Restore operation, the value will be restored to one of the supported values, according to the
value present during the last NVM store operation. During operation, updates to this command with higher
resolution, will be supported, and accepted as long as they fall between the minimum and maximum supported
values given.
Phased Command Behavior
PHASE = 00h to 03h: Writes to (39h) IOUT_CAL_OFFSET modify the current sense offset for individual phases.
Reads to (39h) IOUT_CAL_OFFSET return the configured current sense offset for individual phases.
PHASE = FFh: Writes to (39h) IOUT_CAL_OFFSET modify the total current sense offset for all individual
phases. Individual phases will be assigned an IOUT_CAL_OFFSET value equal to the written value divided by
the number of phases. Reads to (39h) IOUT_CAL_OFFSET return the configured current sense offset for
PHASE = 00h times the number of phases.
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7.6.33 (40h) VOUT_OV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
40h
Write Word
Read Word
ULINEAR16 Relative or Absolute per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense or output
pins that causes an output overvoltage fault. VOUT_OV_FAULT_LIMIT sets an over-voltage threshold relative to
the current VOUT_COMMAND. Updates to VOUT_COMMAND do not update the value of
VOUT_OV_FAULT_LIMIT when the absolute format is used. Note that even with VOUT_MODE configured in
absolute format, the true overvoltage fault limit remains relative to the current VOUT_COMMAND.
VOUT_OV_FAULT_LIMIT is active as soon as the TPS546D24S completes its Power-On Reset, even if output
conversion is disabled.
Following
an
overvoltage
fault
condition,
the
TPS546D24S
responds
according
to
VOUT_OV_FAULT_RESPONSE.
图7-39. (40h) VOUT_OV_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_OVF (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_OVF (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-50. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_ OVF
RW
See Below Sets the overvoltage fault limit. Format is per VOUT_ MODE.
Hardware Support and Value Mapping
The Hardware for VOUT_OV_FAULT_LIMIT is implemented as a fixed percentage of the current output voltage
target. Depending on the VOUT_MODE setting, the value written to VOUT_OV_FAULT_LIMIT must be mapped
to the hardware percentage.
Programmed values not exactly equal to one of the hardware relative values shall be rounded up to the next
available relative value supported by hardware. The hardware supports values from 105% to 140% of
VOUT_COMMAND in 2.5% steps. When output conversion is disabled, the hardware supports values from
110% to 140% of VOUT_COMMAND in 10% steps.
Attempts to write VOUT_OV_FAULT_LIMIT to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
41h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_OV_FAULT_RESPONSE instructs the device on what action to take in response to an output
overvoltage fault. Upon triggering the overvoltage fault, the controller TPS546D24S responds according to the
data byte below, and the following actions are taken:
• Set the VOUT_OV_FAULT bit in the STATUS_BYTE.
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_OVF bit in the STATUS_VOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-40. (41h) VOUT_OV_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
RW
0
RW
RW
RW
RW
RW
RW
RW
VO_OV_RESP
VO_OV_RETRY
VO_ OV_ DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-51. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
VO_OV_RE
SP
RW
NVM
Output overvoltage response
00b: Ignore. Continue operating without interruption.
01b: Shutdown. Shutdown and retry according to VO_OV_RETRY.
10b: Shutdown. Shutdown and retry according to VO_ OV_ RETRY.
11b: Invalid/Unsupported
5:3
2:0
VO_OV_RE
TRY
RW
RW
NVM
NVM
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart up to 1
- 6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off).
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF, or a successful start-up occurs.
VO_OV_DE
LAY
0d: VO_OV HICCUP period is equal to TON_RISE.
1d - 7d: VO_OV HICCUP period is equal to 1 - 7 times TON_RISE.
Attempts to write VOUT_OV_FAULT_RESPONSE to any value outside those specified as valid, will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
A Restart Attempt is successful and the restart limit counter is reset to 0 when no fault with a shut-down
response is observed after one (61h) TON_RISE time after completing (61h) TON_RISE or after (62h)
TON_MAX_FAULT_LIMIT if (62h) TON_MAX_FAULT_LIMIT is not set to 0 ms (Disabled).
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7.6.35 (42h) VOUT_OV_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
42h
Write Word
Read Word
ULINEAR16 Relative or Absolute per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage at the sense or output pins that
causes an output voltage high warning. This value is typically less than the output overvoltage threshold. The
OV_WARN_LIMIT sets an overvoltage threshold relative to the current VOUT_COMMAND. Updates to
VOUT_COMMAND do not update the value of VOUT_OV_FAULT_LIMIT when the absolute format is used.
When the sensed output voltage exceeds the VOUT_OV_WARN_LIMIT threshold, the following actions are
taken:
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_OVW bit in the STATUS_VOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-41. (42h) VOUT_OV_WARN_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_OVW (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_OVW (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-52. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
OVW
RW
NVM
Sets the overvoltage warning limit. Format is per VOUT_ MODE.
Hardware Support and Value Mapping
The Hardware for VOUT_OV_WARN_LIMIT is implemented as a fixed percentage of the current output voltage
target. Depending on the VOUT_MODE setting, the value written to VOUT_OV_WARN_LIMIT must be mapped
to a hardware percentage.
Programmed values not exactly equal to one of the hardware relative values shall be rounded up to the next
available relative value supported by hardware. The hardware supports values from 103% to 116%
VOUT_COMMAND in 1% steps.
Attempts to write (42h) VOUT_OV_WARN_LIMIT to any value outside those specified as valid, will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.36 (43h) VOUT_UV_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
43h
Write Word
Read Word
ULINEAR16 Relative or Absolute per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_UV_WARN_LIMIT command sets the value of the output voltage at the sense or output pins that
causes an output voltage low warning. The VOUT_UV_WARN_LIMIT sets an undervoltage threshold relative to
the current VOUT_COMMAND. Updates to VOUT_COMMAND do not update VOUT_UV_WARN_LIMIT when
the absolute format is used.
When the sensed output voltage exceeds the VOUT_UV_WARN_LIMIT threshold, the following actions are
taken:
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_UVW bit in the STATUS_VOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-42. (43h) VOUT_UV_WARN_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_UVW (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_UVW (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-53. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
UVW
RW
NVM
Sets the undervoltage warning limit. Format is per VOUT_ MODE.
Hardware Mapping and Supported Values
The Hardware for VOUT_UV_WARN_LIMIT is implemented as a fixed percentage relative to the current output
voltage target. Depending on the VOUT_MODE setting, the value written to VOUT_UV_WARN_LIMIT must be
mapped to the hardware percentage.
Programmed values not exactly equal to one of the hardware relative values is rounded down to the next
available relative value supported by hardware. The hardware supports values from 84% to 97%
VOUT_COMMAND in 1% steps.
Attempts to write (43h) VOUT_UV_WARN_LIMIT to any value outside those specified as valid, will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.37 (44h) VOUT_UV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
44h
Write Word
Read Word
ULINEAR16 Absolute per VOUT_MODE
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage at the sense or output pins that
causes an output voltage fault. The VOUT_UV_FAULT_LIMIT sets an undervoltage threshold relative to the
current VOUT_COMMAND. Updates to VOUT_COMMAND do not update VOUT_UV_FAULT_LIMIT when the
absolute format is used.
When the undervoltage fault condition is triggered, the TPS546D24S responds according to
VOUT_UV_FAULT_RESPONSE.
图7-43. (44h) VOUT_UV_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_UVF (High Byte)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_UVF (Low Byte)
LEGEND: R/W = Read/Write; R = Read only
表7-54. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
VOUT_
UVW
RW
NVM
Sets the undervoltage fault limit. Format is per VOUT_ MODE
Hardware Mapping and Supported Values
The Hardware for VOUT_UV_FAULT_LIMIT is implemented as a fixed percentage relative to the current output
voltage target. Depending on the VOUT_MODE setting, the value written to VOUT_UV_FAULT_LIMIT must be
mapped to the hardware percentage.
Programmed values not exactly equal to one of the hardware relative values are rounded down to the next
available relative value supported by hardware. The hardware supports values from 60% to 95% of
VOUT_COMMAND in 2.5% steps.
Attempts to write (44h) VOUT_UV_FAULT_LIMIT to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
45h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
• The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output
undervoltage fault.
The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output
undervoltage fault. Upon triggering the overvoltage fault, the TPS546D24S responds according to the data byte
below, and the following actions are taken:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
• Set the VOUT bit in the STATUS_WORD.
• Set the VOUT_UVF bit in the STATUS_VOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-44. (45h) VOUT_UV_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VO_UV_RESP
VO_UV_RETRY
VO_UV_DLY
LEGEND: R/W = Read/Write; R = Read only
表7-55. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
VO_ UV_
RESP
RW
NVM
Output undervoltage response
00b: Ignore. Continue operating without interruption.
01b: Shutdown after Delay, as set by VO_UV_DELY
10b: Shutdown Immediately
Other: Invalid/Unsupported
5:3
2:0
VO_ UV_
RETRY
RW
RW
NVM
NVM
Output undervoltage retry
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart upto 1 -
6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off).
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF, or a successful start-up occurs.
VO_ UV_
DLY
Output undervoltage delay time for respond after delay and HICCUP
0d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
1d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
2d - 4d: Shutdown delay of three PWM_CLK, HICCUP equal to 2 - 4 times
TON_RISE
5d - 7d: Shutdown delay of seven PWM_CLK, HICCUP equal to 5 - 7 times
TON_RISE
Attempts to write (45h) VOUT_UV_FAULT_RESPONSE to any value outside those specified as valid will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.39 (46h) IOUT_OC_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
46h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM or Pin Detection
On-the-fly
The IOUT_OC_FAULT_LIMIT command sets the value of the output current that causes the overcurrent detector
to indicate an overcurrent fault condition. While each TPS546D24S device in a multi-phase stack has its own
IOUT_OC_FAULT_LIMIT and comparator, the effective current limit of the multi-phase stack is equal to the
lowest IOUT_OC_FAULT_LIMIT setting times the number of phases in the stack.
When
the
overcurrent
fault
is
triggered,
the
TPS546D24S
responds
according
to
IOUT_OC_FAULT_RESPONSE.
图7-45. (46h) IOUT_OC_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
IO_OCF_EXP
IO_OCF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IO_OCF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-56. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
IO_OCF_
EXP
RW
11110b
Linear format two’s complement exponent
10:0
IO_OCF_
MAN
RW
NVM
Linear format two’s complement mantissa. Refer to the table below.
Multi-phase Stack Current Limit up to 62 A x Number of Phases (PHASE = FFh)
Per Phase OCL: up to 62 A (PHASE != FFh)
Attempts to write (46h) IOUT_OC_FAULT_LIMIT to any value outside those specified as valid, will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The Per-PHASE (PHASE != FFh) IOUT_OC_FAULT_LIMIT is implemented in analog hardware. The analog
hardware supports current limits from 8 A to 62 A in 2-A steps. Programmed values not exactly equal to
hardware supported values will be rounded up to the next available supported value. Values less than 8 A per
device can be written to IOUT_OC_FAULT_LIMIT, but values less than 8 A per device will be implemented as 8
A in hardware. The TPS546D24S provides only limited NVM-backed options for this command. Following a
power-cycle or NVM Store/Restore operation, the value will be rounded to the nearest NVM supported value.
The NVM supports values up to 62 A in 0.25-A steps.
Phased Command Behavior
Write when PHASE = FFh: Set IOUT_OC_FAULT_LIMIT for each phase to the written value divided by the
number of phases.
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Read when PHASE = FFh: Report the IOUT_OC_FAULT_LIMIT value of PHASE = 00h (Loop Controller) times
the number of phases.
Write when PHASE != FFh: Set IOUT_OC_FAUL_LIMIT for the current phase to the written value.
Read when PHASE != FFh: Report the IOUT_OC_FAULT_LIMIT value of the current phase.
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7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
47h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The IOUT_OC_FAULT_RESPONSE instructs the device on what action to take in response to an overcurrent
fault. Upon triggering the overcurrent fault, the TPS546D24S responds according to the data byte below, and the
following actions are taken:
• Set the IOUT_OC bit in the STATUS_BYTE.
• Set the IOUT bit in the STATUS_WORD.
• Set the IOUT_OCF bit in the STATUS_IOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-46. (47h) IOUT_OC_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
R
R
R
IO_OC_RESP
IO_OC_RETRY
IO_OC_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-57. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
IO_OC_RE
SP
RW
NVM
Output ovecurrent response
00b: Ignore. Continue operating without interruption.
01b: Ignore. Continue operating without interruption.
10b: Shutdown after Delay, as set by IO_OC_DELAY
11b: Shutdown Immediately
5:3
2:0
IO_OC_RET
RY
RW
RW
NVM
NVM
Output overcurrent retry
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart upto 1 -
6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off).
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF, or a successful start-up occurs.
IO_OC_DEL
AY
Output overcurrent delay time for respond after delay and HICCUP
0d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
1d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
2d - 4d: Shutdown delay of three PWM_CLK, HICCUP equal to 2 - 4 times
TON_RISE
5d - 7d: Shutdown delay of seven PWM_CLK, HICCUP equal to 5 - 7 times
TON_RISE
Attempts to write (47h) IOUT_OC_FAULT_RESPONSE to any value outside those specified as valid will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
4Ah
Write Word
Read Word
SLINEAR11 per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM or Pin Detection
On-the-fly
The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the
overcurrent detector to indicate an overcurrent warning condition. The units are amperes.
IOUT_OC_WARN_LIMIT is a phased command. Each phase will report an output current overcurrent warning
independently.
In response to an overcurrent warning condition, the TPS546D24S takes the following action:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
• Set the IOUT bit in the STATUS_WORD.
• Set the IOUT_OCW bit in the STATUS_IOUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-47. (4Ah) IOUT_OC_WARN_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
IOOCW_EXP
IOOCW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOOCW_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-58. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
IOOCW_
EXP
RW
11110b
Linear format two’s complement exponent
10:0
IOOCW_
MAN
RW
NVM
Linear format two’s complement mantissa
Supported values up to 62 A times the number of phases.
Attempts to write (4Ah) IOUT_OC_WARN_LIMIT to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The Per-PHASE (PHASE != FFh) IOUT_OC_WARN_LIMIT is implemented in analog hardware. The analog
hardware supports current limits from 8 A to 62 A in 2-A steps. Programmed values not exactly equal to
hardware supported values will be rounded up to the next available supported value. Values less than 8 A per
device can be written to IOUT_OC_FAULT_LIMIT, but values less than 8 A per device will be implemented as 8
A in hardware. The TPS546D24S provides only limited NVM-backed options for this command. Following a
power-cycle or NVM Store/Restore operation, the value will be rounded to the nearest NVM supported value.
The NVM supports values up to 62 A in 0.25-A steps.
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7.6.42 (4Fh) OT_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
4Fh
Write Word
Read Word
SLINEAR11 per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The OT_FAULT_LIMIT command sets the value of the temperature limit, in degrees Celsius, that causes an
overtemperature fault condition.
The converter response to an overtemperature event is described in OT_FAULT_RESPONSE.
图7-48. (4Fh) OT_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
OTF_EXP
OTF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-59. Register Field Descriptions
Bit
Field
Access
RW
Reset
00000b
NVM
Description
Linear format two’s complement exponent
Linear format two’s complement mantissa. Refer to the following text.
15:11
10:0
OTF_ EXP
OTF_ MAN
RW
Attempts to write (4Fh) OT_FAULT_LIMIT to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The (4Fh) OT_FAULT_LIMIT command is implemented using the TPS546D24S internal telemetry system. As a
result, the value of this command can be programmed with very high resolution using the linear format. However,
the TPS546D24S provides only limited NVM-backed options for this command. Following a power-cycle or NVM
Store/Restore operation, the value will be restored to the nearest NVM supported value. The NVM supports
values from 0°C to 160°C in 1°C steps. Programming a value of 255°C will disable Programmable
Overtemperature Fault Limit without disabling the on-die Bandgap thermal shutdown.
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7.6.43 (50h) OT_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
50h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an
Overtemperature Fault. Upon triggering the overtemperature fault, the converter responds per the data byte
below, and the following actions are taken:
• Set the TEMP bit in the STATUS_BYTE.
• Set the OTF bit in the STATUS_TEMPERATURE register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
Note: the OT Fault hysteresis is set by the (51h) OT_WARN_LIMIT. When (8Dh) READ_TEMPERATURE_1 falls
below (51h) OT_WARN_LIMIT, the overtemperature fault condition will be released and restart will be allowed if
selected by (50h) OT_FAULT_RESPONSE. If (51h) OT_WARN_LIMIT is programmed higher than (4Fh)
OT_FAULT_LIMIT, a default hysteresis of 20°C will be used instead.
图7-49. (50h) OT_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTF_RESP
OT_RETRY
OT_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-60. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
OTF_RESP
RW
NVM
Overtemperature fault response
00b: Ignore. Continue operating without interruption.
01b: Delayed Shutdown Continue Operating for 10ms x OT_DELAY. If OT_FAULT
is still present, shut down and restart according to OT_RETRY.
10b: Immediate Shutdown. Shut down and restart according to OT_RETRY.
11b: Shutdown until Temperature is below OT_WARN_LIMIT, then restart
according to OT_RETRY*.
5:3
OT_RETRY
RW
RW
NVM
Overtemperature retry
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart up to 1
- 6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off).
Restart attempts that occur while temperature is above OT_WARN_LIMIT will not
be observable but will be counted.
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF or a successful start-up occurs.
2:0
OT_DELAY
NVM
Overtemperature delay time for respond after delay and HICCUP
0d: Shutdown delay of 10 ms, HICCUP equal to TON_RISE, HICCUP delay equal
to TON_RISE
1d - 7d: Shutdown delay of 1-7 ms, HICCUP equal to 2-4 times TON_RISE
Attempts to write (50h) OT_FAULT_RESPONSE to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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*When (50h) OT_FAULT_RESPONSE OTF_RESP (Bits 7:6) are set to 11b - shut down until temperature is
below (51h) OT_WARN_LIMIT, issuing a (03h) CLEAR_FAULTS command while the temperature is between
(4Fh) OT_FAULT_LIMIT and (51h) OT_WARN_LIMIT can result in the TPS546D24S remaining in the OT FAULT
state until the temperature rises above (4Fh) OT_FAULT_LIMIT or disabled and enabled according to (02h)
ON_OFF_CONFIG.
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7.6.44 (51h) OT_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
51h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The OT_WARN_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it must indicate
an Overtemperature Warning alarm. The units are degrees C.
Upon triggering the overtemperature fault, the converter responds per the data byte below, and the following
actions are taken:
• Set the TEMP bit in the STATUS_BYTE.
• Set the OTW bit in the STATUS_TEMPERATURE register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-50. (51h) OT_WARN_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
OTW_EXP
OTW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTW_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-61. Register Field Descriptions
Bit
Field
Access
RW
Reset
00000b
NVM
Description
Linear format two’s complement exponent
Linear format two’s complement mantissa. Refer to the following text.
15:11
10:0
OTW_ EXP
OTW_ MAN
RW
Attempts to write (51h) OT_WARN_LIMIT to any value outside those specified as valid will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying
the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Command Resolution and NVM Store/Restore Behavior
The (51h) OT_WARN_LIMIT command is implemented using the TPS546D24S internal telemetry system. As a
result the value of this command can be programmed with very high resolution using the linear format. However,
the TPS546D24S provides only limited NVM-backed options for this command. Following a power-cycle or NVM
Store/Restore operation, the value will be restored to the nearest NVM supported value. The NVM supports
values from 0°C to 160°C in 1°C steps. Programming OT_WARN_LIMIT to a value of 255°C will disable the
OT_WARN_LIMIT function.
OT_WARN_LIMIT is used to provide hysteresis to OT_FAULT_LIMIT faults. If OT_WARN_LIMIT is programmed
greater than OT_FAULT_LIMIT, including disabling OT_WARN_LIMIT with a value of 255°C, a default hysteresis
of 20°C will be used instead.
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7.6.45 (55h) VIN_OV_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
55h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The (55h) VIN_OV_FAULT_LIMIT command sets the PVIN voltage, in volts, when a VIN_OV_FAULT is
declared. The response to a detected VIN_OV_FAULT is determined by the settings of (56h)
VIN_OV_FAULT_RESPONSE. (55h) VIN_OV_FAULT_LIMIT is typically used to stop switching in the event of
excessive input voltage, which can result in over-stress damage to the power FETs due to ringing on the SW
node.
图7-51. (55h) VIN_OV_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
VINOVF_EXP
VINOVF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VINOVF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-62. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
VINOVF_
EXP
RW
11110b
Linear format two’s complement exponent
Linear format two’s complement mantissa
10:0
VINOVF_
MAN
RW
NVM
Attempts to write (55h) VIN_OV_FAULT_LIMIT beyond the supported range will be considered invalid/
unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying
the host according to the PMBus 1.3.1 Part II specification section 10.9.3. (55h) VIN_OV_FAULT_LIMIT supports
values from 4 V to 20 V in 0.25-V steps. Following a Power Cycle or STORE/RESTORE, (55h)
VIN_OV_FAULT_LIMIT will be restored to the nearest supported value.
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7.6.46 (56h) VIN_OV_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
56h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to a PVIN
Overvoltage Fault. Upon triggering the PVIN overvoltage fault, the converter responds per the data byte below,
and the following actions are taken:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE register.
• Set the INPUT bit in the upper byte of the STATUS_WORD register.
• Set the VIN_OV bit in the STATUS_INPUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-52. (56h) VIN_OV_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VINOVF_RESP
VINOVF_RETRY
VIN_OVF_DLY
LEGEND: R/W = Read/Write; R = Read only
表7-63. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
VIN_OVF_
RESP
RW
NVM
PVIN Overvoltage fault response
00b: Ignore. Continue operating without interruption.
01b: Delayed Shutdown Continue Operating for a number of switching cycles
defined by VIN_OVF_DLY, then if fault persists, shut down and restart according to
VIN_OV_RETRY.
10b: Immediate Shutdown. Shut down and restart according to VIN_OV_RETRY.
11b: Invalid / Not Supported
5:3
VIN_OVF_
RETRY
RW
RW
NVM
PVIN Overvoltage retry
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart up to 1
- 6 times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off).
Restart attempts that occur while PVIN voltage is above VIN_OV_FAULT_LIMIT
will not be observable but will be counted
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF, or a successful start-up occurs.
2:0
VIN_OVF_
DLY
NVM
PVIN Overvoltage delay time for respond after delay and HICCUP
0d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
1d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE
2d - 4d: Shutdown delay of three PWM_CLK, HICCUP equal to 2 - 4 times
TON_RISE
5d - 7d: Shutdown delay of seven PWM_CLK, HICCUP equal to 5 - 7 times
TON_RISE
Attempts to write (56h) VIN_OV_FAULT_RESPONSE to any value outside those specified as valid will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.47 (58h) VIN_UV_WARN_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
58h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Yes
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The (58h) VIN_UV_WARN_LIMIT command sets the value of the PVIN pin voltage, in volts, that causes the
input voltage detector to indicate an input undervoltage warning.
The (58h) VIN_UV_WARN_LIMIT is a phase command, each phase within a stack will independently detect and
report input undervoltage warnings.
In response to an input undervoltage warning condition, the TPS546D24S takes the following action:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
• Set the INPUT bit in the STATUS_WORD.
• Set the VIN_UVW bit in the STATUS_INPUT register.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-53. (58h) VIN_UV_WARN_LIMIT Register Map
15
14
13
12
11
10
9
RW
8
RW
RW
RW
RW
RW
RW
RW
VINUVW_EXP
VINUVW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VINUVW_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-64. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
VINUVW_
EXP
RW
11110b
Linear format two’s complement exponent
10:0
VINUVW_
MAN
RW
NVM
Linear format two’s complement mantissa
Supported values 2.5 V to 15.5 V
Attempts to write (58h) VIN_UV_WARN_LIMIT to any value outside those specified as valid will be considered
invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status bits and
notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.48 (60h) TON_DELAY
CMD Address
Write Transaction:
Read Transaction:
Format:
60h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received (as
programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise.
图7-54. (60h) TON_DELAY Register Map
15
14
13
12
11
10
9
RW
8
RW
RW
RW
RW
RW
RW
RW
TONDLY_EXP
TONDLY_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TONDLY_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-65. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
TONDLY_
EXP
RW
11111b
Linear format two’s complement exponent.
10:0
TONDLY_
MAN
RW
NVM
Linear format two’s complement mantissa.
Note, a minimum turn-on delay of approximately 100 μs is observed even when
TON_DELAY during which the device initializes itself at every power-on.
Attempts to write (60h) TON_DELAY beyond the supported range will be considered invalid/unsupported data
and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according
to the PMBus 1.3.1 Part II specification section 10.9.3. TON_DELAY supports values from 0ms to 127.5 ms in
0.5-ms steps. Following a Power Cycle or STORE/RESTORE, TON_DELAY will be restored to the nearest
supported value.
Refer to the Start-Up and Shutdown behavior section for handling of corner cases with respect to interrupted
TON_DELAY, TON_RISE , TOFF_FALL, and TOFF_DELAY times.
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7.6.49 (61h) TON_RISE
CMD Address
Write Transaction:
Read Transaction:
Format:
61h
Write Word
Read Word
SLINEAR11 per CAPABILITY
No
Phased:
NVM Back-up:
Updates:
EEPROM or Pin Detection
On-the-fly
The TON_RISE command sets the time, in milliseconds, from when the output starts to rise until the voltage has
entered the regulation band. This effectively sets the slew rate of the reference DAC during the soft-start period.
Note that the rise time is equal to TON_RISE regardless of the value of the target output voltage or
VOUT_SCALE_LOOP.
Due to hardware limitations in the resolution of the reference DAC slew-rate control, longer TON_RISE times
with higher VOUT_COMMAND voltages can result in some quantization error in the programmed TON_RISE
times with several TON_RISE times producing the same VOUT slope and TON_RISE time even with different
TON_RISE settings or different TON_RISE times for the same TON_RISE setting and different
VOUT_COMMAND voltages.
图7-55. (61h) TON_RISE Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
TONR_EXP
TONR_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TONR_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-66. Register Field Descriptions
Bit
Field
Access
RW
Reset
11110b
NVM
Description
15:11
10:0
TONR_ EXP
Linear format two’s complement exponent
Linear format two’s complement mantissa
TONR_
MAN
RW
Attempts to write (61h) TON_RISE beyond the supported range will be considered invalid/unsupported data and
cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the
PMBus 1.3.1 Part II specification section 10.9.3. TON_RISE will support the range from 0ms to 31.75 ms in 0.25-
ms steps. Values less than 0.5 ms are supported as 0.5 ms.
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7.6.50 (62h) TON_MAX_FAULT_LIMIT
CMD Address
Write Transaction:
Read Transaction:
Format:
62h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The TON_MAX_FAULT_LIMIT command sets an upper limit, in milliseconds, on how long the unit can attempt to
power up the output without reaching the target voltage.
The TON_MAX time is defined as the maximum allowable amount of time from the end of TON_DELAY, until the
output voltage reaches 85% of the programmed output voltage, as sensed by the READ_VOUT telemetry at
VOSNS - GOSNS.
Note that for the TPS546D24S, the undervoltage fault limit is enabled at the end of TON_RISE. As a
consequence, unless VOUT_UV_FAULT_RESPONSE is set to ignore, in the case of a “real” TON_MAX fault
(for example, output voltage did not rise quickly enough), UV faults / associated response will always precede
TON_MAX.
The converter response to a TON_MAX fault event is described in TON_MAX_FAULT_RESPONSE.
图7-56. (62h) TON_MAX_FAULT_LIMIT Register Map
15
14
13
12
11
10
9
RW
8
RW
RW
RW
RW
RW
RW
RW
TONMAXF_EXP
TONMAXF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TONMAXF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-67. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
TONMAXF_
EXP
RW
11111b
Linear format two’s complement exponent
Linear format two’s complement mantissa
10:0
TONMAXF_
MAN
RW
NVM
Attempts to write (62h) TON_MAX_FAULT_LIMIT will be considered an invalid/unsupported command and
cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according to the
PMBus 1.3.1 Part II specification section 10.9.3. TON_MAX_FAULT_LIMIT supports values from 0 ms to 127 ms
in 0.5-ms steps.
*Note: programming TON_MAX_FAULT to 0 ms disables the TON_MAX functionality.
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7.6.51 (63h) TON_MAX_FAULT_RESPONSE
CMD Address
Write Transaction:
Read Transaction:
Format:
63h
Write Byte
Read Byte
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
The TON_MAX_FAULT_RESPONSE instructs the device on what action to take in response to TON_MAX fault.
Upon triggering the input TON_MAX fault, the converter responds per the byte below and the following actions
are taken:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
• Set the VOUT bit in the STATUS_WORD.
• Set the TON_MAX bit in STATUS_VOUT.
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2.
图7-57. (63h) TON_MAX_FAULT_RESPONSE Register Map
7
6
5
4
3
2
1
RW
0
RW
RW
RW
RW
RW
RW
RW
TONMAX_RESP
TONMAX_RETRY
TONMAX_DELAY
LEGEND: R/W = Read/Write; R = Read only
表7-68. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
TONMAX_
RESP
RW
NVM
TON_ MAX Fault Response
00b: Ignore. Continue operating without interruption.
01b: Continue Operating for the delay time specified by TONMAX_DELAY, if the
fault is still present, shutdown and restart according to TONMAX_RETRY.
10b: Shutdown Immediately and restart according to TONMAX_RETRY.Other:
Invalid/Unsupported
5:3
2:0
TONMAX_
RETRY
RW
RW
NVM
NVM
TON_MAX Fault Retry
0d: Do not attempt to restart (latch off).
1d-6d: After shutting down, wait one HICCUP period, and attempt to restart up to 1
- 6 times.
7d: After shutting down, wait one HICCUP period, and attempt to restart
indefinitely, until commanded OFF, or a successful start-up occurs.
TONMAX_
DELAY
TON_MAX delay time for respond after delay and HICCUP
0d: Shutdown delay of 1 ms, HICCUP equal to TON_RISE
1d - 7d: Shutdown delay of 1-7 ms, HICCUP equal to 2-7 times TON_RISE
Attempts to write (63h) TON_MAX_FAULT_RESPONSE to any value outside those specified as valid, will be
considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate status
bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.52 (64h) TOFF_DELAY
CMD Address
Write Transaction:
Read Transaction:
Format:
64h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received (as
programmed by the ON_OFF_CONFIG command) until the unit stops transferring energy to the output.
图7-58. (64h) TOFF_DELAY Register Map
15
14
13
12
11
10
9
RW
8
RW
RW
RW
RW
RW
RW
RW
TOFFDLY_EXP
TOFFDLY_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TOFFDLY_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-69. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
TOFFDLY_
EXP
RW
11111b
Linear format two’s complement exponent
Linear format two’s complement mantissa
10:0
TOFFDLY_
MAN
RW
NVM
Attempts to write (64h) TOFF_DELAY beyond the supported range will be considered invalid/unsupported data
and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according
to the PMBus 1.3.1 Part II specification section 10.9.3. TOFF_DELAY supports values from 0 ms to 127.5 ms in
0.5-ms steps. An internal delay of up to 50 µs will be added to TOFF_DELAY, even if TOFF_DELAY is equal to 0
ms.
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7.6.53 (65h) TOFF_FALL
CMD Address
Write Transaction:
Read Transaction:
Format:
65h
Write Word
Read Word
SLINEAR11 per CAPABILITY
Phased:
No
NVM Back-up:
Updates:
EEPROM
On-the-fly
The TOFF_FALL command sets the time, in milliseconds, from the end of the turnoff delay time until the voltage
is commanded to zero. Note that this command can only be used with a device whose output can sink enough
current to cause the output voltage to decrease at a controlled rate. This effectively sets the slew rate of the
reference DAC during the soft-off period. Note that the fall time is equal to TOFF_FALL regardless of the value of
the target output voltage or VOUT_SCALE_LOOP for the purposes of slew rate selection based on the target
output voltage.
图7-59. (65h) TOFF_FALL Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
TOFFF_EXP
TOFFF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TOFFF_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-70. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
TOFFF_
EXP
RW
11110b
Linear format two’s complement exponent. Exponent = -2, LSB = 0.25 ms
Linear format two’s complement mantissa
10:0
TOFFF_
MAN
RW
NVM
Attempts to write (65h) TOFF_FALL beyond the supported range will be considered invalid/unsupported data
and cause the TPS546D24S to respond by flagging the appropriate status bits and notifying the host according
to the PMBus 1.3.1 Part II specification section 10.9.3. (65h) TOFF_FALL supports values from 0.5 ms to 31.75
ms in 0.25-ms steps. Values less than 0.5 ms will be implemented as 0.5 ms.
Due to hardware limitations in the resolution of the reference DAC slew-rate control, longer TOFF_FALL times
with higher (21h) VOUT_COMMAND voltages can result in some quantization error in the programmed
TOFF_FALL times with several TOFF_FALL times producing the same VOUT slope and TOFF_FALL time even
with different TOFF_FALL settings, or different TOFF_FALL times for the same TOFF_FALL setting and different
(21h) VOUT_COMMAND voltages.
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7.6.54 (78h) STATUS_BYTE
CMD Address
Write Transaction:
Read Transaction:
Format:
78h
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults, such as
overvoltage, overcurrent, overtemperature, and so forth. The supported STATUS_BYTE message content is
described in the following table. The STATUS_BYTE is equal the low byte of STATUS_WORD. The conditions in
the STATUS_BYTE are summary information only. They are asserted to inform the host as to which other
STATUS registers must be checked in the event of a fault. Setting and clearing of these bits must be done in the
individual status registers. For example, Clearing VOUT_OVF in STATUS_VOUT also clears VOUT_OV in
STATUS_BYTE.
图7-60. (78h) STATUS_BYTE Register Map
7
6
5
4
3
2
1
0
RW
R
R
R
R
R
R
R
NONE OF THE
ABOVE
BUSY
OFF
VOUT_OV
IOUT_OC
VIN_UV
TEMP
CML
LEGEND: R/W = Read/Write; R = Read only
表7-71. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
BUSY
RW
0b
0b: A fault was NOT declared because the device was busy and unable to
respond.
1b. A fault was declared because the device was busy and unable to respond.
6
OFF
R
0b
LIVE (unlatched) status bit
0b. The unit is enabled and converting power.
1b: The unit is NOT converting power for any reason including simply not being
enabled.
5
4
3
2
VOUT_ OV
IOUT_ OC
VIN_ UV
TEMP
R
R
R
R
0b
0b
0b
0b
0b: An output overvoltage fault has NOT occurred.
1b: An output overvoltage fault has occurred.
0b: An output overcurrent fault has NOT occurred.
1b: An output overcurrent fault has occurred.
0b: An input undervoltage fault has NOT occurred.
1b: An input undervoltage fault has occurred.
0b: A temperature fault/warning has NOT occurred.
1b: A temperature fault/warning has occurred, the host must check
STATUS_TEMPERATURE for more information.
1
0
CML
R
R
0b
0b
0b: A communication, memory, logic fault has NOT occurred.
1b: A communication, memory, logic fault has occurred, the host must check
STATUS_ CML for more information.
NONE OF
THE
ABOVE
0b: A fault other than those listed above has NOT occurred.
1b: A fault other than those listed above has occurred. The host must check the
STATUS_ WORD for more information.
Writing 80h to STATUS_BYTE will clear the BUSY bit, if set.
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7.6.55 (79h) STATUS_WORD
CMD Address
Write Transaction:
Read Transaction:
Format:
79h
Write Word
Read Word
Unsigned Binary (2 bytes)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_WORD command returns two bytes of information with a summary of the most critical faults, such
as overvoltage, overcurrent, overtemperature, and so forth. The low byte of the STATUS_WORD is the same
register as the STATUS_BYTE. The supported STATUS_WORD message content is described in the following
table. The conditions in the STATUS_BYTE are summary information only.
图7-61. (79h) STATUS_WORD Register Map
15
R
14
R
13
12
11
10
9
R
8
R
0
R
R
R
R
VOUT
IOUT
INPUT
MFR
PGOOD
0
OTHER
7
6
5
4
3
2
1
0
RW
R
R
R
R
R
R
R
STATUS_BYTE
LEGEND: R/W = Read/Write; R = Read only
表7-72. Register Field Descriptions
Bit
Field
Access
Reset
Description
15
VOUT
R
0b
0b: An output voltage related fault has NOT occurred.
1b: An output voltage fault has occurred. The host must check STATUS_ VOUT for
more information
14
13
12
11
IOUT
INPUT
MFR
R
R
R
R
0b
0b
0b
0b
0b: An output current related fault has NOT occurred.
1b: An output current fault has occurred. The host must check STATUS_ IOUT for
more information
0b: An input related fault has NOT occurred.
1b: An input fault has occurred. The host must check STATUS_ INPUT for more
information
0b: A Manufacturer-defined fault has NOT occurred.
1b: A Manufacturer-defined fault has occurred. The host must check STATUS_
MFR_ SPECIFIC for more information.
PGOOD
LIVE (unlatched) status bit. Should follow always the value of the PGOOD/
RESET_B pin is asserted.
0b: The output voltage is within the regulation window. PGOOD pin is de-asserted.
1b: The output voltage is NOT within the regulation window. PGOOD pin is
asserted.
10
9
Not
Supported
R
R
0b
0b
Not supported and always set to 0b
OTHER
0b: An OTHER fault has not occurred.
1b: An OTHER fault has occurred, the host must check STATUS_ OTHER for more
information.
8
Not
R
0b
Not supported and always set to 0b.
Supported
7:0
STATUS_
BYTE
RW
00h
Always equal to the STATUS_ BYTE value.
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All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
Writing 0080h to STATUS_WORD will clear the BUSY bit, if set. Writing 0180h to STATUS_WORD will clear both
the BUSY bit and UNKNOWN bit, if set.
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7.6.56 (7Ah) STATUS_VOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Ah
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_VOUT command returns one data byte with contents as follows. All supported bits can be cleared
either by CLEAR_FAULTS, or individually by writing 1b to the (7Ah) STATUS_VOUT register in their position, per
the PMBus 1.3.1 Part II specification section 10.2.4.
图7-62. (7Ah) STATUS_VOUT Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
R
R
VOUT_MIN_MA
X
VOUT_OVF
VOUT_OVW
VOUT_UVW
VOUT_UVF
TON_MAX
0
0
LEGEND: R/W = Read/Write; R = Read only
表7-73. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
VOUT_ OVF
RW
0b
0b: Latched flag indicating VOUT OV fault has NOT occurred.
1b: Latched flag indicating a VOUT OV fault has occurred.
Note: the mask bits for VOUT_ OVF will mask fixed, tracking, and pre-biased OVP.
These can be individually controlled in SMBALERT_ MASK_ EXTENDED.
6
VOUT_
OVW
RW
0b
0b: Latched flag indicating VOUT OV warn has NOT occurred.
1b: Latched flag indicating a VOUT OV warn has occurred.
Note: the mask bits for VOUT_ OVF will mask fixed and tracking Overvoltage
Protection.
5
4
VOUT_
UVW
RW
RW
RW
RW
R
0b
0b
0b: Latched flag indicating VOUT UV warn has NOT occurred.
1b: Latched flag indicating a VOUT UV warn has occurred.
VOUT_ UVF
0b: Latched flag indicating VOUT UV fault has NOT occurred.
1b: Latched flag indicating a VOUT UV fault has occurred.
3
VOUT_
MIN_MAX
0b
0b: Latched flag indicating a VOUT_ MIN_MAX has NOT occurred.
1b: Latched flag indicating a VOUT_ MIN_MAX has occurred.
2
TON_ MAX
0b
0b: Latched flag indicating a TON_ MAX has NOT occurred.
1b: Latched flag indicating a TON_ MAX has occurred.
1:0
Not
00b
Not supported and always set to 00b.
supported
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
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7.6.57 (7Bh) STATUS_IOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Bh
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_IOUT command returns one data byte with contents as follows. All supported bits can be cleared
either by CLEAR_FAULTS, or individually by writing 1b to the (7Bh) STATUS_IOUT register in their position, per
the PMBus 1.3.1 Part II specification section 10.2.4.
图7-63. (7Bh) STATUS_IOUT Register Map
7
6
R
0
5
4
RW
0
3
R
0
2
R
0
1
R
0
0
R
0
RW
RW
IOUT_OCF
IOUT_OCW
LEGEND: R/W = Read/Write; R = Read only
表7-74. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
IOUT_ OCF
RW
0b
0b: Latched flag indicating IOUT OC fault has NOT occurred.
1b: Latched flag indicating IOUT OC fault has occurred.
6
5
Not
Supported
R
RW
R
0b
0b
0b
Not supported and always set to 0b.
IOUT_ OCW
0b: Latched flag indicating IOUT OC warn has NOT occurred.
1b: Latched flag indicating IOUT OC warn has occurred.
4:0
Not
Not supported and always set to 00000b
supported
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
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7.6.58 (7Ch) STATUS_INPUT
CMD Address
Write Transaction:
Read Transaction:
Format:
7Ch
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_INPUT command returns one data byte with contents as follows. All supported bits can cleared
either by CLEAR_FAULTS, or individually by writing 1b to the (7Ch) STATUS_INPUT register in their position,
per the PMBus 1.3.1 Part II specification section 10.2.4.
图7-64. (7Ch) STATUS_INPUT Register Map
7
6
0
5
4
R
0
3
2
R
0
1
R
0
0
R
0
RW
R
RW
RW
VIN_OVF
VIN_UVW
LOW_VIN
LEGEND: R/W = Read/Write; R = Read only
表7-75. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
VIN_OVF
RW
0b
0b: Latched flag indicating PVIN OV fault has NOT occurred.
1b: Latched flag indicating PVIN OV fault has occurred.
6
5
VIN_OVW
VIN_UVW
RW
0b
0b
Not supported and always set to 0b
0b: Latched flag indicating PVIN UV warn occurred.
1b: Latched flag indicating PVIN UV warn has occurred.
4
3
Not
Supported
R
0b
0b
Not supported and always set to 0b.
LOW_ VIN
RW
LIVE (unlatched) status bit. Showing the value of PVIN relative to VIN_ON and
VIN_OFF.
0b: PVIN is ON.
1b: PVIN is OFF.
2:0
Not
R
000b
Not supported and always set to 000b.
Supported
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK .
LOW_VIN vs VIN_UVW
The LOW_VIN bit is an information only (will not assert SMBALERT) flag which indicates that the device is not
converting power because its PVIN voltage is less than VIN_ON or the VDD5 voltage is less than its UVLO to
enable conversion. LOW_VIN asserts initially at reset but does not assert SMBALERT.
The VIN_UVW bit is a latched status bit, can assert SMBALERT if it is triggered to alert the host of an input
voltage issue. VIN_UVW IS masked until the first time the sensed input voltage exceeds the VIN_ON threshold.
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7.6.59 (7Dh) STATUS_TEMPERATURE
CMD Address
Write Transaction:
Read Transaction:
Format:
7Dh
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_TEMPERATURE command returns one data byte with contents as follows. All supported bits can
be cleared either by CLEAR_FAULTS, or individually by writing 1b to the (7Dh) STATUS_TEMPERATURE
register in their position, per the PMBus 1.3.1 Part II specification section 10.2.4.
图7-65. (7Dh) STATUS_TEMPERATURE Register Map
7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
RW
OTF
RW
OTW
LEGEND: R/W = Read/Write; R = Read only
表7-76. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
OTF
RW
0b
0b: Latched flag indicating OT fault has NOT occurred.
1b: Latched flag indicating OT fault has occurred.
6
OTW
RW
R
0b
0d
0b: Latched flag indicating OT warn has NOT occurred.
1b: Latched flag indicating OT warn has occurred
5:0
Not
Not supported and always set to 000000b.
supported
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
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7.6.60 (7Eh) STATUS_CML
CMD Address
Write Transaction:
Read Transaction:
Format:
7Eh
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_CML command returns one data byte with contents relating to communications, logic, and
memory as follows. All supported bits can be cleared either by CLEAR_FAULTS, or individually by writing 1b to
the (7Eh) STATUS_CML register in their position, per the PMBus 1.3.1 Part II specification section 10.2.4.
图7-66. (7Eh) STATUS_CML Register Map
7
6
5
4
3
2
R
0
1
0
R
0
RW
IVC
RW
IVD
RW
PEC
RW
MEM
RW
RW
PROC_FLT
COMM
LEGEND: R/W = Read/Write; R = Read only
表7-77. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
IVC
RW
0b
0b: Latched flag indicating invalid or unsupported command was NOT received.
1b: Latched flag indicating an invalid or unsupported command was received.
6
5
4
3
2
1
0
IVD
PEC
RW
RW
RW
RW
R
0b
0b
0b
0b
0b
0b
0b
0b: Latched flag indicating invalid or unsupported data was NOT received.
1b: Latched flag indicating an invalid or unsupported data was received.
0b: Latched flag indicating NO packet error check has failed.
1b: Latched flag indicating a packet error check has failed.
MEM
0b: Latched flag indicating NO memory error was detected.
1b: Latched flag indicating a memory error was detected.
PROC_FLT
0b: Latched flag indicating NO logic core error was detected.
1b: Latched flag indicating a logic core error was detected.
Not
supported
Not supported and always set to 0b.
COMM
RW
R
0b: Latched flag indicating NO communication error detected.
1b: Latched flag indicating communication error detected.
Not
Not supported and always set to 0b.
supported
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
Loop followers will report a Back-Channel communications issue as a CML fault on their phase.
The corresponding bit STATUS_BYTE is an OR’ing of the supported bits in this command. When a fault
condition in this command occurs, the corresponding bit in STATUS_BYTE is updated. Likewise, if this byte is
individually cleared (for example, by a write of 1 to a latched condition), it must clear the corresponding bit in
STATUS_BYTE.
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7.6.61 (7Fh) STATUS_OTHER
CMD Address
Write Transaction:
Read Transaction:
Format:
7Fh
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
No
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_OTHER command returns one data byte with information not specified in the other STATUS bytes.
图7-67. (7Fh) STATUS_OTHER Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
RW
FIRST_
TO_ALERT
0
0
0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only
表7-78. Register Field Descriptions
Bit
7:1
0
Field
Access
R
Reset
Description
Reserved
0h
Reserved
FIRST_ TO_
ALERT
RW
0b
0b: Latched flag indicating that this device was NOT the first to assert SMBALERT.
This can mean either that the SMBALERT signal is not asserted (or has since been
cleared), or that it is asserted, but this device was not the first on the bus to assert
it.
1b: Latched flag indicating that this device was the first to assert SMBALERT.
The corresponding bit STATUS_BYTE is an OR’ing of the supported bits in this command. When a fault
condition in this command occurs, the corresponding bit in STATUS_BYTE is updated. Likewise, if this byte is
individually cleared (for example, by a write of 1 to a latched condition), it must clear the corresponding bit in
STATUS_BYTE.
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7.6.62 (80h) STATUS_MFR_SPECIFIC
CMD Address
Write Transaction:
Read Transaction:
Format:
80h
Write Byte
Read Byte
Unsigned Binary (1 byte)
Phased:
Yes
NVM Back-up:
Updates:
No
On-the-fly
The STATUS_MFR_SPECIFIC command returns one data byte with contents regard of communications, logic,
and memory as follows. All supported bits can be cleared either by CLEAR_FAULTS, or individually by writing 1b
to the (80h) STATUS_MFR_SPECIFIC register in their position, per the PMBus 1.3.1 Part II specification section
10.2.4.
图7-68. (80h) STATUS_MFR_SPECIFIC Register Map
7
6
R
5
R
0
4
R
0
3
2
1
0
R
0
RW
POR
RW
RW
BCX
RW
SELF
RESET
SYNC
LEGEND: R/W = Read/Write; R = Read only
表7-79. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
POR
RW
0b
0: No Power-On Reset Fault has been detected.
1: A Power-On Reset Fault has been detected.
This bit must be set if: Power-On Self-Check of Internal Trim values,
USER_STORE NVM check-sum, or Pin Detection reports an invalid result.
6
SELF
R
0b
LIVE (unlatched) status bit. Showing the status of the Power-On Self-Check.
0b: Power On Self-Check is complete. All expected BCX loop followers have
responded.
1b: Power-On Self-Check is in progress. One or more BCX loop followers have not
responded.
5:4
3
Not
supported
R
00b
0b:
0b
Not supported and always set to 00b.
RESET
RW
RW
RW
R
0b: A RESET_ VOUT event has NOT occurred.
1b: A RESET_ VOUT event has occurred.
2
BCX
0b: A BCX fault event has NOT occurred.
1b: A BCX fault event has occurred.
1
SYNC
0b
0b: No SYNC fault has been detected.
1b: A SYNC fault has been detected.
0
Not
0b
Not supported and always set to 0b.
supported
Per the PMBus Spec writing a 1 to any bit in a STATUS register shall clear that bit if it is set. All bits which can
trigger SMBALERT have a corresponding bit in SMBALERT_MASK.
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7.6.63 (88h) READ_VIN
CMD Address
Write Transaction:
Read Transaction:
Format:
88h
N/A
Read Word
SLINEAR11 per CAPABILITY
Phased:
Yes
NVM Back-up:
Update Rate:
Supported Range:
No
1ms
0 - 24 V
The READ_VIN command returns the output current in amperes.
图7-69. (88h) READ_VIN Register Map
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
READ_VIN_EXP
READ_VIN_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_VIN_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-80. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
READ_
VIN_ EXP
RW
Input
voltage
Linear format two’s complement exponent
Linear format two’s complement mantissa
10:0
READ_
RW
Input
VIN_ MAN
voltage
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
PHASE Behavior
When PHASE = FFh, READ_VIN returns the PVIN voltage of the Loop Controller device.
When PHASE != FFh, READ_VIN returns the PVIN voltage of the device assigned to the current PHASE.
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7.6.64 (8Bh) READ_VOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
8Bh
N/A
Read Word
ULINEAR16 per VOUT_MODE.
Phased:
Yes
NVM Back-up:
Update Rate:
Supported Range
No
1 ms
0 V to 6.0 V
The READ_VOUT command returns the actual, measured output voltage.
图7-70. (8Bh) READ_VOUT Register Map
15
R
14
R
13
12
11
10
9
8
R
R
R
R
R
R
READ_VOUT
READ_VOUT
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only
表7-81. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
READ_
VOUT
RW
Current
Status
Output voltage reading, per VOUT_ MODE
READ_VOUT will report the voltage at the VOSNS pin with respect to AGND when a device is configured as a
loop follower (GOSNS = BP1V5). In this configuration, VOUT_SCALE_LOOP is ignored and VOSNS must be
externally scaled to maintain a voltage between 0 V and 0.75 V for proper reporting of the VOSNS voltage.
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.65 (8Ch) READ_IOUT
CMD Address
Write Transaction:
Read Transaction:
Format:
8Ch
N/A
Read Word
SLINEAR11 per CAPABILITY
Phased:
Yes
NVM Back-up:
Update Rate:
Supported Range:
No
1 ms
-15 A to 90 A per Phase
The READ_IOUT command returns the output current in amperes.
图7-71. (8Ch) READ_IOUT Register Map
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
READ_IOUT_EXP
READ_IOUT_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_IOUT_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-82. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
READ_
IOUT_ EXP
RW
Current
Status
Linear format two’s complement exponent
Linear format two’s complement mantissa
10:0
READ_
IOUT_ MAN
RW
Current
Status
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
PHASE Behavior
When PHASE = FFh, READ_IOUT returns the total current for the stack of devices supporting a single output.
When PHASE != FFh, READ_IOUT returns the measured current of the device assigned to the current PHASE.
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7.6.66 (8Dh) READ_TEMPERATURE_1
CMD Address
Write Transaction:
Read Transaction:
Format:
8Dh
N/A
Read Word
SLINEAR11 per CAPABILITY
Phased:
Yes
NVM Back-up:
Update Rate:
Supported Range:
No
300 μs
-40°C to 175°C
The READ_TEMPERATURE_1 command returns the maximum power stage temperature in degrees Celsius.
图7-72. (8Dh) READ_TEMPERATURE_1 Register Map
15
R
14
R
13
12
11
10
9
8
R
R
R
R
R
R
READ_T1_EXP
READ_T1_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_T1_MAN
LEGEND: R/W = Read/Write; R = Read only
表7-83. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:11
READ_ T1_
EXP
RW
Current
Status
Linear format two’s complement exponent. LSB = 1°C
Linear format two’s complement mantissa
10:0
READ_ T1_
MAN
RW
Current
Status
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
PHASE Behavior
When PHASE = FFh, READ_TEMPERATURE_1 returns the temperature of the hottest of device in the stack of
devices supporting a single output.
When PHASE ! = FFh, READ_TEMPERATURE_1 returns the measured temperature of the device assigned to
the current PHASE.
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7.6.67 (98h) PMBUS_REVISION
CMD Address
Write Transaction:
Read Transaction:
Format:
98h
N/A
Read Byte
Unsigned Binary (1 byte)
Phased:
No
Max Transaction Time:
0.25 ms
The PMBUS_REVISION command reads the revision of the PMBus to which the device is compliant.
图7-73. (98h) PMBUS_REVISION Register Map
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
PART_I
PART_II
LEGEND: R/W = Read/Write; R = Read only
表7-84. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
R
0011b
0011b: Compliant to PMBus Rev 1.3, Part 1
0011b: Compliant to PMBus Rev 1.3, Part 2
PART_ I
PART_ II
3:0
R
0011b
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.68 (99h) MFR_ID
CMD Address
Write Transaction:
Read Transaction:
Format:
99h
Write Block
Read Block
Unsigned Binary (3 bytes)
No
Phased:
NVM Back-up:
EEPROM
The MFR_ID command loads the unit with 3 bytes that contains the manufacturer’s ID. This is typically done
once at the time of manufacture.
图7-74. (99h) MFR_ID Register Map
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
MFR_ID
MFR_ID
MFR_ID
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
表7-85. Register Field Descriptions
Bit
Field
Access
Reset
Description
23:0
MFR_ ID
RW
NVM
3 bytes of arbitrarily writable user-store NVM for manufacturer ID information.
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7.6.69 (9Ah) MFR_MODEL
CMD Address
Write Transaction:
Read Transaction:
Format:
9Ah
Write Block
Read Block
Unsigned Binary (3 bytes)
No
Phased:
NVM Back-up:
EEPROM
The MFR_MODEL command loads the unit with 3 bytes that contains the manufacturer’s ID. This is typically
done once at the time of manufacture.
图7-75. (9Ah) MFR_MODEL Register Map
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
MFR_MODEL
MFR_MODEL
MFR_MODEL
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
表7-86. Register Field Descriptions
Bit
Field
Access
Reset
Description
23:0
MFR_
RW
NVM
3 bytes of arbitrarily writable user-store NVM for manufacturer model information
MODEL
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7.6.70 (9Bh) MFR_REVISION
CMD Address
Write Transaction:
Read Transaction:
Format:
9Bh
Write Block
Read Block
Unsigned Binary (3 bytes)
No
Phased:
NVM Back-up:
EEPROM
The MFR_REVISION command loads the unit with 3 bytes that contains the power supply manufacturer’s
revision number. This is typically done once at the time of manufacture.
图7-76. (9Bh) MFR_REVISION Register Map
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
MFR_REV
MFR_REV
MFR_REV
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
表7-87. Register Field Descriptions
Bit
Field
Access
Reset
Description
23:0
MFR_ REV
RW
NVM
3 bytes of arbitrarily writable user-store NVM for manufacturer revision information
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7.6.71 (9Eh) MFR_SERIAL
CMD Address
Write Transaction:
Read Transaction:
Format:
9Eh
Write Block
Read Block
Unsigned Binary (3 bytes)
No
Phased:
NVM Back-up:
EEPROM
The MFR_SERIAL command loads the unit with 3 bytes that contains the power supply manufacturer’s serial
number. This is typically done once at the time of manufacture.
图7-77. (9Eh) MFR_SERIAL Register Map
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
MFR_SERIAL
MFR_SERIAL
MFR_SERIAL
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
表7-88. Register Field Descriptions
Bit
Field
Access
Reset
Description
23:00
MFR_
RW
NVM
Arbitrary 3-byte Serial Number assigned by manufacturer
SERIAL
Note: Because the value for MFR_SERIAL is included in the NVM memory store used to calculate the
NVM_CHECKSUM, assigning a unique MFR_SERIAL value will also result in a unique NVM_CHECKSUM
value.
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7.6.72 (ADh) IC_DEVICE_ID
CMD Address
Write Transaction:
Read Transaction:
Format:
ADh
N/A
Read Block
Unsigned Binary (6 bytes)
No
Phased:
The IC_DEVICE_ID command is used to either set or read the type or part number of an IC embedded within a
PMBus that is used for the PMBus interface.
图7-78. (ADh) IC_DEVICE_ID Register Map
47
R
46
R
45
44
43
42
41
R
40
R
R
R
R
R
IC_DEVICE_ID[47:40]
39
R
38
R
37
R
36
R
35
R
34
R
33
R
32
R
IC_DEVICE_ID[39:32]
31
R
30
R
29
R
28
R
27
R
26
R
25
R
24
R
IC_DEVICE_ID[31:24]
23
R
22
R
21
R
20
R
19
R
18
R
17
R
16
R
IC_DEVICE_ID[23:16]
15
R
14
R
13
R
12
R
11
R
10
R
9
8
R
R
IC_DEVICE_ID[15:8]
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
IC_DEVICE_ID[7:0]
LEGEND: R/W = Read/Write; R = Read only
表7-89. Register Field Descriptions
Bit
Field
Access
Reset
Description
47:0
IC_
R
See text. See the table below.
DEVICE_ ID
表7-90. IC_DEVICE_ID Values
Byte Number (Bit
Indices)
Byte 0 (7:0)
54h
Byte 1 (15:8)
Byte 2 (23:16)
Byte 3 (31:24)
Byte 4 (39:32)
Byte 5 (47:40)
TPS546D24S
49h
54h
6Bh
24h
62h
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.73 (AEh) IC_DEVICE_REV
CMD Address
Write Transaction:
Read Transaction:
Format:
AEh
N/A
Read Block
Unsigned Binary (2 bytes)
No
Phased:
The IC_DEVICE_REV command is used to either set or read the revision of the IC.
图7-79. (AEh) IC_DEVICE_REV Register Field Descriptions
15
R
14
R
13
12
11
10
9
8
R
R
R
R
R
R
MAJOR_REV
MINOR_REV
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
SUB_MINOR_REV
LEGEND: R/W = Read/Write; R = Read only
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format:
B1h
Write Block
Read Block
Unsigned Binary (5 bytes)
No
Phased:
NVM Back-up:
EEPROM or Pin Detection
Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. To update hardware
after write while enabled, store to NVM with (15h) STORE_USER_ALL and (16h)
RESTORE_USER_ALL or cycle AVIN below UVLO.
Updates:
Configure the control loop compensation.
图7-80. (B1h) USER_DATA_01 (COMPENSATION_CONFIG) Register Map
39
38
37
36
35
34
33
32
RW
RW
RW
RW
RW
RW
RW
RW
SEL_CZI[1:0]
SEL_CPI[4:0]
SEL_CZI_MUL
31
R
30
29
28
27
26
25
24
RW
RW
RW
RW
RW
RW
RW
SEL_RVI[5:0]
SEL_CZI[3:2]
23
22
21
20
19
18
17
16
RW
0
RW
RW
RW
RW
RW
RW
RW
SEL_CZV[1:0]
SEL_CPV[4:0]
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
SEL_RVV[5:0]
SEL_CZV[3:2]
SEL_GMI[1:0]
7
RW
0
6
RW
0
5
4
3
RW
0
2
RW
0
1
0
RW
RW
RW
RW
SEL_GMV[1:0]
LEGEND: R/W = Read/Write; R = Read only
表7-91. Register Field Descriptions
Bit
Field
Access
Reset
Description
25:24,39:38 SEL_CZI[3:
0]
RW
NVM
Selects the value of current loop integrating capacitor.
CZI = 6.66 pF x CZI_MUL x 2SEL_GMI[1:0] x SEL_CZI[3:0]
37:33
SEL_CPI[4:
0]
RW
RW
NVM
NVM
Selects the value of current loop filter capacitor.
CPI = 3.2 pF x SEL_CPI[4:0]
32
SEL_CZI_M
UL
Selects the value of current loop integrating capacitor multiplier.
0b: CZI_MUL = 1
1b: CZI_MUL = 2
31:26
SEL_RVI[5:
0]
RW
RW
RW
NVM
NVM
NVM
Selects the value of current loop mid-band gain resistor.
RVI = 5 kΩx SEL_RVI[5:0]
9:8, 23:22 SEL_CZV[3:
0]
Selects the value of voltage loop integrating capacitor.
CZV = 125 pF x 2SEL_GMV[1:0] x SEL_CZV[3:0]
21:17
SEL_CPV[4:
0]
Selects the value of voltage loop filter capacitor.
CPV = 6.25 pF x SEL_CPV[4:0]
16
Reserved
RW
RW
NVM
NVM
Reserved, set to 0b
15:10
SEL_RVV[5:
0]
Selects the value of voltage loop mid-band gain resistor.
RVV = 5 kΩx SEL_RVV[5:0]
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表7-91. Register Field Descriptions (continued)
Bit
7:6
5:4
Field
Access
Reset
NVM
NVM
Description
Reserved
RW
Reserved, set to 00b
SEL_GMV[1
:0]
RW
Selects the value of voltage error transconductance.
GMV = 25 µS x 2SEL_GMV[1:0]
3:2
1:0
Reserved
RW
RW
NVM
NVM
Reserved, set to 00b
SEL_GMI[1:
0]
Selects the value of current error transconductance.
GMI = 25 µS x 2SEL_GMI[1:0]
(B1h) USER_DATA_01 (COMPENSATION_CONFIG) can be written to while output conversion is enabled, but
updating those values to hardware will be blocked. To update the value used by the control loop:
• Disable conversion, then write to (B1h) USER_DATA_01 (COMPENSATION_CONFIG).
• Write to (B1h) USER_DATA_01 (COMPENSATION_CONFIG) while conversion is enabled, store PMBus
values to NVM using (15h) STORE_USER_ALL, clear the (B1h) USER_DATA_01
(COMPENSATION_CONFIG) bit in (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE), then cycle AVIN
or use the (16h) RESTORE_USER_ALL command.
Due to the complexity of translating the 5-byte HEX value of (B1h) USER_DATA_01
(COMPENSATION_CONFIG) into analog compensation values, users are recommended to use the tools
available on the TPS546D24S product folder such as the TPS546x24S Compensation and Pin-Strap Resistor
Calculator design tool.
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7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format:
B5h
Write Block (per PMBus Spec, even though 1 data byte)
Read Block (per PMBus Spec, even though 1 data byte)
Unsigned Binary (1 byte)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-the-fly
Max Transaction Time:
Max Action Delay:
1.0 ms
1.0 ms (not time critical)
POWER_STAGE_CONFIG allows the user to adjust the VDD5 regulator voltage.
图7-81. (B5h) USER_DATA_05 (POWER_STAGE_CONFIG) Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
R
R
R
R
SEL_VDD5
Reserved
LEGEND: R/W = Read/Write; R = Read only
表7-92. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:4
SEL_VDD5
RW
NVM
3h: VDD5 = 3.9 V (Not Recommended for Production)
4h: VDD5 = 4.1 V
5h: VDD5 = 4.3 V
6h: VDD5 = 4.5 V
7h: VDD5 = 4.7 V
8h: VDD5 = 4.9 V
9h: VDD5 = 5.1 V
Ah: VDD5 = 5.3 V
Other: Invalid
3:0
Reserved
R
0000b
Reserved. Set to 0000b.
Setting 30h is not recommended for production use unless an external VDD5 voltage is provided because the
3.9-V LDO setting can result in a VDD5 voltage less than the VDD5 undervoltage lockout required to enable
conversion and can result in the TPS546D24S device being unable to enable conversion without an external
VDD5 voltage.
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7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format:
D0h
Write Block
Read Block
Unsigned Binary (6 bytes)
No
Phased:
NVM Back-up:
Updates:
EEPROM
On-The-Fly
Configure the priority and averaging for each channel of the internal telemetry system.
The internal telemetry system shares a single ADC across each measurement. The priority setting allows the
user to adjust the relative rate of measurement of each telemetry value. The ADC will first measure each value
with a priority A value. With each pass through all priority A measurements, one priority B measurement will be
taken. With each pass through all priority B measurements, one priority C measurement will be taken.
Example: If output voltage has priority A and output current has priority B, and temperature has priority C, the
telemetry sequence will be VOUT IOUT VOUT TEMPERATURE VOUT IOUT VOUT TEMPERATURE.
图7-82. (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG) Register Map
47
46
45
44
43
42
41
40
RW
RW
RW
RW
RW
RW
RW
RW
Reserved priority
Reserved
Reserved averaging
39
38
37
36
RW
35
34
33
RW
32
RW
RW
RW
RW
RW
RW
Reserved priority
Reserved
Reserved averaging
31
R
30
29
28
RW
27
26
25
RW
24
RW
RW
RW
RW
RW
RD_VI_PRI
Reserved
RD_VI_AVG
23
22
21
20
RW
19
18
17
RW
16
RW
RW
RW
RW
RW
RW
RD_TMP_PRI
Reserved
RD_TMP_AVG
15
14
13
12
RW
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RD_IO_PRI
Reserved
RD_IO_AVG
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RD_VO_PRI
Reserved
RD_VO_AVG
LEGEND: R/W = Read/Write; R = Read only
表7-93. Register Field Descriptions
Bit
Field
Access
R
Reset
Description
47:40
39:32
31:30
Not used
Not used
RD_VI_PRI
00h
Reserved. Set values to 00h.
Reserved. Set values to 03h.
RW
NVM
NVM
RW
00b: Assign priority A to input voltage telemetry.
01b: Assign priority B to input voltage telemetry.
10b: Assign priority C to input voltage telemetry.
11b: Disable input voltage telemetry.
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表7-93. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
31:24
RD_VI_AVG
RW
NVM
0d - 5d: READ_VIN Rolling average of 2N samples
6d-7d: Invalid
23:22
RD_TMP_P
RI
RW
NVM
00b: Assign priority A to temperature telemetry.
01b: Assign priority B to temperature telemetry.
10b: Assign priority C to temperature telemetry.
11b: Invalid
21:19
18:16
Reserved
RW
RW
NVM
NVM
Reserved. Set to 000b.
RD_TMP_A
VG
0d - 5d: READ_TEMPERATURE_1 Rolling average of 2N samples
6d-7d: Invalid
15:14
RD_IO_PRI
RW
NVM
00b: Assign priority A to output current telemetry.
01b: Assign priority B to output current telemetry.
10b: Assign priority C to output current telemetry.
11b: Disable output current telemetry.
13:11
10:8
Reserved
RW
RW
NVM
NVM
Reserved. Set to 000b.
RD_IO_AVG
0d - 5d: READ_IOUT Rolling average of 2N samples
6d-7d: Invalid
7:6
RD_VO_PRI
RW
NVM
00b: Assign priority A to output voltage telemetry.
01b: Assign priority B to output voltage telemetry.
10b: Assign priority C to output voltage telemetry.
11b: Disable output voltage telemetry.
5:3
2:0
Reserved
RW
RW
NVM
NVM
Reserved. Set to 000b.
RD_VO_AV
G
0d - 5d: READ_VOUT Rolling average of 2N samples
6d-7d: Invalid
Disabling any telemetry value will force the associated READ PMBus command to report 0000h.
Because temperature telemetry is used for Overtemperature Protection, temperature telemetry cannot be
disabled.
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7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
CMD Address
Write Transaction:
Read Transaction:
Format:
DAh
NA
Read Block
Unsigned Binary (14 bytes)
Phased:
No
No
NVM Back-up:
READ_ALL provides for a 14-byte BLOCK read of STATUS_WORD and telemetry values to improve bus usage
for poling by combining multiple READ functions into a single command, eliminating the need for multiple
address and command code bytes.
图7-83. (DAh) MFR_SPECIFIC_10 (READ_ALL) Register Map
111
R
110
R
109
108
107
106
105
R
104
R
R
R
R
R
Not Supported = 00h
103
R
102
R
101
R
100
R
99
R
98
R
97
R
96
R
Not Supported = 00h
95
R
94
R
93
R
92
R
91
R
90
R
89
R
88
R
Not Supported = 00h
87
R
86
R
85
R
84
R
83
R
82
R
81
R
80
R
Not Supported = 00h
79
R
78
R
77
R
76
R
75
R
74
R
73
R
72
R
READ_VIN (MSB)
71
R
70
R
69
R
68
R
67
R
66
R
65
R
64
R
READ_VIN (LSB)
63
R
62
R
61
R
60
R
59
R
58
R
57
R
56
R
READ_TEMPERATURE1 (MSB)
55
R
54
R
53
R
52
R
51
R
50
R
49
R
48
R
READ_TEMPERATURE1 (LSB)
47
R
46
R
45
R
44
R
43
R
42
R
41
R
40
R
READ_IOUT (MSB)
39
R
38
R
37
R
36
R
35
R
34
R
33
R
32
R
READ_IOUT (LSB)
28 27
31
30
29
26
25
24
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R
R
R
R
R
R
R
R
READ_VOUT (MSB)
23
R
22
R
21
R
20
R
19
R
18
R
17
R
16
R
READ_VOUT (LSB)
15
R
14
R
13
R
12
R
11
R
10
R
9
8
R
R
STATUS_WORD (High Byte)
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
STATUS_BYTE
LEGEND: R/W = Read/Write; R = Read only
表7-94. Register Field Descriptions
Bit
Field
Access
Reset
Description
111:96
READ_
DUTY_CYC
LE
R
0000h
Not supported = 0000h
95:80
79:64
63:48
READ_ IIN
READ_ VIN
R
R
R
0000h
0000h
0000h
Not supported = 0000h
READ_VIN (Linear Format)
READ_
TEMPERAT
URE1
READ_ TEMPERATURE1 (Linear Format)
47:32
31:16
15:0
READ_
IOUT
R
R
R
0000h
0000h
0000h
READ_ IOUT (Linear Format)
READ_VOU
T
READ_ VOUT (ULinear16 Format, Per VOUT_MODE)
STATUS_WORD
STATUS_W
ORD
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
CMD Address
Write Transaction:
Read Transaction:
Format:
DBh
NA
Read Block
Unsigned Binary (7 bytes)
Phased:
No
No
NVM Back-up:
STATUS_ALL provides for a 7-byte block of STATUS command codes. This can reduce bus usage to read
multiple faults.
图7-84. (DBh) MFR_SPECIFIC_11 (STATUS_ALL) Register Map
55
R
54
R
53
52
51
50
49
R
48
R
R
R
R
R
STATUS_MFR
47
R
46
R
45
R
44
R
43
R
42
R
41
R
40
R
STATUS_OTHER
39
R
38
R
37
R
36
35
R
34
R
33
R
32
R
R
STATUS_CML
31
R
30
R
29
R
28
R
27
R
26
R
25
R
24
R
STATUS_TEMPERATURE
23
R
22
R
21
R
20
R
19
R
18
R
17
R
16
R
STATUS_INPUT
15
R
14
R
13
R
12
R
11
R
10
R
9
8
R
R
STATUS_IOUT
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
STATUS_VOUT
LEGEND: R/W = Read/Write; R = Read only
表7-95. Register Field Descriptions
Bit
Field
Access
Reset
Description
55:48
STATUS_
MFR
R
Current
Status
STATUS_ MFR
47:40
39:32
31:24
STATUS_
OTHER
R
R
R
Current
Status
STATUS_ OTHER
STATUS_
CML
Current
Status
STATUS_ CML
STATUS_
TEMPERAT
URE
Current
Status
STATUS_ TEMPERATURE
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表7-95. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
23:16
STATUS_
INPUT
R
Current
Status
STATUS_ INPUT
15:8
7:0
STATUS_
IOUT
R
R
Current
Status
STATUS_ IOUT
STATUS_ VOUT
STATUS_
VOUT
Current
Status
Attempts to write read-only commands cause the CML: invalid command (IVC) fault condition, the TPS546D24S
responds as follows:
• Set the CML bit in STATUS_BYTE.
• Set the CML_IVC (bit 7) bit in STATUS_CML.
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Writes to STATUS_ALL do not clear asserted status bits.
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7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
CMD Address
Write Transaction:
Read Transaction:
Format:
DCh
Write Word
Read Word
Unsigned Binary (2 bytes)
Phased:
Yes
Updates:
On-the-fly
No
NVM Back-up:
When PHASE = FFh or 80h, reads to this command return a data word detailing which phases have
experienced fault conditions. When PHASE != FFh, reads to this command return a data worddetailing which
faults the current PHASE has experienced. PHASE number assignment is per PHASE_CONFIG. Bits
corresponding to unused (unassigned or disabled) phase numbers are always equal to 0b.
图7-85. (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
15
R
14
R
13
R
12
R
11
RW
0
10
RW
0
9
RW
0
8
RW
0
7
RW
0
6
RW
0
5
RW
0
4
RW
0
3
2
1
0
RW
PH3
RW
PH2
RW
PH1
RW
PH0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only
表7-96. Register Field Descriptions
Bit
15:4
3
Field
Reserved
PH3
Access
R
Reset
Description
0b
Reserved
RW
0b
0b: The TPS546D24S assigned to PHASE = 3d has NOT experienced a fault.
1b: The TPS546D24S assigned to PHASE = 3d has experienced a fault. Set
PHASE = 3d, and read STATUS_WORD or STATUS_ALL for more information.
2
1
0
PH2
PH1
PH0
RW
RW
RW
0b
0b
0b
0b: The TPS546D24S assigned to PHASE = 2d has NOT experienced a fault.
1b: The TPS546D24S assigned to PHASE = 2d has experienced a fault. Set
PHASE = 2d, and read STATUS_WORD or STATUS_ALL for more information.
0b: The TPS546D24S assigned to PHASE = 1d has NOT experienced a fault.
1b: The TPS546D24S assigned to PHASE = 1d has experienced a fault. Set
PHASE = 1d, and read STATUS_WORD or STATUS_ALL for more information.
0b: The TPS546D24S assigned to PHASE = 0d has NOT experienced a fault.
1b: The TPS546D24S assigned to PHASE = 0d has experienced a fault. Set
PHASE = 0d, and read STATUS_WORD or STATUS_ALL for more information.
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7.6.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format
E3h
Write Word
Read Word
Unsigned Word
Phased:
No
NVM Backup:
Updates:
EEPROM or Pin Detect
Conversion Disable: see below. Conversion Enable: Read-Only
图7-86. (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG) Register Map
15
R
14
13
12
11
10
9
8
R
R
R
R
R
R
R
PGOOD_OFF_DELAY[3:0]
PGOOD_ON_DELAY[3:0]
7
R
6
R
5
R
4
R
3
2
1
0
RW
RW
RW
RW
pgmOVF
pgmOVW
pgmUVW
pgmUVF
pgmOCW
pgmOCF
pgmINOVW
pgmINOVF
LEGEND: R/W = Read/Write; R = Read only
表7-97. Register Field Descriptions
Bit
Field
Access
Reset
Description
NVM
15:12
PGOOD_OF
F_DELAY[3:
0]
RW
Sets Delay from the detection of an unmasked Fault or Warning event to the
assertion of PGOOD low.
0d: Delay PGOOD high-low 1 PWM CLK
1d-15d: Delay PGOOD high-low 2N+1 PWM CLKs
NVM
11:8
PGOOD_O
N_DELAY[3:
0]
RW
Sets Delay from the detection of no unmasked Fault or Warning events to the
release of PGOOD low.
0d: Delay PGOOD low-hight to 1 PWM CLK
1d-15d: Delay PGOOD low-high 2N+1 PWM CLKs
7
6
5
4
3
2
1
0
pgmOVF
pgmOVW
pgmUVF
RW
RW
RW
RW
RW
RW
RW
RW
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
0b: Output Overvoltage Fault can assert PGOOD low.
1b: Output Overvoltage Fault cannot assert PGOOD low.
0b: Output Overvoltage Warning can assert PGOOD low.
1b: Output Overvoltage Warning cannot assert PGOOD low.
0b: Output Undervoltage Fault can assert PGOOD low.
1b: Output Undervoltage Fault cannot assert PGOOD low.
pgmUVW
pgmOCW
pgmOCF
0b: Output Undervoltage Warning can assert PGOOD low.
1b: Output Undervoltage Warning cannot assert PGOOD low.
0b: Output Overcurrent Warning can assert PGOOD low.
1b: Output Overcurrent Warning cannot assert PGOOD low.
0b: Output Overcurrent Fault can assert PGOOD low.
1b: Output Overcurrent Fault cannot assert PGOOD low.
pgmINOVW
pgmINOVF
0b: Input Overvoltage Warning can assert PGOOD low.
1b: Input Overvoltage Warning cannot assert PGOOD low.
0b: Input Overvoltage Fault can assert PGOOD low.
1b: Input Overvoltage Fault cannot assert PGOOD low.
Power Good indicates the status of the converter. (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG) provides
control of the delays asserting and releasing Power Good. Power Good is always low while conversion is
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disabled, during (60h) TON_DELAY, (61h) TON_RISE, (65h) TOFF_FALL, and during a fault shut-down or
hiccup delay. PGOOD_OFF_DELAY is bypassed during (65h) TOFF_FALL and during a fault shut-down or
hiccup. Power Good will still be asserted on an unmasked fault event unless that fault's RESPONSE command
is configured to Continue Operating without Interruption.
PGOOD_OFF_DELAY and PGOOD_ON_DELAY are sensed and timed independently from each other. If
PGOOD_ON_DELAY is less than PGOOD_OFF_DELAY and an unmasked fault or warning event lasts less than
PGOOD_OFF_DELAY - PGOOD_ON_DELAY, Power Good will not be asserted low during the fault or warning
events.
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7.6.81 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format:
E4h
Write Byte
Read Byte
Unsigned Binary
No
Phased:
NVM Back-up:
Updates:
EEPROM or Pin Detect
On-the-fly
图7-87. (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) Register Map
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
SYNC_ DIR
SYNC_EDGE
10000b
LEGEND: R/W = Read/Write; R = Read only
表7-98. Register Field Descriptions
Bit
Field
Access
Reset
Description
7:6
SYNC_DIR
RW
NVM
00b: SYNC disabled
01b: Enable SYNC OUT.
10b: Enable SYNC IN.
11b: Enable Auto Detect SYNC
5
SYNC_EDG
E
RW
RW
NVM
0b: Synchronize to falling edge of SYNC.
1b: Synchronize to rising edge of SYNC.
4:0
Not
10000b
Not supported. Set to 10000b.
supported
Attempts to write (E4h) MFR_SPECIFIC_E4 (SYNC_CONFIG) to any value outside those specified as valid will
be considered invalid/unsupported data and cause the TPS546D24S to respond by flagging the appropriate
status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
When SYNC_DIR = 11b - Enable Auto Detect, the TPS546D24S will select SYNC_IN or SYNC_OUT based on
the state of the SYNC pin when the Enable Condition, as defined by ON_OFF_CONFIG is met. If the SYNC_PIN
is >2 V or switching faster than 75% of FRQUENCY_SWITCH, SYNC_IN shall be enabled. If the SYNC_PIN is
less than 0.8 V and not switching, SYNC_OUT will be selected.
Changing SYNC_DIR from SYNC_IN to SYNC_OUT on a multi-phase stack while conversion is enabled but
prevented due to a SYNC_FAULT results in the internal oscillator operating at 70% of its nominal frequency.
Because this result is outside of the ensured SYNC_IN range of the loop follower device, this can result in
unsynchronized operation.
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7.6.82 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
CMD Address
Write Transaction:
Read Transaction:
Format
ECh
Write Word
Read Word
Unsigned Word
Phased:
No
NVM Backup:
Updates:
EEPROM or Pin Detect
Conversion Disable: see below. Conversion Enable: Read-Only
图7-88. (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) Register Map
15
R
14
13
12
11
10
9
8
R
R
R
R
R
R
R
Reserved 0000h
7
6
5
4
3
2
1
0
R
R
R
R
RW
RW
RW
RW
BCX_START
BCX_STOP
LEGEND: R/W = Read/Write; R = Read only
表7-99. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:8
Not
R
0000h
Reserved. Equal 0000h.
supported
7:4
3:0
BCX_STAR
T
R
0000b
NVM
BCX_Address for Stack Loop Controller. Equal to 0000b.
BCX_STOP
RW
0000b: Stand Alone, Single-phase
0001b: One Loop Follower, 2-phase
0010b: Two Loop Followers, 3-phase
0011b: Three Loop Followers, 4-phase
Other: Not supported / Invalid
Attempts to write (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) to any value outside those specified as valid,
will be considered invalid/unsupported data and cause TPS546D24S to respond by flagging the appropriate
status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
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7.6.83 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
CMD Address
Write Transaction:
Read Transaction:
Format:
EDh
Write Word
Read Word
Unsigned Binary (2 bytes)
No
Phased:
NVM Backup:
Updates:
EEPROM
on-the-fly
MFR_SPECIFIC_29 is used to configure miscellaneous settings.
图7-89. (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
Reserv
ed
PEC
RESET_CNT
RESET_FLT
RESET#
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserv
ed
Reserved
Reserved
Reserved
PULLUP#
FLT_CNT
ADC_RES
LEGEND: R/W = Read/Write; R = Read only
表7-100. Register Field Descriptions
Bit
Field
Access
Reset
Description
15
PEC
RW
NVM
0b: PEC Optional. Transactions received without PEC byte will be processed.
1b: PEC Required. Transactions received without PEC byte will be rejected as
invalid PEC.
14
13
12
RESET_CN
T
RW
RW
RW
NVM
NVM
NVM
0b: VOUT_COMMAND will be unchanged following a shutdown.
1b: VOUT_COMMAND will be changed to VBOOT on a Control or OPERATION
shutdown.
RESET_FLT
RESET#
0b: VOUT_COMMAND will be unchanged following a Fault Restart.
1b: VOUT_COMMAND will be changed to VBOOT on Restart from a Fault when
Fault Retry is set to Retry after Fault.
Sets the function of the PGD/RESET_B pin.
0b: PGD/RESET_B functions as PGOOD and internal pullup is disabled.
1b: PGD/RESET_B functions as RESET# and internal pullup is set by bit 3
PULLUP#.
11:3
3
Reserved
PULLUP#
RW
RW
NVM
NVM
Reserved. Must be 000000000b
Sets the pullup of the PGD/RESET_B pin when RESET# = 1b.
0b: Internal pullup of PGD/RESET_B pin enabled when RESET# = 1b.
1b: Internal pullup of PGD/RESET_B pin disabled when RESET# = 1b.
2
FLT_CNT
ADC_RES
RW
RW
NVM
NVM
0b: Fault Counter counts down one cycle on PWM cycle without fault
1b: Fault Counter resets counter to 0 on PWM cycle without fault
1:0
ADC Resolution Control
00b: Set ADC Resolution to 12-bit
01b: Set ADC Resolution to 10-bit
10b: Set ADC Resolution to 8-bit
11b: Set ADC Resolution to 6-bit
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7.6.84 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
CMD Address
Write Transaction:
Read Transaction:
Format:
EEh
Write Word
Read Word
Unsigned Binary (1 byte)
Phased:
No
NVM Backup:
Updates:
EEPROM
on-the-fly (pin detection occurs on POR only).
PMBUS specified that NVM (Default or User) stored values will overwrite Pin Programmed Values. Setting a
“1” in each bit of this register will prevent DEFAULT or USER STORE values from overwriting the Pin-
Programmed Value associated that bit.
图7-90. (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
STACK_CONFI
G
COMP_CONFI
G
Reserved
SYNC_CONFIG
Reserved
ADDRESS
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
INTERLEAVE
Reserved
TON_RISE
IOUT_OC
FREQ
VOUT
LEGEND: R/W = Read/Write; R = Read only
表7-101. Register Field Descriptions
Bit
15:13
12
Field
Access
RW
Reset
NVM
NVM
Description
Reserved
Not used and set to 000b.
STACK_CO
NFIG
RW
0b: At power-up or RESTORE, STACK_CONFIG will be reset to NVM value.
1b: At power-up or RESTORE, STACK_CONFIG will be reset to pin-detected
value.
11
SYNC_CON
FIG
RW
NVM
0b: At power-up or RESTORE, SYNC_CONFIG will be reset to NVM value.
1b: At power-up or RESTORE, SYNC_CONFIG will be reset to pin-detected value.
10
9
Reserved
RW
RW
NVM
NVM
Not used and set to 0b or 1b.
COMP_CO
NFIG
0b: At power-up or RESTORE, COMPENSATION_CONFIG will be reset to NVM
value.
1b: At power-up or RESTORE, COMPENSATION_CONFIG will be reset to pin-
detected value.
8
ADDRESS
RW
NVM
0b: At power-up or RESTORE, DEVICE_ADDRESS will be reset to NVM value.
1b: At power-up or RESTORE, DEVICE_ADDRESS will be reset to pin-detected
value.
7:6
5
Reserved
RW
RW
NVM
NVM
Not used and set to 00b.
INTERLEAV
E
0b: At power-up or RESTORE, INTERLEAVE will be reset to NVM value.
1b: At power-up or RESTORE, INTERLEAVE will be reset to pin-detected value.
4
3
Reserved
RW
RW
NVM
NVM
Not used and set to 0b or 1b.
TON_RISE
0b: At power-up or RESTORE, TON_RISE will be reset to NVM value.
1b: At power-up or RESTORE, TON_RISE will be reset to pin-detected value.
2
IOUT_OC
FREQ
RW
NVM
0b: At power-up or RESTORE, IOUT_OC_FAULT_LIMIT and
IOUT_OC_WARN_LIMIT will be reset to NVM value.
1b: At power-up or RESTORE, IOUT_OC_FAULT_LIMIT and
IOUT_OC_WARN_LIMIT will be reset to pin-detected value.
1
RW
NVM
0b: At power-up or RESTORE, FREQUENCY_SWITCH will be reset to NVM value.
1b: At power-up or RESTORE, FREQUENCY_SWITCH will be reset to pin-
detected value.
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表7-101. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
0
VOUT
RW
NVM
0b: At power-up or RESTORE, VOUT_COMMAND, VOUT_SCALE_LOOP,
VOUT_MAX, and VOUT_MIN will be reset to NVM value.
1b: At power-up or RESTORE, VOUT_COMMAND, VOUT_SCALE_LOOP,
VOUT_MAX, and VOUT_MIN will be reset to pin-detected value.
PIN_DETECT_OVERRIDE allows the user to force Pin Detected values to override the User Store NVM value
for various PMBus commands during Power On Reset and RESTORE_USER_ALL.
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7.6.85 (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS)
CMD Address
Write Transaction:
Read Transaction:
Format:
EFh
Write Byte
Read Byte
Unsigned Binary (1 bytes)
No
Phased:
NVM Backup:
Updates:
EEPROM or Pin Detect
on-the-fly
The DEVICE_ADDRESS command can be used to program or read-back the device address of digital
communication. Note, when a device address is updated, the TPS546D24S starts responding to the new
address immediately.
图7-91. (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS) Register Map
7
R
0
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
ADDR_PMBUS
LEGEND: R/W = Read/Write; R = Read only
表7-102. Register Field Descriptions
Bit
Field
Access
Reset
Description
7
Not
R
0b
Not supported. Set to b'0.
supported
6:0
ADDR_
PMBUS
RW
NVM/
Pinstrap
PMBus device address
There are a number of device address values which are reserved in the SMBus specification. The following
reserved addresses are invalid and can not be programmed:
• 0x0C
• 0x28
• 0x37
• 0x61
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7.6.86 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
CMD Address
Write Transaction:
Read Transaction:
Format:
F0h
NA
Read Word
Unsigned Binary (2 bytes)
Phased:
No
NVM Back-up:
Updates:
EEPROM
At boot-up, and following NVM Store/Restore operations.
NVM_CHECKSUM reports the CRC-16 (polynomial 0x8005) checksum for the current NVM settings.
图7-92. (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM) Register Map
15
R
14
13
12
11
10
9
8
R
R
R
R
R
R
R
NVM_CHECKSUM
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
NVM_CHECKSUM
LEGEND: R/W = Read/Write; R = Read only
表7-103. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
NVM_
CHECKSU
M
R
Per NVM CRC16 for EEPROM settings.
Settings
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7.6.87 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
CMD Address
Write Transaction:
Read Transaction:
Format:
F1h
Write Word
Read Word
Unsigned Binary (2 bytes)
Phased:
Yes
No
NVM Back-up:
SIMULATE_FAULT will allow the user to simulate fault and warning conditions by triggering the output of the
detection circuit for that controls it. Multiple faults and or can be simulated at once.
图7-93. (F1h) MFR_SPECIFIC_F1 (SIMULATE_FAULT) Register Map
15
14
13
12
11
10
9
8
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
FAULT_PERSI SIM_TEMP_OT
SIM_IOUT_OC
F
SIM_VOUT_UV SIM_VOUT_OV
Reserved
SIM_VIN_OFF SIM_VIN_OVF
ST
F
F
F
7
6
5
4
3
2
1
0
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
WARN_PERSIS
T
SIM_IOUT_OC
W
SIM_VOUT_UV SIM_VOUT_OV
Reserved
Reserved
SIM_VIN_UVW
Reserved
W
W
LEGEND: R/W = Read/Write; R = Read only
表7-104. Register Field Descriptions
Bit
Field
Access
Reset
Description
15
FAULT_PER
SIST
W/R
0b
0b: Simulated faults are automatically removed after one fault response.
1b: Simulated faults persist until SIMULATE_FAULTS is written again.
14
13
12
11
10
9
SIM_TEMP_
OTF
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
0b
0b
0b
0b
0b
0b
0b
0b: No change
1b: Simulate overtemperature fault
Reserved
0b: No change
1b: Not used
SIM_IOUT_
OCF
0b: No change
1b: Simulate output current overcurrent fault.
SIM_VIN_O
FF*
0b: No change
1b: Simulate PVIN undervoltage lockout.
SIM_VIN_O
VF
0b: No change
1b: Simulate PVIN overvoltage fault.
SIM_VOUT_
UVF
0b: No change
1b: Simulate VOUT undervoltage fault.
8
SIM_VOUT_
OVF*
0b: No change
1b: Simulate VOUT overvoltage fault.
7
WARN_PER
SIST
Default
Settings
0b: Simulated warnings are automatically removed after one Fault response.
1b: Simulated warnings persist until SIMULATE_FAULTS is written again.
6
Reserved
Default
Settings
0b: No change
1b: Not used
5
Reserved
Default
Settings
0b: No change
1b: Not used
4
SIM_IOUT_
OCW
Default
Settings
0b: No change
1b: Simulate output current overcurrent warning.
3
SIM_VIN_U
VW
Default
Settings
0b: No change
1b: Simulate PVIN undervoltage warning.
2
Reserved
Default
Settings
0b: No change
1b: Not used
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表7-104. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
1
SIM_VOUT_
UVW
W/R
Default
Settings
0b: No change
1b: Simulate VOUT undervoltage warning.
0
SIM_VOUT_
OVW
W/R
Default
Settings
0b: No change, 1b: Simulate VOUT overvoltage warning.
*Only SIM_VIN_OFF and SIM_VOUT_OVF are allowed to trigger their analog comparator while conversion is
disabled. All other faults, including SIM_TEMP_OTF and SIM_VIN_OVF will only simulate while conversion is
enabled to allow these faults to simulate repeated shut-down and restart responses when FAULT_PERSIST is
selected.
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7.6.88 (FAh) MFR_SPECIFIC_42 (PASSKEY)
CMD Address
Write Transaction:
Read Transaction:
Format:
FAh
Write Word
Read Word
Unsigned Binary (2 bytes)
No
Phased:
NVM Back-up:
Updates:
EEPROM
At Boot-up
PASSKEY sets a User Programmable 16-bit passkey to disable write access to EXT_WRITE_PROTECT and
User Store Non-Volatile Memory (NVM). When PASSKEY is set to 0000h, access to STORE_USER_ALL is
enabled and writes to PASSKEY will update the active register value for PASSKEY. When PASSKEY is set to a
value other than 0000h during boot-up, write access to EXT_WRITE_PROTECT and STORE_USER_ALL is
disabled until the 16-bit word stored in NVM at boot-up is written to PASSKEY.
If 3 writes to PASSKEY are received that do not match the passkey without receiving a write that does match the
passkey, PASSKEY access will be locked and all future writes to PASSKEY will be treated as invalid until the
device receives a Power On Reset
To protect against unauthorized access to PASSKEY, reading PASSKEY will not respond with the passkey value
but a fixed 16-bit word response based on the state of the PASSKEY
1. 0000h - PASSKEY is Unlocked
2. 000Fh - PASSKEY is Locked and no invalid writes have been made
3. 001Fh - PASSKEY is Locked and one invalid write has been made
4. 002Fh - PASSKEY is Locked and two invalid writes have been made
5. 00FFh - PASSKEY is Locked and three or more invalid writes have been made
图7-94. (FAh) MFR_SPECIFIC_42 (PASSKEY) Register Map
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
PASSKEY
PASSKEY
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
表7-105. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
PASSKEY
RW
NVM
Write: PASSKEY passkey
Read:
•
•
•
•
•
0000h - PASSKEY is Unlocked
000Fh - PASSKEY is Locked and no invalid writes have been made
001Fh - PASSKEY is Locked and one invalid write has been made
002Fh - PASSKEY is Locked and two invalid writes have been made
00FFh - PASSKEY is Locked and three or more invalid writes have been made
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7.6.89 (FBh) MFR_SPECIFIC_43 (EXT_WRITE_PROTECT)
CMD Address
Write Transaction:
Read Transaction:
Format:
FBh
Write Word
Read Word
Unsigned Binary (2 bytes)
No
Phased:
NVM Back-up:
Updates:
EEPROM
At Boot-up
EXT_WRITE_PROTECT provides the user with greater resolution to Write Protect features than the Standard
PMBus Function. Each bit in the EXT_WRITE_PROTECT provides individual and independent
WRITE_PROTECTION.
图7-95. (FBh) MFR_SPECIFIC_43 (EXT_WRITE_PROTECT) Register Map
15
14
13
12
11
10
9
8
RW
RW
WP
RW
RW
RW
VOF
RW
WN
RW
ITF
RW
MAR
HWP
TRIM
VOUT
7
6
5
4
3
2
1
0
RW
OP
RW
CFG
RW
VIN
RW
SEQ
RW
DAT
RW
BOT
RW
PSK
RW
STR
LEGEND: R/W = Read/Write; R = Read only
表7-106. Register Field Descriptions
Bit
Field
Access
Reset
Description
HWP
NVM
Command List: EXT_WRITE_PROTECT (This command), PASSKEY
0b: Commands are Writable unless:
15
RW
a. EXT_WRITE_PROTECT is Write Protected by PASSKEY
b. PASSKEY is Write Protected by EXT_WRITE_PROTECT[1]
1b: Commands are Read Only (if stored to NVM, this will permanently lock
EXT_WRITE_PROTECT)
14
13
WP
RW
RW
NVM
NVM
Command List: WRITE_PROTECT (Standard PMBus Command)
0b: Commands are Writable (No other command controls write access to
WRITE_PROTECT
1b: Commands are Read Only
TRIM
Command List: VOUT_TRIM, VOUT_SCALE_LOOP, IOUT_CAL_GAIN,
IOUT_CAL_OFFSET
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
12
11
VOUT
VOF
RW
RW
NVM
NVM
Command List: VOUT_MODE, VOUT_COMMAND
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
Command List: VOUT_MAX, VOUT_OV_FAULT_LIMIT,
VOUT_OV_FAULT_RESPONSE, VOUT_UV_FAULT_LIMIT,
VOUT_UV_FAULT_RESPONSE, VOUT_MIN
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
10
9
WN
ITF
RW
RW
NVM
NVM
Command List: VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
IOUT_OC_WARN_LIMIT, OT_WARN_LIMIT, SMBALERT_MASK
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
Command List: IOUT_OC_FAULT_LIMIT, IOUT_OC_FAULT_RESPONSE,
OT_FAULT_LIMIT, OT_FAULT_RESPONSE, SIMULATE_FAULTS
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
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表7-106. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
8
MAR
RW
NVM
Command List: VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW,
VOUT_TRANSITION_RATE
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
7
6
OP
RW
RW
NVM
NVM
Command List: OPERATION
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
CFG
Command List: FREQUENCY_SWITCH, INTERLEAVE,
COMPENSATION_CONFIG, TRANSIENT_REDUCTION_CONFIG,
TELEMETRY_CONFIG, POWER_STAGE_CONFIG, PGOOD_CONFIG,
SYNC_CONFIG, MISC_OPTIONS, STACK_CONFIG
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
5
4
VIN
RW
RW
NVM
NVM
Command List: VIN_UV_WARN_LIMIT, VIN_OV_FAULT_LIMIT,
VIN_OV_WARN_LIMIT, VIN_OV_FAULT_RESPONSE
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
SEQ
Command List: TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT,
TON_MAX_FAULT_RESPONSE, TOFF_DELAY, TOFF_FALL, and
ON_OFF_CONFIG, VIN_ON, VIN_OFF
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
3
2
1
DAT
BOT
PSK
RW
RW
RW
NVM
NVM
NVM
Command List: MFR_ID, MFR_MODEL, MFE_REVISION, MFR_SERIAL
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
Command List: PIN_DETECT_OVERRIDE, PMBUS_ADDRESS
0b: Command are Writable unless Read Only from WRITE_PROTECT
1b: Commands are Read Only
Command List: PASSKEY
0b: Commands are Writable unless Write Protected by WRITE_PROTECT
1b: Commands are Read Only
备注
Because PASSKEY write protects EXT_WRITE_PROTECT when
PASSKEY != 0000h, setting this bit when PASSKEY != 0000h and
storing to NVM permanently locks access to EXT_WRITE_PROTECT.
Setting this bit when PASSKEY is set to 0000h prevents the
programming of a PASSKEY value.
0
STR
RW
NVM
Command List: STORE_USER_ALL
0b @ Power On Reset: Commands are Writable unless Read Only from
WRITE_PROTECT or PASSKEY
0b @ RESTORE: Commands are Writable unless Read Only from
WRITE_PROTECT or PASSKEY
0b at All other Times: Commands are Writable unless Read Only from
WRITE_PROTECT or PASSKEY
1b @ Power On Reset: Commands are Read Only
1b @ RESTORE: Commands are Read Only
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7.6.90 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
CMD Address
Write Transaction:
Read Transaction:
Format:
FCh
Write Word (writes accepted but otherwise ignored)
Read Word
Unsigned Binary (2 bytes)
Phased:
No
No
NVM Back-up:
FUSION_ID0 provides a platform level Identification code to be used by Texas Instruments Digital Power
Designer for identifying a TI device.
Writes to this command will be accepted, but ignored otherwise (the readback value of this command does not
change following a write attempt). This command is writeable for some TI devices, so to maintain cross-
compatibility, the TPS546D24S accepts write transactions to this command as well. No STATUS_CML bits are
set as a result of the receipt of a write attempt to this command.
图7-96. (FCh) MFR_SPECIFIC_44 (FUSION_ID0) Register Map
15
R
14
R
13
12
11
10
9
8
R
R
R
R
R
R
FUSION_ID0
FUSION_ID0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only
表7-107. Register Field Descriptions
Bit
Field
Access
Reset
Description
15:0
FUSION_
ID0
R
02C0h
Hard Coded to 02C0h
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7.6.91 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
CMD Address
Write Transaction:
Read Transaction:
Format:
FDh
Block Write (writes accepted but otherwise ignored)
Block Read
Unsigned Binary (6 bytes)
Phased:
No
No
NVM Back-up:
FUSION_ID1 provides a platform level Identification code to be used by Texas Instruments Digital Power
Designer for identifying a TI device.
Writes to this command will be accepted, but ignored otherwise (the readback value of this command does not
change following a write attempt). This command is writeable for some TI devices, so to maintain cross-
compatibility, the TPS546D24S accepts write transactions to this command as well. No STATUS_CML bits are
set as a result of the receipt of a write attempt to this command.
图7-97. (FDh) MFR_SPECIFIC_45 (FUSION_ID1) Register Map
47
R
46
R
45
44
43
42
41
R
40
R
R
R
R
R
FUSION_ID1
39
R
38
R
37
R
36
R
35
R
34
R
33
R
32
R
FUSION_ID1
FUSION_ID1
31
30
29
28
27
26
25
24
23
R
22
R
21
R
20
R
19
R
18
R
17
R
16
R
FUSION_ID1
FUSION_ID1
FUSION_ID1
15
R
14
R
13
R
12
R
11
R
10
R
9
8
R
R
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only
表7-108. Register Field Descriptions
Bit
Field
Access
Reset
Description
47:40
FUSION_
ID1
R
4Bh
Hard coded to 4Bh
39:32
31:24
23:16
15:8
FUSION_
ID1
R
R
R
R
43h
4Fh
4Ch
49h
Hard coded to 43h
Hard coded to 4Fh
Hard coded to 4Ch
Hard coded to 49h
FUSION_
ID1
FUSION_
ID1
FUSION_
ID1
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表7-108. Register Field Descriptions (continued)
Bit
Field
Access
Reset
Description
7:0
FUSION_
ID1
R
54h
Hard coded to 54h
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The TPS546D24S is a highly integrated, synchronous step-down DC/DC converter. This device is used to
convert a higher DC-input voltage to a lower DC-output voltage, with a maximum output current of 40 A for a
single device. Use the following design procedures to select key component values for single phasethrough four-
phase designs. The appropriate behavioral options can be set through PMBus.
8.2 Typical Application
U1
R1
PVIN
C1
21
22
23
24
25
7
VIN
PVIN
PVIN
PVIN
PVIN
PVIN
BOOT
R2
10
0
8
SW
SW
SW
SW
SW
C2
100uF
C3
100uF
C4
C5
C6
C7
C8
C9
C10
C11
0.1uF
9
22uF 22uF
22uF 22uF 6800pF 6800pF 6800pF
1uF
10
11
12
L1
26
27
28
AGND
AVIN
GND
GND
VOUT
CNTL
EN/UVLO
VDD5
300nH
VDD5
13
14
15
16
17
18
19
20
41
C12
1000pF
GND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PAD
C16
470uF
C17
470uF
C18
47uF
C13
47uF
C14
47uF
C15
47uF
AGND
C19
4.7uF
R3
NT1
1.0
Net-Tie
GND
GND
GND
R4
33
BP1V5
VOSNS
4
49.9
R5
BP1V5
C20
100pF
34
35
36
38
GOSNS/SLAVE
VSHARE
NC
R6
R7
R8
R9
49.9
C21
2.2uF
9.09k
78.7k
TBD
44.2k
MSEL2
VSEL
29
30
31
32
MSEL2
VSEL
MSEL2
GND
DRTN
VSEL
ADRSEL
ADRSEL
MSEL1
ADRSEL
MSEL1
SYNC
SYNC
MSEL1
39
40
BCX_CLK
BCX_DAT
R10
4.64k
R11
31.6k
R12
TBD
R13
17.8k
1
5
PG
PGD/RST
DRTN
PGD
2
3
PMB_DATA
PMB_CLK
PMB_DATA
PMB_CLK
R14
10.0k
DRTN
VDD5
6
37 AGND
SMB_ALRT
SMB_ALRT
AGND
AGND
TPS546D24SRVFR
图8-1. TPS546D24S Standalone Application
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8.2.1 Design Requirements
For this design example, use the input parameters listed in 表8-1.
表8-1. Design Parameters
DESIGN PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
VIN
5
16
V
V
V
VIN(ripple)
VOUT
Input ripple voltage
VIN =12 V, IOUT = 20 A
0.3
1.0
Output voltage
Line regulation
0.5%
0.5%
ΔVO(ΔVI)
ΔVO(ΔIO)
VPP
5 V ≤VIN ≤16 V
0 V ≤IOUT ≤35 A
IOUT = 35 A
Load regulation
Output ripple voltage
VOUT deviation during load transient
Output current
20
50
mV
mV
A
∆VOUT
IOUT
∆IOUT = 10 A, VIN = 12 V
5 V ≤VIN ≤16 V
0
35
IOCP
Output overcurrent protection threshold
Switching frequency
Full load efficiency
40
325
90%
3
A
FSW
VIN = 12 V
kHz
VIN = 12 V, IOUT = 35 A
ηFull load
tSS
Soft-start time (TON_RISE
)
ms
8.2.2 Detailed Design Procedure
The TPS546D24S provides four pins to program critical PMBus register values without requiring PMBus
communication. Please refer to 表 7-7 for the pin-strapping options. Some equations include a variable N, which
is the number of devices stacked together. In this stand-alone device example, the value of N is equal to 1.
The TPS546x24S Compensation and Pin-Strap Resistor Calculator can also be used to aid in design
calculations and pin-strap resistor selection.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS546D24S device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency
The MSEL1 pin programs USER_DATA_01 (COMPENSATION_CONFIG) and FREQUENCY_SWITCH. The
resistor divider ratio for MSEL1 selects the nominal switching frequency. In the design procedure for MSEL1,
switching frequency is configured first, compensation is chosen after output capacitance is determined.
There is a tradeoff between higher and lower switching frequencies for buck converters. Higher switching
frequencies can produce smaller solution size using lower valued inductors and smaller output capacitors
compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes
extra switching losses, which decrease efficiency and impact thermal performance.
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In this design, a moderate switching frequency of 325 kHz achieves both a small solution size and a high-
efficiency operation. Use the MSEL1 pin program table to select the frequency option. See 表 7-8 for resistor
divider code selection. Resistor divider code 2 or 3 is needed to set the switching frequency to 325 kHz.
8.2.2.3 Inductor Selection
Use 方程式 9 to calculate the value of the output inductor (L). The coefficient, KIND, represents the amount of
inductor-ripple current relative to the maximum output current. The output capacitor filters the inductor-ripple
current. Therefore, selecting a high inductor-ripple current impacts the selection of the output capacitor because
the output capacitor must have a ripple-current rating equal to or greater than the inductor-ripple current.
Generally, the KIND coefficient must be kept between 0.2 and 0.3 for balanced performance. Additionally the
product of KIND and IOUT(Max) must be kept above 2 Ato prevent the inductance from being too large. Using this
target ripple current, the required inductor size can be calculated as shown in 方程式9.
V
- VOUT
(
)
16 V -1 V
35 A
ì0.3
1
IN Max
VOUT
(
)
IOUT Max
(
)
= 275 nH
1 V
L =
ì
=
ì
V
) ì fSW Min
)
16 V ì325 kHz
(
N
)
IN Max
(
(
ìKIND
(9)
Selecting a value of 0.3 for the KIND coefficient, the target inductance, L, is 275 nH. An inductance of 300 nH is
selected. Use 方程式 10, 方程式 11, and 方程式 12 to calculate the inductor-ripple current (IRIPPLE), RMS current
(IL(rms)), and peak current (IL(peak)), respectively. Use these values to select an inductor with approximately the
target inductance value, and current ratings that allow normal operation with some margin.
V
IN(Max) - VOUT
VOUT
ì fSW(Min)
1 V ì (16 V -1 V)
16V ì 325 kHz ì 300 nH
IRIPPLE
=
ì
=
= 9.62 A
V
L1
IN(Max)
(10)
2
2
I
≈
’
OUT Max
1
35 A
1
1
(
N
)
2
≈
’
2
∆
∆
«
÷
÷
◊
IL rms
=
+
I
(
=
+
9.62 A = 35.1A
)
(
)
RIPPLE
∆
«
÷
◊
(
)
12
12
(11)
(12)
IOUT Max
1
2
35 A
1
1
2
(
)
IL peak
=
+
I
=
+
ì 9.62 A = 39.8 A
(
)
(
)
RIPPLE
(
)
N
Considering the required inductance, RMS current and peak current, the 300-nH inductor, SLC1480-301ML,
from Coilcraft was selected for this application.
8.2.2.4 Output Capacitor Selection
Consider the following when selecting the value of the output capacitor:
• The output-voltage deviation during load transient
• The output-voltage ripple
8.2.2.4.1 Output Voltage Deviation During Load Transient
The desired response to a load transient is the first criterion for output capacitor selection. The output capacitor
must supply the load with the required current when not immediately provided by the regulator. When the output
capacitor supplies load current, the impedance of the capacitor affects the magnitude of the voltage deviation
during the transient.
To meet the requirements for control-loop stability, the device requires the addition of compensation components
in the design of the error amplifier. While these compensation components provide for a stable control loop, they
often also reduce the speed with which the regulator can respond to load transients. The delay in the regulator
response to load changes can be two or more clock cycles before the control loop reacts to the change. During
that time, the difference (delta) between the old and the new load current must be supplied (or absorbed) by the
output capacitance. The output capacitor impedance must be designed to supply or absorb the delta current
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while maintaining the output voltage within acceptable limits. 方程式 13 and 方程式 14 show the relationship
between the transient response overshoot (VOVER), the transient response undershoot (VUNDER), and the
required output capacitance (COUT).
2
(ITRAN
)
ì L
VOVER
<
VOUT ì COUT
(13)
(14)
2
(ITRAN
) ì L
VUNDER
<
(VIN - VOUT ) ì COUT
If
• VIN(min) > 2 × VOUT, use overshoot to calculate minimum output capacitance.
• VIN(min) < 2 × VOUT, use undershoot to calculate minimum output capacitance.
In this case, the minimum designed input voltage, VIN(min), is greater than 2 × VOUT, so VOVER dictates the
minimum output capacitance. Therefore, using 方程式 15, the minimum output capacitance required to meet the
transient requirement is 600 µF.
I
2 ìL
10 A 2 ì300 nH
(
)
(
)
TRAN
COUT Min
=
=
= 600 µF
(
)
VOUT ì VOVER
1 V ì50 mV
(15)
The bandwidth of the voltage loop must also be considered when calculating the minimum output capacitance.
The voltage loop can typically be compensated to have a bandwidth of 1/10th the fSW. 方程式 16 calculates the
minimum output capacitance to be 979 µF.
1
1
COUT Min
=
=
= 979 µF
(
)
fSW VTRAN
325 kHz 50 mV
2pì
ì
2pì
ì
10
10 A
10 ITRAN
(16)
8.2.2.4.2 Output Voltage Ripple
The output-voltage ripple is the second criterion for output capacitor selection. Use 方程式 17 to calculate the
minimum output capacitance required to meet the output-voltage ripple specification.
IRIPPLE
9.62 A
COUT(Min)
=
=
= 185 ꢀF
8ì fSW ì VOUT RIPPLE
8ì325 kHzì20 mV
(
)
(17)
In this case, the target maximum output-voltage ripple is 20 mV. Under this requirement, the minimum output
capacitance for ripple is 185 µF. This capacitance value is smaller than the output capacitance required for the
transient response, so select the output capacitance value based on the transient requirement. Considering the
variation and derating of capacitance, in this design, two 470-µF low-ESR tantalum polymer bulk capacitors and
four 47-µF ceramic capacitors were selected to meet the transient specification with sufficient margin. Therefore
the selected nominal COUT is equal to 1128 µF.
With the output capacitance value selected the ESR must be considered. This is an important consideration in
this example because it uses mixed output capacitor types. First use 方程式 18 to calculate the maximum
allowable impedance for the output capacitor bank at the switching frequency to meet the output voltage ripple
specification. 方程式 18 indicates the output capacitor bank impedance must be less than 2.1 mΩ. The
impedance of the ceramic capacitors is calculated with 方程式 19 and the impedance of the bulk capacitor is
calculated with 方程式 20. The result from 方程式 20 shows the impedance of the bulk capacitor at the switching
frequency is dominated by its ESR.方程式 21 calculates the total output impedance of the output capacitor bank
at the switching frequency to be 1.7 mΩwhich meets the 2.1 mΩrequirement.
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VOUT RIPPLE
20 mV
9.62 A
(
IRIPPLE
)
ZCOUT Max _ f
=
=
= 2.1 mꢀ
(
)
SW
(18)
(19)
1
1
ZCER_ f
=
=
= 2.6 mꢀ
SW
2pì fSW ìCCER 2pì325 kHzì 4ì 47 ꢁF
2
2
2
≈
’
≈
∆
«
’
÷
1
10 mꢀ
1
≈
’
2
ZBULK _ f = ESRBULK
+
=
+
= 5.0 mꢀ
∆
∆
÷
÷
∆
«
÷
◊
SW
2pì fSW ìCBULK ◊
2
2pì325 kHzì 2ì 470 ꢁF
(
)
«
◊
(20)
Z
ì Z
BULK _ fSW
2.6 mꢀì5.0 mꢀ
2.6 mꢀ + 5.0 mꢀ
CER_ fSW
ZCOUT _ f
=
=
= 1.7 mꢀ
SW
ZCER_ f + ZBULK _ f
SW
SW
(21)
8.2.2.5 Input Capacitor Selection
The power-stage input-decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be
sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while
providing minimal input-voltage ripple as a result. This effective capacitance includes any DC-bias effects. The
voltage rating of the input capacitor must be greater than the maximum input voltage with derating. The capacitor
must also have a ripple-current rating greater than the maximum input-current ripple to the device during full
load. Use 方程式22 to estimate the input RMS current.
V
- VOUT
IOUT Max
(
)
4.5 V -1 V
IN Min
(
VOUT
)
(
)
= 14.6 A
35 A
1
1 V
(
N
)
I
=
ì
ì
=
ì
ì
IN rms
(
)
V
V
4.5 V
4.5 V
IN Min
(
IN Min
(
)
)
(22)
The minimum input capacitance and ESR values for a given input voltage-ripple specification, VIN(ripple), are
shown in 方程式 23 and 方程式 24. The input ripple is composed of a capacitive portion (VRIPPLE(cap)) and a
resistive portion (VRIPPLE(esr)).
IOUT Max
35 A
1
(
)
ì VOUT
ì1V
N
CIN Min
=
=
= 67.3 ꢀF
(
)
VRIPPLE cap ì V
ì fSW 0.1V ì16 V ì325 kHz
IN Max
(23)
VRIPPLE ESR
0.2 V
(
)
ESRC
=
=
= 5.5 mꢀ
IN Max
(
)
IOUT Max
35 A
1
1
2
1
2
(
N
)
+
ì9.62 A
+
IRIPPLE
(24)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations because of temperature can be minimized by selecting a dielectric material
that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power-regulator
capacitors because these components have a high capacitance-to-volume ratio and are fairly stable over
temperature. The input capacitor must also be selected with consideration of the DC bias. For this example
design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage.
For this design, allow 0.1-V input ripple for VRIPPLE(cap) and 0.2-V input ripple for VRIPPLE(esr). Using 方程式 23
and 方程式 24, the minimum input capacitance for this design is 67.3 µF, and the maximum ESR is 5.5 mΩ. For
this design example, four 22-μF, 25-V ceramic capacitors, three 6800-pF, 25-V ceramic capacitors, and
twoadditional 100-μF, 25-V low-ESR electrolytic capacitors in parallel were selected for the power stage with
sufficient margin. For all designs a minimum input capacitance of 10 µF is required and a maximum input ripple
of 500 mV is recommended.
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To minimize the high frequency ringing, the high frequency 6800-pF PVIN bypass capacitors must be placed
close to power stage.
8.2.2.6 AVIN, BP1V5, VDD5 Bypass Capacitor
The BP1V5 pin requires a minimum capacitance of 1 μF connected to DRTN. The VDD5 pin must have
approximately 4.7 μF of capacitance connected to PGND. The AVIN pin must have approximately 1 μF of
capacitance connected to AGND. To filter switching noise on the AVIN pin, a small value resistor of typically 10-
Ω is recommended to be placed between PVIN and AVIN. If using split rail inputs and if the AVIN pin is
connected to the VDD5 pin, a small value resistor is recommended to be placed between AVIN and VDD5.
8.2.2.7 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric with a voltage rating of
25 V or higher. Lower voltage rating capacitors can be used as long as the capacitance is greater than 0.08 µF
after AC and DC bias derating.
8.2.2.8 R-C Snubber
An R-C snubber must be placed between the switching node and PGND to reduce voltage spikes on the
switching node. The power rating of the resistor must be larger than the power dissipation on the resistor with
sufficient margin. To balance efficiency and voltage spike amplitude, a 1-nF capacitor and a 1-Ω resistor were
selected for this design. In this example, an 0805 resistor was selected, which is rated for 0.125 W.
8.2.2.9 Output Voltage Setting (VSEL Pin)
The output voltage can be set using the VSEL pin. The resistor divider ratio for VSEL programs the
VOUT_COMMAND range, VOUT_SCALE_LOOP divider, VOUT_MIN, and VOUT_MAX levels according to 表
7-12. Select the resistor divider code for the range of VOUT desired. For this 1-V output example, resistor divider
code 2, a single resistor to AGND or floating the VSEL pin can be used.
With the resistor divider code selected for the range of VOUT, select the resistor to AGND code with the
VOUT_COMMAND Offset and VOUT_COMMAND step from 表 7-13. To calculate the resistor to AGND code
subtract the VOUT_COMMAND offset from the target output voltage and divide by the VOUT_COMMAND step.
For this example, a single resistor to AGND was used and the result is code 10. A 31.6-kΩ resistor to AGND at
VSEL programs the desired setting.
VOUT - VOUT _COMMAND(Offset
1- 0.5
0.05
)
Code =
=
= 10
VOUT _COMMAND(STEP
)
(25)
8.2.2.10 Compensation Selection (MSEL1 Pin)
The resistor to AGND for MSEL1 selects the (B1h) USER_DATA_01 (COMPENSATION_CONFIG) values to
program the following voltage loop and current loop gains. For options other than the EEPROM code (MSEL1
shorted to AGND or MSEL1 to AGND resistor code 0), the current and voltage loop zero and pole frequencies
are scaled with the programmed switching frequency.
Based on Current Error Integrator, calculate the mid-band current loop gain with 方程式26.
V
fSW
4
1.7
1.7ìp
4ì5.5ì6.155ì10-3
ramp
ILOOPMB = GMIìRVI =
ì
ìLìpì
=
ìLì fSW = 39.4ìLì fSW = 39.4ì300nHì325kHz = 3.842
VPVIN CSA
(26)
Find the smaller value closest to 3.8 in 表7-9 and this is 3.
To calculate the target voltage loop gain, first use 方程式 27 through 方程式 29 to calculate the output
impedance. Use 方程式30 to calculate the target voltage loop gain.
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1
1
ZCER _ f
=
=
= 26 mꢀ
BW
fSW
325 kHz
10
2pì
ì 4ì 47 ꢁF
2pì
ìCCER
(
)
10
.
(27)
2
2
≈
’
≈
∆
∆
’
2
∆
÷
÷
÷
1
10 mꢀ
1
≈
’
2
ZBULK _ f = ESRBULK
+
=
+
= 7.2 mꢀ
∆
÷
∆
«
÷
◊
BW
fSW
325 kHz
10
2
∆
∆
«
÷
÷
◊
∆
∆
÷
÷
2pì
ì 2ì 470 ꢁF
2pì
ìCBULK
(
)
«
◊
10
(28)
Z
ì Z
26 mꢀì7.2 mꢀ
26 mꢀ + 7.2 mꢀ
CER _ fBW
BULK _ fBW
ZCOUT _ f
=
=
= 5.6 mꢀ
BW
ZCER _ f + ZBULK _ f
BW
BW
(29)
(30)
mV
A
6.155
1
CSA
1
VLOOPMB = GMV ìRVV =
ì
=
ì
= 2.2
VOUT _SCALE_LOOP Nì ZCOUT _ f
0.5 1ì5.6 mW
BW
Find the smaller value closest to 2.2 in 表 7-9 for voltage loop gain and this is 2. This setting gives a stable
design but through bench evaluation the voltage loop gain was reduced to 1 to improve the gain and phase
margin. The calculated current and voltage loop gain correspond to compensation setting 7. To use this
compensation setting resistor to AGND code 7 is needed. With this compensation code the even resistor divider
code must be used to set the switching frequency. Divider code 2 sets the fsw to 325 kHz. Resistor to AGND
code 9 and resistor divider code 2 is selected using an MSEL1 resistor divider of RTOP = 44.2 kΩ and RBOT
17.8 kΩ.
=
The procedure given is meant to give a stable design. Further optimization of the compensation is often possible
through testing the design on the bench. Increasing the voltage loop gain increases the loop bandwidth to
improve the transient response but make sure to verify there is still sufficient gain and phase margin. The
maximum voltage loop bandwidth possible is limited by these stability margins. Decreasing the current loop gain
can help to minimize pulse-width jitter but this typically comes with a tradeoff of decreased phase margin. Lastly,
the pole and zero locations can also be adjusted through PMBus. For example, it can be beneficial to use the
CPV capacitor in the voltage loop to add a pole at the same frequency of the ESR zero when using high ESR
output capacitors.
When using a larger inductance, the current loop gain that can be selected through pin strapping can be much
lower than the calculated target value. If this happens, the voltage loop gain must also be scaled back by about
the same amount to keep sufficient phase margin. For higher voltage loop bandwidth, the inductance can be
decreased to reduce the current loop gain needed or higher current loop gain can be programmed through the
PMBus command USER_DATA_01 (COMPENSATION_CONFIG).
8.2.2.11 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
Soft-start time, overcurrent protection thresholds, and stacking configuration can be configured using the MSEL2
pin. The TPS546D24S device support several soft-start times from 0 to 31.75 ms in 250-µs steps (7 bits)
selected by the TON_RISE command. Eight times are selectable using the MSEL2 pin. The TPS546D24S
device support several low-side overcurrent warn and fault thresholds from 8 to 62 A selected by the
IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT commands. Four thresholds are selectable using the
MSEL2 pin. The response to an OC fault can be changed through PMBus. Lastly, the number of devices stacked
is set using the MSEL2 pin.
The resistor divider code for MSEL2 selects the soft-start values. The resistor to AGND determines the number
of devices sharing common output and the overcurrent thresholds. Use 表7-11 and 表7-10 to select the resistor
to AGND code and resistor divider code needed for the desired configuration.
In this single phase design, resistor divider code 3 is selected for 5-ms soft start and resistor to AGND code 0 is
selected for the highest current limit thresholds and stand alone configuration.
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8.2.2.12 Enable and UVLO
The ON_OFF_CONFIG command is used to select the turnon behavior of the converter. For this example, the
EN/UVLO pin or CONTROL pin was used to enable or disable the converter, regardless of the state of
OPERATION, as long as the input voltage is present and above the UVLO threshold. The EN/UVLO pin is pulled
low internally if it is floating.
A resistor divider can be added the EN/UVLO pin to program an additional UVLO. Additionally 0.1 µF can be
placed on this pin to filter noise or short glitches. Use 方程式 31 and 方程式 32 to calculate the resistor values to
target a 4.75-V turnon and a 4.25-V turnoff. Standard resistor values of 30.1 kΩ and 7.50 kΩ are selected for
this example. Use 方程式33 and 方程式34 to calculate the thresholds based on selected resistor values.
VON ì VENFALL - VOFF ì VENRISE
NìIENHYS ì VENRISE
5.25 V ì0.98 V - 4.75 V ì1.05 V
1ì5.5 µA ì1.05 V
RENTOP
=
=
= 27.3 kꢀ
(31)
(32)
(33)
RENTOP ì VENFALL
30.1kWì0.98 V
RENBOT
=
=
= 7.50 kꢀ
VOFF - VENFALL +NìIENHYS ìRENTOP 4.75 V - 0.98 V +1ì5.5 µAì30.1kW
VENRISE ì R
+ RENTOP
1.05 V ì 7.50 kW + 30.1 kW
(
)
(
)
= 5.26 V
ENBOT
VON
=
=
RENBOT
7.50 kW
VENFALL ì R
+ RENTOP
0.98 V ì 8.66 kW + 30.1 kW
(
)
(
)
-1ì5.5 µA ì30.1 kW = 4.22 V
ENBOT
VOFF
=
-NìIENHYS ìRENTOP
=
RENBOT
8.66 kW
(34)
8.2.2.13 ADRSEL
In this example, the ADRSEL pin is left floating. This sets the PMBus device address to the EEPROM value,
0x24h (36d) by default, and the SYNC pin to auto detect with 0 degrees phase shift. Use 表 7-14 and 表 7-15 to
select the resistor to AGND code and resistor divider code needed for the desired configuration.
If through pin-strapping, the desired address is not possible with the SYNC pin set to auto detect and
synchronization is not needed in the application, configure the SYNC pin for SYNC_OUT. The device still
regulates normally with the SYNC pin configured for SYNC_IN, however, if there is not clock input to the SYNC
pin, the device declares a SYNC fault in the STATUS_MFR_SPECIFIC command.
8.2.2.14 Pin-Strapping Resistor Selection
The following tables provide the resistor to AGND values, in ohms, in the highlighted top rows and the top
resistor (pin to BP1V5) values, in ohms, in the unhighlighted cells. Select the column associated with the desired
resistor to AGND code and the row with the desired resistor divide code in 表7-17 and 表7-18.
8.2.2.15 BCX_CLK and BCX_DAT
For a stand-alone device, the BCX_CLK and BCX_DAT pins are not used. As shown in 表 7-5, TI recommends
ground them to the thermal pad.
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8.2.3 Application Curves
100
1.002
1.001
1
PVIN = 5V
PVIN = 12V
90
80
70
60
0.999
0.998
PVIN = 5V
PVIN = 9V
PVIN = 12V
0
5
10
15
20 25
Load Current (A)
30
35
40
45
0
5
10
15
20 25
Load Current (A)
30
35
40
45
AP03
AP04
VOUT = 1.0 V
fSW = 325 kHz
L = 300 nH
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
VVIN = 12 V
VOUT = 1.0 V
RDCR = 0.2 mΩ
图8-3. Load Regulation
图8-2. Efficiency vs Output Current
40
30
200
150
100
50
VIN = 10 V / div
20
CNTL = 5 V / div
10
0
0
-10
-20
-30
-40
-50
-100
-150
-200
VO = 1 V / div
Gain (dB)
Phase (°)
PGOOD = 5 V / div
1000
10000
100000
1000000
Frequency (Hz)
AP02
Time = 500 μsec / div
VOUT = 1.0 V
VIN = 12 V
IOUT = 20 A
VIN = 12 V VOUT = 1.0 V
IOUT = 20 A
图8-5. Start-Up from EN/UVLO
图8-4. Total-Loop Bode Plot
VIN = 10 V / div
VIN = 10 V / div
CNTL = 5 V / div
CNTL = 5 V / div
VO = 1 V / div
VO = 1 V / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 500 μsec / div
VOUT = 1.0 V
Time = 50 msec / div
VOUT = 1.0 V
VIN = 12 V
IOUT = 0 A
VIN = 12 V
IOUT = 20 A
图8-7. Shutdown from CNTL
图8-6. Shutdown from CNTL
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ILOAD= 10 A / div
ILOAD= 10 A / div
VO = 100 mV / div
SW = 5 V / div
VO = 100 mV / div
SW = 5 V / div
Time = 20 μsec / div
VOUT = 1.0 V IOUT = 15 A to 25 A, 2.5 A/µs
Time = 20 μsec / div
VOUT = 1.0 V IOUT = 25 A to 15 A, 2.5 A/µs
VIN = 12 V
VIN = 12 V
图8-8. Load Transient Response
图8-9. Load Transient Response
VO = 10 mV / div
SW = 5 V / div
Time = 2 μsec / div
VIN = 12 V
VOUT = 1.0 V
IOUT = 20 A
图8-10. VOUT Steady-State Ripple
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8.3 Two-Phase Application
Use the following design procedure to select key component values for two-phase design. The appropriate
behavioral options can be set through PMBus. Refer to 节 8.2.2 for the equations used to calculate the
component values in this example. The only difference is to increase value of N to 2 because there are two
devices stacked for a two-phase design. This procedure can also be used as reference for three-phase and four-
phase designs. Again the only difference is to increase the value of N to 3 and 4 for a three-phase and four-
phase design, respectively.
WEBENCH includes support for creating two-phase designs. The SLUC686 calculator can also be used to aid in
design calculations and pin-strap resistor selection.
8.3.1 Design Requirements
For this design example, use the input parameters listed in 表8-1.
表8-2. Design Parameters
DESIGN PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
VIN
5
16
V
V
V
VIN(ripple)
VOUT
Input ripple voltage
VIN =12 V, IOUT = 40 A
0.3
0.8
Output voltage
Line regulation
0.5%
0.5%
ΔVO(ΔVI)
ΔVO(ΔIO)
VPP
5 V ≤VIN ≤16 V
0 V ≤IOUT ≤80 A
IOUT = 80 A
Load regulation
Output ripple voltage
VOUT deviation during load transient
Output current
10
32
mV
mV
A
∆VOUT
IOUT
∆IOUT = 20 A, VIN = 12 V
5 V ≤VIN ≤16 V
0
80
IOCP
Output overcurrent protection threshold
Switching frequency
Full load efficiency
104
550
85%
3
A
FSW
VIN = 12 V
kHz
VIN = 12 V, IOUT = 80 A
ηFull load
tSS
Soft-start time (TON_RISE
)
ms
U1
R1
PVIN
C1
21
22
23
24
25
7
PVIN
BOOT
R2
10
PVIN
PVIN
PVIN
PVIN
0
8
9
10
11
12
SW
C2
100uF
C3
22uF
C4
22uF
C5
22uF
C6
22uF
C7
C8
C9
C10
0.1uF
SW
SW
SW
SW
6800pF 6800pF 6800pF
1uF
L1
26
27
28
AGND
AVIN
150nH
CNTL
EN/UVLO
VDD5
VDD5
13
14
15
16
17
18
19
20
41
C11
1000pF
GND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PAD
C12
470uF
C13
470uF
C14
47uF
C15
47uF
C16
47uF
C17
47uF
C18
47uF
C19
47uF
C20
47uF
C21
47uF
AGND
C22
4.7uF
R3
1.0
NT1
Net-Tie
GND
GND
R4
33
VOSNS
SNS+
BP1V5
4
49.9
R5
BP1V5
C23
100pF
34
VIN
GOSNS/SLAVE
VSHARE
NC
SNS-
R6
9.09k
R7
78.7k
R8
TBD
R9
44.2k
49.9
C24
2.2uF
MSEL2
VSEL
29
30
31
32
35
C25
100uF
C26
100uF
MSEL2
VSEL
VSHARE
MSEL2
36 GND
38
DRTN
GND
GND
VSEL
ADRSEL
ADRSEL
MSEL1
ADRSEL
MSEL1
SYNC
SYNC
MSEL1
39
40
BCX_CLK
BCX_DAT
BCX_CLK
BCX_DAT
GND
R10
4.64k
R11
14.7k
R12
TBD
R13
5.62k
SNS+
1
PG
PGD/RST
DRTN
PGD
2
3
PMB_DATA
PMB_CLK
PMB_DATA
PMB_CLK
R14
10.0k
5
DRTN
VDD5
VOUT
GND
C27
33pF
6
37 AGND
C28
47uF
C29
47uF
C30
47uF
C31
47uF
C32
47uF
C33
47uF
C34
47uF
C35
47uF
C36
47uF
C37
47uF
SMB_ALRT
SMB_ALRT
AGND
AGND
TPS546D24SRVFR
SNS-
GND
U2
R15
0
PVIN
21
22
23
24
25
7
PVIN
PVIN
PVIN
PVIN
PVIN
BOOT
R16
10
C38
1uF
8
SW
SW
SW
SW
SW
C39
100uF
C40
22uF
C41
22uF
C42
22uF
C43
22uF
C44
C45
C46
C47
0.1uF
9
6800pF 6800pF 6800pF
10
11
12
L2
26
27
28
AGND_S
AVIN
150nH
CNTL
EN/UVLO
VDD5
VDD5_S
13
14
15
16
17
18
19
20
41
C48
1000pF
GND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PAD
C49
470uF
C50
470uF
C51
47uF
C52
47uF
C53
47uF
C54
47uF
C55
47uF
C56
47uF
C57
47uF
C58
47uF
AGND_S
C59
4.7uF
R17
1.0
NT2
Net-Tie
GND
GND
33
VOSNS
BP1V5_S
4
BP1V5
R18
10.0k
34
BP1V5_S
GOSNS/SLAVE
VSHARE
NC
R19
9.09k
C60
2.2uF
MSEL2_S
29
30
31
32
35
MSEL2
VSEL
VSHARE
SYNC
36 GND
38
DRTN_S
MSEL2_S
ADRSEL
MSEL1
SYNC
39
40
BCX_CLK
BCX_DAT
BCX_CLK
BCX_DAT
R20
0
1
5
GND
PGD/RST
DRTN
2
3
PMB_DATA
PMB_CLK
DRTN_S
C61
33pF
AGND_S
GND
6
37 AGND_S
SMB_ALRT
AGND
TPS546D24SRVFR
图8-11. TPS546D24S Two-Phase Application
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8.3.2 Switching Frequency
Only the loop controller device (U1) needs a resistor divider at the MSEL1 pin to program USER_DATA_01
(COMPENSATION_CONFIG) and FREQUENCY_SWITCH. The MSEL1 pin of loop follower devices are not
used. In this design, a moderate switching frequency of 550 kHz achieves both a small solution size and a high-
efficiency operation. Use MSEL1 pin program table to select the frequency option. See 表 7-8 for resistor divider
code selection. With 550 kHz switching frequency a single resistor to AGND can be used to program
compensation settings 7 to 25. To program all 32 compensation settings possible through MSEL1, resistor
divider code 6 or 7 sets the switching frequency to 550 kHz.
8.3.3 Inductor Selection
Use 方程式 9 to calculate the value of the output inductor (L) for each phase. The current is shared between
each phase so the output current used in this calculation is divided by the number of phases.
Selecting a value of 0.3 for the KIND coefficient, the target inductance, L, is 120 nH. An inductance of 150 nH is
selected. Use 方程式 10, 方程式 11, and 方程式 12 to calculate the inductor-ripple current (IRIPPLE), RMS current
(IL(rms)), and peak current (IL(peak)), respectively. The resulting values are IRIPPLE = 9.2 A, IL(rms) = 40.1 A and
IL(peak) = 44.6 A. Use these values to select an inductor with approximately the target inductance value and
current ratings that allow normal operation with some margin.
Considering the required inductance, RMS current and peak current, the 150-nH inductor, SLC1480-151ML,
from Coilcraft was selected for this application.
8.3.4 Output Capacitor Selection
In this example the target output voltage deviation with a 20 A step is 40 mV. Using 方程式 16, assuming the
voltage loop is compensated to 1/10th the fSW, the minimum output capacitance needed to meet the transient
response specification is 1810 µF.
The target maximum output-voltage ripple is 10 mV. Under this requirement, the minimum output capacitance for
ripple is 210 µF. Depending on the duty cycle and the number of phases there can also be some inductor ripple
current cancellation. This will reduce the amount of ripple current the capacitors need to absorb reducing the
output voltage ripple. This capacitance value is smaller than the output capacitance required for the transient
response, so select the output capacitance value based on the transient requirement. Considering the variation
and derating of capacitance, in this design, four 470-µF low-ESR tantalum polymer bulk capacitors and twenty-
six 47-µF ceramic capacitors were selected to meet the transient specification with sufficient margin. The
selected nominal COUT is equal to 3102 µF. The 470-µF capacitors selected have an ESR of 10 mΩ.
With the output capacitance value selected the ESR must be considered because this example uses mixed
output capacitor types. First use 方程式 18 to calculate the maximum allowable impedance for the output
capacitor bank at the switching frequency to meet the output voltage ripple specification. 方程式 18 indicates the
output capacitor bank impedance must be less than 1.1 mΩ. The impedance of the ceramic capacitors alone is
calculated with 方程式 19 to be 0.2 mΩ. This is much less than the calculated maximum so the ESR of tantalum
polymer capacitors does not need to be considered for the output ripple specification.
8.3.5 Input Capacitor Selection
Using 方程式22 the maximum input RMS current is 14.7 A and the input capacitors must be rated to handle this.
When calculating this, the maximum output current must be divided by the number of phases. The output current
is divided by the number of phases because the switching nodes are interleaved. Interleaving the switching node
effectively divides the amplitude of the current pulses the input capacitor by the number of phases. With the 16-V
maximum input in this example a ceramic capacitor with at least a 25-V voltage rating is required to support the
maximum input voltage.
For this design, allow 0.1-V input ripple for VRIPPLE(cap) and 0.2-V input ripple for VRIPPLE(esr). Using 方程式 23
and 方程式 24, the minimum input capacitance for this design is 36 µF and the maximum ESR is 4.5 mΩ
respectively. Again the maximum output current must be divided by the number of phases and the calculated
capacitance must be placed near the loop controller converter and all of the loop follower converters. Eight 22-
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μF, 25-V ceramic capacitors and six 6800-pF, 25-V ceramic capacitors in parallel were selected to bypass the
power stage with sufficient margin. Additionally four 100-μF, 25-V low-ESR electrolytic capacitors were placed
on the input to minimize deviations on the input during transients. These capacitors are distributed equally
between the phases. To minimize the high frequency ringing, the high frequency 6800-pF PVIN bypass
capacitors must be placed close to power stage.
When stacking converters the amount of input RMS current and the amount if input capacitance required can be
further reduced. The amount of ripple cancellation depends on the number of phases and the duty cycle. PCB
inductance between the phases can also reduce the effects of ripple cancellation. The calculations given in this
example ignore the effects of ripple cancellation.
8.3.6 AVIN, BP1V5, VDD5 Bypass Capacitor
See AVIN, BP1V5, VDD5 Bypass Capacitor.
8.3.7 Bootstrap Capacitor Selection
See Bootstrap Capacitor Selection.
8.3.8 R-C Snubber
See R-C Snubber.
8.3.9 Output Voltage Setting (VSEL Pin)
Only the loop controller device (U1) needs a resistor divider at the VSEL pin to program the output voltage. The
VSEL pin of loop follower devices are not used. The resistor divider code selected for this 0.8-V output example
using 表 7-12 is a single resistor to AGND. With the resistor divider code selected for the range of VOUT, select
the resistor to AGND code with the VOUT_COMMAND Offset and VOUT_COMMAND step from the 表 7-13.
With VOUT = 0.8 V, VOUT_COMMAND(Offset) = 0.5 V and VOUT_COMMAND(STEP) = 0.05, the result is code 6. A
14.7-kΩresistor to AGND at VSEL programs the desired setting.
8.3.10 Compensation Selection (MSEL1 Pin)
Only the loop controller device (U1) uses the resistor to AGND for MSEL1 to program the (B1h)
USER_DATA_01 (COMPENSATION_CONFIG) values to set the following voltage loop and current loop gains.
The MSEL1 pin of loop follower devices are not used. For options other than the EEPROM code (MSEL1
shorted to AGND or MSEL1 to AGND resistor code 0) the current and voltage loop zero and pole frequencies
are scaled with the programmed switching frequency.
Calculate the mid-band current loop gain with 方程式 26. The resulting value is 3.3. Find the smaller value
closest in the look-up table 表7-9 and this is 3.
To calculate the target voltage loop gain, first use 方程式 27 through 方程式 29 to calculate the output
impedance. Use 方程式 30 to calculate the target voltage loop gain. With an estimated 85% derating, the
ceramic capacitor impedance is 2.4 mΩ. The bulk capacitor impedance is 2.9 mΩ. The total output impedance
is 1.3 mΩ. When using a stacked configuration, the CSA gain must be divided by the number of phases when
calculating the target voltage loop gain. The resulting target voltage loop gain is 4.7. Find the smaller value
closest in the look-up 表7-9 for voltage loop gain and this is 4.
These settings gives a stable design but through bench evaluation the voltage loop gain was reduced to 2 to
improve the gain and phase margin. The current loop and voltage loop gains are selected with compensation
setting 8. With (33h) FREQUENCY_SWITCH of 550 kHz, this compensation setting can be selected using a
single resistor to AGND. A 5.62-kΩresistor to AGND at MSEL1 programs the desired settings.
8.3.11 GOSNS/FLWR Pin of Loop Follower Devices
Loop follower devices must have their GOSNS/FLWR pin tied to BP1V5 through a resistor. A 10-kΩ resistor is
recommended.
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8.3.12 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
The resistor divider code for MSEL2 pin of the loop controller device (U1) selects the soft-start values. The
resistor to AGND determines the number of devices sharing common output and the overcurrent thresholds. Use
the following tables, 表 7-11 and 表 7-10 to select the resistor values. In this two-phase design, the desired
settings can be selected by floating the MSEL2 pin. This selects 3-ms soft-start time, the highest current limit
thresholds and two-phase configuration.
In stackable configuration, loop follower devices use the resistor from MSEL2 to AGND to program
IOUT_OC_WARN_LIMIT,
IOUT_OC_FAULT_LIMIT,
MFR_SPECIFIC_28
(STACK_CONFIG),
and
INTERLEAVE. The loop follower receives all other pin programmed values from the loop controller over the
back-channel communication (BCX_CLK and BCX_DAT) as part of the Power On Reset function. In this two-
phase design, the desired settings can be selected by shorting the MSEL2 pin of the loop follower device to
AGND. This selects the highest current limit thresholds and programs the loop follower device to be the 180° out
of phase from the loop controller device.
8.3.13 Enable, UVLO
TI recommends connecting the EN/UVLO pins of stacked devices together. When this is done, the hysteresis
current is multiplied by the number devices stacked. This increased hysteresis current must be included in
calculations for a resistor divider to the EN/UVLO pins. See 节8.2.2.12 for more details.
8.3.14 VSHARE Pin
When using a stacked configuration, bypass the VSHARE pin of each device to AGND with a 33 pF or larger
capacitor. This capacitor is used to prevent external noise from adding to the VSHARE signal between stacked
devices.
8.3.14.1 ADRSEL Pin
Only the loop controller device (U1) needs a resistor divider at the ADRSEL pin. In this example the ADRSEL pin
is left floating. This sets the PMBus device address to the EEPROM value, 0x24h (36d) by default, and the
SYNC pin to auto detect with 0 degrees phase shift. Use the following tables, 表 7-14 and 表 7-15, to select the
resistor to AGND code and resistor divider code needed for the desired configuration.
8.3.15 SYNC Pin
The SYNC pins of stacked devices must be connected together. Loop follower devices are always configured for
SYNC_IN while the loop controller device (U1) can be configured for auto-detect, SYNC_IN or SYNC_OUT.
8.3.16 VOSNS Pin of Loop Follower Devices
The VOSNS pin of loop follower devices can be used to monitor voltages other than VOUT through the
READ_VOUT command. A resistor divider must be used to scale to voltage at VOSNS to be less than 0.75 V.
The appropriate phase must be selected using the PHASE command.
8.3.17 Unused Pins of Loop Follower Devices
Multiple pins of loop follower devices are not used and TI recommends grounding to the thermal pad. See 表7-5
for more information.
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8.3.18 Two-phase Application Curves
100
90
80
70
60
50
40
0.805
0.804
0.803
0.802
0.801
0.8
0.799
0.798
0.797
0.796
0.795
VIN = 5 V
VIN = 12 V
VIN = 16 V
VIN = 5 V
VIN = 12 V
VIN = 16 V
0
10
20
30
Output Current (A)
40
50
60
70
80
0
10
20
30
Output Current (A)
40
50
60
70
80
VOUT = 0.8 V
fSW = 550 kHz
L = 150 nH
VOUT = 0.8 V
fSW = 550 kHz
Snubber = 1 nF + 1 Ω
RBOOT = 0 Ω
RDCR = 0.2 mΩ
图8-13. Load Regulation
图8-12. Efficiency vs Output Current
0.805
0.804
0.803
0.802
0.801
0.8
60
40
180
120
60
20
0
0
0.799
0.798
-20
-40
-60
-60
-120
-180
0.797
IOUT = 0 A
IOUT = 40 A
IOUT = 80 A
Gain
Phase
0.796
0.795
5
6
7
8
9
10 11 12 13 14 15 16
1000 2000 5000 10000
100000
1000000
Input Voltage (V)
Frequency (Hz)
VOUT = 0.8 V
fSW = 550 kHz
VIN = 12 V
fSW = 550 kHz
VOUT = 0.8 V
IOUT = 40 A
图8-14. Load Regulation
图8-15. Total-Loop Bode Plot
VOUT(AC) = 10 mV/div
VOUT(AC) = 20 mV/div
SWU2 = 5 V/div
IOUT(STEP) = 10 A/div
SWU1 = 5 V/div
Time = 200 µs/div
Time = 1 µs/div
VIN = 12 V
VOUT = 0.8 V
IOUT(DC) = 30 A
VIN = 12 V
VOUT = 0.8 V
IOUT = 40 A
IOUT(STEP) = 20 A IOUT(SLEW) > 3 A/µs
图8-17. VOUT Steady-State Ripple
图8-16. Load Transient Response
8.4 Four-Phase Application
PMP21814 gives an example four-phase design using the TPS546D24S.
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8.5 Power Supply Recommendations
The TPS546D24S devices are designed to operate from split input voltage supplies. AVIN is designed to operate
from 2.95 V to 18 V. AVIN must be powered to enable POR, PMBus communication, or output conversion. For
AVIN voltages less than 4 V, VDD5 must be supplied with an input voltage greater than 4 V to enable switching.
PVIN is designed to operate from 2.95 V to 16 V. PVIN must be powered to enable switching, but not for POR or
PMBus communication. The TPS546D24S can be operated from a single 4-V or higher supply voltage by
connecting AVIN to PVIN. TI recommends a 10-Ωresistor between AVIN and PVIN to reduce switching noise on
AVIN. See the recommendations in Layout.
8.6 Layout
8.6.1 Layout Guidelines
Layout is critical for good power-supply design. 图8-18 shows the recommended PCB-layout configuration. A list
of PCB layout considerations using these devices is listed as follows:
• As with any switching regulator, several power or signal paths exist that conduct fast switching voltages or
currents. Minimize the loop area formed by these paths and their bypass connections.
• Bypass the PVIN pins to PGND with a low-impedance path. Place the input bypass capacitors of the power-
stage as close as physically possible to the PVIN and PGND pins. Additionally, a high-frequency bypass
capacitor in a 0402 package on the PVIN pins can help reduce switching spikes. This capacitor can be
placed on the other side of the PCB directly underneath the device to keep a minimum loop.
• The VDD5 bypass capacitor carries a large switching current for the gate driver. Bypassing the VDD5 pin to
AGND at the thermal pad with a low-impedance path is very critical to the stable operation of the
TPS546D24S devices. Place the VDD5 high-frequency bypass capacitors as close as possible to the device
pins, with a minimum return loop back to the Thermal Pad.
• The AVIN bypass capacitor must be placed close to the AVIN pin and provide a low-impedance path to
PGND at the thermal pad. If AVIN is powered from PVIN for single supply operation, AVIN and PVIN must be
seperated with a 10-µs R-C filter to reduce PVIN switching noise on AVIN.
• The BP1V5 bypass capacitor must be placed close to the BP1V5 pin and provide a low-impedance path to
DRTN. DRTN must not be connected to any other pin or node. DRTN is internally connected to AGND and by
external connection to System Ground. Connecting DRTN to PGND or AGND can introduce a ground loop
and errant operation.
• Keep signal components local to the device, and place them as close as possible to the pins to which they
are connected. These components include the VOSNS and GOSNS series resistors and differential filter
capacitor as well as MSEL1, MSEL2, VSEL, and ADRSEL resistors. Those components can be terminated to
AGND with a minimum return loop or bypassed to the copper area of a separate low-impedance analog
ground (AGND) that is isolated from fast switching voltages and current paths and has single connection to
PGND on the thermal pad through the AGND pin. For placement recommendations, see 图8-18.
• The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low-
noise, low-impedance path.
• Minimize the SW copper area for best noise performance. Route sensitive traces away from the SW and
BOOT pins as these nets contain fast switching voltages and lend easily to capacitive coupling.
• Snubber component placement is critical for effective ringing reduction. These components must be on the
same layer as the TPS546D24S devices, and be kept as close as possible to the SW and PGND copper
areas.
• Route the VOSNS and GOSNS lines from the output capacitor bank at the load back to the device pins as a
tightly coupled differential pair. These traces must be kept away from switching or noisy areas which can add
differential-mode noise.
• Use caution when routing of the SYNC, VSHARE, BCX_CLK, and BCX_DAT traces for stackable
configurations. The SYNC trace carries a rail-to-rail signal and must be routed away from sensitive analog
signals, including the VSHARE, VOSNS, and GOSNS signals. The VSHARE traces must also be kept away
from fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and VDD5 pins.
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8.6.2 Layout Example
(Not to scale)
Place PVIN bypass capacitors as close
as possible to IC, with best high frequency
capacitor closest to PVIN/PGND pins
Bypass for internal regulators, AVIN.
Use multiple vias to reduce parasitic inductance
EN Signal
Internal AGND Plane to
reduce the VDD5/BP1V5
bypass parasitics.
Keep
feedback
and pin-strap
components
localized to
the IC.
PGND
PVIN
Kelvin Connect
to
IC VOSNS and
GOSNS pins
GOSNS/FLWR
If needed,
place node
breaking
Place best
high
frequency
output
RSNS–
resistor here
capacitor
between
sense points
AGND and
PGND are only
connected
together on
Thermal Pad.
Optional
RC
Snubber
VOUT
RSNS+
CBOOT
RBOOT
AGND
VOSNS
Sense point
should be
directly at the
load
L1
Minimize SW area
for least noise. Keep
For best efficiency, use a
heavy weight copper and
place these planes on multiple
PCB layers
PMBus
Communica
tion
sensitive traces
away from SW and
BOOT on all layers
图8-18. PCB Layout Recommendation
8.6.3 Mounting and Thermal Profile Recommendation
Proper mounting technique adequately covers the exposed thermal pad with solder. Excessive heat during the
reflow process can affect electrical performance. 图 8-19 shows the recommended reflow-oven thermal profile.
Proper post-assembly cleaning is also critical to device performance. Refer to QFN and SON PCB Attachment
application report for more information.
tP
TP
TL
TS(max)
TS(min)
tL
rRAMP(up)
rRAMP(down)
tS
t25P
Time (s)
图8-19. Recommended Reflow-Oven Thermal Profile
25
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表8-3. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
RAMP UP AND RAMP DOWN
rRAMP(up)
Average ramp-up rate, TS(max) to TP
Average ramp-down rate, TP to TS(max)
3
6
°C/s
°C/s
rRAMP(down)
PRE-HEAT
TS
Preheat temperature
150
60
200
180
°C
s
tS
Preheat time, TS(min) to TS(max)
REFLOW
TL
TP
tL
Liquidus temperature
217
°C
°C
s
Peak temperature
260
150
40
Time maintained above liquidus temperature, TL
Time maintained within 5°C of peak temperature, TP
Total time from 25°C to peak temperature, TP
60
20
tP
s
t25P
480
s
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.1.2 Development Support
9.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS546D24S device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.1.2.2 Texas Instruments Fusion Digital Power Designer
The TPS546x24x devices are supported by Texas Instruments Digital Power Designer. Fusion Digital Power
Designer is a graphical user interface (GUI) which can be used to configure and monitor the devices via PMBus
using a Texas Instruments USB-to-GPIO adapter.
Click this link to download the Texas Instruments Fusion Digital Power Designer software package.
9.2 Documentation Support
9.2.1 Related Documentation
Texas Instruments, QFN and SON PCB Attachment application report
9.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.5 Trademarks
SWIFT™ and TI E2E™ are trademarks of Texas Instruments.
PMBus® is a registered trademark of System Management Interface Forum, Inc..
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. These data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS546D24SRVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
TPS546D24S
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RVF0040A
LQFN-CLIP - 1.52 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
7.1
6.9
C
1.52
1.32
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.3 0.1
EXPOSED
THERMAL PAD
36X 0.5
13
20
12
21
41
SYMM
2X
5.3 0.1
5.5
32
1
0.3
40X
0.2
40
33
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.05
0.5
0.3
40X
4222989/B 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220.
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EXAMPLE BOARD LAYOUT
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.3)
6X (1.4)
40
33
40X (0.6)
1
32
40X (0.25)
2X
(1.12)
36X (0.5)
6X
(1.28)
(6.8)
(5.3)
41
SYMM
(R0.05) TYP
(
0.2) TYP
VIA
12
21
13
20
SYMM
(4.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222989/B 10/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RVF0040A
LQFN-CLIP - 1.52 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.815) TYP
40
33
40X (0.6)
1
41
32
40X (0.25)
(1.28)
TYP
36X (0.5)
(0.64)
TYP
SYMM
(6.8)
(R0.05) TYP
8X
(1.08)
12
21
METAL
TYP
20
13
8X (1.43)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222989/B 10/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号:
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4.5 to 5.5V Input, 8A Synchronous Step-Down SWIFT™ Converter 28-HTSSOP -40 to 85
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