TPS54974 [TI]
DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs; 双输入总线电压（2.5V ， 3.3V ）， 9 -A输出同步降压PWM具有集成FET SWITCHER
| 型号： | TPS54974 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs |
| 文件： | 总18页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Size
6,4 mm X 9,7 mm
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
DUAL INPUT BUS (2.5 V, 3.3 V) 9-A OUTPUT SYNCHRONOUS BUCK
PWM SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
DESCRIPTION
•
Low Voltage Separate Power Bus
As a member of the SWIFT™ family of dc/dc regu-
lators, the TPS54974 low-input voltage, high-output
current synchronous buck PWM converter integrates
all required active components. Included on the
•
15-mΩ MOSFET Switches for High Efficiency
at 9-A Continuous Output
•
•
Adjustable Output Voltage
substrate with the listed features are
a true,
Externally Compensated With 1% Internal
Reference Accuracy
high-performance, voltage error amplifier that enables
maximum performance under transient conditions
and flexibility in choosing the output filter L and C
components; an undervoltage-lockout circuit to pre-
vent start-up until the VIN input voltage reaches 3 V;
an internally and externally set slow-start circuit to
limit in-rush currents; and a power-good output useful
for processor/logic reset, fault signaling, and supply
sequencing.
•
•
Fast Transient Response
Wide PWM Frequency: Adjustable 280 kHz to
700 kHz
•
•
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
The TPS54974 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks.
APPLICATIONS
•
Low-Voltage, High-Density Systems
With Power Distributed at 2.5 V,
3.3 V Available
•
Point-of-Load Regulation for
High-Performance
DSPs, FPGAs, ASICs, and
Microprocessors
•
•
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
SIMPLIFIED SCHEMATIC
EFFICIENCY
vs
OUTPUT CURRENT
SIMPLIFIED SCHEMATIC
2.5 V or 3.3 V
100
95
Input1
PVIN
PH
Output
TPS54974
90
85
BOOT
PGND
3.3 V
80
75
70
Input2
VIN
COMP
VBIAS
VSENSE
AGND
65
60
VIN = 3.3 V,
PVIN = 2.5 V,
V
= 1.8 V,
Compensation
Network
O
55
50
f = 700 kHz
s
0
1
2
3
4
5
6
7
8
9
10
I
- Output Current - A
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
–40°C to 85°C
Adjustable down to 0.9 V
Plastic HTSSOP (PWP)(1)
TPS54974PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54974PWPR). See the application
section of the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54974
SS/ENA
–0.3 V to 7 V
–0.3 V to 6 V
–0.3 V to 4 V
–0.3 V to 4.5 V
–0.3 V to 10 V
–0.3 V to 7 V
–0.6 V to 6 V
Internally limited
6 mA
RT
VI
Input voltage range
VSENSE
PVIN, VIN
BOOT
VBIAS, COMP, PWRGD
PH
VO
Output voltage range
Source current
PH
IO
COMP, VBIAS
PH
16 A
IS
Sink current
COMP
6 mA
SS/ENA, PWRGD
AGND to PGND
10 mA
Voltage differential
±0.3 V
TJ
Operating virtual junction temperature range
Storage temperature
–40°C to 125°C
–65°C to 150°C
300°C
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VI
Input voltage, VIN
3
2.2
4
4.0
V
V
PVIN
TJ
Power input voltage
2.5
Operating junction temperature
–40
125
°C
DISSIPATION RATINGS(1)(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
28-Pin PWP with solder
14.4°C/W
6.94 W(3)
3.81 W
2.77 W
28-Pin PWP without solder
27.9°C/W
3.58 W
1.97 W
1.43 W
(1) For more information on the PWP package, see TI technical brief, literature number SLMA002.
(2) Test board conditions:
a. 3-inch x 3-inch, 4 layers, thickness: 0.062-inch
b. 1.5-oz. copper traces located on the top of the PCB
c. 1.5-oz. copper ground plane on the bottom of the PCB
d. 0.5-oz. copper ground planes on the 2 internal layers
e. 12 thermal vias (see "Recommended Land Pattern" in applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
2
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 2.8 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage range, VIN
3.0
2.2
4.0
4.0
V
V
Supply voltage range, PVIN
Output = 1.8 V
2.5
6.3
fs = 350 kHz, RT open, PH pin open, PVIN = 2.5 V
SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V
fs = 350 kHz, RT open, PH pin open, VIN = 3.3 V
SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V
10.0
1.4
VIN
mA
1
I(Q) Quiescent current
4.0
7.0
mA
µA
PVIN
<100
UNDER VOLTAGE LOCKOUT (VIN)
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.95
2.80
0.16
2.5
3.0
V
V
2.70
0.14
V
Rising and falling edge deglitch, UVLO(1)
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS(2)
I(VBIAS) = 0
2.70
2.80
2.90
100
V
µA
CUMULATIVE REFERENCE
0.88
2
Vref Accuracy
0.891 0.900
V
REGULATION
Line regulation(1)(3)
Load regulation(1)(3)
IL = 4.5 A, fs = 350 kHz, TJ = 85°C
0.07 %/V
0.03 %/A
IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C
OSCILLATOR
Internally set—free-running frequency
RT open(1)
RT = 180 kΩ (1% resistor to AGND)(1)
280
252
460
663
350
280
500
700
0.75
1
420 kHz
308
Externally set—free-running frequency range RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
Ramp valley(1)
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
540 kHz
762
V
V
200
ns
Maximum duty cycle(1)
90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10.
3
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 2.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
ERROR AMPLIFIER
Error amplifier open-loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND(1)
90 110
dB
Parallel 10 kΩ, 160 pF COMP to AGND(1)
Powered by internal LDO(1)
VSENSE = Vref
3
5
MHz
Error amplifier common mode input voltage
range
0
VBIAS
250
V
Input bias current, VSENSE
60
nA
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding
dead-time)
10-mV overdrive(1)
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA(1)
Falling edge deglitch, SS/ENA(1)
Internal slow-start time
0.82
1.2
0.03
2.5
1.4
V
V
µs
ms
µA
mA
2.6 3.35
4.1
8
Charge current, SS/ENA
SS/ENA = 0 V
3
5
Discharge current, SS/ENA
SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V
1.5
2.3
4.0
POWER GOOD
Power-good threshold voltage
Power-good hysteresis voltage(1)
Power-good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
VSENSE falling
90
3
%Vref
%Vref
µs
35
I(sink) = 2.5 mA
0.18
0.3
1
V
VIN = 3.3 V, PVIN = 2.5 V
µA
CURRENT LIMIT
Current limit
VIN = 3.3 V, PVIN = 2.5 V(1), Output shorted
11
15
100
200
A
Current limit leading edge blanking time(1)
Current limit total response time(1)
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip-point(1)
Thermal shutdown hysteresis(1)
135 150
10
165
°C
°C
OUTPUT POWER MOSFETS
VIN = 3 V, PVIN = 2.5 V
VIN = 3.6 V, PVIN = 2.5 V
15
14
30
28
rDS(on) Power MOSFET switches
mΩ
(1) Specified by design
4
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
PWP PACKAGE
(TOP VIEW)
1
28
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
VIN
2
27
26
25
24
23
22
21
20
19
18
17
16
15
3
SS/ENA
VBIAS
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
4
5
6
7
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
8
9
10
11
12
13
14
Terminal Functions
TERMINAL
DESCRIPTION
NAME
AGND
NO.
1
5
3
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT
resistor. Connect PowerPAD to AGND.
BOOT
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
PGND
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
15-19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single-point
connection to AGND is recommended.
PH
6-14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PVIN
20-24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high-quality, low-ESR 10-µF ceramic capacitor.
PWRGD
4
Power-good, open-drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or the internal shutdown signal is active.
RT
28
26
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
27
2
Input supply for the internal bias regulator. An external capacitor of 1 µF to be connected to the VIN pin.
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
VSENSE
5
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
VIN
REG
Enable
Comparator
SS/ENA
Falling
Edge
SHUTDOWN
ILIM
Comparator
1.2 V
Deglitch
Thermal
Shutdown
150°C
Hysteresis: 0.03 V
Leading
Edge
2.5 µs
Blanking
VIN UVLO
Comparator
Falling
100 ns
and
Rising
Edge
VIN
2.95 V
Deglitch
Hysteresis: 0.16 V
1
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
+
−
Adaptive Dead-Time
and
Control Logic
R
S
Q
Error
Amplifier
PWM
Comparator
Reference
VIN
VREF = 0.891 V
1
OSC
Power-Good
Comparator
VSENSE
Falling
Edge
0.90 V
ref
Deglitch
TPS54974
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
VSENSE
COMP
RT
RELATED DC/DC PRODUCTS
•
•
•
•
TPS40000—dc/dc controller
TPS56300—dc/dc controller
PT6600 series—9-A plug-in modules
TPS54910—dc/dc converter
6
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
25
20
750
650
550
25
20
VIN = 3.6 V
PVIN = 2.5 V
VIN = 3.0 V
PVIN = 2.5 V
I
= 9 A
I
= 9 A
O
O
15
15
10
10
5
450
350
250
5
0
0
-40
-40
0
25
85
125
0
25
85
125
-40
0
25
85
125
T - Junction Temperature - °C
J
T
J
- Junction Temperature - °C
T
J
- Junction Temperature - °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
JUNCTION TEMPERATURE
LOAD CURRENT
800
700
600
0.895
0.893
0.891
0.889
8
V = 3.3 V
I
7
6
5
4
3
2
1
0
T
J
= 125°C
RT = 68 kΩ
RT = 100 kΩ
RT = 180 kΩ
500
400
300
200
0.887
0.885
-40
0
25
85
125
0
2
4
6
8
10 12 14 16
-40
0
25
85
125
T
J
- Junction Temperature - °C
T
J
- Junction Temperature - °C
I
- Load Current - A
L
Figure 4.
Figure 5.
Figure 6.
REFERENCE VOLTAGE
vs
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
ERROR AMPLIFIER
OPEN-LOOP RESPONSE
INPUT VOLTAGE
0
3.80
0.895
0.893
0.891
0.889
140
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
VIN = 3.3 V,
PVIN = 2.5 V
PVIN = 2.5 V
-20
-40
-60
-80
120
100
80
L
3.65
3.50
A
Phase
Gain
3.35
-100
-120
-140
-160
-180
-200
60
3.20
3.05
40
20
0.887
0.885
0
2.90
2.75
-20
1
10 100 1 k 10 k 100 k 1 M 10 M
-40
0
25
85
125
3
3.1
3.2
3.3
3.4
3.5
3.6
f - Frequency - Hz
T
J
- Junction Temperature - °C
V - Input Voltage - V
I
Figure 7.
Figure 8.
Figure 9.
7
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54974 application. The TPS54974 (U1) can provide up
to 9 A of output current at a nominal outputvoltage of 1.8 V. For proper thermal performance, the exposed
thermal PowerPAD underneath the integrated circuit, TPS54974, package must be soldered to the printed-circuit
board.
PVIN
2.2 - 4.0 V
C13
22 µF
C10
22 µF
C12
22 µF
U1
TPS54974PWP
R6
28
24
23
RT
PVIN
71.5 kΩ
27
PVIN
PVIN
PVIN
PVIN
PH
VIN
3 - 4 V
22
21
C14
1 µF
C6
VIN
26
25
4
20
14
13
SS/ENA
R5
10 kΩ
0.047 µF
C3
PH
VBIAS
PWRGD
COMP
12
11
10
9
1 µF
PH
L1
0.65 µH
PH
C1
C4
PH
R2
R3
3
PH
V
O
4.02 kΩ
C2
8
7
6
C8
C7
C5
383 Ω
1200 pF
R1
3300 pF
PH
22 µF
22 µF
22 µF
PH
PH
BOOT
PGND
PGND
C9
120 pF
2
1
5
VSENSE
10 kΩ
19
18
17
16
15
0.047 µF
R7
2.4 Ω
R4
9.76 kΩ
PGND
PGND
PGND
AGND
C11
3300 pF
POWERPAD
Analog and Power Grounds Are Tied at the Pad Under the Package of IC
Figure 10. Application Circuit
The resistor divider network of R1 and R4 sets the
output voltage for the circuit at 1.8 V. R1 along with
R2, R3, C1, C2, and C4 forms the loop compensation
network for the circuit. For this design, a Type-3
topology is used.
COMPONENT SELECTION
The values for the components used in this design
example were selected for best load transient re-
sponse and small PCB area. Additional design infor-
mation is available at www.ti.com.
OPERATING FREQUENCY
INPUT FILTER
In the application circuit, RT is grounded through a
71.5-kΩ resistor to select the operating frequency of
700 kHz. To set a different frequency, place a 68-kΩ
to 180-kΩ resistor between RT (pin 28) and analog
ground or leave RT floating to select the default of
350 kHz. The resistance can be approximated using
the following equation:
The PVIN input voltage is nominally at 2.5 VDC. The
input filter consists of three 22-µF ceramic capacitors
(C10, C12, and C13) which must be located as close
as possible to the PVIN and PGND pins or the device
to provide high-frequency decoupling. Ripple current
is carried in all three capacitors. The return path to
PGND must be made so as to avoid introducing
circulating currents in the output filter stage.
500 kHz
Switching Frequency
R +
100 [kW]
(1)
FEEDBACK CIRCUIT
OPERATING WITH SEPARATE PVIN
The values for these components are selected to
provide fast transient response times.
The TPS54974 is designed to operate with the power
stage (high-side and low-side MOSFETs) with the
8
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
V
PVIN
0.9
PVIN input connected to a separate power source
from VIN. The primary intended application has VIN
connected to a 3.3-V bus and PVIN connected to a
2.5-V bus. The TPS54974 cannot be damaged by
any sequencing of these voltages. However, the
UVLO (see detailed description section) is referenced
to the VIN input. Some conditions may cause unde-
sirable operation.
O(max)
(min)
(2)
Care must be taken while operating when nominal
conditions cause duty cycles near 90%. Load transi-
ents can require momentary increases in duty cycle.
If the required duty cycle exceeds 90%, the output
may fall out of regulation.
PCB LAYOUT
If PVIN is absent when the VIN input is high, the
slow-start is released, and the PWM circuit goes to
maximum duty factor. When the PVN input ramps up,
the output of the TPS54974 follows the PVIN input
until enough voltage is present to regulate to the
proper output value.
Figure 12 shows a generalized PCB layout guide for
the TPS54974.
The PVIN pins should be connected together on the
printed-circuit board (PCB) and bypassed with a
low-ESR ceramic bypass capacitor. Care should be
taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the
TPS54974 ground pins. The minimum recommended
bypass capacitance is 10 µF ceramic with a X5R or
X7R dielectric and the optimum placement is closest
to the VIN pins and the PGND pins. If the VIN is
connected to a separate source supply, it should be
bypassed with its own capacitor.
NOTE:
If the PVIN input is controlled via a fast bus switch, it
results in a hard-start condition and may damage the
load (i.e., whatever is connected to the regulated
output of the TPS54974). If a power-good signal is
not available from the 2.5-V power supply, one can
be generated using a comparator and hold the
SS/ENA pin low until the 2.5-V bus power is good. An
example of this is shown in Figure 11. This circuit can
also be used to prevent the TPS54974 output from
following the PVIN input while the PVIN power supply
is ramping up.
The TPS54974 has two internal grounds (analog and
power). Inside the TPS54974, the analog ground ties
to all of the noise-sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54974, particularly at higher
output currents. Ground noise on an analog ground
plane can also cause problems with some of the
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
There should be an area of ground on the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND
pins should be tied to the PCB ground by connecting
them to the ground area under the device as shown.
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling ca-
pacitor, and the PGND pins of the TPS54974. Use a
separate wide trace for the analog ground signal
path. This analog ground should be used for the
voltage set-point divider, timing resistor RT, slow-start
capacitor, and bias-capacitor grounds. Connect this
trace directly to AGND (pin 1).
100 kΩ
VIN
10 kΩ
PVIN
VBIAS
+
-
SS/ENA
1/2 LM293
10 kΩ
27.4 kΩ
Figure 11. Undervoltage Lockout Circuit for PVIN
Using Open-Collector or Open-Drain Comparator
PVIN and VIN can be tied together for 3.3-V bus
operation.
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor
and 3 x 22-µF capacitor. The inductor is a low
dc-resistance (0.017 Ω) type, Pulse Engineering
PA0277. The capacitors used are 22-µF, 6.3-V cer-
amic types with X5R dielectric. The feedback loop is
compensated so that the unity gain frequency is
approximately 75 kHz.
The PH pins should be tied together and routed to
the output inductor. Because the PH connection is
the switching node, the inductor should be located
close to the PH pins and the area of the PCB
conductor minimized to prevent excessive capacitive
coupling.
MAXIMUM OUTPUT VOLTAGE
The maximum attainable output voltage is limited by
the minimum voltage at the PVIN pin. Nominal
maximum duty cycle is limited to 90% in the
TPS54974, so maximum output voltage is:
9
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace
lengths.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pinout,
they have to be routed somewhat close, but maintain
as much separation as possible while still keeping the
layout compact.
Connect the output filter capacitor(s) as shown be-
tween the VOUT trace and PGND. It is important to
keep the loop formed by the PH pins, Lout, Cout, and
PGND as small as practical.
Connect the bias capacitor from the VBIAS pin to
analog ground using the isolated analog ground
trace. If an RT resistor or slow-start capacitor is used,
connect them to this trace as well.
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
SYNC
SS/ENA
VBIAS
VIN
SLOW-START
INPUT
CAPACITOR
BYPASS
VSENSE
CAPACITOR
COMPENSATION
NETWORK
COMP
BIAS CAPACITOR
PWRGD
BOOT
BOOT
CAPACITOR
VIN
PVIN
EXPOSED
PH
PH
PH
PH
PH
PH
PH
PH
PH
VOUT
PVIN
POWERPAD
PVIN
PVIN
PH
PVIN
AREA
PGND
PGND
PGND
PGND
PGND
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
INPUT
INPUT
BULK
BYPASS
CAPACITOR
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 12. PCB Layout for 28-Pin PWP PowerPAD
10
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
any area available must be used when 6-A or greater
operation is desired. Connection from the exposed
area of the PowerPAD to the analog ground plane
layer must be made using 0.013-inch diameter vias to
avoid solder wicking through the vias.
For operation at full rated load current, the analog
ground plane must provide an adequate heat dissi-
pating area. A 3-inch by 3-inch plane of 1-ounce
copper is recommended, though not mandatory, de-
pending on ambient temperature and airflow. Most
applications have larger areas of internal ground
plane available, and the PowerPAD must be connec-
ted to the largest area available. Additional areas on
the top or bottom layers also help dissipate heat, and
Eight vias must be in the PowerPAD area with four
additional vias located under the device package. The
size of the vias under the package, but not in the
exposed thermal pad area, can be increased to
0.018-inch. Additional vias, beyond the twelve rec-
ommended that enhance thermal performance, must
be included in areas not under the device package.
PERFORMANCE GRAPHS
Data shown is for the circuit of Figure 10. All data is for VIN = 3.3 V, PVIN = 2.5 V, VOUT = 1.8 V, fs = 700 kHz,
and TA = 25°C, unless otherwise specified
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT VOLTAGE CHANGE
OUTPUT VOLTAGE CHANGE
vs
vs
OUTPUT CURRENT
VIN INPUT VOLTAGE
0.5
100
95
0.5
I
= 0 A
O
0.4
0.3
0.4
0.3
90
85
0.2
0.1
0.2
0.1
0
80
75
70
I
= 4.5 A
O
0
−0.1
−0.1
−0.2
65
60
−0.2
−0.3
VIN = 3.3 V,
PVIN = 2.5 V,
I
= 9 A
−0.3
−0.4
−0.5
O
V
= 1.8 V,
O
55
50
−0.4
−0.5
f = 700 kHz
s
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
3
3.2
3.4
3.6
3.8
4
I
− Output Current − A
I
− Output Current − A
V
− VIN Input Voltage − V
I(VIN)
O
O
Figure 13.
Figure 14.
Figure 15.
OUTPUT VOLTAGE CHANGE
vs
AMBIENT TEMPERATURE
vs
PVIN INPUT VOLTAGE
LOAD CURRENT(1)
OUTPUT RIPPLE VOLTAGE
125
115
105
95
0.5
PVIN = 2.5 V,
I
= 0 A
O
0.4
0.3
0.2
0.1
f
= 700 kHz,
s
Vout
T
J
= 125°C,
VIN = 3.3 V,
= 1.8 V
V
O
85
I
= 4.5 A
O
Vphase
75
0
Safe Operating Area
65
−0.1
−0.2
−0.3
55
45
I
= 9 A
O
35
−0.4
−0.5
25
0
2
4
6
8
10 12 14 16
2.2
2.4
2.6
2.8
1 µs/div
I
− Output Current − A
V
− PVIN Input Voltage − V
O
I(PVIN)
Figure 16.
Figure 17.
Figure 18.
11
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
PERFORMANCE GRAPHS (continued)
INPUT RIPPLE VOLTAGE
LOAD TRANSIENT RESPONSEDummy
START UP WAVEFORM(2)
SS/ENA
Non Inverting Comparator Input
Vphase
Iout = 2.25 to 6.75 A Step
1 µs/div
500 µs/div
5 ms/div
Figure 19.
Figure 20.
Figure 21.
1. Safe operating area is applicable to the test board conditions in the Dissipation Ratings.
2. Using the undervoltage lockout circuit of Figure 11.
DETAILED DESCRIPTION
Adding a capacitor to the SS/ENA pin has two effects
UNDERVOLTAGE LOCKOUT (UVLO)
on start-up. First, a delay occurs between release of
the SS/ENA pin and start-up of the output. The delay
is proportional to the slow-start capacitor value and
lasts until the SS/ENA pin reaches the enable
threshold. The start-up delay is approximately:
The TPS54974 incorporates an undervoltage lockout
circuit to keep the device disabled when the input
voltage (VIN) is insufficient. During power up, internal
circuits are held inactive until VIN exceeds the
nominal UVLO threshold voltage of 2.95 V. Once the
UVLO start threshold is reached, device start-up
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
the UVLO comparator, and a 2.5-µs rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN. The UVLO is
with respect to VIN and not PVIN; see application
note.
1.2 V
t
+ C
d
(SS)
5 mA
(3)
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be ob-
served before the externally set slow-start rate takes
control and the output rises at a rate proportional to
the slow-start capacitor. The slow-start time set by
the capacitor is approximately:
0.7 V
t
+ C
SLOW-START/ENABLE (SS/ENA)
(SS)
(SS)
5 mA
(4)
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage ex-
ceeds the start threshold voltage of approximately 1.2
V. When SS/ENA exceeds the enable threshold,
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5-µs falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
high quality, low-ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R- or X5R-grade
dielectrics are recommended because their values
are more stable over temperature. The bypass ca-
pacitor must be placed close to the VBIAS pin and
returned to AGND.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
and AGND.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
12
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
VBIAS of 2.7 V, and external loads on VBIAS with ac
or digital switching noise may degrade performance.
The VBIAS pin may be useful as a reference voltage
for external circuits. VBIAS is derived from the VIN
pin (see the internal block diagram).
error amplifier output voltage, the PWM comparator
resets the latch, thus turning off the high-side FET
and turning on the low-side FET. The low-side FET
remains on until the next oscillator pulse discharges
the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset, and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
low-side FET on. The device operates at its maxi-
mum duty cycle until the output voltage rises to the
regulation set-point, setting VSENSE to approxi-
mately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually
reset and the high-side FET does not turn on. The
low-side FET remains on until the VSENSE voltage
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature-stable
bandgap circuit. During manufacture, the bandgap
and scaling circuits are trimmed to produce 0.891 V
at the output of the error amplifier, with the amplifier
connected as a voltage follower. The trim procedure
adds to the high-precision regulation of the
TPS54974, because it cancels offset errors in the
scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
decreases to
a
range that allows the PWM
The oscillator frequency is set to an internally fixed
value of 350 kHz. The oscillator frequency can be
externally adjusted from 280 to 700 kHz by con-
necting a resistor between the RT pin to ground. The
switching frequency is approximated by the following
equation, where R is the resistance from RT to
AGND:
comparator to change states. The TPS54974 is
capable of sinking current continuously until the
output reaches the regulation set-point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
turns off and low-side FET turns on to decrease the
energy in the output inductor and consequently the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
100 kW
Switching Frequency +
500 [kHz]
R
(5)
ERROR AMPLIFIER
The high-performance, wide bandwidth, voltage error
amplifier sets the TPS54974 apart from most dc/dc
converters. The user is given the flexibility to use a
wide range of output L and C filter components to suit
the particular application needs. Type-2 or Type-3
compensation can be employed using external com-
pensation components.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs during the switching transitions by actively
controlling the turnon times of the MOSFET drivers.
The high-side driver does not turn on until the voltage
at the gate of the low-side FET is below 2 V. While
the low-side driver does not turn on until the voltage
at the gate of the high-side MOSFET is below 2 V.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time
and control-logic block. During steady-state operation
below the current limit threshold, the PWM
comparator output and oscillator pulse train alter-
nately reset and set the PWM latch. Once the PWM
latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width.
During this period, the PWM ramp discharges rapidly
to its valley voltage. When the ramp begins to charge
back up, the low-side FET turns off and high-side
FET turns on. As the PWM ramp voltage exceeds the
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is sup-
plied from VIN, while the high-side drive is supplied
from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω
bootstrap switch connected between the VIN and
BOOT pins. The integrated bootstrap switch improves
drive efficiency and reduces external component
count.
13
TPS54974
www.ti.com
SLVS458B–JANUARY 2003–REVISED FEBRUARY 2005
OVERCURRENT PROTECTION
Thermal shutdown provides protection when an over-
load condition is sustained for several milliseconds.
With a persistent fault condition, the device cycles
continuously; starting up by control of the slow-start
circuit, heating up due to the fault condition, and then
shutting down on reaching the thermal shutdown
trip-point. This sequence repeats until the fault con-
dition is removed.
The cycle-by-cycle current limiting is achieved by
sensing the current flowing through the high-side
MOSFET and comparing this signal to a preset
overcurrent threshold. The high-side MOSFET is
turned off within 200 ns of reaching the current limit
threshold. A 100-ns leading edge blanking circuit
prevents current limit false tripping. Current limit
detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
POWER-GOOD (PWRGD)
The power-good circuit monitors for undervoltage
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold or SS/ENA
is low. When VIN ≥ UVLO threshold, SS/ENA ≥
enable threshold, and VSENSE > 90% of Vref, the
open-drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs
falling edge deglitch circuit prevent tripping of the
power-good comparator due to high-frequency noise.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown automatically when the junc-
tion temperature decreases to 10°C below the ther-
mal shutdown trip-point, and starts up under control
of the slow-start circuit.
14
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
TPS54974PWP
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
28
28
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS54974PWPR
TPS54974PWPRG4
HTSSOP
HTSSOP
PWP
PWP
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
TPS54974PWP
DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs
TI
TPS54974PWPG4
16A SWITCHING REGULATOR, 762kHz SWITCHING FREQ-MAX, PDSO28, GREEN, PLASTIC, HTSSOP-28
TI
TPS54974PWPR
DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs
TI
TPS54974PWPRG4
DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs
TI
TPS54980
3-V TO 4-V INPUT 9-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS FOR SEQUENCING
TI
TPS54980PWP
3-V TO 4-V INPUT 9-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS FOR SEQUENCING
TI
TPS54980PWPR
3-V TO 4-V INPUT 9-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS FOR SEQUENCING
TI
TPS54980PWPRG4
3-V TO 4-V INPUT,9-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTERRATED FETs(SWIFT)FOR SEQUENCING
TI
TPS54980_16
3-V TO 4-V INPUT,9-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTERRATED FETs(SWIFT)FOR SEQUENCING
TI
©2020 ICPDF网 联系我们和版权申明