TPS54JB20 [TI]
具有遥感功能和闭锁电流限制的 2.7V 至 16V 输入、20A 同步降压转换器;
| 型号： | TPS54JB20 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有遥感功能和闭锁电流限制的 2.7V 至 16V 输入、20A 同步降压转换器 转换器 |
| 文件： | 总47页 (文件大小：2839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSMS1B – JULY 2020 – REVISED NOVEMBER 2020
TPS54JB20
具有遥感、3V 内部 LDO 和闭锁电流限制功能的
TPS54JB20 2.7V 至 16V 输入、20A 同步降压转换器
1 特性
2 应用
•
输入范围为 4V 至 16V，电流高达 20A，无外部偏
压
•
•
•
•
机架式服务器和刀片式服务器
硬件加速卡和插件卡
数据中心交换机
•
输入范围为 2.7V 至 16V，电流高达 20A，外部偏
压范围为 3.13V 至 3.6V
工业 PC
•
•
输出电压范围：0.9V 至 5.5V
集成 7.7mΩ 和 2.4mΩ MOSFET 支持 20A 持续输
出电流
3 说明
TPS54JB20 器件是一款具有自适应导通时间 D-CAP3
控制模式的小型高效同步降压转换器。该器件不需要外
部补偿，因此易于使用并且仅需要很少的外部元件。该
器件非常适合空间受限的数据中心应用。
• D-CAP3™，可提供超快负载阶跃响应
•
支持所有陶瓷输出电容器
•
在 –40°C 至 +125°C 结温下实现差分遥感，VREF
为 0.9V ±1%
TPS54JB20 器件具有差分遥感功能和高性能集成
MOSFET，在整个工作结温范围具有高精度 (±1%)
0.9V 电压基准。该器件具有快速负载瞬态响应、精确
负载调节和线路调节、跳跃模式或 FCCM 运行以及可
编程软启动功能。
•
•
•
•
•
•
•
•
•
自动跳跃 Eco-mode™ 可实现高轻负载效率
通过 RTRIP 实现可编程电流限制
引脚可选开关频率：600kHz、800kHz、1MHz
可实现高输出精度的差分遥感功能
可编程软启动时间
TPS54JB20 器件是一款无铅器件。完全符合 RoHS 标
准，无需豁免。
外部基准输入，用于跟踪
预偏置启动功能
器件信息
开漏电源正常状态输出
器件型号(1)
TPS54JB20
封装尺寸（标称值）
封装
在发生 OC、UV 和 OV 故障时进入闭锁模式
VQFN-HR (21)
4.00mm × 3.00mm
• 4mm × 3mm 21 引脚 QFN 封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
与 12A TPS54JA20 引脚兼容
完全符合 RoHS 标准，无需豁免
100
96
92
88
84
80
VIN
10
21
1
VIN
VIN
BOOT
VOUT
8
20
EN
SW
TPS54JB20
19
9
VCC
Vosns+
76
7
FB
PGOOD
MODE
TRIP
Vin = 12 V
600 kHz
800 nH
VCC = INT
FCCM
72
68
64
60
4
Vosns-
6
5
VSNS-
3
Vout = 3.3 V
16 18 20
SS/
2
REFIN
AGND
0
2
4
6
8
10
Output Current (A)
12
14
PGND
Net-tie
D001
效率图
简化版原理图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBM9
TPS54JB20
ZHCSMS1B – JULY 2020 – REVISED NOVEMBER 2020
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................23
8 Application and Implementation..................................27
8.1 Application Information............................................. 27
8.2 Typical Application.................................................... 27
9 Power Supply Recommendations................................39
10 Layout...........................................................................39
10.1 Layout Guidelines................................................... 39
10.2 Layout Example...................................................... 40
11 Device and Documentation Support..........................41
11.1 Documentation Support.......................................... 41
11.2 Trademarks............................................................. 41
11.3 Electrostatic Discharge Caution..............................41
11.4 Glossary..................................................................41
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics..............................................10
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
Information.................................................................... 42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2020) to Revision B (November 2020)
Page
•
首次公开发布...................................................................................................................................................... 1
Changes from Revision * (July 2020) to Revision A (October 2020)
Page
• Changed minimum RTRIP min value to 0 kΩ......................................................................................................5
• Changed maximum peak inductor current max value to 35 A............................................................................5
• Updated current limit clamp max value to 25 A.................................................................................................. 6
• Updated TRIP pin resistance range min value to 0 kΩ......................................................................................6
• Updated Rtrip resistor range for current limit clamp........................................................................................... 6
• Updated current limit clamp typical value to 22.9 A............................................................................................6
• Added Series BOOT Resistor and RC Snubber section...................................................................................32
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5 Pin Configuration and Functions
VIN
21
SW
20
SW
20
VIN
21
BOOT
1
19 VCC
VCC
19
1
BOOT
AGND
TRIP
2
3
4
5
6
7
8
18 PGND
17 PGND
16 PGND
15 PGND
14 PGND
13 PGND
12 PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
18
17
16
15
14
13
12
2
3
4
5
6
7
8
AGND
TRIP
MODE
SS/REFIN
VSNS-
FB
MODE
SS/REFIN
VSNS-
FB
EN
EN
PGOOD
9
11 PGND
PGND
11
9
PGOOD
10
10
VIN
VIN
图 5-1. RWW Package 21-Pin VQFN-HR Top View
图 5-2. RWW Package 21-Pin VQFN-HR Bottom
View
表 5-1. Pin Functions
NO.
NAME
BOOT
AGND
I/O(1)
I/O
G
DESCRIPTION
Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap
capacitor from this pin to SW node.
1
2
Ground pin. Reference point for the internal control circuits.
Current limit setting pin. Connect a resistor to AGND to set the current limit trip
point. ±1% tolerance resistor is highly recommended. See 节 7.3.9 for details on
OCL setting.
3
4
TRIP
I/O
I
The MODE pin sets the forced continuous-conduction mode (FCCM) or skip-
mode operation. It also selects the operating frequency by connecting a resistor
from MODE pin to AGND pin. ±1% tolerance resistor is recommended. See 表
7-1 for details.
MODE
Dual-function pin. Soft-start function: Connecting a capacitor to VSNS– pin
programs soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. A
minimum 1-nF capacitor is required for this pin to avoid overshoot during the
charge of soft-start capacitor. REFIN function: The device always looks at the
voltage on this SS/REFIN pin as the reference for the control loop. The internal
reference voltage can be overridden by an external DC voltage source on this pin
for tracking application.
5
SS/REFIN
I/O
The return connection for a remote voltage sensing configuration. It is also used
as ground for the internal reference. Short to AGND for single-end sense
configuration.
6
7
I
I
VSNS–
Output voltage feedback input. A resistor divider from the VOUT to VSNS–
(tapped to FB pin) sets the output voltage.
FB
Enable pin. The enable pin turns the DC/DC switching converter on or off.
Floating EN pin before start-up disables the converter. The recommended
operating condition for EN pin is maximum 5.5-V. Do not connect EN pin to VIN
pin directly.
8
9
EN
I
Open-drain power-good status signal. When the FB voltage moves outside the
specified limits, PGOOD goes low after 2-µs delay.
PGOOD
O
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表 5-1. Pin Functions (continued)
NO.
10, 21
NAME
I/O(1)
DESCRIPTION
Power-supply input pins for both integrated power MOSFET pair and the internal
LDO. Place the decoupling input capacitors from VIN pins to PGND pins as close
as possible.
VIN
P
Power ground of internal low-side MOSFET. At least six PGND vias are required
to be placed as close as possible to the PGND pins. This minimizes parasitic
impedance and also lowers thermal resistance.
11, 12, 13, 14,
15, 16, 17, 18
PGND
G
Internal 3-V LDO output. An external bias with 3.3-V or higher voltage can be
connected to this pin to save the power losses on the internal LDO. The voltage
source on this pin powers both the internal circuitry and gate driver. Requires a
2.2-µF, at least 6.3-V, rating ceramic capacitor from VCC pin to PGND pins as the
decoupling capacitor and the placement is required to be as close as possible.
19
20
VCC
SW
I/O
O
Output switching terminal of the power converter. Connect this pin to the output
inductor.
(1) I = Input, O = Output, P = Supply, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–1.5
–0.3
–5
MAX
18
18
25
18
21.5
22
4
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
VIN
V
VIN – SW, DC
VIN – SW, < 10 ns transient
SW – PGND, DC
SW – PGND, < 10 ns transient
BOOT – PGND
BOOT – SW
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
VCC
4
V
EN, PGOOD
6
V
MODE
4
V
TRIP, SS/REFIN, FB
VSNS–
3
V
0.3
10
150
150
V
Sinking current Power Good sinking current capability
Operating junction temperature, TJ
mA
°C
°C
–40
–55
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
16
UNIT
V
VIN
VIN
Input voltage range when VCC pin is powered by a valid external bias
Input voltage range when using the internal VCC LDO
4.0
16
V
Minimum VIN before enabling the converter when using the internal VCC
LDO
VIN
3.3
V
VOUT
Output voltage range
0.9
3.13
5.5
3.6
V
V
Pin voltage External VCC bias
Pin voltage BOOT to SW
Pin voltage EN, PGOOD
Pin voltage MODE
3.6
V
–0.1
–0.1
–0.1
–0.1
–50
5.5
V
VCC
1.5
V
Pin voltage TRIP, SS/REFIN, FB
V
Pin voltage
50
mV
VSNS– (refer to AGND)
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Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
mA
A
IPG
Power Good input current capability
Maximum peak inductor current
Minimum RTRIP
0
10
35
ILPEAK
0
kΩ
°C
TJ
Operating junction temperature
125
–40
6.4 Thermal Information
TPS54JB20
THERMAL METRIC(1)
RWW (QFN, JEDEC)
RWW (QFN, TI EVM)
UNIT
21 PINS
49.0
23.0
9.2
21 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
24.1
°C/W
°C/W
°C/W
°C/W
°C/W
Not applicable (2)
Not applicable (2)
0.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
9.0
8.7
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM layout.
6.5 Electrical Characteristics
TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VIN = 12 V, VEN = 2 V, VFB = VINTREF
50mV (non-switching), no external
bias on VCC pin
+
IQ(VIN)
VIN quiescent current
910
9.5
680
40
1007
20
µA
µA
µA
µA
VIN = 12 V, VEN = 0 V, no external bias
on VCC pin
ISD(VIN)
IQ(VCC)
ISD(VCC)
VIN shutdown supply current
VCC quiescent current
VCC shutdown current
TJ = 25°C, VIN = 12 V, VEN = 2 V, VFB
= VINTREF + 50mV (non-switching), 3.3
V external bias on VCC pin
820
60
VEN = 0 V, VIN = 0 V, 3.3 V external
bias on VCC pin
UVLO
VINUVLO(rise)
VINUVLO(fall)
ENABLE
VEN(rise)
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN rising, VCC = 3.3 V external bias
VIN falling, VCC = 3.3 V external bias
2.1
2.4
2.7
V
V
1.55
1.85
2.15
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
EN rising, enable switching
EN falling, disable switching
1.17
0.97
1.22
1.02
0.2
1.27
1.07
V
V
VEN(fall)
VEN(hyst)
VEN(LKG)
V
Input leakage current into EN pin
VEN = 3.3 V
0.5
5
µA
EN pin to AGND. EN floating disables
the converter.
EN internal pull-down resistance
6500
kΩ
INTERNAL LDO (VCC PIN)
Internal LDO output voltage
VIN = 12 V, IVCC(Load) = 2 mA
VCC rising
2.90
2.80
2.62
3.02
2.87
2.70
0.17
3.12
2.94
2.77
V
V
V
VCCUVLO(rise)
VCCUVLO(fall)
VCCUVLO(hys)
VCC UVLO rising threshold
VCC UVLO falling threshold
VCC UVLO hysteresis
VCC falling
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TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TJ = 25°C, VIN = 4.0 V, IVCC(Load) = 20
mA, non-switching
VCC LDO dropout voltage, 20mA load
VCC LDO short-circuit current limit
FB Threshold to turn off VCC LDO
1.037
158
V
VIN = 12 V, all temperature
52
105
90
mA
mV
VCC LDO turn-off is controlled by FB
voltage during EN shutdown event
146
REFERENCE VOLTAGE
VINTREF
Internal voltage reference
TJ = 25°C
900
1
mV
mV
mV
nA
Internal voltage reference range
Internal voltage reference range
Input leakage current into FB pin
TJ = 0°C to 85°C
TJ = –40°C to 125°C
VFB = VINTREF
896
891
904
909
40
IFB(LKG)
TJ = -40°C to 125°C, VSS/REFIN = 0.9 V,
VSNS- = AGND, refer to VINTREF
SS/REFIN-to-FB Accuracy
0.6%
–0.6%
SWITCHING FREQUENCY
TJ = 25°C, VIN = 12 V, VOUT=1.25V,
RMODE = 0 Ω to AGND
0.5
0.6
0.6
0.7
0.7
TJ = 25°C, VIN = 12 V, VOUT=1.25V,
RMODE = 30.1 kΩ to AGND
SW switching frequency, FCCM
operation
fSW
0.8 MHz
1.0
TJ = 25°C, VIN = 12 V, VOUT=1.25V,
RMODE = 60.4 kΩ to AGND
0.70
0.85(2)
STARTUP
The delay from EN goes high to the
first SW rising edge with internal LDO
configuration. CVCC = 2.2 µF. CSS/REFIN
= 220 nF.
EN to first switching delay, internal
LDO
0.93
2
ms
The delay from EN goes high to the
first SW rising edge with external VCC
bias configuration. VCC bias should
reach regulation before EN ramp up.
CSS/REFIN = 220 nF.
EN to first switching delay, external
VCC bias
0.55
1.5
0.9
ms
ms
VO rising from 0 V to 95% of final
setpoint, CSS/REFIN = 1nF
tSS
Internal fixed Soft-start time
1
SS/REFIN sourcing current
SS/REFIN sinking current
VSS/REFIN = 0 V
VSS/REFIN = 1 V
36
12
µA
µA
POWER STAGE
RDSON(HS)
RDSON(LS)
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
Minimum on-time
7.7
2.4
70
TJ = 25°C, BOOT–SW = 3 V
TJ = 25°C, VCC = 3 V
mΩ
mΩ
ns
tON(min)
TJ = 25°C, VCC = Internal LDO
85
TJ = 25°C, VCC = Internal LDO, HS
FET Gate falling to rising
tOFF(min)
Minimum off-time
220
ns
BOOT CIRCUIT
IBOOT(LKG)
BOOT leakage current
TJ = 25°C, VBOOT-SW = 3.3 V
35
50
µA
V
VBOOT-SW(UV_F)
BOOT-SW UVLO falling threshold
TJ = 25°C, VIN = 12 V, VBOOT-SW falling
2.0
OVERCURRENT PROTECTION
RTRIP
TRIP pin resistance range
0
20
25
kΩ
Valley current on LS FET, 0-Ω ≤
Current limit clamp
19.2
22.9
120000
22.9
A
R
TRIP ≤ 5.24-kΩ
KOCL
Constant for RTRIP equation
Current limit threshold
A×Ω
Valley current on LS FET, RTRIP
=
IOCL (valley)
19.2
25
A
5.23kΩ
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MAX UNIT
TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Valley current on LS FET, RTRIP = 6.04
kΩ
IOCL (valley)
IOCL (valley)
IOCL (valley)
IOCL (valley)
IOCL (valley)
Current limit threshold
Current limit threshold
Current limit threshold
Current limit threshold
Current limit threshold
17.5
19.9
22.3
17.9
13.4
9.7
A
A
A
A
A
Valley current on LS FET, RTRIP = 7.5
kΩ
14.1
10.6
6.7
16
12
8.2
6
Valley current on LS FET, RTRIP = 10
kΩ
Valley current on LS FET, RTRIP = 14.7
kΩ
Valley current on LS FET, RTRIP = 20
kΩ
4.7
7.3
KOCL
KOCL
KOCL
KOCL
INOCL
Constant KOCL tolerance
Constant KOCL tolerance
Constant KOCL tolerance
Constant KOCL tolerance
Negative current limit threshold
-16.4%
-12%
-18%
-21%
–12
9%
12%
18%
21%
–8
RTRIP = 5.23 kΩ
6.04 kΩ ≤ RTRIP ≤ 10 kΩ
RTRIP = 14.7 kΩ
RTRIP = 20 kΩ
All VINs
A
–10
Zero-cross detection current threshold,
open loop
IZC
VIN = 12 V, VCC = Internal LDO
400
mA
OUTPUT OVP AND UVP
Output Overvoltage-protection (OVP)
threshold voltage
VOVP
113%
77%
116%
400
80%
68
119%
83%
tOVP(delay)
VUVP
Output OVP response delay
With 100-mV overdrive
ns
µs
Output Undervoltage-protection (UVP)
threshold voltage
tUVP(delay)
Output UVP filter delay
PGOOD threshold
POWER GOOD
PGOOD high, FB rising
PGOOD low, FB rising
PGOOD low, FB falling
PGOOD high, FB rising
89%
113%
77%
92.5%
116%
80%
95%
119%
83%
VPGTH
OOB (Out-Of-Bounds) threshold
PGOOD sink current
103% 105.5%
108%
VPGOOD = 0.4 V, VIN = 12 V, VCC =
Internal LDO
IPG
17
mA
mV
IPGOOD = 5.5 mA, VIN = 12 V, VCC =
Internal LDO
VPG(low)
PGOOD low-level output voltage
400
tPGDLY(rise)
tPGDLY(fall)
Delay for PGOOD from low to high
Delay for PGOOD from high to low
1.06
0.5
1.33
5
ms
µs
PGOOD leakage current when pulled TJ = 25°C, VPGOOD = 3.3 V, VFB
=
IPG(LKG)
5
µA
high
VINTREF
VIN = 0 V, VCC = 0 V, VEN = 0 V,
PGOOD pulled up to 3.3 V through a
100-kΩ resistor
710
850
850
mV
PGOOD clamp low-level output
voltage
VIN = 0 V, VCC = 0 V, VEN = 0 V,
PGOOD pulled up to 3.3 V through a
10-kΩ resistor
1000
1.5
mV
V
Min VCC for valid PGOOD output
V
PGOOD ≤ 0.4 V
OUTPUT DISCHARGE
VIN = 12 V, VCC = Internal LDO, VSW
= 0.5 V, power conversion disabled
RDischg
Output discharge resistance
70
Ω
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold(1)
Temperature rising
150
165
°C
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TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THYST
Thermal shutdown hysteresis(1)
30
°C
(1) Specified by design. Not production tested.
(2) Fsw variates with Vout due to D-CAP3 control mode.
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6.6 Typical Characteristics
100
96
92
88
84
80
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
76
Vin = 12 V
600 kHz
800 nH
VCC = INT
Skip
Vin = 12 V
600 kHz
800 nH
VCC = INT
FCCM
72
68
64
60
Vout = 3.3V
Vout = 3.3 V
16 18 20
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
0
2
4
6
8
10
Output Current (A)
12
14
D002
D001
图 6-2. Efficiency vs Output Current, VCC = Int
图 6-1. Efficiency vs Output Current, VCC = Int
Skip-Mode
115
105
95
115
105
95
85
85
75
75
65
65
55
55
Nat Conv
100 LFM
Nat Conv
100 LFM
45
45
200LFM
400LFM
200LFM
400LFM
35
35
25
25
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
D002
D001
Vin = 12 V
800 nH
Vout = 5 V
600 Khz
Int Vcc
Vin = 12 V
300 nH
Vout = 1 V
800 Khz
Int Vcc
图 6-4. Safe Operating Area, VOUT = 5 V
图 6-3. Safe Operating Area, VOUT = 1.0 V
115
115
105
95
85
75
65
55
45
35
25
105
95
85
75
65
55
45
35
25
Nat Conv
100 LFM
200LFM
400LFM
Nat Conv
100 LFM
200LFM
400LFM
0
2
4
6
8
Output Current (A)
10
12
14
16
18
20
0
2
4
6
8
Output Current (A)
10
12
14
16
18
20
D003
D004
Vin = 12 V
300 nH
Vout = 1 V
800 Khz
Ext Vcc 3.3 V
Vin = 12 V
800 nH
Vout = 5 V
600 Khz
Ext Vcc 3.3 V
图 6-5. Safe Operating Area, VOUT = 1 V
图 6-6. Safe Operating Area, VOUT = 5 V
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20
15
10
5
3.355
Vin = 8V
Vin = 12V
Vin = 16V
800 nH
3.35
3.345
3.34
600 kHz
VCC = Int
FCCM
3.335
3.33
3.325
3.32
3.315
3.31
0
-50
-25
0
25
50
75
100
125
150
3.305
3.3
Junction Temperature (èC)
D014
VIN = 12 V
VEN = 0 V
Internal VCC LDO
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
D010
图 6-8. ISD(VIN) vs Junction Temperature
图 6-7. Output Voltage vs Output Current
3.04
0.904
3.03
3.02
3.01
3
0.902
0.9
0.898
2.99
-50
-25
0
25
50
75
100
125
150
0.896
Junction Temperature (èC)
D015
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D016
VIN = 12 V
IVCC = 2 mA
VIN = 12 V
图 6-9. VCC LDO vs Junction Temperature
图 6-10. VINTREF vs Junction Temperature
40
39
38
37
36
35
34
33
32
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D020
VIN = 12 V
图 6-12. FCCM Mode Load Transient
图 6-11. ISS(source) vs Junction Temperature
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图 6-13. FCCM Mode Load Transient
图 6-15. Enable Power-Down, Full Load
图 6-17. Vout Ripple, FCCM, Full Load
图 6-14. Enable Start-Up, Full Load
图 6-16. Enable Power-Up, Pre-Bias
图 6-18. Vout Ripple, FCCM, No Load
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80
70
60
50
40
30
20
10
0
280
Gain
240
Phase
200
160
120
80
40
0
-40
-80
-120
-160
-200
-10
-20
-30
-40
1000 2000 5000 10000
100000
1000000
Frequency (Hz)
D016
图 6-19. Vout Ripple, Skip-mode, 10mA Load
图 6-20. Frequency Response, 20 A Load
图 6-21. Overcurrent Protection
图 6-22. Enable into Overcurrent
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7 Detailed Description
7.1 Overview
The TPS54JB20 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The
device suits low output voltage point-of-load applications with 20-A or lower output current in server, storage, and
similar computing applications. The TPS54JB20 features proprietary D-CAP3 mode control combined with
adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response
DC/DC converters in an ideal fashion. The output voltage ranges from 0.9-V to 5.5-V. The conversion input
voltage ranges from 2.7-V to 16-V, and the VCC input voltage ranges from 3.13-V to 3.6-V. The D-CAP3 mode
uses emulated current information to control the modulation. An advantage of this control scheme is that it does
not require a phase-compensation network outside which makes the device easy-to-use and also allows low
external component count. Another advantage of this control scheme is that it supports stable operation with all
low ESR output capacitors (such as ceramic capacitor and low ESR polymer capacitor). Adaptive on-time control
tracks the preset switching frequency over a wide range of input and output voltages while increasing switching
frequency as needed during load-step transient.
7.2 Functional Block Diagram
PGOOD
SS/
REFIN
Soft-start
generator
PG Falling
Threshold
+
UV
Internal
Soft-start
VIN
EN
PGOOD Driver
LDO
+
OV
VCC
Reference
generator
VCC
PG Rising
Threshold
FB
BOOT
REG
PGOOD
+
+
+
VCCOK
Control Logic
VINOK
BOOT
VIN
VCC UVLO
VSNS-
VIN
PWM
+
VIN UVLO
ñ
ñ
ñ
ñ
ñ
ñ
ñ
ñ
tON generator
Minimum On/Off
Light Load
FCCM/Skip
Internal
Ramp
VCC UVLO
VIN UVLO
SW
XCON
EN
Enable
Output OVP/UVP
Thermal Shutdown
EN
+
1.22V / 1.02V
SW
Valley Current
Limit & ZCD
OC
Limit
TRIP
MODE
AGND
PGND
MODE
Selection
Fsw &
Mode
+
ThermalOK
165°C /
135°C
Output Soft
Discharge
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7.3 Feature Description
7.3.1 Internal VCC LDO And Using External Bias On VCC Pin
The TPS54JB20 has an internal 3-V LDO featuring input from VIN and output to VCC. When the EN voltage
rises above the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output
voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also
provides the supply voltage for the gate drives.
The VCC pin needs to be bypassed with a 2.2-µF, at least 6.3-V rating ceramic capacitor. An external bias that is
above the output voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the
converter because the VCC current now runs off this external bias instead of the internal linear regulator.
The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the
VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of
the device.
Considerations when using an external bias on the VCC pin are as follows:
• When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the
internal LDO will be always forced off and the internal analog circuits will have a stable power supply rail at
their power enable.
• (Not recommended) When the external bias is applied on the VCC pin late (for example, after EN signal
comes in), any power-up and power-down sequencing can be applied as long as there is no excess current
pulled out of the VCC pin. It is important to understand that an external discharge path on the VCC pin, which
can pull a current higher than the current limit of the internal LDO from the VCC pin, can potentially turn off
VCC LDO, thereby shutting down the converter output.
• A good power-up sequence is when at least one of VIN UVLO rising threshold or EN rising threshold is
satisfied later than VCC UVLO rising threshold. For example, a practical power-up sequence is: VIN applied
first, then the external bias applied, and then EN signal goes high.
7.3.2 Enable
When the EN pin voltage rises above the enable threshold voltage (typically 1.22 V) and VIN rises above the VIN
UVLO rising threshold, the device enters its internal power-up sequence. The EN to first switching delay is
specified in Start-up Section in Electrical Characteristics table.
When using the internal VCC LDO, the internal power-up sequence includes three sequential steps. During the
first period, the VCC voltage is charged up on a VCC bypass capacitor by an 11-mA current source. The length
of this VCC LDO start-up time varies with the capacitance on VCC pin. However, if VIN voltage ramps up very
slowly, the VCC LDO output voltage will be limited by the VIN voltage level, thus the VCC LDO start-up time can
be extended longer. Since the VCC LDO start-up time is relatively long, the internal VINTREF build-up happens
and finishes during this period. Once the VCC voltage crosses above VCC UVLO rising threshold (typically 2.87
V), the device moves to the second step, power-on delay. The MODE pin setting detection, SS/REFIN pin
detection, and control loop initialization are finished within this 285-μs delay. Soft-start ramp starts when the
285-μs power-on delay finishes. During the soft-start ramp power stage, switching does not happen until the
SS/REFIN pin voltage reaches 50 mV. This introduces a SS delay that varies with the external capacitance on
SS/REFIN pin.
图 7-1 shows an example where the VIN UVLO rising threshold is satisfied earlier than the EN rising threshold.
In this scenario, the VCC UVLO rising threshold becomes the gating signal to start the internal power-up
sequence, and the sequence between VIN and EN does not matter.
When using an external bias on VCC pin, the internal power-up sequence still includes three sequential steps.
The first period is much shorter since VCC voltage is built up already. A 100-µs period allows the internal
references to start up and reach regulation points. This 100-µs period includes not only the 0.9-V VINTREF, but
also all of the other reference voltages for various functions. The device then moves to the second step, power-
on delay. The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization are finished
within this 285-μs delay. Soft-start ramp starts when the 285-μs power-on delay finishes. During the soft-start
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ramp power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This introduces a
SS delay that varies with the external capacitance on SS/REFIN pin.
图 7-2 shows an example where the VIN UVLO rising threshold and EN rising threshold are satisfied later than
the VCC UVLO rising threshold. In this scenario, the VIN UVLO rising threshold or EN rising threshold, whoever
is satisfied later, becomes the gating signal to start the internal power-up sequence.
2.4V
VIN
1.22V
EN
2.87V
VCC LDO
Power-on
delay
VCC LDO
Startup
50mV
SS/REFIN
SS delay
FB
SW pulses are omitted to
simplify the illustration
……
SW
图 7-1. Internal Power-up Sequence Using Internal LDO
2.87V
VCC
External
3.3V Bias
2.4V
VIN
EN
1.22V
Power-on
delay
VREF
Build-up
SS/REFIN
50mV
SS delay
FB
SW pulses are omitted to
simplify the illustration
……
SW
图 7-2. Internal Power-up Sequence Using External Bias
The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this
RC filter is 5 µs. For example, when applying 3.3-V voltage source on the EN pin that jumps from 0 V to 3.3 V
with an ideal rising edge, the internal EN signal will reach 2.086 V after 5 µs, which is 63.2% of applied 3.3-V
voltage level.
A internal pulldown resistor is implemented between the EN pin and AGND pin. To avoid impact to the EN rising/
falling threshold, this internal pulldown resistor is set to 6.5 MΩ. With this pulldown resistor, floating EN pin
before start-up keeps the TPS54JB20 device under disabled state. During nominal operation when the power
stage switches, this large internal pulldown resistor may not have enough noise immunity to hold EN pin low.
The recommended operating condition for EN pin is maximum 5.5 V. Do not connect the EN pin to the VIN pin
directly.
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7.3.3 Output Voltage Setting
The output voltage is programmed by the voltage-divider resistors, RFB_HS and RFB_LS. Connect RFB_HS between
the FB pin and the positive node of the load, and connect RFB_LS between the FB pin and VSNS– pin. The
recommended RFB_LS value is 10 kΩ, ranging from 1 kΩ to 20 kΩ. Determine RFB_HS by using 方程式 1.
VO - V
INTREF
RFB _HS
=
ìRFB _LS
V
INTREF
(1)
The FB accuracy is determined by two elements. The first element is the accuracy of the internal 900-mV
reference, which will be applied to SS/REFIN pin unless an external VREF is applied. The TPS54JB20 device
offers ±0.5% VINTREF accuracy from 0°C to 85°C temperature range, and ±1.0% VINTREF accuracy from –40°C
to 125°C temperature range. The second element is the SS/REFIN-to-FB accuracy which tells how accurately
the control loop regulates FB node to SS/REFIN pin. The TPS54JB20 device offers ±0.6% SS/REFIN-to-FB
accuracy from –40°C to 125°C temperature range. For example, when operating from a 0°C to 85°C
temperature range, the total FB accuracy is ±1.1% which includes the impact from chip junction temperature and
also the variation from part to part.
To improve the overall VOUT accuracy, using a ±1% accuracy or better resistor for the FB voltage divider is highly
recommended.
Regardless of remote sensing or single-end sensing connection, the FB voltage divider, RFB_HS and RFB_LS
should be always placed as close as possible to the device.
,
7.3.3.1 Remote Sense
The TPS54JB20 device offers remote sense function through FB and VSNS– pins. Remote sense function
compensates a potential voltage drop on the PCB traces thus helps maintain VOUT tolerance under steady state
operation and load transient event. Connecting the FB voltage divider resistors to the remote location allows
sensing to the output voltage at a remote location. The connections from the FB voltage divider resistors to the
remote location should be a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin
sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing
signal must be connected to the VSNS– pin. The VOUT connection of the remote sensing signal must be
connected to the feedback resistor divider with the lower feedback resistor, RFB_LS, terminated at VSNS– pin.
To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines should stay away from
any noise sources such as inductor and SW nodes, or high frequency clock lines. It is recommended to shield
the pair of remote sensing lines with ground planes above and below.
Single-ended Vo sensing is often used for local sensing. For this configuration, connect the higher FB resistor,
RFB_HS, to a high-frequency local bypass capacitor of 0.1 μF or higher, and short VSNS– to AGND.
The recommended VSNS– operating range (refer to AGND pin) is –50 mV to +50 mV.
7.3.4 Internal Fixed Soft Start and External Adjustable Soft Start
The TPS54JB20 implements a circuit to allow both internal fixed soft start and external adjustable soft start. The
internal soft-start time is typically 1.5 ms. The soft-start time can be increased by adding a soft-start (SS)
capacitor between the SS/REFIN and VSNS- pins. The total SS capacitor value can be determined by Equation
2. The device follows the longer SS ramp among the internal SS time and the SS time determined by the
external SS capacitors. The recommended maximum SS capacitor is 1 µF. A minimum 1-nF SS capacitor is
required.
The device does not require a capacitor from SS/REFIN pin to AGND, thus it is not recommenced to place a
capacitor from the SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND capacitors
exist, place CSS/REFIN-to-VSNS– more closely with shortest trace back to VSNS– pin.
t
SS(ms)ì36(mA )
CSS(nF)=
VINTREF( V)
(2)
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The TPS54JB20 provides an analog input pin (SS/REFIN) to accept an external reference. When an external
voltage signal is applied between SS/REFIN pin and VSNS- pin, it acts as the reference voltage thus FB voltage
follows this external voltage signal exactly. Apply this external reference to SS/REFIN pin before the EN high
signal is recommended. The external reference must be equal to or higher than the internal reference level to
ensure correct Power Good thresholds during soft start.
With an external reference applied, the internal fixed soft-start controls output voltage ramp during start-up. After
soft start finishes, the external voltage signal can be in a range of 0.5 V to 1.2 V.
When driving the SS/REFIN pin with an external resistor divider, the resistance should be low enough so that the
external voltage source can overdrive the internal current source.
7.3.5 External REFIN For Output Voltage Tracking
The TPS54JB20 provides an analog input pin (SS/REFIN) to accept an external reference (that is a DC voltage
source). The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop.
When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts as the
reference voltage thus FB voltage follows this external voltage reference exactly. The same ±0.6% SS/REFIN-to-
FB accuracy from -40°C to 125°C temperature range applies here too.
In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell
whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to
discharge any energy on SS/REFIN capacitors through an internal 120-Ω resistor to AGND. This discharge lasts
for 125 µs. Then, within a 32-µs window, the detection circuit compares the SS/REFIN pin voltage with an
internal reference equal to 89% of VINTREF. This discharge operation ensure a SS capacitor with left-over energy
will not be wrongly detected as a voltage reference. If the external voltage reference failed to supply sufficient
current and hold voltage level higher than 89% of VINTREF, the SS/REFIN detection circuit will provide wrong
detection result.
If the detection result is that SS/REFIN pin voltage falls below 89% of VINTREF which tells no external reference is
connected, the device first uses the internal fixed VINTREF as the reference for PGOOD, VOUT OVP, and VOUT
UVP threshold. On this configuration, given SS/REFIN pin sees a soft-start ramp on this pin, the slower ramp
among the internal fixed soft start and the external soft start determines the start-up of FB. Once both the
internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay.
The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes high when FB
reaches threshold equal to VINTREF – 50 mV. The device waits for the PGOOD status transition from low to high,
then starts using the SS/REFIN pin voltage, instead of the internal VINTREF as the reference for PGOOD, VOUT
OVP, and VOUT UVP threshold.
If the detection result is that SS/REFIN pin voltage holds higher than 89% of VINTREF which tells an active DC
voltage source is used as an external reference, the device always uses the SS/REFIN pin voltage instead of the
internal VINTREF as the reference for PGOOD, VOUT OVP, and VOUT UVP threshold. On this configuration, since
the SS/REFIN pin sees a DC voltage and no soft-start ramp on this pin, the internal fixed soft start is used for
start-up. Once the internal soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal
delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp goes beyond VINTREF
.
On this external REFIN configuration, applying a stabilized DC external reference to the SS/REFIN pin before
EN high signal is recommended. During the internal power-on delay, the external reference should be capable of
holding the SS/REFIN pin equal to or higher than 89% of VINTREF, so that the device can correctly detect the
external reference and choose the right thresholds for power good, VOUT OVP, and VOUT UVP. After the power
good status transits from low to high, the external reference can be set in a range of 0.5 V to 1.2 V. To overdrive
the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than 36-µA
current if the external reference is lower than the internal VINTREF, or source more than 12-µA current if the
external reference is higher than the internal VINTREF. When driving the SS/REFIN pin by an external reference
through a resistor divider, the resistance of the divider should be low enough to provide the sinking, or sourcing
current capability.
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The configuration of applying EN high signal first, then applying an external ramp on the SS/REFIN pin as a
tracking reference can be achieved, as long as design considerations for power good, VOUT OVP, and VOUT UVP
have been taken. Please contact Texas Instruments for detailed information about this configuration.
If the external voltage source must transition up and down between any two voltage levels, the slew rate must be
no more than 1 mV/μs.
7.3.6 Frequency and Operation Mode Selection
The TPS54JB20 provides forced CCM operation for tight output ripple application and auto-skip Eco-mode for
high light-load efficiency. The TPS54JB20 allows users to select the switching frequency and operation mode by
connecting a resistor from the MODE pin to AGND pin. 表 7-1 lists the resistor values for the switching frequency
and operation mode selection. TI recommends ±1% tolerance resistors with a typical temperature coefficient of
±100 ppm/°C.
The MODE state will be set and latched during the internal power-on delay period. Changing the MODE pin
resistance after the power-on delay will not change the status of the device. The internal circuit will set the
MODE pin status to 600 kHz / skip-mode if MODE pin is left open during the power-on delay period.
To make sure the internal circuit detects the desired option correctly, do not place any capacitor on the MODE
pin.
表 7-1. MODE Pin Selection
MODE PIN
CONNECTIONS
OPERATION MODE UNDER LIGHT
LOAD
SWITCHING FREQUENCY
(fSW) (kHz)(1)
Short to VCC
Skip-mode
Skip-mode
600
800
243-kΩ ± 10% to AGND
121-kΩ ± 10% to AGND
60.4-kΩ ±10% to AGND
30.1-kΩ ±10% to AGND
Short to AGND
Skip-mode
1000
1000
800
Forced CCM
Forced CCM
Forced CCM
600
(1) Switch frequency is based on 3.3 Vout. Frequency varies with Vout.
7.3.7 D-CAP3 Control
The TPS54JB20 uses D-CAP3 mode control to achieve the fast load transient while maintaining the ease-of-use
feature. The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very
low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low ESR polymer capacitors.
No external current sensing network or voltage compensators are required with D-CAP3 control architecture.
The role of the internal ripple generation network is to emulate the ripple component of the inductor current
information and then combine it with the voltage feedback signal to regulate the loop operation. The amplitude of
the ramp is determined by VIN, VOUT, operating frequency, and the R-C time-constant of the internal ramp circuit.
At different switching frequency settings (see 表 7-1), the R-C time-constant varies to maintain relatively constant
ramp amplitude. Also, the device uses internal circuitry to cancel the dc offset caused by injected ramp, and
significantly reduces the dc offset caused by the output ripple voltage, especially under light load condition.
For any control topologies supporting no external compensation design, there is a minimum range, maximum
range, or both, of the output filter it can support. The output filter used with the TPS54JB20 is a low-pass L-C
circuit. This L-C filter has double pole that is described in Equation 3.
1
f
=
P
2´ p´ L
´ C
OUT
OUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54JB20. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
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generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase by 90 degrees per decade above the zero frequency.
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 15% and 40% of the maximum output current.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is
located no higher than 1/30th of operating frequency. Choose very small output capacitance leads to relative
high frequency L-C double pole which allows that overall loop gain stays high until the L-C double frequency.
Given the zero from the internal ripple generation network is relative high frequency as well, the loop with very
small output capacitance may have too high crossover frequency which is not desired. Use 表 7-2 to help locate
the internal zero based on the selected switching frequency.
表 7-2. Locating the Zero
SWITCHING FREQUENCIES
ZERO (fZ) LOCATION (kHz)
(fSW) (kHz)
600
800
84.5
84.5
106
1000
In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load
transient requirement can be used to determine the necessary output capacitance for stable operation.
For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C
double pole frequency is no less than 1/100th of operating frequency. With this starting point, verify the small
signal response on the board using the following one criteria:
• Phase margin at the loop crossover is greater than 50 degrees
The actual maximum output capacitance can go higher as long as phase margin is greater than 50 degrees.
However, small signal measurement (bode plot) should be done to confirm the design.
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10 µF, X5R and 6.3 V, the derating by DC bias and AC
bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case
is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in
the system/applications.
For higher output voltage at or above 2-V, additional phase boost might be required to secure sufficient phase
margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed-on-time topology
based operation. A feedforward capacitor placing in parallel with RFB_HS is found to be very effective to boost the
phase margin at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc
Converters With Feedforward Capacitor application report for details.
Besides boosting the phase, a feedforward capacitor feeds more VOUT node information into FB node by the AC
coupling. This feedforward during load transient event enables the control loop a faster response to VOUT
deviation. However, this feedforward during steady state operation also feeds more VOUT ripple and noise into
FB. High ripple and noise on FB usually leads to more jitter, or even double pulse behavior. To determine the
final feedforward capacitor value, impacts to phase margin, load transient performance, and ripple and nosie on
FB should be all considered. Using Frequency Analysis equipment to measure the crossover frequency and the
phase margin is recommended.
7.3.8 Low-side FET Zero-Crossing
The TPS54JB20 uses a zero-crossing circuit to perform the zero inductor-current detection during skip-mode
operation. The function compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C
detection circuit. The zero-crossing threshold is set to a positive value to avoid negative inductor current. As a
result, the device delivers better light-load efficiency.
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7.3.9 Current Sense and Positive Overcurrent Protection
For a buck converter, during the on-time of the high-side FET, the switch current increases at a linear rate
determined by input voltage, output voltage, the on-time, and the output inductor value. During the on-time of the
low-side FET, this current decreases linearly. The average value of the switch current equals to the load current.
The output overcurrent limit (OCL) in the TPS54JB20 device is implemented using a cycle-by-cycle valley
current detect control circuit. The inductor current is monitored during the on-time of the low-side FET by
measuring the low-side FET drain-to-source current. If the measured drain-to-source current of the low-side FET
is above the current limit threshold, the low-side FET stays ON until the current level becomes lower than the
current limit threshold. This type of behavior reduces the average output current sourced by the device. During
an overcurrent condition, the current to the load exceeds the current to the output capacitors. Thus, the output
voltage tends to decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold
(80%), the UVP comparator detects it and shuts down the device after a wait time of 68 µs. The device remains
in latched off state (both high-side and low-side FETs are latched off) until a reset of VIN or a re-toggling on EN
pin.
If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side
valley current. After soft start is finished, the UV event which is caused by the OC event shuts down the device
and enters latch-off mode with a wait time of 68-µs.
The resistor, RTRIP connected from the TRIP pin to AGND sets current limit threshold. A ±1% tolerance resistor
is highly recommended because a worse tolerance resistor provides less accurate OCL threshold. Equation 4
calculates the RTRIP for a given overcurrent limit threshold on the device. To simplify the calculation, use a
constant, KOCL, to replace the value of 12x104 . Equation 4 calculates the overcurrent limit threshold for a given
RTRIP value. The tolerance of KOCL is listed in 节 6.5 to help you analyze the tolerance of the overcurrent limit
threshold.
To protect the device from unexpected connection on TRIP pin, an internal fixed OCL clamp is implemented.
This internal OCL clamp limits the maximum valley current on LS FET when TRIP pin has too small resistance to
AGND, or is accidentally shorted to ground.
(4)
where
• IOCLIM is overcurrent limit threshold for load current in A
• RTRIP is TRIP resistor value in Ω
• KOCL is a constant for the calculation
• VIN is input voltage value in V
• VO is output voltage value in V
• L is output inductor value in µH
• fSW is switching frequency in MHz
7.3.10 Low-side FET Negative Current Limit
The device has a fixed, cycle-by-cycle negative current limit. Similar with the positive overcurrent limit, the
inductor current is monitored during the on-time of the low-side FET. To prevent too large negative current
flowing through low-side FET, when the low-side FET detects a –10-A current (typical threshold), the device
turns off low-side FET and then turns on the high-side FET for a proper ON-time (determined by VIN/VO/fSW).
After the high-side FET on-time expires, the low-side FET turns on again.
The device should not trigger the –10-A negative current limit threshold during nominal operation, unless a
small inductor value that is too small is chosen or the inductor becomes saturated. This negative current limit is
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utilized to discharge output capacitors during an output OVP or an OOB event. See 节 7.3.12 and 节 7.3.13 for
details.
7.3.11 Power Good
The device has power-good output that indicates high when the converter output is within the target. The power-
good output is an open-drain output and must be pulled up to VCC pin or an external voltage source (<5.5 V)
through a pullup resistor (typically 30.1 kΩ). The recommended power-good pullup resistor value is 1 kΩ to 100
kΩ.
Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-
ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal
goes high when FB reaches threshold equal to VINTREF – 50 mV. If the FB voltage drops to 80% of the VINTREF
voltage or exceeds 116% of the VINTREF voltage, the power-good signal latches low after a 2-µs internal delay.
The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.
If the input supply fails to power up the device, for example VIN and VCC both stays at zero volt, the power-good
pin clamps low by itself when this pin is pulled up through an external resistor.
Once VCC voltage level rises above the minimum VCC threshold for valid PGOOD output (maximum 1.5 V),
internal power-good circuit is enabled to hold the PGOOD pin to the default status. By default, PGOOD is pulled
low and this low-level output voltage is no more than 400 mV with 5.5-mA sinking current. The power-good
function is fully activated after the soft-start operation is completed.
7.3.12 Overvoltage and Undervoltage Protection
The device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage events. When
the FB voltage becomes lower than 80% of the VINTREF voltage, the UVP comparator detects and an internal
UVP delay counter begins counting. After the 68-µs UVP delay time, the device latches OFF both high-side and
low-side FETs drivers. The UVP function enables after the soft-start period is complete.
When the FB voltage becomes higher than 116% of the VINTREF voltage, the OVP comparator detects and the
circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative
current limit INOCL. Upon reaching the negative current limit, the low-side FET is turned off, and the high-side
FET is turned on again, for a proper on-time (determined by VIN/VO/fSW). The device operates in this cycle until
the output voltage is pulled down under the UVP threshold voltage for 68 µs. After the 68 µs UVP delay time,
both the high-side FET and the low-side FET are latched OFF. The fault is cleared with a reset of VIN or by re-
toggling the EN pin.
During the 68-μs UVP delay time, if the output voltage becomes higher than UV threshold, thus is not qualified
for UV event, the timer will be reset to zero. When the output voltage triggers UV threshold again, the timer of
the 68 μs re-starts.
7.3.13 Out-Of-Bounds (OOB) Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 5% above the VINTREF voltage. OOB protection does not trigger an overvoltage fault, so
the device is on non-latch mode after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced CCM mode. Turning on the
low-side FET beyond the zero inductor current quickly discharges the output capacitor thus helps the output
voltage to fall quickly towards the setpoint. During the operation, the cycle-by-cycle negative current limit is also
activated to ensure the safe operation of the internal FETs.
7.3.14 Output Voltage Discharge
When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both
high-side and low-side FETs to latch off, but turns on the discharge FET, which is connected from SW to PGND,
to discharge the output voltage. Once the FB voltage drops below 90 mV, the discharge FET is turned off.
The output voltage discharge mode is activated by any of the following fault events:
1. EN pin goes low to disable the converter.
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2. Thermal shutdown (OTP) is triggered.
3. VCC UVLO (falling) is triggered.
4. VIN UVLO (falling) is triggered.
7.3.15 UVLO Protection
The device monitors the voltage on both the VIN and the VCC pins. If the VCC pin voltage is lower than the
VCCUVLO falling threshold voltage, the device shuts off. If the VCC voltage increases beyond the VCCUVLO rising
threshold voltage, the device turns back on. VCC UVLO is a non-latch protection.
When the VIN pin voltage is lower than the VINUVLO falling threshold voltage but the VCC pin voltage is still
higher than VCCUVLO rising threshold voltage, the device stops switching and discharges SS/REFIN pin. Once
the VIN voltage increases beyond the VINUVLO rising threshold voltage, the device re-initiates the soft start and
switches again. VIN UVLO is a non-latch protection.
7.3.16 Thermal Shutdown
The device monitors internal junction temperature. If the temperature exceeds the threshold value (typically
165°C), the device stops switching and discharges SS/REFIN pin. When the temperature falls approximately
30°C below the threshold value, the device turns back on with a re-initiated soft start. Thermal shutdown is a
non-latch protection.
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-mode Light Load Operation
While the MODE pin is pulled to VCC directly or connected to AGND pin through a resistor larger than 121 kΩ,
the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This
section describes the operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation
so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuous-
and discontinuous-conduction mode) is calculated as shown in Equation 5.
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
OUT LL
( )
2´L ´ f
SW
(5)
where
• fSW is the switching frequency
Using only ceramic capacitors is recommended for skip-mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the AGND pin through a resistor less than 60.4 kΩ, the controller operates in
continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency
maintained to an almost constant level over the entire load range which is suitable for applications requiring tight
control of the switching frequency at the cost of lower efficiency.
7.4.3 Powering The Device From A 12-V Bus
The device works well when powering from a 12-V Bus with single Vin configuration. As a single VIN
configuration, the internal LDO is powered by 12-V Bus and generates a 3.0-V output to bias the internal analog
circuitry and also powers up the gate drives. The VIN input range under this configuration is 4 V to 16 V for up to
20-A load current. 图 7-3 shows an example for this single VIN configuration.
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VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and
EN signals can power the device up correctly.
VIN: 4V œ 16V
CBOOT
10
21
1
VIN
VIN
BOOT
SW
CIN
LOUT
VOUT
20
EN
8
9
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
7
FB
19
4
VCC
RFB_HS
RFB_LS
CVCC
RMODE
MODE
TRIP
Vosns-
RTRIP
6
5
VSNS-
3
CSS
SS/
REFIN
2
AGND
PGND
图 7-3. Single VIN Configuration For 12-V Bus
7.4.4 Powering The Device From A 3.3-V Bus
The device can also work for up to a 20-A load current when powering from a 3.3-V Bus with a single Vin
configuration. To ensure the internal analog circuitry and the gate drives are powered up properly, VCC pin
should be shorted to VIN pins with low impedance trace. A trace with at least 24-mil width is recommended. A
2.2-µF, at least 6.3-V rating VCC-to-PGND decoupling capacitor is still recommended to be placed as close as
possible to VCC pin. Due to the maximum rating limit on VCC pin, the VIN input range under this configuration is
3 V to 3.6 V. The input voltage must stay higher than both VIN UVLO and VCC UVLO, otherwise the device will
shut down immediately. 图 7-4 shows an example for this single VIN configuration.
VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and
EN signals can power the device up correctly.
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VIN: 3.3V bus
CBOOT
10
21
1
VIN
VIN
BOOT
SW
CIN
LOUT
VOUT
20
EN
8
9
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
7
FB
19
4
VCC
RFB_HS
RFB_LS
CVCC
RMODE
MODE
TRIP
Vosns-
RTRIP
6
5
VSNS-
3
CSS
SS/
REFIN
2
AGND
PGND
图 7-4. Single VIN Configuration For 3.3-V Bus
7.4.5 Powering The Device From A Split-rail Configuration
When an external bias, which is at a different level from main VIN bus, is applied onto the VCC pin the device
can be configured to split-rail by utilizing both the main VIN bus and VCC bias. Connecting a valid VCC bias to
VCC pin overrides the internal LDO, thus saves power loss on that linear regulator. This configuration helps to
improve overall system level efficiency but requires a valid VCC bias. 3.3-V rail is the common choice as VCC
bias. With a stable VCC bias, the VIN input range under this configuration can be as low as 2.7 V and up to 16 V.
The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-
noise external bias and good local decoupling capacitor from VCC pin to PGND pin are required. 图 7-5 shows
an example for this split rail configuration.
The VCC external bias current during nominal operation varies with the bias voltage level and also the operating
frequency. For example, by setting the device to skip-mode, the VCC pins draws less and less current from the
external bias when the frequency decreases under light load condition. The typical VCC external bias current
under FCCM operation is listed in 节 6.5 to help you prepare the capacity of the external bias.
Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence, it
is recommended that at least one of VIN UVLO rising threshold and EN rising threshold is satisfied later than
VCC UVLO rising threshold. A practical start-up sequence example is: VIN applied first, the external bias
applied, and then EN signal goes high.
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VIN: 2.7V œ 16V
CBOOT
10
21
1
VIN
VIN
BOOT
SW
CIN
LOUT
VOUT
20
EN
8
9
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
VCC bias
7
FB
19
4
VCC
RFB_HS
RFB_LS
RMODE
CVCC
MODE
TRIP
Vosns-
RTRIP
6
5
VSNS-
3
CSS
SS/
REFIN
2
AGND
PGND
图 7-5. Split Rail Configuration With External VCC Bias
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54JB20 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The
device suits low output voltage point-of-load applications with 20-A or lower output current in server, storage, and
similar computing applications. The TPS54JB20 features proprietary D-CAP3 mode control combined with
adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response
DC/DC converters in an ideal fashion. The output voltage ranges from 0.9 V to 5.5 V. The conversion input
voltage ranges from 2.7 V to 16 V, and the VCC input voltage ranges from 3.13 V to 5.3 V. The D-CAP3 mode
uses emulated current information to control the modulation. An advantage of this control scheme is that it does
not require an external phase-compensation network, which makes the device easy-to-use and also allows for a
low external component count. Another advantage of this control scheme is that it supports stable operation with
all low ESR output capacitors (such as ceramic capacitor and low ESR polymer capacitor). Adaptive on-time
control tracks the preset switching frequency over a wide range of input and output voltages while increasing
switching frequency as needed during a load-step transient.
8.2 Typical Application
The schematic shows a typical application for TPS54JB20. This example describes the design procedure of
converting an input voltage range of 4 V to 16 V down to 1 V with a maximum output current of 20 A.
图 8-1. TPS54JB20Application Circuit Diagram
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8.2.1 Design Requirements
This design uses the parameters listed in 表 8-1.
表 8-1. Design Example Specifications
DESIGN PARAMETER
Voltage range
CONDITION
MIN
TYP
12
MAX
UNIT
V
VIN
4
16
VOUT
Output voltage
3.3
V
ILOAD
Output load current
Output voltage ripple
20
A
VRIPPLE
V TRANS
VIN = 12 V, IOUT = 20 A
IOUT = 25% to 75% step, 2 A/µs slew rate
12
mVPP
Output voltage undershoot
and overshoot after load
step
120
mV
IOVER
tSS
Output overcurrent
Soft-start time
24
5.5
A
ms
fSW
Switching frequency
Operating mode
0.6
MHz
FCCM
25
TA
Operating temperature
°C
8.2.2 Detailed Design Procedure
The external component selection is a simple process using D-CAP3 mode. Select the external components
using the following steps.
8.2.2.1 Output Voltage Setting Point
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Equation 6. Connect R1
between the FB pin and the output, and connect R2 between the FB pin and VSNS–. The recommended R2
value is 10 kΩ, but it can also be set to another value between the range of 1 kΩ to 20 kΩ. Determine R1.
≈
∆
«
’
÷
◊
VOUT - VREF
VREF
3.3 V - 0.9 V
0.9 V
≈
’
R = R ì
= 10 kWì
= 26.7 kW
1
2
∆
«
÷
◊
(6)
8.2.2.2 Choose the Switching Frequency and the Operation Mode
The switching frequency and operation mode are configured by the resistor on MODE pin. Select one of three
switching frequencies: 600 kHz, 800 kHz, or 1 MHz. Refer to 表 7-1 for the relationship between the switching
frequency, operation mode and RMODE
.
Switching frequency selection is a tradeoff between higher efficiency and smaller system solution size. Lower
switching frequency yields higher overall efficiency but relatively bigger external components. Higher switching
frequencies cause additional switching losses which impact efficiency and thermal performance. For this design,
short MODE pin to AGND to set the switching frequency to 0.6 MHz and set operation mode as FCCM.
When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must
be considered. Equation 7 calculates the maximum fSW before being limited by the minimum on-time. When
hitting the minimum on-time limits of a converter with D-CAP3 control, the effective switching frequency will
change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a
worst case estimation.
VOUT
max tON_MIN max
1
3.3 V
1
fSW max =
ì
=
ì
= 2426 kHz
(
)
V
16 V 85 ns
IN
(7)
Equation 7 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum
off-time limits of a converter with D-CAP3 control, the operating duty cycle will max out and the output voltage
will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR, selected
in the following step so this preliminary calculation assumes a resistance of 2.2 mΩ. If operating near the
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maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be
considered when using Equation 8. The selected fSW of 600 kHz is below the two calculated maximum values.
V
min - V
-IOUT max ì R
+ R
DCR
DS ON _HS
(
)
(
)
(
)
(
IN
OUT
(
)
fSW max =
(
)
tOFF_MIN max ì V min -I
max ì R
-RDS ON _LS
(
)
(
)
(
)
(
)
IN
OUT
)
(
DS ON _HS
(
)
)
8 V - 3.3 V - 20 A ì 2.2 mW + 7.7 mW
(
)
fSW max =
= 2595 kHz
(
)
220 nsì 8 V - 20 A ì 7.7 mW - 2.4 mW
(8)
8.2.2.3 Choose the Inductor
To calculate the value of the output inductor (LOUT), use Equation 9. The output capacitor filters the inductor-
ripple current (IIND(ripple)). Therefore, selecting a high inductor-ripple current impacts the selection of the output
capacitor because the output capacitor must have a ripple-current rating equal to or greater than the inductor-
ripple current. On the other hand, larger ripple current increases output ripple voltage, but improves signal-to-
noise ratio and helps to stabilize operation. Generally speaking, the inductance value should set the ripple
current at approximately 15% to 40% of the maximum output current for a balanced performance.
For this design, the inductor-ripple current is set to 30% of output current. With a 0.6-MHz switching frequency,
16 V as maximum VIN, and 3.3 V as the output voltage, the calculated inductance is 0.728 μH. A nearest
standard value of 0.80 µH is chosen.
V
max - V
ì V
(
)
16 V - 3.3 V ì3.3 V
(
)
(
)
IN
OUT
OUT
L =
=
= 0.728 ꢀH
IRIPPLE ì V max ì f
0.3ì 20A ì16 V ì600 kHz
IN
SW
(9)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above
peak inductor current before saturation. The peak inductor current is estimated using Equation 10. For this
design, by selecting 6.04 A as the RTRIP, IOC(valley) is set to 20 A, thus peak inductor current under maximum VIN
is calculated as 5.457 A.
V
max - V
ì V
(
)
16 V - 3.3 V ì3.3 V
(
)
(
)
IN
OUT
OUT
IRIPPLE
=
=
= 5.457 A
Lì V max ì f
0.8ꢀHì16 V ì 600 kHz
IN
SW
(10)
(11)
IRIPPLE
5.457 A
= 22.729 A
2
IL PEAK = IOUT
+
= 20 A +
(
)
2
2
5.457 A2
IRIPPLE
2
IL RMS
=
IOUT
+
=
20 A2
+
= 20.06 A
(
)
12
12
(12)
The selected inductance is a Coilcraft XAL7070-801. This has a saturation current rating of 37.8 A , RMS current
rating of and a DCR of 2.29 mΩ max. This inductor was selected for its low DCR to get high efficiency.
8.2.2.4 Set the Current Limit (TRIP)
The RTRIP resistor sets the valley current limit. Equation 13 calculates the recommended current limit target. This
includes the tolerance of the inductor and a factor of 0.85 for the tolerance of the current limit threshold.
Equation 14 calculates the RTRIP resistor to set the current limit. The typical valley current limit target is 17.98 A
and the closest standard value for RTRIP is 6.0 kΩ.
≈
’
V
min - V
ì V
(
)
(
)
OUT OUT
1
2
IN
ILIM_ VALLEY = ∆IOUT
-
ì
ì
÷
÷
◊
∆
Lì V min ì f
(
)
IN
SW
«
≈
8 V - 3.3 V ì3.3 V
’
(
)
1
2
ILIM_ VALLEY
=
20A -
= 17.98 A
∆
∆
÷
÷
0.8 µHì8 V ì 600 kHz
«
◊
(13)
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120000
120000
20 A
RTRIP
=
=
= 6.0 kW
ILIM_ VALLEY
(14)
With the current limit set, Equation 15 calculates the typical maximum output current at current limit. Equation 16
calculates the typical peak current at current limit. As mentioned in 节 8.2.2.3, the saturation behavior of the
inductor at the peak current during current limit must be considered. For worst case calculations, the tolerance of
the inductance and the current limit must be included.
V
min - V
ì V
(
)
8 V - 3.3 V ì3.3 V
(
)
OUT OUT
(
)
1
2
1
2
IN
IOUT _LIM min = I
+
ì
= 20 A +
ì
= 22.02 A
(
)
LIM_ VALLEY
Lì V min ì f
0.8 µHì8 V ì600 kHz
IN
SW
(15)
(16)
V
(
max - V
ì V
(
)
16 V - 3.3 V ì3.3 V
)
OUT OUT
(
)
IN
IL PEAK = ILIM_ VALLEY
+
= 20 A +
= 22.73 A
(
)
Lì V max ì f
0.8 µHì16 V ì600 kHz
IN
SW
8.2.2.5 Choose the Output Capacitor
There are three considerations for selecting the value of the output capacitor.
1. Stability
2. Steady state output voltage ripple
3. Regulator transient response to a change load current
First the minimum output capacitance should be calculated based on these three requirements. Equation 17
calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW in order to meet stability
requirements. This requirement helps to keep the LC double pole close to the internal zero. Equation 18
calculates the minimum capacitance to meet the steady state output voltage ripple requirement of . This
calculation is for CCM operation and does not include the portion of the output voltage ripple caused by the ESR
or ESL of the output capacitors.
(17)
IRIPPLE
8ì VRIPPLE ì fSW 8ì33 mV ì 600 kHz
5.457 A
COUT _RIPPLE
>
=
= 34.5 µF
(18)
Equation 19 and Equation 20 calculate the minimum capacitance to meet the transient response requirement of
132 mV with a 10-A step. These equations calculate the necessary output capacitance to hold the output voltage
steady while the inductor current ramps up or ramps down after a load step.
≈
’
VOUT
LìISTEP2 ì
+ tOFF_MIN max
(
)
∆
∆
÷
÷
V
min ì f
(
)
IN
SW
«
◊
COUT _UNDERSHOOT
>
>
≈
’
V
min - V
(
IN
)
IN
OUT
2ì VTRANS ì VOUT
0.8 µHì10 A2 ì
ì
≈
- tOFF_MIN max
(
)
∆
∆
÷
÷
V
min ì f
(
3.3 V
)
SW
«
◊
’
+ 220 ns
∆
«
÷
◊
8 V ì 600 kHz
8 V - 3.3 V
8 V ì 600 kHz
COUT _UNDERSHOOT
= 109.8 µF
≈
’
2ì132 mV ì3.3 V ì
- 220 ns
∆
«
÷
◊
(19)
(20)
2
0.8 µHì10A2
LìISTEP
COUT _OVERSHOOT
>
=
= 91.8 µF
2ì VTRANS ì VOUT 2ì132 mV ì3.3 V
The output capacitance needed to meet the overshoot requirement is the highest value so this sets the required
minimum output capacitance for this example. Stability requirements can also limit the maximum output
capacitance and Equation 21 calculates the recommended maximum output capacitance. This calculation keeps
the LC double pole above 1/100th the fSW. It can be possible to use more output capacitance but the stability
must be checked through a bode plot or transient response measurement. The selected output capacitance is
ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias
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effects. The selected capacitors derate to their nominal value giving an effective total capacitance of 879.5 μF.
This effective capacitance meets the minimum and maximum requirements.
2
2
≈
∆
«
’
÷
50
1
L
50
1
≈
’
COUT _STABILITY
<
ì
=
ì
= 879.5 µF
∆
«
÷
◊
pì fSW ◊
pì 600 kHz
0.8 µH
(21)
This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If
using non ceramic capacitors, as a starting point, the ESR should be below the values calculated in Equation 22
to meet the ripple requirement and Equation 23 to meet the transient requirement. For more accurate
calculations or if using mixed output capacitors, the impedance of the output capacitors should be used to
determine if the ripple and transient requirements can be met.
VRIPPLE
33 mV
RESR _RIPPLE
<
=
= 6 mW
IRIPPLE
5.457 A
(22)
(23)
VTRANS
132 mV
10 A
RESR _ TRANS
<
=
= 13.2 mW
ISTEP
8.2.2.6 Choose the Input Capacitors (CIN)
The device requires input bypass capacitors between the VIN and PGND pins to bypass the power-stage. The
bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least 10
µF of ceramic capacitance and 1-µF high frequency ceramic bypass capacitors are required. A 1-uF, 16-V X6S
size 0402 ceramic capacitor on VIN pin 21 is required. A 1-uF, 16-V X6S ceramic capacitor on VIN pin 10 is
required. A 1-uF 16-V X6S ceramic capacitor on the bottom layer is recommended for high current applications.
The high frequency bypass capacitor minimizes high frequency voltage overshoot across the power-stage. The
ceramic capacitors must be a high-quality dielectric of X6S or better for their high capacitance-to-volume ratio
and stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the
input depending on the application to minimize variations on the input voltage during transient conditions.
The input capacitance required to meet a specific input ripple target can be calculated with Equation 24. A
recommended target input voltage ripple is 5% the minimum input voltage, 400 mV in this example. The
calculated input capacitance is 20.2 μF and the minimum input capacitance of 10 µF exceeds this. This
example meets these two requirements with 4 x 22-µF ceramic capacitors.
≈
’
VOUT
min
3.3
8
≈
«
’
◊
VOUT ìIOUT ì 1-
∆
÷
÷
3.3 V ì 20 A ì 1-
∆
∆
÷
V
(
)
IN
«
◊
CIN
>
=
= 20.2 ꢀF
fSW ì V min ì V
600 kHzì8 V ì 400 mV
IN
IN_RIPPLE
(24)
The capacitor must also have an RMS current rating greater than the maximum input RMS current in the
application. The input RMS current the input capacitors must support is calculated by Equation 25 and is 9.874 A
in this example. The ceramic input capacitors have a current rating greater than this.
Iripple2
12
≈
’
V
min - V
OUT
(
)
min
(
)
ìIOUT
VOUT
min
IN
2
ICIN RMS
=
=
ì∆
∆
+
÷ =
÷
(
)
)
V
V
(
)
(
)
IN
IN
«
◊
5.4572
12
≈
’
8 V - 3.3 V
(
)
3.3 V
8 V
ICIN RMS
ì
ì 202
+
= 9.874 A
∆
∆
÷
÷
(
8 V
«
◊
(25)
For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,
the selection process in this article is recommended.
8.2.2.7 Soft Start Capacitor (SS/REFIN Pin)
ISS ì tSS
VREF
36 µA ì5.5 ms
0.9 V
CSS
=
=
= 220 nF
(26)
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A minimum capacitor value of 1 nF is required at the SS/REFIN pin. The SS/REFIN capacitor must use the
VSNS– pin for its ground.
8.2.2.8 EN Pin Resistor Divider
A resistor divider on the EN pin can be used to increase the input voltage the converter begins its start-up
sequence. To set the start voltage, first select the bottom resistor (REN_B). The recommended value is between 1
kΩ and 100 kΩ. There is an internal pulldown resistance with a nominal value of 6 MΩ and this must be
included for the most accurate calculations. This is especially important when the bottom resistor is a higher
value, near 100 kΩ. This example uses a 10-kΩ resistor and this combined with the internal resistance in
parallel results in an equivalent bottom resistance of 9.98 kΩ. The top resistor value for the target start voltage is
calculated with Equation 27. In this example, the nearest standard value of 20 kΩ is selected for REN_T. When
selecting a start voltage in a wide input range application, be cautious that the EN pin absolute maximum voltage
of 6 V is not exceeded.
REN_B ì VSTART
10 kWì3.7 V
1.22 V
REN_ T
=
-REN_B
=
-10 kW = 20 kW
VENH
(27)
The start and stop voltages with the selected EN resistor divider can be calculated with Equation 28 and
Equation 29.
REN_B + REN_ T
10 kW + 20 kW
10 kW
VSTART = VENH
ì
= 1.22 V ì
= 3.66V
REN_B
(28)
(29)
REN_B + REN_ T
10 kW + 20 kW
10 kW
VSTOP = VENL
ì
= 1.02 V ì
= 3.06 V
REN_B
8.2.2.9 VCC Bypass Capacitor
At a minimum, a 2.2-µF, at least 6.3V rating, X5R ceramic bypass capacitor is needed on VCC pin located as
close to the pin as the layout will allow.
8.2.2.10 BOOT Capacitor
At a minimum, a 0.1-µF 10V X5R ceramic bypass capacitor is needed between the BOOT and SW pins located
as close to the pin as the layout will allow. It is good practice to use a 0-Ω resistor in series with BOOT capacitor.
8.2.2.11 Series BOOT Resistor and RC Snubber
A series BOOT resistor can help reduce the overshoot at the SW pin. As a best practice, include a 0-Ω resistor
in series with boot capacitor during layout for 12-V or higher input applications. The BOOT resistor can be used
to reduce the voltage overshoot on the SW pin to within the absolute maximum ratings, in case the overshoot is
higher than normal due to parasitic inductance in PCB layout. Including a 0-Ω BOOT resistor is recommended
with external VCC as the SW node overshoot is increased.
An RC snubber on the SW pin can also help reduce voltage overshoot and ringing at the SW pin. In order for the
RC snubber to be as effective as possible, it should be placed on the same side as the IC and be as close as
possible to the SW pins with a very low impedance return to PGND pins.
8.2.2.12 PGOOD Pullup Resistor
The PGOOD pin is open-drain so a pullup resistor is required when using this pin. The recommended value is
between 1 kΩ and 100 kΩ.
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8.2.3 Application Curves
100
96
92
88
84
80
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
76
Vin = 12 V
600 kHz
800 nH
VCC = INT
Skip
Vin = 12 V
600 kHz
800 nH
VCC = INT
FCCM
72
68
64
60
Vout = 3.3V
Vout = 3.3 V
16 18 20
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
0
2
4
6
8
10
Output Current (A)
12
14
D002
D001
图 8-3. Efficiency vs Output Current, Internal VCC
图 8-2. Efficiency vs Output Current, Internal VCC
Bias
Bias
100
96
92
88
84
80
100
96
92
88
84
80
76
76
Vin = 12 V
600 kHz
800 nH
VCC = 3.3 V
FCCM
Vin = 12 V
600 kHz
800 nH
VCC = 3.3 V
Skip
72
68
64
60
72
68
64
60
Vout = 3.3 V
16 18 20
Vout = 3.3 V
16 18 20
0
2
4
6
8
10
12
Output Current (A)
14
0
2
4
6
8
10
12
Output Current (A)
14
D003
D004
图 8-4. Efficiency vs Output Current, VCC = 3.3V
图 8-5. Efficiency vs Output Current, VCC = 3.3V
External VCC Bias
External VCC Bias
1100
1000
900
1050
950
850
750
650
800
700
600
550
450
350
250
VIN = 12 V
Vout = 3.3 V
800 nH
VCC = Int
CCM
VIN = 12 V
Vout = 3.3 V
800 nH
VCC = Int
CCM
500
400
600 kHz
800 kHz
1000 kHz
600 kHz
800 kHz
1000 kHz
300
200
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
4
5
6
7
8
9 10 11 12 13 14 15 16
Input Voltage (V)
D005
D006
图 8-6. Switching Frequency vs Output Current
图 8-7. Switching Frequency vs Input Voltage
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3.355
3.355
3.35
Vin = 8V
Vin = 12V
Vin = 16V
Vin = 8V
Vin = 12V
Vin = 16V
800 nH
3.35
600 kHz
3.345
3.34
800 nH
600 kHz
VCC = Int
FCCM
3.345
3.34
VCC = Int
Skip
3.335
3.33
3.335
3.33
3.325
3.32
3.325
3.32
3.315
3.31
3.315
3.31
3.305
3.3
3.305
3.3
0
2
4
6
8
Output Current (A)
10
12
14
16
18
20
0
2
4
6
8
Output Current (A)
10
12
14
16
18
20
D008
D010
图 8-8. Output Voltage vs Output Current
图 8-9. Output Voltage vs Output Current
3.355
3.355
Vin = 8V
Vin = 12V
Vin = 16V
Vin = 8V
Vin = 12V
Vin = 16V
800 nH
3.35
3.345
3.34
3.35
3.345
3.34
800 nH
600 kHz
VCC = 3.3 V
FCCM
600 kHz
VCC = 3.3 V
Skip
3.335
3.33
3.335
3.33
3.325
3.32
3.325
3.32
3.315
3.31
3.315
3.31
3.305
3.3
3.305
3.3
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
0
2
4
6
8
10
12
Output Current (A)
14
16
18
20
D012
D011
图 8-11. Output Voltage vs Output Current, VCC =
图 8-10. Output Voltage vs Output Current, VCC =
3.3V External Bias
3.3V External Bias
3.352
3.352
Skip 0 A
FCCM 0 A
FCCM 5 A
FCCM 10 A
FCCM 20A
Skip 0 A
FCCM 0 A
FCCM 5 A
FCCM 10 A
FCCM 20A
3.348
3.348
3.344
3.34
3.344
3.34
3.336
3.332
3.328
3.324
3.32
3.336
3.332
3.328
3.324
3.32
3.316
3.312
3.308
3.304
3.316
3.312
3.308
3.304
5
7
9 11
Input Voltage (V)
13
15 16
5
7
9 11
Input Voltage (V)
13
15 16
D013
D014
图 8-12. Output Voltage vs Input Voltage VCC = Int
图 8-13. Output Voltage vs Input Voltage VCC =
3.3V External Bias
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0.018
0.016
0.014
0.012
0.01
0.008
0.006
0.004
0.002
0
VIN = 12 V
Vout = 3.3 V
Iout = 5 A
800 nH
600 kHz
800 kHz
1000 kHz
3.2 3.24 3.28 3.32 3.36 3.4 3.44 3.48 3.52 3.56 3.6
VCC Voltage (V)
D015
图 8-15. Enable Start-Up, Full Load
图 8-14. ICC Current vs External VCC Voltage
图 8-16. Enable Power Down Full Load
图 8-18. Enable Power Down Iout = 0.1 A
图 8-17. Enable to Power Up Iout = 0.1 A
图 8-19. Enable Start-Up, Prebias
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图 8-20. Prebias Power-Down
图 8-21. Enable Power Up, Skip
图 8-22. Enable Power Down, Skip
图 8-23. Enable Power Up into Pre-bias, Skip
图 8-24. Enable Power Down with Pre-bias, Skip
图 8-25. FCCM Mode Load Transient
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图 8-26. Unload Transient
图 8-27. Output Voltage Ripple
图 8-29. Output Voltage Ripple
图 8-31. Output Voltage Ripple, Skip
图 8-28. Output Voltage Ripple
图 8-30. Output Voltage Ripple, Skip
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图 8-32. Over Temperature Protection in FCCM
图 8-33. Overcurrent Protection
80
280
240
Gain
Phase
70
60
50
40
30
20
10
0
200
160
120
80
40
0
-40
-80
-120
-160
-200
-10
-20
-30
-40
1000 2000 5000 10000
100000
1000000
Frequency (Hz)
D016
图 8-35. Frequency Response, 20 A Load
图 8-34. Enabled into Overcurrent
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9 Power Supply Recommendations
The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when VCC
pin is powered by external bias ranging from 3.13 V to 3.6 V. Both input supplies (VIN and VCC bias) must be
well regulated. Proper bypassing of input supplies (VIN and VCC bias) is also critical for noise performance, as
are PCB layout and grounding scheme. See the recommendations in 节 10.
10 Layout
10.1 Layout Guidelines
Before beginning a design using the device, consider the following:
• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side
of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert at least one
solid ground inner plane.
• VIN decoupling capacitors are important for FET robustness. A 1-μF/25-V/X6S/0402 ceramic capacitor on
VIN pin 21 is required. The PGND vias for this decoupling capacitor should be placed so that the decoupling
capacitor is closer to IC than the PGND vias. To lower ESL from via connection, two 8-mil vias are
recommended for the PGND connection to inner PGND plane.
• A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is
not used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as
possible to IC pin 10 and pin 11.
• Two 1-μF/25-V/X6S/0402 ceramic capacitors on bottom layer are recommended for high current applications
(Iout > 13 A). One of these two capacitors should be centered between VIN pin 10 and pin 21. To have good
connection for this capacitor, a VIN copper on bottom layer and two VIN vias are needed. The other one can
be placed close to IC package just like a mirrored copy to the 0402 capacitor on top layer.
• At least six PGND vias are required to be placed as close as possible to the PGND pins (pin 11 to pin 15).
This minimizes parasitic impedance and also lowers thermal resistance.
• Place the VCC decoupling capacitor (2.2-μF/6.3-V/X6S/0402 or 2.2-μF/6.3-V/X7R/0603) as close as
possible to the device. Ensure the VCC decoupling loop is smallest.
• Place BOOT capacitor as close as possible to the BOOT and SW pins. Use traces with a width of 12 mil or
wider to route the connection. TI recommends using a 0.1-µF to 1-µF bootstrap capacitor with 10-V rating.
• The PCB trace, which connects the SW pin and high-voltage side of the inductor, is defined as switch node.
The switch node must be as short and wide as possible.
• Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end
sensing or remote sensing.
– For remote sensing, the connections from the FB voltage divider resistors to the remote location should be
a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin sensing across a high
bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be
connected to VSNS– pin. The VOUT connection of the remote sensing signal must be connected to the
feedback resistor divider with the lower feedback resistor terminated at VSNS– pin. To maintain stable
output voltage and minimize the ripple, the pair of remote sensing lines should stay away from any noise
sources such as inductor and SW nodes, or high frequency clock lines. It is recommended to shield the
pair of remote sensing lines with ground planes above and below.
– For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of 0.1
μF or higher, and short VSNS– to AGND with shortest trace.
• This device does not require a capacitor from SS/REFIN pin to AGND, thus it is not recommenced to place a
capacitor from SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND capacitors exist,
place CSS/REFIN-to-VSNS– more closely with shortest trace to VSNS– pin.
• Pin 2 (AGND pin) must be connected to a solid PGND plane on inner layer. Use the common AGND via to
connect the resistors to the inner ground plane if applicable.
• See 节 10.2 for the layout recommendation.
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10.2 Layout Example
Vosns+
Vosns-
Via down to connect to solid
PGND plane on inner layer
8/20
8/20
0402
0402
8/20
8/20
2x VIN-to-PGND decoupling
capacitors on bottom layer
8/20
PGND
8/20
8/20
8/20
8/20
8/20
8/20
SW
VIN
VIN
SW
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
0603
LOUT
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
0402
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
8/20
PGND
0805
0805
VOUT
图 10-1. Layout Recommendation
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ZHCSMS1B – JULY 2020 – REVISED NOVEMBER 2020
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor
• Non-isolated Point-of-load Solutions for VR13.HC in Rack Server and Datacenter Applications
11.2 Trademarks
D-CAP3™ and Eco-mode™ are trademarks of TI.
所有商标均为其各自所有者的财产。
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54JB20RWWR
ACTIVE
VQFN-HR
RWW
21
3000 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
-40 to 125
T54JB20
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RWW0021A
3.1
2.9
A
B
4.1
3.9
PIN 1
INDEX AREA
C0.15
PIN 1 IDENTIFICATION
(OPTIONAL)
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
PKG
0.4
0.3
0.35
0.25
REF 0.15
3X
10
(0.2) TYP
9
8
11
12X 0.4
1.8
3X
1.6
3.25
3.05
2X
3.4
0.25
PKG
14X
2X
2.4
0.15
0.1
C A B
C
0.05
2
1
18
19
4X 0.5
21
0.35
0.25
20
4X
PIN 1 ID
(OPTIONAL)
3X 0.3
0.1
C A B
C
0.6
0.4
18X
0.05
4223950/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RWW0021A
(2.7)
3X (0.3)
18X (0.7)
4X (0.3)
20
21
1
2
19
14X (0.2)
4X (0.5)
18
EXPOSED METAL
PKG
2X
2X
(3.4) (2.4)
3X
(1.9)
12
8
9
12X (0.4)
11
(0.35)
(R0.05) TYP
10
3X (0.3)
PKG
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL EDGE
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223950/C 04/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RWW0021A
(2.7)
PKG
18X (0.7)
4X (0.3)
20
21
1
2
19
4X (0.5)
18
14X (0.2)
PKG
2X
2X
(3.4) (2.4)
3X
(0.73)
3X
(1.05)
12
11
8
9
12X (0.4)
(0.35)
(R0.05) TYP
6X
(0.85)
10
6X (0.3)
(0.3)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
89% PRINTED COVERAGE BY AREA
SCALE: 20X
4223950/C 04/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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