TPS55289RYQR [TI]
36V、8A 完全集成式降压/升压转换器 | RYQ | 21 | -40 to 125;
| 型号： | TPS55289RYQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36V、8A 完全集成式降压/升压转换器 | RYQ | 21 | -40 to 125 升压转换器 |
| 文件： | 总48页 (文件大小：3553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS55289
ZHCSNR7A –MARCH 2022 –REVISED AUGUST 2022
TPS55289 具有I2C 接口的30V、8A 降压/升压转换器
TPS55289 采用平均电流模式控制方案。开关频率可通
过外部电阻在 200 kHz 至 2.2 MHz 之间进行编程，并
且可与外部时钟同步。TPS55289 还提供展频选项，从
而更大限度地减少峰值EMI。
1 特性
• 可编程电源(PPS) 支持USB 供电(USB PD)
– 3.0V 至30V 的宽输入电压范围
– 可编程输出电压范围为0.8V 至22V，阶跃为10
mV
TPS55289 提供输出过压保护、平均电感器电流限制、
逐周期峰值电流限制和输出短路保护功能。TPS55289
还具有可选输出电流限制和断续模式保护功能，确保在
持续过载情况下安全运行。
– ±1% 基准电压精度
– 电缆上压降的可调输出电压补偿
– 可编程输出电流限值高达6.35A，阶跃为50mA
– ±5% 精密输出电流监测
– I2C 接口
TPS55289 可在高开关频率下使用小型电感器和小型电
容器。此器件采用3.0mm × 5.0mm QFN 封装。
• 在整个负载范围内具有高效率
– VIN = 12V、VOUT = 20V 且IOUT = 3A 时效率为
96%
– 轻负载状态下的可编程PFM 和FPWM 模式
• 避免频率干扰和串扰
器件信息
封装(1)
器件型号
封装尺寸
TPS55289
VQFN-HR
3.0mm × 5.0mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 可选的时钟同步
– 可编程开关频率范围为200 kHz 至2.2 MHz
• 降低EMI
L1
4.7µH
C5
C4
– 可选可编程扩展频谱
– 无引线封装
• 丰富的保护特性
BOOT1 SW1
SW2 BOOT2
VIN = 3V to 30V
R4
VOUT = 0.8V to 22V
VIN
VOUT
C1
C2
VCC
PGND
ISP
4 x 22µF
– 输出过压保护
– 利用断续模式实现输出短路保护
– 热关断保护
C3
AGND
ON
EN/UVLO
SCL
ISN
TPS55289
OFF
Internal Vcc
External Vcc
FB/INT
COMP
SDA
– 8A 平均电感器电流限值
• 小解决方案尺寸
EXTVCC
74h
DITH/SYNC
FSW
MODE
CDC
R3
C7
75h
C8
– 开关频率高达2.2 MHz（最大值）
– 3.0mm × 5.0mm HotRod™ QFN 封装
C6
R2
R1
2 应用
典型应用电路
• 无线充电器
• USB PD
• 集线站
• 工业PC
• 移动电源
• 显示器
3 说明
TPS55289 同步降压/升压转换器经优化，可将电池电
压或适配器电压转换为电源轨。TPS55289 集成了四个
MOSFET 开关，可为USB 电力输送(USB PD) 应用提
供紧凑型解决方案。
TPS55289 的输入电压高达 30V。通过 I2C 接口，
TPS55289 的输出电压可以在 0.8V 至22V 之间（阶跃
为10mV）进行编程。在升压模式下，输入电压为 12V
时，该器件可提供 60W 的输出功率。它能够通过 9V
输入电压提供45W 的功率。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGA9
TPS55289
www.ti.com.cn
ZHCSNR7A –MARCH 2022 –REVISED AUGUST 2022
Table of Contents
7.5 Programming............................................................ 22
7.6 Register Maps...........................................................25
8 Application and Implementation..................................33
8.1 Application Information............................................. 33
8.2 Typical Application.................................................... 33
9 Power Supply Recommendations................................41
10 Layout...........................................................................41
10.1 Layout Guidelines................................................... 41
10.2 Layout Example...................................................... 42
11 Device and Documentation Support..........................43
11.1 Device Support........................................................43
11.2 接收文档更新通知................................................... 43
11.3 支持资源..................................................................43
11.4 Trademarks............................................................. 43
11.5 Electrostatic Discharge Caution..............................43
11.6 术语表..................................................................... 43
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 I2C Timing Characteristics.......................................... 9
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................21
Information.................................................................... 43
4 Revision History
Changes from Revision * (March 2022) to Revision A (August 2022)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Pin Configuration and Functions
EN/UVLO
MODE
1
2
3
4
17 AGND
16
15
CDC
SCL
COMP
SDA
14 FB/INT
图5-1. 21-Pin VQFN-HR RYQ Package (Transparent Top View)
表5-1. Pin Functions
Pin
Name
I/O
Description
NO.
Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high
level enables the device. Logic low level disables the device and turns it into shutdown mode. After
the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as
programmable UVLO input with 1.23-V internal reference.
EN/UVLO
1
I
I
I2C target address selection. When it is connected to the logic high voltage, the I2C target address is
74H. When it is connected to the logic low voltage, the I2C target address is 75H.
MODE
2
SCL
SDA
3
4
I
Clock of I2C interface
Data of I2C interface
I/O
Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and
ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is
no dithering function. An external clock can be applied at this pin to synchronize the switching
frequency.
DITH/SYNC
5
I
FSW
VIN
6
7
I
The switching frequency is programmed by a resistor between this pin and the AGND pin.
Input of the buck-boost converter
PWR
The switching node pin of the buck side. It is connected to the drain of the internal buck low-side
power MOSFET and the source of internal buck high-side power MOSFET.
SW1
PGND
SW2
8
9
PWR
PWR
PWR
PWR
Power ground of the IC
The switching node pin of the boost side. It is connected to the drain of the internal boost low-side
power MOSFET and the source of internal boost high-side power MOSFET.
10
11
VOUT
Output of the buck-boost converter
Positive input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
ISP
12
I
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表5-1. Pin Functions (continued)
Pin
Name
I/O
Description
NO.
Negative input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
ISN
13
I
When the device is set to use external output voltage feedback, connect to the center tap of a
resistor divider to program the output voltage. When the device is set to use internal feedback, this
pin is a fault indicator output. When there is an internal fault happening, this pin outputs logic low
level.
FB/INT
14
I/O
Output of the internal error amplifier. Connect the loop compensation network between this pin and
the AGND pin.
COMP
CDC
15
16
O
O
Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a
resistor between this pin and AGND to increase the output voltage to compensate voltage droop
across the cable caused by the cable resistance.
AGND
VCC
17
18
Signal ground of the IC
—
Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this
pin and the AGND pin.
O
Power supply for high-side MOSFET gate driver in boost side. A 0.1-µF ceramic capacitor must be
connected between this pin and the SW2 pin.
BOOT2
BOOT1
EXTVCC
19
20
21
O
O
I
Power supply for high-side MOSFET gate driver in buck side. A 0.1-µF ceramic capacitor must be
connected between this pin and the SW1 pin.
Select the internal LDO or external 5 V for VCC. When it is connected to logic high voltage, select
the internal LDO. When it is connected to logic low voltage, select the external 5 V for VCC.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
35
UNIT
V
VIN, SW1
BOOT1
SW1 + 6
V
SW1 –0.3
VCC, SCL, SDA, FSW, COMP, FB/INT, MODE, CDC, DITH/SYNC,
EXTVCC
6
V
–0.3
Voltage range
VOUT, SW2, ISP, ISN
at pins (2)
25
20
V
V
V
–0.3
–0.3
EN/UVLO
BOOT2
SW2 + 6
SW2 –0.3
SCL, SDA, FSW, COMP, FB/INT, MODE, CDC, DITH/SYNC,
EXTVCC
VCC + 0.3
V
–0.3
(3)
TJ
Junction temperature, TJ
Storage temperature
150
150
°C
°C
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground pin.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.8
1
NOM
MAX
30
UNIT
V
VIN
VOUT
L
Input voltage range
Output voltage range
22
V
Effective inductance range
Effective input capacitance range
Effective output capacitance range
Operating junction temperature
4.7
22
10
µH
µF
µF
°C
CIN
COUT
TJ
4.7
10
100
1000
125
–40
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UNIT
ZHCSNR7A –MARCH 2022 –REVISED AUGUST 2022
6.4 Thermal Information
RYQ (VQFN)
26 PINS
Standard
43.4
RYQ (VQFN)
26 PINS
EVM (2)
27.5
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
22.3
N/A
7.4
N/A
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
0.7
ΨJT
YJB
7.2
11.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on TPS55289EVM-093, 4-layer, 2-oz/1-oz/1-oz/2-oz copper 91-mmx66-mm PCB.
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
3.0
2.8
2.6
30
3.0
2.7
V
V
V
VIN rising
2.9
VVIN_UVLO
Under voltage lockout threshold
VIN falling
2.65
IC enabled, no load, no switching. VIN
= 3.0 V to 24 V, VOUT = 0.8 V, VFB
VREF + 0.1 V, RFSW = 100 kΩ, TJ up to
125°C
=
Quiescent current into VIN pin
Quiescent current into VOUT pin
760
760
860
860
µA
µA
IQ
IC enabled, no load, no switching, VIN
= 3.0 V, VOUT = 3 V to 20 V, VFB
=
VREF + 0.1 V, RFSW = 100 kΩ, TJ up to
125°C
IC disabled, VIN = 3.0 V to 14 V, TJ up
to 125°C
ISD
Shutdown current into VIN pin
Internal regulator output
0.8
5.2
3
µA
V
VCC
IVCC = 50 mA, VIN = 8 V, VOUT = 20 V
5.0
5.4
EN/UVLO
VEN_H
EN logic high threshold
EN logic low threshold
Enable threshold hysteresis
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
1.15
V
V
V
VEN_L
0.4
VEN_HYS
0.04
UVLO rising threshold at the EN/UVLO
pin
VUVLO
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
1.20
1.23
1.26
5.5
V
VUVLO_HYS
IUVLO
UVLO threshold hysteresis
10
5
mV
µA
Sourcing current at the EN/UVLO pin VEN/UVLO = 1.3 V
4.5
OUTPUT
VOUT
Output voltage range
0.8
22
V
V
Output overvoltage protection
threshold
VOVP
22.5
23.5
1
24.5
VOVP_HYS
IFB_LKG
Overvoltage protection hysteresis
V
Leakage current at FB pin
Leakage current into VOUT pin
Output discharge current
Tj up to 125°C
100
20
nA
IC disabled, VOUT = 20 V, VSW2 = 0 V,
TJ up to 125°C
IVOUT_LKG
IDISCHG
1
µA
VOUT = 20 V, VCC = 5.2 V
40
100
170
mA
INTERNAL REFERENCE DAC
Resolution of reference voltage DAC
11
bits
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT_FS=03h, REF=0780h, VREF
1.129 V
=
=
=
=
=
=
=
=
19.7
20
20.3
V
VOUT_FS=02h, REF=0780h, VREF
1.129 V
14.78
9.85
4.93
0.74
0.55
0.36
0.18
15
10
15.22
10.15
5.07
0.86
0.65
0.44
0.22
V
V
V
V
V
V
V
Output voltage when VREF is set to
1.129 V
VOUT_FULL
VOUT_FS=01h, REF=0780h, VREF
1.129 V
VOUT_FS=00h, REF=0780h, VREF
1.129 V
5
VOUT_FS=03h, REF=0000h, VREF
45 mV
0.8
0.6
0.4
0.2
VOUT_FS=02h, REF=0000h, VREF
45 mV
Output voltage when VREF is set to 45
mV
VOUT_ZERO
VOUT_FS=01h, REF=0000h, VREF
45 mV
VOUT_FS=00h, REF=0000h, VREF
45 mV
REFERENCE VOLTAGE
External feedback with REF=0780H
External feedback with REF=058CH
External feedback with REF=0334H
External feedback with REF=01A4H
1.117
0.837
0.502
0.276
1.129
0.846
0.508
0.282
1.141
0.855
0.514
0.288
V
V
V
V
Reference voltage at the FB/INT pin
when using external feedback
VREF
POWER SWITCH
Low-side MOSFET on resistance on
VOUT = 20 V, VCC = 5.2 V
VOUT = 20 V, VCC = 5.2 V
VOUT = 20 V, VCC = 5.2 V
VOUT = 20 V, VCC = 5.2 V
22
14
11
11
mΩ
mΩ
mΩ
mΩ
buck side
High-side MOSFET on resistance on
buck side
RDS(on)
Low-side MOSFET on resistance on
boost side
High-side MOSFET on resistance on
boost side
INTERNAL CLOCK
RFSW = 100 k
RFSW = 8.4 k
Boost mode
Buck mode
180
200
2200
90
220
2400
145
kHz
kHz
ns
fSW
Switching frequency
2000
tOFF_min
tON_min
VSW
Minimum off time
Minimum on time
90
130
ns
Voltage at the FSW pin
1
V
CURRENT LIMIT
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz,
FPWM
6.7
6.7
8
8
A
A
ILIM_AVG
ILIM_PK
VSNS
Average inductor current limit
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz,
PFM
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz,
FPWM
13
13
30
50
A
Peak inductor current limit at boost
high side
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz,
PFM
A
VISN = 2 V to 21 V, IOUT_LIMIT
register = 10111100b
28.5
48
31.5
52
mV
mV
Current loop regulation voltage
between ISP and ISN pin
VISN = 2 V to 21 V, IOUT_LIMIT
register = 11100100b
CABLE VOLTAGE DROP COMPENSATION
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RCDC = 20 kΩ or floating, VISP –VISN
= 50 mV
0.93
1
1.05
V
VCDC
Voltage at the CDC pin
RCDC = 20 kΩ or floating, VISP –VISN
= 2 mV
40
700
30
100
20
7.5
0
75
750
60
mV
mV
mV
mV
mV
µA
Internal output feedback,
CDC[2:0]=111, VISP –VISN = 50 mV
650
70
Internal output feedback,
CDC[2:0]=111, VISP –VISN = 2 mV
VOUT increase for cable drop
compensation
VOUT_CDC
Internal output feedback,
CDC[2:0]=001, VISP –VISN = 50 mV
130
40
Internal output feedback,
CDC[2:0]=001, VISP –VISN = 10 mV
External output feedback, RCDC = 20
kΩ, VISP –VISN = 50 mV
7.23
7.87
0.3
0.3
External output feedback, RCDC = 20
kΩ, VISP –VISN = 0 mV
IFB_CDC
FB/INT pin sinking current
µA
External output feedback, RCDC
floating, VISP –VISN = 50 mV
=
0
µA
ERROR AMPLIFIER
VFB = VREF + 400 mV, VCOMP = 1.1 V,
VCC = 5 V
ISINK
COMP pin sink current
20
60
µA
µA
VFB = VREF –400 mV, VCOMP = 1.1 V,
VCC = 5 V
ISOURCE
COMP pin source current
VCCLPH
VCCLPL
GEA
High clamp voltage at the COMP pin
Low clamp voltage at the COMP pin
Error amplifier transconductance
1.2
0.7
V
V
190
µA/V
SOFT START
tSS
Soft-start time
2.5
3.6
5
ms
SPREAD SPECTRUM
IDITH_CHG Dithering charge current
IDITH_DIS
VDITH/SYNC = 1.0 V; RFSW = 49.9 kΩ;
voltage rising from 0.9 V
2
2
µA
µA
VDITH/SYNC = 1.0 V; RFSW = 49.9 kΩ;
voltage falling from 1.1 V
Dithering discharge current
VDITH_H
VDITH_L
Dither high threshold
Dither low threshold
1.07
0.93
V
V
SYNCHRONOUS CLOCK
VSNYC_H
VSYNC_L
tSYNC_MIN
HICCUP
tHICCUP
Sync clock high voltage threshold
1.2
V
V
Sync clock low voltage threshold
Minimum sync clock pulse width
0.4
50
ns
Hiccup off time
76
ms
MODE
VMODE_H
VMODE_L
EXTVCC
VEXTVCC_H
VEXTVCC_L
MODE logic high threshold
MODE logic low threshold
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
1.2
1.2
V
V
0.4
0.4
EXTVCC logic high threshold
EXTVCC logic low threshold
VCC = 3.0 V to 5.5 V
VCC = 3.0 V to 5.5 V
V
V
LOGIC INTERFACE
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI2C_IO
VI2C_H
VI2C_L
IO voltage range for I2C
I2C input high threshold
I2C input low threshold
1.7
5.5
V
V
V
VCC = 3.0 V to 5.5 V
1.2
VCC = 3.0 V to 5.5 V
VFB/INT = 5 V
0.4
Leakage current into FB/INT pin when
outputting high impedance
IFB/INT_H
VFB/INT_L
100
0.1
nA
V
Output low voltage range of the FB/
INT pin
Sinking 4-mA current
0.03
PROTECTION
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
20
°C
°C
TSD_HYS
TJ falling below TSD
6.6 I2C Timing Characteristics
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C TIMING
fSCL
SCL clock frequency
100
0.5
1000
kHz
µs
Bus free time between a STOP and
START condition
tBUF
Fast mode plus
tHD(STA)
tLOW
Hold time (repeated) START condition
Low period of the SCL clock
260
0.5
ns
µs
ns
tHIGH
High period of the SCL clock
260
Setup time for a repeated START
condition
tSU(STA)
260
ns
tSU(DAT)
tHD(DAT)
tRCL
Data setup time
50
0
ns
µs
ns
Data hold time
Rise time of SCL signal
120
120
Rise time of SCL signal after a
repeated START condition and after
an ACK bit
tRCL1
ns
tFCL
Fall time of SCL signal
120
120
120
ns
ns
ns
ns
pF
tRDA
tFDA
tSU(STO)
CB
Rise time of SDA signal
Fall time of SDA signal
Setup time of STOP condition
Capacitive load for SDA and SCL
260
200
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6.7 Typical Characteristics
VIN = 12 V, TA = 25°C, fSW = 400 kHz, unless otherwise noted
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
30
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20
10
0
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
Output Current (A)
Output Current (A)
图6-1. Efficiency vs Output Current,
图6-2. Efficiency vs Output Current,
VOUT = 5 V, FPWM
VOUT = 5 V, PFM
100
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
Output Current (A)
图6-3. Efficiency vs Output Current,
图6-4. Efficiency vs Output Current,
VOUT = 9 V, FPWM
VOUT = 9 V, PFM
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
Output Current (A)
Output Current (A)
图6-5. Efficiency vs Output Current,
图6-6. Efficiency vs Output Current,
VOUT = 12 V, FPWM
VOUT = 12 V, PFM
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6.7 Typical Characteristics (continued)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20
10
VIN = 9 V
VIN = 12 V
VIN = 20 V
0
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
Output Current (A)
Output Current (A)
图6-7. Efficiency vs Output Current,
图6-8. Efficiency vs Output Current,
VOUT = 15 V, FPWM
VOUT = 15 V, PFM
100
90
80
70
60
50
40
30
20
10
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
0
0.0001
0.001
0.01
0.1 0.2 0.5 1 2 3 5 710
Output Current (A)
图6-9. Efficiency vs Output Current,
图6-10. Efficiency vs Output Current,
VOUT = 20 V, FPWM
VOUT = 20 V, PFM
2400
2200
2000
1800
1600
1400
1200
1000
800
0.2865
0.285
0.2835
0.282
0.2805
0.279
600
400
200
0.2775
0
0
-40
-20
0
20
40
60
80
100 120 140
10
20
30
40
50
60
70
80
90 100
Temperature (°C)
Resistance (k)
图6-12. Reference Voltage vs Temperature (VREF = 0.282 V)
图6-11. Switching Frequency vs Setting Resistance
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6.7 Typical Characteristics (continued)
0.514
0.855
0.852
0.849
0.846
0.843
0.84
0.512
0.51
0.508
0.506
0.504
0.502
0.837
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
图6-13. Reference Voltage vs Temperature (VREF = 0.508 V)
图6-14. Reference Voltage vs Temperature (VREF = 0.846 V)
1.146
800
1.14
1.134
1.128
1.122
1.116
1.11
790
780
770
760
750
Into VIN, VIN = 24 V, VOUT = 3 V
Into VOUT, VIN = 3.1 V, VOUT = 20 V
740
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
图6-15. Reference Voltage vs Temperature (VREF = 1.129 V)
图6-16. Quiescent Current vs Temperature
1.2393
1.2383
1.2373
1.2363
1.2353
1.2343
1.2333
1.2323
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
图6-18. ENABLE/UVLO Rising Threshold vs Temperature
图6-17. Shutdown Current vs Temperature
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6.7 Typical Characteristics (continued)
2500
1.2
1.1
1
2000
1500
1000
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
fSW = 2200 kHz
fSW = 200 kHz
500
0
-40
-20
0
20
40
60
80
100 120 140
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Temperature (°C)
Output Current (A)
图6-19. Switching Frequency vs Temperature
图6-20. CDC Voltage vs Output Current with RSENSE = 10 mΩ
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7 Detailed Description
7.1 Overview
The TPS55289 is a 8-A buck-boost DC-to-DC converter with the four integrated MOSFETs. The TPS55289 can
operate over a wide range of 3.0-V to 30-V input voltage and 0.8-V to 22-V output voltage. The device can
smoothly transition amongst buck mode, buck-boost mode, and boost mode according to the input voltage and
the set output voltage. The TPS55289 operates in buck mode when the input voltage is greater than the output
voltage and in boost mode when the input voltage is less than the output voltage. When the input voltage is
close to the output voltage, the TPS55289 alternates between one-cycle buck mode and one-cycle boost mode.
The TPS55289 uses an average current mode control scheme. Current mode control provides simplified loop
compensation, rapid response to the load transients, and inherent line voltage rejection. An error amplifier
compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines
the average inductor current.
An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.2 MHz. The
internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the
TPS55289 can dither the switching frequency at ±7% of the set frequency.
The TPS55289 works in fixed-frequency PWM mode at moderate to heavy load currents. In light load condition,
the TPS55289 can be configured to automatically transition to PFM mode or be forced in PWM mode by setting
the corresponding bit in an internal register.
The output voltage of the TPS55289 is adjustable by setting the internal register through I2C interface. An
internal 11-bit DAC adjusts the reference voltage related to the value written into the REF register. The device
can also limit the output current by placing a current sense resistor in the output path. These two functions
support the programmable power supply (PPS) feature of the USB PD.
The TPS55289 provides average inductor current limit of 8 A typically. In addition, the device provides cycle-by-
cycle peak inductor current limit during transient to protect the device against overcurrent condition beyond the
capability of the device.
A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable
input undervoltage lockout (UVLO) with hysteresis. The output overvoltage protection (OVP) feature turns off the
high-side FETs to prevent damage to the devices powered by the TPS55289.
The device provides a hiccup mode option to reduce the heating in the power components when the output short
circuit happens. When the hiccup mode is enabled, the TPS55289 turns off for 76 ms and restarts at soft-start–
up.
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7.2 Functional Block Diagram
L1
C4
BOOT1
C5
SW1
BOOT2
SW2
R4
VOUT
VIN
VOUT
C2
VIN
VCC
Current
Sense
C1
VIN VOUT
CDC
R2
I-V
EXTVCC
VCC
VCC
SELECT
LDO
I_limit
Iref
Buck-Boost
Control
ISP
ISN
C3
FB/INT
COMP
Gm
Gm
BOOST
BUCK
MODE
R3
Vref
DAC
SDA
SCL
Logic Core
C6
EN/UVLO
PGND
AGND
Iref
DAC
VSYNC/DITH
1.0V
VCC
VIN UVLO
VOUT OVP
Thermal
VIN
VOUT
FSW
fMOD
R1
DITH/SYNC
C7
7.3 Feature Description
7.3.1 VCC Power Supply
An internal LDO to supply the TPS55289 outputs regulated 5.2-V voltage at the VCC pin. When VIN is less than
VOUT, the internal LDO selects the power supply source by comparing VIN to a rising threshold of 6.2 V with 0.3-
V hysteresis. When VIN is higher than 6.2 V, the supply for LDO is VIN. When VIN is lower than 5.9 V, the supply
for LDO is VOUT. When VOUT is less than VIN, the internal LDO selects the power supply source by comparing
VOUT to a rising threshold of 6.2 V with 0.3-V hysteresis. When VOUT is higher than 6.2 V, the supply for LDO is
VOUT. When VOUT is lower than 5.9 V, the supply for LDO is VIN. 表7-1 shows the supply source selection for the
internal LDO.
表7-1. VCC Power Supply Logic
VIN
VOUT
Input for VCC LDO
VIN > 6.2 V
VIN < 5.9 V
VIN > VOUT
VOUT > VIN
VOUT > VIN
VOUT > 6.2 V
VIN
VOUT
VOUT
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表7-1. VCC Power Supply Logic (continued)
VIN
VOUT
Input for VCC LDO
VIN > VOUT
VOUT < 5.9 V
VIN
7.3.2 EXTVCC Power Supply
To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an
external 5-V power source can be applied at the VCC pin to supply the TPS55289. The external 5-V power
supply must have at least 100-mA output current capability and must be within the 4.75-V to 5.5-V regulation
range. When the EXTVCC pin is connected to logic low, the device selects the external power supply to supply
the device through VCC pin. When the EXTVCC pin is connected to logic high, the device selects internal LDO.
7.3.3 Operation Mode Setting
By configuring the MODE pin logic status, the TPS55289 selects two different I2C addresses. 表 7-2 shows the
I2C target address setting.
表7-2. I2C Target Address Setting
MODE Pin
Low
I2C Target Address
75h
74h
High
7.3.4 Input Undervoltage Lockout
When the input voltage is below 2.6 V, the TPS55289 is disabled. When the input voltage is above 3 V, the
TPS55289 can be enabled by pulling the EN pin to a high voltage above 1.3 V.
7.3.5 Enable and Programmable UVLO
The TPS55289 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage at
the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V but less
than the enable UVLO threshold of 1.23 V, the TPS55289 is enabled but still in standby mode. The TPS55289
starts to detect the MODE pin logic status and select the I2C target address.
The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout
with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS55289 is
enabled for I2C communication and switching operation. A hysteresis current, IUVLO_HYS, is sourced out of the
EN/UVLO pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly
changing input voltage.
By using resistor divider as shown in 图7-1, the turn-on threshold is calculated using 方程式1.
R1
8
= 8
× (1 +
)
+0(78.1 _10)
78.1
(1)
where
• VUVLO is the UVLO threshold of 1.23 V at the EN/UVLO pin.
The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/
UVLO resistor divider and is given by 方程式2.
¿8
= +78.1_*;5 × 41
+0(78.1)
(2)
where
• IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above
VUVLO
.
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VIN
IUVLO_HYS
R1
EN/UVLO
Enable
R2
C1
UVLO Comparator
1.23V
图7-1. Programmable UVLO With Resistor Divider at the EN/UVLO Pin
Using an NMOSFET together with a resistor divider can implement both logic enable and programmable UVLO
as shown in 图 7-2. The EN logic high level must be greater than the enable threshold plus the Vth of the
NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor
divider during shutdown mode.
VIN
R1
IUVLO_HYS
EN
EN/UVLO
Enable
R2
C1
UVLO Comparator
1.23V
图7-2. Logic Enable and Programmable UVLO
7.3.6 Soft Start
When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable
UVLO threshold, the TPS55289 is ready to accept the command from the I2C controller device. An I2C controller
device can configure the internal registers of the TPS55289 before setting the OE bit of the register 06h. Once
an I2C controller device sets the OE bit to 1, the TPS55289 starts to ramp up the output voltage by ramping an
internal reference voltage from 0 V to a voltage set in the internal registers 00h and 01h within 3.6 ms (typical).
7.3.7 Shutdown and Load Discharge
When the EN/UVLO pin voltage is pulled below 0.4 V, the TPS55289 is in shutdown mode, and all functions are
disabled. All internal registers are reset to default values.
When the EN/UVLO pin is at a high logic level and the OE bit is cleared to 0, the TPS55289 turns off the
switching operation but keeps the I2C interface active. Simultaneously, if the DISCHG bit in the register 06h is
set to 1, the TPS55289 discharges the output voltage below 0.8 V by an internal constant current.
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7.3.8 Switching Frequency
The TPS55289 uses a fixed frequency average current control scheme. The switching frequency is between 200
kHz and 2.2 MHz set by placing a resistor at the FSW pin. An internal amplifier holds this pin at a fixed voltage of
1 V. The setting resistance is between maximum of 100 kΩ and minimum of 8.4 kΩ. Use 方程式 3 to calculate
the resistance by a given switching frequency.
1000
f
=
(3)
SW
0.05 × R
+ 35
FSW
where
• RFSW is the resistance at the FSW pin.
For noise-sensitive applications, the TPS55289 can be synchronized to an external clock signal applied to the
DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. A resistor
also must be connected to the FSW pin when the TPS55289 is switching by the external clock. The external
clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within ±30% of
the corresponding frequency set by the resistor. 图7-3 is a recommended configuration.
External Clock
DITH/SYNC
FSW
RFSW
图7-3. External Clock Configuration
7.3.9 Switching Frequency Dithering
The TPS55289 provides an optional switching frequency dithering that is enabled by connecting a capacitor from
the DITH/SYNC pin to ground. 图7-4 illustrates the dithering circuit. By charging and discharging the capacitor, a
triangular waveform centered at 1 V is generated at the DITH/SYNC pin. The triangular waveform modulates the
oscillator frequency by ±7% of the nominal frequency set by the resistance at the FSW pin. The capacitance at
the DITH/SYNC pin sets the modulation frequency. A small capacitance modulates the oscillator frequency at a
faster rate than a large capacitance. For the dithering circuit to effectively reduce peak EMI, the modulation rate
normally is below 1 kHz. 方程式4 calculates the capacitance required to set the modulation frequency, FMOD
.
1
%
=
(()
&+6*
2.8 × 4(59 × (/1&
(4)
where
• RFSW is the switching frequency setting resistance (Ω) at the FSW pin.
• FMOD is the modulation frequency (Hz) of the dithering.
Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering
function also is disabled when an external synchronous clock is used.
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1.07V
1.0V
0.93V
DITH/SYNC
CDITH
FMOD
FSW
RFSW
图7-4. Switching Frequency Dithering
7.3.10 Inductor Current Limit
The TPS55289 implements both peak current and average inductor current limit. The average current mode
control loop uses the current sense information at the high-side MOSFET of the boost leg to clamp the maximum
average inductor current to 8 A (typical).
Besides the average current limit, a peak current limit protection is implemented during transient to protect the
device against overcurrent conditions beyond the capability of the device.
7.3.11 Internal Charge Path
Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally re-
charged by VCC through internal bootstrap diodes when the low-side MOSFET is turned on. When the
TPS55289 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is constantly on. An
internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2, charges the
bootstrap capacitor to VCC so that the high-side MOSFET remains on.
7.3.12 Output Voltage Setting
There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage.
The TPS55289 has a 11-bit DAC to program the reference voltage from 45 mV to 1.2 V. The TPS55289 can also
select an internal feedback resistor divider or an external resistor divider by setting the FB bit in register 04h.
When the FB bit is set to 0, the output voltage feedback ratio is set in internal register 04h. When the FB bit is
set to 1, the output voltage feedback ratio is set by an external resistor divider.
When using internal output voltage feedback settings, use 方程式 8 to calculate the output voltage. There are
four feedback ratios programmable by writing the INTFB[1:0] bits of register 04h. With this function, the
TPS55289 can limit the maximum output voltage to different values. In addition, the minimum step of the output
voltage change is also programmed to 10 mV, 7.5 mV, 5 mV, and 2.5 mV, accordingly.
When using an external output voltage feedback resistor divider as shown in 图 7-5, use 方程式 5 to calculate
the output voltage with the reference voltage at the FB/INT pin.
4($_72
V176 = 8 × (1 +
)
4'(
4($_$6
(5)
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RSNS
VOUT
VOUT
ISP
RFB_UP
ISN
FB/INT
¯
RFB_BT
图7-5. Output Voltage Setting by External Resistor Divider
TI recommends using 100 kΩ for the up resistor, RFB_UP. The reference voltage, VREF, at the FB/INT pin is
programmable from 45 mV to 1.2 V by writing 11-bit data into registers 00h and 01h.
7.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
The TPS55289 outputs a voltage at the CDC pin proportional to the sensed voltage across an output current
sensing resistor between the ISP pin and the ISN pin. 方程式 6 shows the exact voltage at the CDC pin related
to the sensed output current.
V%&% = 20 × (8 F 8
)
+52
+50
(6)
To compensate the voltage droop across a cable from the output of the USB port to its powered device, the
TPS55289 can lift its output voltage in proportion to the load current. There are two methods in the TPS55289 to
implement the compensation: by setting internal register 05h or by placing a resistor between the CDC pin and
AGND pin.
When using internal output voltage feedback, use the internal compensation setting. When using an external
resistor divider at the FB/INT pin to set the output voltage, use the external compensation setting by placing a
resistor at the CDC pin.
By default, the internal cable voltage droop compensation function is enabled with 0 V added to the output
voltage. Write the value into the bit CDC [2:0] in register 05h to get the desired voltage compensation.
When using external output voltage feedback, external compensation is better than the internal register for its
high accuracy. The output voltage rises in proportion to the current sourcing from the CDC pin through the
resistor at the CDC pin. Use 100-kΩ resistance for the up resistor of the feedback resistor divider. 方程式 7
shows the output voltage rise related to the sensed output current, the resistance at the CDC pin, and the up
resistor of the output voltage feedback resistor divider.
8
F 8
+50
+52
V176_%&% = 3 × 4($_72 × (
)
4%&%
(7)
where
• RFB_UP is the up resistor of the resistor divider between the output and the FB/INT pin.
• RCDC is the resistor at the CDC pin.
图 7-6 shows the output voltage rise versus the sensed output current and the resistor at the CDC pin when
RFB_UP is 100 kΩ.
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VOUT_CDC(V)
0.8
RCDC=20K
0.75V
0.5V
0.2V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
RCDC=30K
RCDC=75K
RCDC=150K
RCDC=floating
40
0.1V
VISP œ VISN
(mV)
10
20
30
50
图7-6. Output Voltage Rise Versus Output Current
7.3.14 Output Current Limit
The output current limit is programmable from 0 A to 6.35 A by placing a 10-mΩ current sensing resistor
between the ISP pin and the ISN pin. Smaller resistance results in a higher current limit and larger resistance
results in a lower current limit. An internal register sets the current sense voltage across the ISP pin and the ISN
pin. The programmable voltage step between the ISP pin and the ISN pin is 0.5 mV.
Connecting the ISP and the ISN pin together to the VOUT pin disables the output current limit because the
sensed voltage is always 0. The output current limit can also be disabled by resetting the Current_Limit_EN bit in
the Current_Limit register to 0.
7.3.15 Overvoltage Protection
The TPS55289 has output overvoltage protection. When the output voltage at the VOUT pin is detected above
23.5 V (typical), the TPS55289 turns off two high-side FETs and turns on two low-side FETs until its output
voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function prevents
overvoltage on the output and secures the circuits connected to the output from excessive overvoltage.
7.3.16 Output Short Circuit Protection
In addition to the average inductor current limit, the TPS55289 implements output short-circuit protection by
entering hiccup mode. To enable hiccup mode, the HICCUP bit in register 06h must be set. After a 3.6-ms soft-
start–up time, the TPS55289 monitors the average inductor current and output voltage. Whenever the output
short circuit happens, causing the average inductor current to reach the set limit and the output voltage is below
0.8 V, the TPS55289 shuts down the switching for 76 ms (typical) and then repeats the soft start for 3.6 ms. The
hiccup mode helps reduce the total power dissipation on the TPS55289 in output short-circuit or overcurrent
condition.
7.3.17 Thermal Shutdown
The TPS55289 is protected by a thermal shutdown circuit that shuts down the device when the internal junction
temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers values remain
unchanged when thermal shutdown is triggered. The converter automatically restarts when the junction
temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown threshold.
7.4 Device Functional Modes
In light load condition, the TPS55289 can work in PFM or forced PWM mode to meet different application
requirements. PFM mode decreases switching frequency to reduce the switching loss, thus it gets high efficiency
at light load condition. FPWM mode keeps the switching frequency unchanged to avoid undesired low switching
frequency, but the efficiency becomes lower than that of PFM mode.
By default, the TPS55289 works in PFM mode. To set the device in forced PWM mode, write the FPWM bit in
the MODE register to 1.
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7.4.1 PWM Mode
In FPWM mode, the TPS55289 keeps the switching frequency unchanged in light load condition. When the load
current decreases, the output of the internal error amplifier decreases as well to reduce the average inductor
current down to deliver less power from input to output. When the output current further reduces, the current
through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned off
even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to
zero. The power flow is from the output side to input side. The efficiency is low in light load condition. However,
with the fixed switching frequency, there is no audible noise or other problems that can be caused by low
switching frequency in light load condition.
7.4.2 Power Save Mode
The TPS55289 improves the efficiency at light load condition with PFM mode. By enabling the PFM function in
the internal register, the TPS55289 can work in PFM mode at light load condition. When the TPS55289 operates
at light load condition, the output of the internal error amplifier decreases to make the inductor peak current
down to deliver less power to the load. When the output current further reduces, the current through the inductor
will decrease to zero during the switch-off time. When the TPS55289 works in buck mode, once the inductor
current becomes zero, the low-side switch of the buck side is turned off to prevent the reverse current from
output to ground. When the TPS55289 works in boost mode, once the inductor current becomes zero, the high
side-switch of the boost side is turned off to prevent the reverse current from output to input. The TPS55289
resumes switching until the output voltage drops, so PFM mode reduces switching cycles and eliminates the
power loss by the reverse inductor current to get high efficiency in light load condition.
7.5 Programming
The TPS55289 uses I2C interface for flexible converter parameter programming. I2C is a bi-directional 2-wire
serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I2C
devices can be considered as controllers or targets when performing data transfers. A controller is the device
that initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any
device addressed is considered a target.
The TPS55289 operates as a target device with address 74h and 75h set by the MODE pin. Receiving control
inputs from the controller device, like a microcontroller or a digital signal processor, reads and writes the internal
registers 00h through 07h. The I2C interface of the TPS55289 supports both standard mode (up to 100 kbit/s)
and fast mode plus (up to 1000 kbit/s). Both SDA and SCL must be connected to the positive supply voltage
through current sources or pullup resistors. When the bus is free, both lines are in high voltage.
7.5.1 Data Validity
The data on the SDA line must be stable during the high level period of the clock. The high level or low level
state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is
generated for each data bit transferred.
SDA
SCL
Data line stable
Data valid
Change of data
allowed
图7-7. I2C Data Validity
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7.5.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A high level to low level transition
on the SDA line while SCL is at high level defines a START condition. A low level to high level transition on the
SDA line when the SCL is at high level defines a STOP condition.
START and STOP conditions are always generated by the controller. The bus is considered busy after the
START condition, and free after the STOP condition.
SDA
SCL
START (S)
STOP (P)
图7-8. I2C START and STOP Conditions
7.5.3 Byte Format
Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit
(MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some other
function, it can hold the clock line SCL low to force the controller into a wait state (clock stretching). Data transfer
then continues when the target is ready for another byte of data and release the clock line SCL.
Acknowledgement signal
from receiver
Acknowledgement signal
from receiver
MSB
SDA
SCL
1
2
7
8
9
1
2
8
9
S or Sr
P or Sr
START or
Repeated
START
STOP or
Repeated
START
图7-9. Byte Format
7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte can be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the controller.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
to low level and it remains stable low level during the high level period of this clock pulse.
The Not Acknowledge signal is when SDA remains high level during the ninth clock pulse. The controller can
then generate either a STOP to abort the transfer or a repeated START to start a new transfer.
7.5.5 Target Address and Data Direction Bit
After the START, a target address is sent. This address is seven bits long followed by the eighth bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
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SDA
SCL
1 - 7
8
9
1 - 7
8
9
1 - 7
8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
图7-10. Target Address and Data Direction
7.5.6 Single Read and Write
图7-11 and 图7-12 show the single-byte write and single-byte read format of the I2C communication.
1
7
1
1
8
1
8
1
1
S
Target Address
0
ACK
Register Address
ACK
Data to Address
ACK
P
图7-11. Single-Byte Write
1
7
1
0
1
8
1
1
7
1
1
1
S
Target Address
ACK
Register Address
ACK
S
Target Address
ACK
From controller to target
From target to controller
8
1
1
Data from Address
NACK
P
图7-12. Single-Byte Read
If the register address is not defined, the TPS55289 sends back NACK and goes back to the idle state.
7.5.7 Multiread and Multiwrite
The TPS55289 supports multiread and multiwrite.
1
7
1
0
1
8
1
S
Target Address
ACK
Register Address
ACK
8
1
8
1
8
1
1
Data to Address
ACK Data to Address + 1 ACK
······
Data to Address + N ACK
P
图7-13. Multibyte Write
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1
7
1
0
1
8
1
1
7
1
1
1
S
Target Address
ACK
Register Address
ACK
S
Target Address
ACK
8
1
8
1
8
1
1
NACK
Data from Address
ACK Data from Address + 1 ACK
······
Data from Address + N
P
图7-14. Multibyte Read
7.6 Register Maps
表 7-3 lists the memory-mapped registers for the device registers. All register offset addresses not listed in 表
7-3 should be considered as reserved locations, and the register contents should not be modified.
表7-3. Device Registers
Address
0h, 1h
2h
Acronym
REF
Register Name
Reference Voltage
Current Limit Setting
Slew Rate
Section
Go
IOUT_LIMIT
VOUT_SR
VOUT_FS
CDC
Go
3h
Go
4h
Feedback Selection
Cable Compensation
Mode Control
Go
5h
Go
6h
MODE
Go
7h
STATUS
Operating Status
Go
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7.6.1 REF Register (Address = 0h, 1h)
REF is shown in 图7-15 and 图7-16 and described in 表7-4.
Return to Summary Table.
REF sets the internal reference voltage of the TPS55289. The 01h register is the high byte and the 00h register
is the low byte. One LSB of register 00h stands for 0.5645 mV of the internal reference voltage. When the
register value is 00000000 00000000b, the reference voltage is 45 mV. When the register value is 00000111
10000000b, the reference voltage is 1.129 V. The output voltage of the TPS55289 also depends on the output
feedback ratio, which is either set by INTFB bit in register 04h or set by an external resistor divider. The default
REF = 282 mV.
When using internal output voltage feedback, the output voltage VOUT is calculated by 方程式8.
V
REF
V
=
(8)
OUT
INTFB
The REF register can be configured by an I2C controller before setting the OE bit in register 06h. For 5-V output
voltage, set the REF register value to 00000001 10100100b. To set the internal reference voltage, write the
register 00h first, then write the register 01h.
图7-15. REF_LSB
7
6
5
4
3
2
1
0
VREF
图7-16. REF_MSB
15
14
13
12
11
10
9
8
Reserved
VREF
表7-4. REF Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15-11
10-0
Reserved
VREF
000000b
Reserved
001
Sets the internal reference voltage
10100100b
000 00000000b = 45-mV reference voltage
000 00000001b = 45.5645-mV reference voltage
000 00000010b = 46.129-mV reference voltage
...... = ......
001 10100100b = 282-mV reference voltage
...... = ......
011 00110100b = 508-mV reference voltage
...... = ......
101 10001100b = 846-mV reference voltage
...... = ......
111 10000000b = 1129-mV reference voltage
...... = ......
111 11111110b = 1200-mV reference voltage
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7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
IOUT_LIMIT is shown in 图7-17 and described in 表7-5.
Return to Summary Table.
IOUT_LIMIT sets the current limit target voltage between the ISP pin and the ISN pin. The default value in the
current limit register is 11100100b standing for 50 mV. One LSB stands for 0.5 mV. The bit7 enables the current
limit or disables the current limit.
图7-17. IOUT_LIMIT Register
7
6
5
4
3
2
1
0
Current_Limit_EN
R/W-1b
Current_Limit_Setting
R/W-1100100b
表7-5. IOUT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Current_Limit_EN
R/W
1b
Enable or disable current limit.
0b = Current limit disabled
1b = Current limit enabled (Default)
6-0
Current_Limit_Setting
R/W
1100100b
Sets the current limit target voltage between the ISP pin and the ISN
pin
0000000b = VISP-VISN = 0 (mV)
0000001b = VISP-VISN = 0.5 (mV)
0000010b = VISP-VISN = 1 (mV)
0000011b = VISP-VISN = 1.5 (mV)
0000100b = VISP-VISN = 2.0 (mV)
...... = ......
1100100b = VISP-VISN = 50.0 (mV) (Default)
...... = ......
1111111b = VISP-VISN = 63.5 (mV)
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7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
VOUT_SR is shown in 图7-18 and described in 表7-6.
Return to Summary Table.
Register 03h sets the slew rate of the output voltage change and the response delay time after the output
current exceeds the setting output current limit.
The OCP_DELAY [1:0] bits set the response time of the TPS55289 when the output overcurrent limit is hit. This
allows the TPS55289 to output high current in a relative short duration time. The default setting is 128 µs so that
the TPS55289 immediately limits the output current.
The SR [1:0] bits set 1.25 mV/μs, 2.5 mV/μs, 5 mV/μs, and 10 mV/μs slew rate for output voltage change.
图7-18. VOUT_SR Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
OCP_DELAY
R/W-00b
RESERVED
R/W-00b
SR
R/W-01b
表7-6. VOUT_SR Register Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
Description
RESERVED
OCP_DELAY
00b
Reserved
00b
Sets the response time of the device when the output overcurrent
limit is reached
00b = 128 µs (Default)
01b = Delay 1.024 × 3 ms
10b = Delay 1.024 × 6 ms
11b = Delay 1.024 × 12 ms
3-2
1-0
RESERVED
SR
R/W
R/W
00b
01b
Reserved
Sets slew rate for output voltage change
00b = 1.25-mV/µs output change slew rate
01b = 2.5-mV/µs output change slew rate (Default)
10b = 5-mV/µs output change slew rate
11b = 10-mV/µs output change slew rate
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7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
VOUT_FS is shown in 图7-19 and described in 表7-7.
Return to Summary Table.
Register 04h sets the selection for the output feedback voltage, either by an internal resistor divider or external
resistor divider, and sets the internal feedback ratio when using internal feedback resistor divider.
图7-19. VOUT_FS Register
7
6
5
4
3
2
1
0
FB
RESERVED
R/W-00000b
INTFB
R/W-0b
R/W-11b
表7-7. VOUT_FS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FB
R/W
0b
Output feedback voltage
0b = Use internal output voltage feedback. The FB/INT pin is the
indicator for output short circuit protection, overcurrent status, and
overvoltage status (Default).
1b = Use external output voltage feedback. The FB/INT pin is the
feedback input of the output voltage.
6-2
1-0
RESERVED
INTFB
R
00000b
11b
Reserved
R/W
Internal feedback ratio
00b = Set internal feedback ratio to 0.2256
01b = Set internal feedback ratio to 0.1128
10b = Set internal feedback ratio to 0.0752
11b = Set internal feedback ratio to 0.0564 (Default)
表7-8. Output Voltage vs Internal Reference
INTFB1 INTFB0
REF=0000h
REF=001Ah
REF=0050h
REF=00F0h
REF=0780h
5 V
Output Voltage Step
2.5 mV
0
0
1
1
0
1
0
1
0.8 V
0.8 V
10 V
5 mV
0.8 V
15 V
7.5 mV
0.8 V
20 V
10 mV
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7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
CDC is shown in 图7-20 and described in 表7-9.
Return to Summary Table.
Register 05h sets masks for SC bit, OCP bit, and OVP bit in register 07h. In addition, register 05h sets the
voltage rise added to the setting output voltage with respect to the sensed differential voltage between the ISP
pin and the ISN pin.
图7-20. CDC Register
7
6
5
4
3
2
1
0
SC_MASK
R/W-1b
OCP_MASK
R/W-1b
OVP_MASK
R/W-1b
RESERVED
R/W-0b
CDC_OPTION
R/W-0b
CDC
R/W-000b
表7-9. CDC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
SC_MASK
R/W
1b
Short circuit mask
0b = Disabled SC indication
1b = Enable SC indication (Default)
OCP_MASK
OVP_MASK
R/W
R/W
1b
1b
Over current mask
0b = Disabled OCP indication
1b = Enable OCP indication (Default)
Over voltage mask
0b = Disabled OVP indication
1b = Enable OVP indication (Default)
4
3
RESERVED
R/W
R/W
0b
0b
Reserved
CDC_OPTION
Select the cable voltage droop compensation approach.
0b = Internal CDC compensation by the register 05H (Default)
1b = External CDC compensation by a resistor at the CDC pin
2-0
CDC
R/W
000b
Compensation for voltage droop over the cable
000b = 0-V output voltage rise with 50 mV at VISP - VISN (Default)
001b = 0.1-V output voltage rise with 50 mV at VISP - VISN
010b = 0.2-V output voltage rise with 50 mV at VISP - VISN
011b = 0.3-V output voltage rise with 50 mV at VISP - VISN
100b = 0.4-V output voltage rise with 50 mV at VISP - VISN
101b = 0.5-V output voltage rise with 50 mV at VISP - VISN
110b = 0.6-V output voltage rise with 50 mV at VISP - VISN
111b = 0.7-V output voltage rise with 50 mV at VISP - VISN
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7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
MODE is shown in 图7-21 and described in 表7-10.
Return to Summary Table.
MODE controls the operating mode of the TPS55289.
图7-21. MODE Register
7
6
5
4
3
2
1
0
OE
FSW
HICCUP
R/W-1b
DISCHG
R/W-0b
Reserved
R/W-0b
Reserved
R/W-0b
FPWM
R/W-0b
Reserved
R/W-0b
R/W-0b
R/W-0b
表7-10. MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OE
R/W
0b
Output enable
0b = Output disabled (Default)
1b = Output enable
6
FSWDBL
R/W
0b
Switching frequency doubling in buck-boost mode
TI does not recommend using double frequency function at switching
frequency above 1.6 MHz.
0b = Keep the switching frequency unchanged during buck-boost
mode (Default)
1b = Double the switching frequency during buck-boost mode
5
4
HICCUP
DISCHG
R/W
R/W
1b
0b
Hiccup mode
0b = Disable the hiccup during output short circuit protection.
1b = Enable the hiccup during output short circuit protection (Default)
Output discharge
0b = Disabled VOUT discharge when the device is in shutdown
mode (Default)
1b = Enable VOUT discharge. VOUT is discharged to ground by an
internal 100-mA current sink
3
2
1
RESERVED
RESERVED
FPWM
R
0b
0b
0b
Reserved
Reserved
R
R/W
Select operating mode at light load condition
0b = PFM operating mode at light load condition (Default)
1b = FPWM operating mode at light load condition
0
RESERVED
R
0b
Reserved
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7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
STATUS is shown in 图7-22 and described in 表7-11.
Return to Summary Table.
The STATUS register stores the operating status of the TPS55289. When any of the SCP bit, the OCP bit, or the
OVP bit are set, and the corresponding mask bit in register 05h is set as well, the FB/INT pin outputs low logic
̅
level to indicate the situation. Reading register 07h clears the SCP bit, OCP bit, and OVP bit. After the SCP bit,
OCP bit, or OVP bit is set, it does not reset until the register is read. If the situation still exists, the corresponding
bit is set again.
图7-22. STATUS Register
7
6
5
4
3
2
1
0
SCP
R-0b
OCP
R-0b
OVP
R-0b
Reserved
R/W-0b
Reserved
R/W-0b
Reserved
R/W-0b
STATUS
R-11b
表7-11. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SCP
R
0b
Short circuit protection
0b = No short circuit
1b = Short circuit happens. Does not reset until it is read.
6
5
OCP
OVP
R
R
0b
0b
Overcurrent protection
0b = No output overcurrent
1b = Output current hits the current limit sensed at the ISP and the
ISN pin. Does not reset until it is read.
Overvoltage protection
0b = No OVP
1b = Output voltage exceeds the OVP threshold. Does not reset until
it is read.
4
RESERVED
RESERVED
RESERVED
STATUS
R
R
R
R
0b
Reserved
Reserved
Reserved
3
0b
2
0b
1-0
11b
Operating status
00b = Boost
01b = Buck
10b = Buck-Boost
11b = Reserved
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS55289 can operate over a wide range of 3.0-V to 30-V input voltage and output 0.8 V to 22 V. The
device can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input
voltage and the setting output voltage. The TPS55289 operates in buck mode when the input voltage is greater
than the output voltage and in boost mode when the input voltage is less than the output voltage. When the input
voltage is close to the output voltage, the TPS55289 operates in one-cycle buck and one-cycle boost mode
alternately. The switching frequency is set by an external resistor. To reduce the switching power loss in high
power conditions, set the switching frequency below 500 kHz. If a system requires higher switching frequency
above 500 kHz, set the lower switch current limit for better thermal performance.
8.2 Typical Application
The TPS55289 provides a small size solution for USB PD power supply application with the input voltage
ranging from 9 V to 30 V.
L1
4.7µH
C5
C4
SW1
BOOT1
SW2 BOOT2
VIN = 9V to 30V
R4
VOUT = 3.3V to 21V
VOUT
VIN
C1
C2
VCC
PGND
ISP
4 x 22µF
C3
AGND
ON
ISN
EN/UVLO
SCL
TPS55289
OFF
FB/INT
COMP
SDA
Internal Vcc
EXTVCC
External Vcc
74h
DITH/SYNC
FSW
MODE
CDC
R3
C7
75h
C8
C6
R2
R1
图8-1. USB PD Power Supply With 9-V to 30-V Input Voltage
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8.2.1 Design Requirements
The design parameters are listed in 表8-1:
表8-1. Design Parameters
Parameters
Input voltage
Values
9 V to 30 V
3.3 V to 20 V
2.25 A
Output voltage
Output current limit
Output voltage ripple
Operating mode at light load
±50 mV
FPWM
8.2.2 Detailed Design Procedure
8.2.2.1 Switching Frequency
The switching frequency of the TPS55289 is set by a resistor at the FSW pin. Use 方程式 3 to calculate the
resistance for the desired frequency. To reduce the switching power loss with such a high current application, a
1% standard resistor of 49.9 kΩ is selected for 400-kHz switching frequency for this application.
8.2.2.2 Output Voltage Setting
The TPS55289 has I2C interface to set the internal reference voltage. A microcontroller can easily set the
desired output voltage by writing the proper data into the reference voltage registers through I2C bus.
8.2.2.3 Inductor Selection
Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications: inductance, saturation current, and DC resistance.
The TPS55289 is designed to work with inductor values between 1 µH and 10 µH. The inductor selection is
based on consideration of both buck and boost modes of operation.
For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum input voltage. In CCM, Equation 9 shows the relationship between the
inductance and the inductor ripple current.
k
o
VIN(MAX)-VOUT ×VOUT
L=
∆IL(P-P)×fSW×VIN MAX
:
;
(9)
where
• VIN(MAX) is the maximum input voltage.
• VOUT is the output voltage.
• ΔIL(P-P) is the peak to peak ripple current of the inductor.
• fSW is the switching frequency.
For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals half of the
maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum output voltage. In CCM, 方程式 10 shows the relationship between the
inductance and the inductor ripple current.
k
VIN× VOUT(MAX)-VIN
o
L=
∆IL(P-P)×fSW×VOUT(MAX)
(10)
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where
• VIN is the input voltage.
• VOUT(MAX) is the maximum output voltage.
• ΔIL(P-P) is the peak-to-peak ripple current of the inductor.
• fSW is the switching frequency.
For a certain inductor, the inductor ripple current achieves maximum value when VIN equals to the half of the
maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor
current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average
inductor current in boost mode.
In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can
be calculated with 方程式11.
VOUT×IOUT
IL(DC)
=
VIN×ꢀ
(11)
where
• VOUT is the output voltage.
• IOUT is the output current.
• VIN is the input voltage.
• ηis the power conversion efficiency.
For a given maximum output current of the TPS55289, the maximum inductor DC current happens at the
minimum input voltage and maximum output voltage. Set the inductor current limit of the TPS55289 higher than
the calculated maximum inductor DC current to make sure the TPS55289 has the desired output current
capability.
In boost mode, the inductor ripple current is calculated with 方程式12.
:
VIN× VOUT-VIN
;
∆IL(P-P)
=
L×fSW×VOUT
(12)
where
• ΔIL(P-P) is the inductor ripple current.
• L is the inductor value.
• fSW is the switching frequency.
• VOUT is the output voltage.
• VIN is the input voltage.
Therefore, the inductor peak current is calculated with 方程式13.
∆IL(P-P)
IL(P) = IL(DC)
+
2
(13)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The
selected inductor must have higher saturation current than the calculated peak current.
The conversion efficiency is dependent on the resistance of its current path. The switching loss associated with
the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the inductor
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DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss. 表 8-2
lists recommended inductors for the TPS55289. In this application example, the Coilcraft inductor XAL7070-472
is selected for its small size, high saturation current, and small DCR.
表8-2. Recommended Inductors
DCR
(Maximum)
Saturation Current/Heat
Part Number
L (µH)
Size (L × W × H mm)
Vendor(1)
Rating Current (A)
(mΩ)
XAL7070-472ME
VCHA085D-4R7MS6
IHLP4040DZER4R7M01
4.7
4.7
4.7
14.3
15.6
16.5
15.2/10.5
16.0/8.8
17/9.5
7.5 × 7.2 × 7.0
8.7 × 8.2 × 5.2
10.2 × 10.2 × 4.0
Coilcraft
Cyntec
Vishay
(1) See the Third-party Products disclaimer.
8.2.2.4 Input Capacitor
In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given
by 方程式14.
:
VOUT× VIN-VOUT
;
¨
ICIN RMS; = I
:
×
OUT
VIN×VIN
(14)
where
• ICIN(RMS) is the RMS current through the input capacitor.
• IOUT is the output current.
The maximum RMS current occurs at the output voltage is half of the input voltage, which gives ICIN(RMS) = IOUT
/
2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20 µF
effective capacitance is a good starting point for this application. Add a 0.1-µF/0402 package ceramic capacitor
and place it close to VIN pin and GND pin to suppress high frequency noise.
8.2.2.5 Output Capacitor
In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by 方程式 15, where the minimum input voltage and the maximum output voltage correspond to the
maximum capacitor current.
VOUT
¨
ICOUT RMS; = I
:
×
-1
OUT
VIN
(15)
where
• ICOUT(RMS) is the RMS current through the output capacitor.
• IOUT is the output current.
In this example, the maximum output ripple RMS current is 2.5 A.
The ESR of the output capacitor causes an output voltage ripple given by 方程式16 in boost mode.
IOUT×VOUT
VRIPPLE(ESR)
=
×RCOUT
VIN
(16)
where
• RCOUT is the ESR of the output capacitance.
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The capacitance also causes a capacitive output voltage ripple given by 方程式 17 in boost mode. When input
voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest
output voltage ripple caused by the capacitance.
VIN
VOUT
l
IOUT× 1-
p
VRIPPLE(CAP)
=
COUT×fSW
(17)
Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR,
high ripple current, and small output voltage ripple. From the required output voltage ripple, use 方程式 16 and
方程式17 to calculate the minimum required effective capacitance of the COUT
.
Add a 0.1-μF/0402 package ceramic capacitor and place it close to VOUT pin and GND pin to suppress high
frequency noise.
8.2.2.6 Output Current Limit
The output current limit is implemented by placing a current sense resistor between the ISP and ISN pins along
with setting a limit voltage between the ISP pin and the ISN pin through register 02h. The maximum value of the
limit voltage between the ISP and ISN pins is 63.5 mV. The default limit voltage is 50 mV. The current sense
resistor between the ISP and ISN pins should be selected to ensure that the output current limit is set high
enough for output. The output current limit setting resistor is given by 方程式18.
VSNS
RSNS
=
IOUT_LIMIT
(18)
where
• VSNS is the current limit setting voltage between the ISP and ISN pins.
• IOUT_LIMIT is the desired output current limit.
Because the power dissipation is large, make sure the current sense resistor has enough power dissipation
capability with a large package.
8.2.2.7 Loop Stability
The TPS55289 uses average current control scheme. The inner current loop uses internal compensation and
requires the inductor value must be larger than 1.2/fSW. The outer voltage loop requires an external
compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation
network comprised of resistor and ceramic capacitors is connected to the COMP pin.
The TPS55289 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require
loop compensations. The restrictive one of both compensations is selected as the overall compensation from a
loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost
mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).
The power stage in boost mode can be modeled by 方程式18.
s
s
l
p l
× 1-
p
1+
:
RLOAD× 1-D
;
2N×fESRZ
2N×fRHPZ
GPS(s) =
×
s
2×RSENSE
1+
2N×fP
(19)
where
• RLOAD is the output load resistance.
• D is the switching duty cycle in boost mode.
• RSENSE is the equivalent internal current sense resistor, which is 0.055 Ω.
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The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use 方程式
20 to 方程式22 to calculate them.
2
fP =
2N×RLOAD×COUT
(20)
(21)
(22)
1
fESRZ
=
2N×RCOUT×COUT
2
:
RLOAD× 1-D
;
fRHPZ
=
2N×L
The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the
control portion of the loop. The transfer function of the control portion is shown by 方程式23.
s
l
p
1+
GEA×REA×VREF
VOUT
2N×fCOMZ
GC(s) =
×
s
s
l
p
l
× 1 +
p
1+
2N×fCOMP1
2N×fCOMP2
(23)
where
• GEA is the transconductance of the error amplifier.
• REA is the output resistance of the error amplifier.
• VREF is the reference voltage input to the error amplifier.
• VOUT is the output voltage.
• fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network.
• fCOMZ is the zero’s frequency of the compensation network.
The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover
frequency, fC, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain
stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain
cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW, or 1/5 of
the RHPZ frequency, fRHPZ
.
Then, set the value of RC, CC, and CP by 方程式24 to 方程式26.
2N×VOUT×R
×COUT×fC
SENSE
RC =
: ;
1-D ×VREF×GEA
(24)
where
• fC is the selected crossover frequency.
RLOAD×COUT
CC =
2×RC
(25)
(26)
RCOUT×COUT
CP=
RC
If the calculated CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output
voltage ringing during the line and load transient.
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8.2.3 Application Curves
VOUT
VOUT
SW1
SW2
iL
SW1
SW2
iL
图8-3. Switching Waveforms in VIN = 12 V, VOUT = 5
图8-2. Switching Waveforms in VIN = 12 V, VOUT = 5
V, IO = 0 A, PFM
V, IO = 5 A, FPWM
VOUT
VOUT
SW1
SW2
iL
SW1
SW2
iL
图8-4. Switching Waveforms in VIN = 12 V, VOUT = 图8-5. Switching Waveforms in VIN = 12 V, VOUT
12 V, IO = 3 A, FPWM 12 V, IO = 0 A, PFM
=
VOUT
VOUT
SW1
SW1
SW2
iL
SW2
iL
图8-6. Switching Waveforms in VIN = 12 V, VOUT = 图8-7. Switching Waveforms in VIN = 12 V, VOUT
=
20 V, IO = 2 A, FPWM
20 V, IO = 0 A, PFM
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VOUT
VOUT
iL
iL
图8-8. Start-up Waveforms in VIN = 12 V, VOUT = 5 图8-9. Shutdown Waveforms in VIN = 12 V, VOUT = 5
V, RLOAD = 1.2 Ω, FPWM V, RLOAD = 1.2 Ω, FPWM
VIN
VOUT
VOUT
Io
iL
图8-10. Line Transient Waveforms in VIN = 9 V to
20 V, VOUT = 12 V, IO = 3 A with 200-μs Slew Rate,
FPWM
图8-11. Load Transient Waveforms in VIN = 12 V,
V
OUT = 5 V, IO = 2.5 A to 5 A with 20-μs Slew Rate,
FPWM
VOUT
Io
图8-12. 3-A Output Current Limit Waveforms in VIN = 12 V,
VOUT = 5 V, RLOAD = 1 Ω, RSNS = 10 mΩFPWM
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3.0 V to 30 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum
electrolytic capacitor with a value of 100 μF.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and
noise problems.
• Place the 0.1-μF small package (0402) ceramic capacitors close to the VIN/VOUT pins to minimize high
frequency current loops. This improves the radiation of high-frequency noise (EMI) and efficiency.
• Use multiple GND vias near PGND pin to connect the PGND to the internal ground plane. This also improves
thermal performance.
• Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes. Use a ground plane under the
switching regulator to minimize interplane coupling.
• Use Kelvin connections to RSENSE for the current sense signals ISP and ISN and run lines in parallel from the
RSENSE terminals to the IC pins. Place the filter capacitor for the current sense signal as close to the IC pins
as possible.
• Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins. Place
the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 and SW2 pins.
• Place the VCC capacitor close to the IC with wide and short trace. The GND terminal of the VCC capacitor
should be directly connected with PGND plane through three to four vias.
• Isolate the power ground from the analog ground. The PGND plane and AGND plane are connected at the
terminal of the VCC capacitor. Thus the noise caused by the MOSFET driver and parasitic inductance does
not interface with the AGND and internal control circuit.
• Place the compensation components as close to the COMP pin as possible. Keep the compensation
components, feedback components, and other sensitive analog circuitry far away from the power
components, switching nodes SW1 and SW2, and high-current trace to prevent noise coupling into the
analog signals.
• To improve thermal performance, it is recommended to use thermal vias beneath the TPS55289 connecting
the VIN pin to a large VIN area, and the VOUT pin to a large VOUT area separately.
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10.2 Layout Example
PGND
17
16
15
14
AGND
1
2
3
4
VIN
VOUT
PGND
trace on bottom layer
AGND plane on an inner layer
The first inner layer is the PGND plane
图10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RYQ0021A
VQFN - 1.0 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 4.08
SYMM
0.3
16X
0.2
0.38
0.28
(0.1) TYP
SEE TERMINAL
DETAIL
13
5
18X 0.5
4
14
SYMM
2X
1.5
(2.35)
17
1
18
21
19
20
0.55
0.35
0.1
0.5
0.3
4X
12X
2X 0.54
C A B
0.1
C A B
PIN 1 ID
(OPTIONAL)
0.3
0.2
0.05
5X
0.05
0.1
0.05
C A B
4226658/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RYQ0021A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
2X (0.54)
(R0.05) TYP
21
18
12X (0.6)
1
21X (0.25)
17
5X
(3.4)
(2.8)
(2.75)
(2.35)
SYMM
18X (0.5)
14
4
4X (0.65)
5
13
(0.33)
2X (4.08)
4.8
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226658/A 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RYQ0021A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
2X (0.54)
21
18
16X (0.6)
1
30X (0.25)
SYMM
17
(2.8)
(2.75)
(2.4)
15X
(1)
18X (0.5)
14
METAL
TYP
4
4X (0.65)
13
5
(0.33)
2X (4.08)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PIN 7,8, 10 & 11 SOLDER COVERAGE = 88%
PIN 9 SOLDER COVERAGE = 64%
SCALE:20X
4226658/A 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: TPS55289
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS55289RYQR
ACTIVE
VQFN-HR
RYQ
21
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
S55289
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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