TPS560430XDBVT [TI]
具有高效睡眠模式的 SIMPLE SWITCHER® 36V 600mA 降压稳压器 | DBV | 6 | -40 to 125;
| 型号： | TPS560430XDBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高效睡眠模式的 SIMPLE SWITCHER® 36V 600mA 降压稳压器 | DBV | 6 | -40 to 125 稳压器 |
| 文件： | 总33页 (文件大小：1332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
TPS560430 SIMPLE SWITCHER®4V 至 36V、600mA 同步降压转换器
1 特性
2 应用
1
•
专用于条件严苛的工业 应用
•
•
电网基础设施：先进抄表基础设施
电机驱动系统：交流逆变器、变频驱动器、伺服系
统、场传动器
–
–
–
–
–
–
–
输入电压范围：4V 至 36V
600mA 持续输出电流
最短打开时间：60ns
98% 最大占空比
•
工厂和楼宇自动化：PLC、工业计算机、电梯控
制、HVAC 控制
•
•
汽车售后市场：摄像头
通用宽输入电压电源
支持利用预偏置输出进行启动
间断模式短路保护
在 –40°C 至 125°C 工作温度范围内提供 ±1.5%
的容差电压基准
3 说明
TPS560430 是一款简单易用的同步降压直流/直流转换
器，能够驱动高达 600mA 的负载电流。该器件具有
4V 至 36V 的宽输入范围，因此适用于 从工业到汽车
领域中 非稳压电源的电源调节。
–
精密使能端
•
•
•
解决方案小巧且易于使用
–
–
–
集成同步整流
方便易用的内部补偿
SOT-23-6 封装
TPS560430 具有 1.1MHz 和 2.1MHz 两种工作频率，
适用于高频率或小型解决方案。TPS560430 还具有
FPWM（强制 PWM）模式，在全负载范围内可实现恒
定频率和小输出电压纹波。在内部实现了软启动和补偿
电路，从而最大限度地减少了器件所用的外部组件。
采用引脚到引脚兼容封装的各种选项
–
–
–
1.1MHz 和 2.1MHz 频率选项
PFM 和强制 PWM (FPWM) 选项
固定 3.3V 输出选项
使用 TPS560430 并借助 WEBENCH® 电源设计器
该器件具有内置的保护 功能，例如逐周期电流限制、
间断模式短路保护以及在出现过多功率损耗时执行的热
关断功能。TPS560430 采用 SOT-23-6 封装。
创建定制设计方案
器件信息 (1)
器件型号
封装
封装尺寸（标称值）
TPS560430
SOT-23-6
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
效率与输出电流间的关系
VOUT = 5V，1100kHz，PFM
简化原理图
VIN up to 36 V
100
95
90
85
80
75
CB
VIN
CIN
CBOOT
L
VOUT
SW
FB
EN
RFBT
GND
COUT
RFBB
70
VIN = 8 V
VIN = 12 V
VIN = 24 V
Copyright © 2017, Texas Instruments Incorporated
65
60
0.01
0.1
1
IOUT (A)
D000
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE22
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Switching Characteristics.......................................... 6
7.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 器件支持................................................................ 24
12.2 文档支持................................................................ 24
12.3 接收文档更新通知 ................................................. 24
12.4 社区资源................................................................ 24
12.5 商标....................................................................... 24
12.6 静电放电警告......................................................... 24
12.7 术语表 ................................................................... 24
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (May 2018) to Revision B
Page
•
•
•
•
•
Changed marketing status of the TPS560430X orderable from Product Preview to Production........................................... 3
Changed marketing status of the TPS560430Y orderable from Product Preview to Production........................................... 3
Changed marketing status of the TPS560430YF orderable from Product Preview to Production. ....................................... 3
已添加 图 4 Efficiency vs Load Current.................................................................................................................................. 7
已添加 图 5 Efficiency vs Load Current.................................................................................................................................. 7
2
Copyright © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
5 Device Comparison Table
PART NUMBER
TPS560430XF
TPS560430X3F
TPS560430X
Frequency
1.1 MHz
1.1 MHz
1.1 MHz
2.1 MHz
2.1 MHz
PFM or FPWM
Output
FPWM
FPWM
PFM
Adjustable
Fixed 3.3 V
Adjustable
Adjustable
Adjustable
TPS560430Y
PFM
TPS560430YF
FPWM
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23-6
Top View
CB
GND
FB
1
6
SW
VIN
2
3
5
4
EN
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NO.
NAME
Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF capacitor
from this pin to the SW pin.
1
2
3
4
5
6
CB
P
G
A
A
P
P
Power ground terminals, connected to the source of low-side FET internally. Connect to system
ground, ground side of CIN and COUT. Path to CIN must be as short as possible.
GND
FB
Feedback input to the convertor. Connect a resistor divider to set the output voltage. Never short
this terminal to ground during operation.
Precision enable input to the convertor. Do not float. High = on, Low = off. Can be tied to VIN.
Precision enable input allows adjustable UVLO by external resistor divider.
EN
Supply input terminal to internal bias LDO and high-side FET. Connect to input supply and input
bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and GND.
VIN
SW
Switching output of the convertor. Internally connected to source of the high-side FET and drain of
the low-side FET. Connect to power inductor.
(1) A = Analog, P = Power, G = Ground.
Copyright © 2017–2018, Texas Instruments Incorporated
3
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
(1)
PARAMETER
VIN to GND
MIN
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–40
MAX
38
UNIT
Input Voltages
EN to GND
FB to GND
SW to GND
VIN + 0.3
5.5
V
VIN + 0.3
38
Output Voltages SW to GND less than 10 ns transient
V
CB to SW
5.5
(2)
TJ
Junction temperature
Storage temperature
150
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE
± 2500
± 750
UNIT
V
(1)
Human-body model (HBM)
Charged-device model (CDM)
VESD
Electrostatic discharge
(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
(1)
PARAMETER
MIN
4
MAX
36
UNIT
VIN to GND
Input Voltages
EN
0
VIN
4.5
V
FB
0
Output Voltage
Output Current
Temperature
VOUT
1.0
0
95% of VIN
600
V
IOUT
mA
°C
Operating junction temperature range, TJ
–40
+125
(1) Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific
performance limits. For guaranteed specifications, see Electrical Characteristics
7.4 Thermal Information
(1)
THERMAL METRIC
DBV (6 PINS)
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (TOP) thermal resistance
Junction-to-case (BOTTOM) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
173
116
31
RθJC_T
RθJC_B
ψJT
20
ψJB
30
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a specified JEDEC board. They do not represent the
performance obtained in an actual application.
4
Copyright © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN
Operation input voltage
4
3.55
3.25
36
4.00
3.65
V
Rising threshold
3.75
3.45
0.3
VIN_UVLO
Undervoltage lockout thresholds
Falling threshold
Hysteresis
V
IQ
Operating quiescent current (non-
switching)
PFM version, VEN = 3.3 V, VFB
1.1V
=
80
120
10
µA
µA
ISHDN
Shutdown current
VEN = 0 V
3
ENABLE (EN PIN)
VEN_H
VEN_L
VEN_HYS
IEN
Enable rising threshold voltage
1.1
1.23
1.1
1.36
1.22
V
V
Enable falling threshold voltage
Enable hysteresis voltage
Leakage current at EN pin
0.95
0.13
10
V
VEN = 3.3 V
200
nA
VOLTAGE REFERENCE (FB PIN)
TJ = 25 °C
0.995
0.985
3.28
1.00
1.00
3.3
1.005
1.015
3.32
V
V
V
V
TJ = –40 °C to 125 °C
Fixed 3.3-V output, TJ = 25 °C
VREF
Reference voltage
Fixed 3.3-V output, TJ = –10 °C to
85 °C
3.272
3.3
3.328
Fixed 3.3-V output, TJ = –40 °C to
125 °C
3.25
3.3
3.35
50
V
IFB
Leakage current at FB pin
VFB = 1.2 V
0.2
1.7
nA
µA
Fixed 3.3-V output, VFB = 3.96 V
CURRENT LIMITS AND HICCUP
IHS_LIMIT
ILS_LIMIT
ILS_ZC
Peak inductor current limit
0.8
1.1
0.8
20
1.4
A
A
Valley inductor current limit
0.62
0.98
Zero cross current (PFM version)
mA
A
ILS_NEG
Negative current limit (FPWM
version)
-0.7
-0.5
-0.3
VHICCUP
Hiccup threshold of FB pin
% of reference voltage
40%
INTEGRATED MOSFETS
RDS_ON_HS
High-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V
Low-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V
450
240
mΩ
mΩ
RDS_ON_LS
(1)
THERMAL SHUTDOWN
TSHDN
THYS
Thermal shutdown threshold
Hysteresis
170
12
°C
°C
(1) Guaranteed by design.
Copyright © 2017–2018, Texas Instruments Incorporated
5
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
7.6 Timing Requirements
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
Internal soft-start time
Hiccup time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
The time of internal reference to
increase from 10% to 90% of VREF
VIN = 12 V
TSS
,
1.8
ms
HICCUP
THICCUP
VIN = 12 V
135
ms
7.7 Switching Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING NODE (SW PIN)
tON_MIN
Minimum turn-on time
Minimum turn-off time
Maximum turn-on time
IOUT = 600 mA
60
100
7.5
ns
ns
µs
tOFF_MIN
IOUT = 600 mA
tON_MAX
OSCILLATOR
1.1-MHz version
2.1-MHz version
0.935
1.785
1.1
2.1
1.265
2.415
MHz
MHz
fSW
Oscillator frequency
6
版权 © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
7.8 Typical Characteristics
VIN = 12 V, fSW = 1.1 MHz, TA = 25°C, unless otherwise specified.
100
90
80
70
60
50
100
90
80
70
60
50
40
30
20
10
0
FPWM, 8 VIN
FPWM, 12 VIN
FPWM, 24 VIN
FPWM, 36 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
PFM, 36 VIN
FPWM, 8 VIN
FPWM, 12 VIN
FPWM, 24 VIN
FPWM, 36 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
PFM, 36 VIN
40
30
20
10
0
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
IOUT (A)
IOUT (A)
D001
D002
fSW = 1.1 MHz
VOUT = 3.3 V
fSW = 1.1 MHz
VOUT = 5 V
图 1. Efficiency vs Load Current
图 2. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
FPWM, 15 VIN
FPWM, 8 VIN
FPWM, 24 VIN
FPWM, 36 VIN
PFM, 15 VIN
PFM, 24 VIN
PFM, 36 VIN
FPWM, 12 VIN
FPWM, 24 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
0.0001
0.001
0.01
IOUT (A)
0.1
1
0.0001
0.001
0.01
IOUT (A)
0.1
1
D003
D011
fSW = 1.1 MHz
VOUT = 12 V
fSW = 2.1 MHz
VOUT = 3.3 V
图 3. Efficiency vs Load Current
图 4. Efficiency vs Load Current
5.036
5.035
5.034
5.033
5.032
5.031
5.03
100
90
80
70
60
50
40
30
20
10
0
VIN = 8 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
FPWM, 8 VIN
FPWM, 12 VIN
FPWM, 24 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
0
0.1
0.2
0.3
IOUT (A)
0.4
0.5
0.6
0.0001
0.001
0.01
IOUT (A)
0.1
1
D004
D012
fSW = 1.1 MHz
VOUT = 5 V
FPWM version
fSW = 2.1 MHz
VOUT = 5 V
图 6. Load Regulation
图 5. Efficiency vs Load Current
版权 © 2017–2018, Texas Instruments Incorporated
7
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
Typical Characteristics (接下页)
VIN = 12 V, fSW = 1.1 MHz, TA = 25°C, unless otherwise specified.
5.036
5.5
5
5.035
5.034
5.033
5.032
4.5
4
IOUT = 0 mA
IOUT = 100 mA
IOUT = 300 mA
IOUT = 600 mA
IOUT = 0 mA
3.5
3
IOUT = 100 mA
IOUT = 300 mA
IOUT = 600 mA
5.031
5.03
5
10
15
20
25
30
35
40
4
4.5
5
5.5
VIN (V)
6
6.5
7
VIN (V)
D005
D006
fSW = 1.1 MHz
VOUT = 5 V
FPWM version
fSW = 1.1 MHz
VOUT = 5 V
FPWM version
图 7. Line Regulation
图 8. Dropout
80
75
70
65
3.9
3.8
3.7
3.6
3.5
3.4
Rising
Falling
60
-50
3.3
-50
0
50
100
150
0
50
100
150
Temperature (èC)
Temperature (èC)
D007
D008
VFB = 1.1 V
PFM verison
图 9. IQ vs Temperature
图 10. VIN UVLO vs Temperature
1.0002
1
1.2
1.1
1
HS
LS
0.9998
0.9996
0.9994
0.9992
0.999
0.9988
0.9
0.8
0.7
0.9986
-50
0
50
100
150
-50
0
50
100
150
Temperature (èC)
Temperature (èC)
D009
D010
图 11. Reference Voltage vs Temperature
图 12. HS and LS Current Limit vs Temperature
8
版权 © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
8 Detailed Description
8.1 Overview
The TPS560430 regulator is an easy to use synchronous step-down DC-DC converter operating from 4-V to 36-
V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution size. The
family has multiple versions applicable to various applications, refer to Device Comparison Table for detailed
information.
The TPS560430 employs fixed-frequency peak-current mode control. The device enters PFM Mode at light load
to achieve high efficiency for PFM version. And FPWM version is provided to achieve low output voltage ripple,
tight output voltage regulation, and constant switching frequency at light load. The device is internally
compensated, which reduces design time, and requires few external components.
Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for
a wide range of applications. Protection features include thermal shutdown, VIN under-voltage lockout, cycle-by-
cycle current limit, and hiccup mode short-circuit protection.
The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.
8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
CB
Precision
Enable
HSI Sense
Internal
SS
EA
REF
RC
CC
TSD
UVLO
FB
PWM CONTROL LOGIC
PFM
SW
Detector
Slope
Comp
Ton_min/Toff_min
Detector
Freq
Foldback
HICCUP
Detector
Zero
Cross
LSI Sense
Oscillator
FB
GND
Copyright © 2017, Texas Instruments Incorporated
版权 © 2017–2018, Texas Instruments Incorporated
9
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operation description of the TPS560430 will refer to the Functional Block Diagram and to the
waveforms in 图 13. TPS560430 is a step-down synchronous buck regulator with integrated high-side (HS) and
low-side (LS) switches (synchronous rectifier). The TPS560430 supplies a regulated output voltage by turning on
the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage
swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT) / L. When the
HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time.
Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control parameter of a
buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an idea Buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
TSW
iL
ILPK
IOUT
DiL
t
0
图 13. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS560430 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light-load
condition, the TPS560430 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for
low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).
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Feature Description (接下页)
8.3.2 Adjustable Output Voltage
A precision 1.0-V reference voltage, VREF, is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It
is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor RFBB for the desired divider current and use 器件支持 to calculate top-side resistor RFBT
.
RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used
if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT reduces efficiency at very light
load. Less static current goes through a larger RFBT and might be more desirable when light-load efficiency is
critical. But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to
noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and
temperature variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
图 14. Output Voltage Setting
VOUT - VREF
RFBT
=
× RFBB
VREF
(1)
8.3.3 Enable
The voltage on the EN pin controls the ON or OFF operation of TPS560430. A voltage of less than 0.95 V shuts
down the device, while a voltage of more than 1.36 V is required to start the regulator. The EN pin is an input
and cannot be left open or floating. The simplest way to enable the operation of the TPS560430 is to connect the
EN to VIN. This allows self-start-up of the TPS560430 when VIN is within the operating range.
Many applications will benefit from the employment of an enable divider RENT and RENB (图 15) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection. Kindly note that, the EN pin voltage should never be higher than VIN + 0.3 V. It is not
recommended to apply EN voltage when VIN is 0 V.
VIN
RENT
EN
RENB
图 15. System UVLO by Enable Divider
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Feature Description (接下页)
8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 60
ns in the TPS560430. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off.
TOFF_MIN is typically 100 ns. In CCM operation, TON_MIN and TOFF_MIN limit the voltage conversion range without
switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is
DMIN = TON_MIN X fSW
(2)
(3)
The maximum duty cycle without frequency foldback allowed is
DMAX = 1 - TOFF_MIN X fSW
Given a required output voltage, the maximum VIN without frequency foldback can be found by
VOUT
VIN_MAX
=
fSW × TON_MIN
(4)
(5)
The minimum VIN without frequency foldback can be calculated by
VOUT
VIN_MIN
=
1- fSW × TOFF_MIN
In the TPS560430, a frequency foldback scheme is employed once the TON_MIN or TOFF_MIN is triggered, which
may extend the maximum duty cycle or lower the minimum duty cycle.
The on-time decreases while VIN voltage increases. Once the on-time decreases to TON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to 公式 2.
The frequency foldback scheme also works once larger duty cycle is needed under low VIN condition. The
frequency decreases once the device hits its TOFF_MIN, which extends the maximum duty cycle according to 公式
3. In such condition, the frequency can be as low as about 133 kHz minimum. Wide range of frequency foldback
allows the TPS560430 output voltage stay in regulation with a much lower supply voltage VIN, which leads to a
lower effective drop-out.
With frequency foldback, VIN_MAX is raised, and VIN_MIN is lowered by decreased fSW
.
VOUT = 1 V
fSW = 1.1 MHz
VOUT = 5 V
fSW = 1.1 MHz
图 16. Frequency Foldback at TON_MIN
图 17. Frequency Foldback at TOFF_MIN
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Feature Description (接下页)
8.3.5 Bootstrap Voltage
The TPS560430 provides an integrated bootstrap voltage regulator. A small capacitor between the CB and SW
pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the bootstrap capacitor is
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is
recommended for stable performance over temperature and voltage.
8.3.6 Over Current and Short Circuit Protection
The TPS560430 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating.
High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer
to Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum
peak current threshold IHS_LIMIT which is constant.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until
the inductor current ramps below the ILS_LIMIT. Then the LS switch will be turned OFF and the HS switch will be
turned on after a dead time. This is somewhat different to the more typical peak current limit, and results in 公式
6 for the maximum load current.
V
- VOUT
VOUT
VIN
(
)
×
IN
IOUT_MAX = ILS
+
2 × fSW × L
(6)
If the feedback voltage is lower than 40% of the VREF, the current of the LS switch triggers ILS_LIMIT for 256
consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the regulator shuts down and
keeps off for a period of hiccup, THICCUP (135 ms typical), before the TPS560430 tries to start again. If over-
current or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode
reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to
the device.
For FPWM version, the inductor current is allowed to go negative. Should this current exceed the LS negative
current limit ILS_NEG, the LS switch is turned off and HS switch is turned on immediately. This is used to protect
the LS switch from excessive negative current.
8.3.7 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the TPS560430 and the input power
supply. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled
or powered up. The typical soft-start time is 1.8 ms.
The TPS560430 also employs over-current protection blanking time TOCP_BLK (33 ms typical) at the beginning of
power-up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the inrush
current is large enough to trigger the current-limit protection, which may make the device entering into hiccup
mode. The device tries to restart after the hiccup period, then hit current-limit and enter into hiccup mode again,
so VOUT cannot ramp up to the setting voltage ever. By introducing OCP blanking feature, the hiccup protection
function is disabled during TOCP_BLK, and TPS560430 charges the VOUT with its maximum limited current, which
maximizes the output current capacity during this period. Kindly note that, the peak current limit (IHS_LIMIT) and
valley current limit (ILS_LIMIT) protection function are still available during TOCP_BLK, so there is no concern of
inductor current running away.
8.3.8 Thermal Shutdown
The TPS560430 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C. Both HS and LS FETs stop switching in thermal shutdown. Once the die temperature falls below
158°C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS560430. When VEN is below 0.95 V, the device is
in shutdown mode. The TPS560430 also employs VIN under voltage lock out protection (UVLO). If VIN voltage is
below its UVLO threshold 3.25 V, the regulator is turned off.
8.4.2 Active Mode
The TPS560430 is in Active Mode when both VEN and VIN are above their respective operating threshold. The
simplest way to enable the TPS560430 is to connect the EN pin to VIN pin. This allows self-startup when the
input voltage is in the operating range: 4.0 V to 36 V. Please refer to Enable section for details on setting these
operating levels.
In Active Mode, depending on the load current, the TPS560430 will be in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple (for both PFM and FPWM versions).
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation (only for PFM version).
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM version).
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM version).
8.4.3 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the TPS560430 when the load current is higher
than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output
voltage ripple is at a minimum in this mode and the maximum output current of 600 mA can be supplied by the
TPS560430.
8.4.4 Light-Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
TPS560430 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM).
In DCM operation, the LS switch is turned off when the inductor current drops to ILS_ZC (20 mA typical) to improve
efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation
at light load.
At even lighter current load, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum HS switch ON time tON_MIN or the minimum peak inductor current IPEAK_MIN
(150mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode, switching
frequency is decreased by the control loop to maintain output voltage regulation when load current reduces.
Switching loss is further reduced in PFM operation due to less frequent switching actions.
8.4.5 Light-Load Operation (FPWM Version)
For FPWM version, TPS560430 is locked in PWM mode at full load range. This operation is maintained, even in
no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced
light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS560430 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 600 mA. The following design procedure can be used to select
components for the TPS560430. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components. Please go to ti.com for more details.
9.2 Typical Application
The TPS560430 only requires a few external components to convert from a wide voltage range supply to a fixed
output voltage. 图 18 shows a basic schematic.
VIN 12 V
CB
VIN
CBOOT
0.1 µF
CIN
2.2 µF
L
10 µH
VOUT 5 V
SW
FB
EN
RFBT
88.7 kΩ
COUT
22 µF
GND
RFBB
22.1 kΩ
Copyright © 2017, Texas Instruments Incorporated
图 18. Application Circuit
The external components have to fulfill the needs of the application, but also the stability criteria of the device's
control loop. 表 1 can be used to simplify the output filter component selection.
表 1. L and COUT Typical Values
(1)
fSW (MHz)
VOUT (V)
L (µH)
12
COUT (µF)
RFBT (kΩ)
51
RFBB (kΩ)
22.1
3.3
5
22 µF / 10 V
22 µF / 10 V
10 µF / 25 V
10 µF / 10 V
10 µF / 10 V
10 µF / 25 V
1.1
18
88.7
243
22.1
12
3.3
5
33
22.1
6.8
10
51
22.1
2.1
88.7
243
22.1
12
18
22.1
(1) Ceramic capacitor is used in this table.
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9.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in 表 2 as the input parameters.
表 2. Design Example Parameters
PARAMETER
VALUE
Input voltage, VIN
12 V typical, range from 6 V to 36 V
Output voltage, VOUT
5 V ±3%
600 mA
30 mA
5%
Maximum output current, IOUT_MAX
Minimum output current, IOUT_MIN
Output overshoot/ undershoot (0mA to 600mA )
Output voltage ripple
0.5%
Operating frequency
1.1 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS560430 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.2.2 Output Voltage Set-Point
The output voltage of the TPS560430 device is externally adjustable using a resistor divider network. The divider
network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. 公式 7 is used to
determine the output voltage of the converter:
VOUT - VREF
RFBT
=
× RFBB
VREF
(7)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1.0 V, the
RFBT value can then be calculated using 公式 7. The formula yields to a value 88.4 kΩ, a standard value of 88.7
kΩ is selected.
9.2.2.3 Switching Frequency
The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in
smaller solution size and lower component cost. However higher switching frequency brings more switching loss,
which makes the solution less efficient and produce more heat. The switching frequency is also limited by the
minimum on-time of the integrated power switch, the input voltage, the output voltage and the frequency shift
limitation as mentioned in Minimum ON-Time, Minimum OFF-Time and Frequency Foldback section. For this
example, a switching frequency of 1.1 MHz is selected.
9.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use 公式 9
to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of inductor
ripple current relative to the maximum output current of the device. A reasonable value of KIND should be 20% to
60%. During an instantaneous over current operation event, the RMS and peak inductor current can be high. The
inductor current rating should be a bit higher than current limit.
VOUT
×
V
- VOUT
IN_MAX
(
)
ûiL =
VIN_MAX × L × fSW
(8)
VIN_MAX - VOUT
VOUT
LMIN
=
×
IOUT × K IND
VIN_MAX × fSW
(9)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger
inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current
mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple
improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 16.3 µH. Choose the
nearest standard 18-µH ferrite inductor with a capability of 1-A RMS current and 1.5-A saturation current.
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9.2.2.5 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output
capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with care
since it directly affects the steady state output voltage ripple, loop stability, output voltage overshoot and
undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One is
caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output
capacitors:
ûVOUT_ESR = ûiL × ESR = KIND ×IOUT × ESR
(10)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
ûiL
K IND ×IOUT
ûVOUT_C
=
=
8×fSW × COUT 8×fSW × COUT
(11)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a large load step happens, output
capacitors provide the required charge before the inductor current can slew up to the appropriate level. The
regulator’s control loop usually needs 8 or more clock cycles to regulate the inductor current equal to the new
load level. The output capacitance must be large enough to supply the current difference for 8 clock cycles to
maintain the output voltage within the specified range. 公式 12 shows the minimum output capacitance needed
for specified VOUT overshoot and undershoot.
8 × IOH -IOL
(
)
1
2
COUT
>
×
fSW × ûVOUT_SHOOT
(12)
where
•
•
•
•
KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
IOL = Low level output current during load transient
IOH = High level output current during load transient
VOUT_SHOOT = Target output voltage overshoot or undershoot
For this design example, the target output ripple is 30 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30 mV, and
chose KIND = 0.4. 公式 10 yields ESR no larger than 125 mΩ and 公式 11 yields COUT no smaller than 0.91 µF.
For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV. The COUT
can be calculated to be no smaller than 8.3 µF by 公式 12. In summary, the most stringent criteria for the output
capacitor is 8.3 µF. Consider of derating, one 22-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR is used.
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9.2.2.6 Input Capacitor Selection
The TPS560430 device requires high frequency input decoupling capacitor(s). The typical recommended value
for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type X5R or X7R with
sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input voltage.
To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is
recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is used for the input
decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the current rating is 1
A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the
device pins.
9.2.2.7 Bootstrap Capacitor
Every TPS560430 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.1 µF
and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.8 Under Voltage Lockout Set-Point
The system under voltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO
level.
RENT + RENB
VIN_RISING = VENH
×
RENB
(13)
The EN rising threshold (VENH) for TPS560430 is set to be 1.23 V (typical). Choose the value of RENB to be 200
kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can
be calculated using 公式 14:
≈
’
÷
◊
VIN_RISING
RENT
=
-1 × R
∆
∆
«
÷
ENB
VENH
(14)
The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling
UVLO threshold, equals 5.3 V, can be calculated by 公式 15, where EN hysteresis voltage, VEN_HYS, is 0.13 V
(typical).
RENT + RENB
VIN_FALLING = V
- VEN_HYS ×
(
)
ENH
RENB
(15)
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW = 1.1 MHz, L = 18 µH, COUT = 22 µF, TA
= 25 °C
VSW [5V/div]
VSW [5V/div]
VOUT(AC) [10mV/div]
iL [500mA/div]
VOUT(AC) [10mV/div]
iL [500mA/div]
Time [2ꢀs/div]
Time [2ꢀs/div]
IOUT = 0 mA
FPWM Version
IOUT = 600 mA
FPWM Version
图 19. Ripple at No Load
图 20. Ripple at Full Load
VEN [2V/div]
VIN [5V/div]
VOUT [2V/div]
VOUT [2V/div]
iL [500mA/div]
iL [500mA/div]
Time [1ms/div]
Time [1ms/div]
IOUT = 600 mA
FPWM Version
IOUT = 600 mA
FPWM Version
图 21. Start Up by VIN
图 22. Start-Up by EN
VIN [10V/div]
VOUT(AC) [100mV/div]
VOUT(AC) [50mV/div]
iOUT [200mA/div]
iL [500mA/div]
Time [10ꢀs/div]
Time [200ꢀs/div]
IOUT = 0 to 600
mA, 100 mA / µs
FPWM Version
VIN = 12 V to 30 V,
0.18 V / µs
IOUT = 600 mA
FPWM Version
图 23. Load Transient
图 24. Line Transient
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Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW = 1.1 MHz, L = 18 µH, COUT = 22 µF, TA
= 25 °C
VOUT [2V/div]
iL [500mA/div]
VOUT [2V/div]
iL [500mA/div]
Time [100ms/div]
Time [100ms/div]
IOUT = 0 mA to
short
FPWM Version
IOUT = short to 0
mA
FPWM Version
图 25. Short Protection
图 26. Short Recovery
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10 Power Supply Recommendations
The TPS560430 is designed to operate from an input voltage supply range between 4.0 V and 36 V. This input
supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the TPS560430 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is located more than a few inches from the TPS560430 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF
or 22-µF electrolytic capacitor is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and GND pins. Grounding for
both the input and output capacitors should consist of localized top side planes that connect to the GND pin.
2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to
the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT
sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
4. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
5. Provide adequate device heat-sinking. GND, VIN and SW pins provide the main heat dissipation path, make
the GND, VIN and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top
side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these
thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area
is used for heat-sinking to keep the junction temperature below 125 °C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
ceramic bypass capacitor(s) as close as possible to the VIN and GND pins is the key to EMI reduction.
The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current
conduction path to minimize parasitic resistance. The output capacitors should be placed close to the VOUT end
of the inductor and closely grounded to GND pin.
11.1.2 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider close
to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace
length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from
VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
22
版权 © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
11.2 Layout Example
VOUT
Output Bypass
Capacitor
Output
Inductor
BOOT
Capacitor
GND
SW
CB
GND
FB
VIN
EN
VIN
Input Bypass
Capacitor
Output Voltage
Set Resistor
GND
VIA (Connect to GND Plane)
图 27. Layout
版权 © 2017–2018, Texas Instruments Incorporated
23
TPS560430
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 TPS560430 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
《AN-1149 开关电源布局指南》
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
24
版权 © 2017–2018, Texas Instruments Incorporated
TPS560430
www.ti.com.cn
ZHCSI48B –SEPTEMBER 2017–REVISED JUNE 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS560430X3FDBVR
TPS560430X3FDBVT
TPS560430XDBVR
TPS560430XDBVT
TPS560430XFDBVR
TPS560430XFDBVT
TPS560430YDBVR
TPS560430YDBVT
TPS560430YFDBVR
TPS560430YFDBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
N3XF
N3XF
NAXS
NAXS
NAXF
NAXF
NAYS
NAYS
NAYF
NAYF
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
RoHS & Green
XTPS560430X3FDBVR
XTPS560430XFDBVR
OBSOLETE
OBSOLETE
SOT-23
SOT-23
DBV
DBV
6
6
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS560430 :
Automotive : TPS560430-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS560430X3FDBVR
TPS560430X3FDBVT
TPS560430XDBVR
TPS560430XDBVT
TPS560430XFDBVR
TPS560430XFDBVT
TPS560430YDBVR
TPS560430YDBVT
TPS560430YFDBVR
TPS560430YFDBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS560430X3FDBVR
TPS560430X3FDBVT
TPS560430XDBVR
TPS560430XDBVT
TPS560430XFDBVR
TPS560430XFDBVT
TPS560430YDBVR
TPS560430YDBVT
TPS560430YFDBVR
TPS560430YFDBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS56100PWPR
1.4A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO28, GREEN, PLASTIC, HTSSOP-28
TI
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