TPS56121_14 [TI]
4.5-V to 14-V Input High-Current Synchronous Buck Converter;
| 型号： | TPS56121_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5-V to 14-V Input High-Current Synchronous Buck Converter |
| 文件： | 总22页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS56121
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SLUSAH4 –MARCH 2011
4.5-V to 14-V Input High-Current Synchronous Buck Converter
Check for Samples: TPS56121
1
FEATURES
DESCRIPTION
2
•
•
•
•
4.5-V to 14-V Input Voltage Range
Incorporates Power Block Technology
Up to 15-A Output Current
TPS56121 is
a high-efficiency and high-current
synchronous buck converter designed to operate
from a supply between 4.5 V and 14 V. The device is
capable of producing an output voltage as low as
0.6 V at loads up to 15 A. Integrated NexFET™
Power MOSFETs provide a small foot print and ease
of use.
Fixed Frequency Options of 300 kHz, 500 kHz
and 1 MHz
•
High-Side and Low-Side MOSFET RDS(on)
Sensing
The device implements a voltage-mode control with
voltage feed-forward compensation that responds
instantly to input voltage change.
•
•
•
•
•
•
Programmable Soft-Start
600-mV Reference Voltage with 1% Accuracy
Voltage Mode Control with Feed-Forward
Supports Pre-Biased Output
TPS56121 is available in a thermally enhanced
22-pin PQFN (DQP) PowerPAD™ package.
Thermal Shutdown
The device offers design flexibility with a variety of
user programmable functions, including soft-start,
overcurrent protection (OCP) levels, and loop
compensation. OCP levels are programmed by a
single external resistor connected from the ILIM pin to
the circuit ground. During the initial power-on
sequence, the device enters a calibration cycle,
measures the voltage at the ILIM pin, and sets an
internal OCP voltage level. During operation, the
programmed OCP voltage level is compared to the
voltage drop across the low-side FET when it is on to
determine whether there is an overcurrent condition.
It then enters a shutdown/restart cycle until the fault
is removed.
22-Pin 5 mm x 6 mm PQFN PowerPAD™
Package
APPLICATIONS
•
Point-of-Load (POL) Power Modules
•
High Density DC-DC Converters for Telecom
and Networking Applications
SIMPLIFIED APPLICATION
TPS56121
VOUT
FB
VIN
BOOT
SW
VIN
COMP
PGD
EN/SS
VDD
VOUT
ILIM
BP
VIN
SD
GND
UDG-11047
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, NexFET are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS56121
SLUSAH4 –MARCH 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
MINIMUM QUANTITY
ORDERABLE
NUMBER
TA
PINS
TRANSPORT MEDIA
250
TPS56121DQPT
TPS56121DQPR
-40°C to 150°C
Plastic QFN (DQP)
22
Tape-and-reel
2500
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
–3
TYP
16.5
25
VDD, VIN
SW
V
SW (< 100 ns pulse width, 10 µJ)
-5
Voltage Range
BOOT
–0.3
–0.3
–0.3
30
7
BOOT-SW (differential from BOOT to SW)
COMP, PGOOD, FB, BP, EN/SS, ILIM
7
(HBM) QSS 009-105 (JESD22-A114A)
Electrostatic discharge
2
kV
(CBM) QSS 009-147 (JESD22-C101B.01)
1.5
Junction, TJ
Temperature
–40
–55
150 °C
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
THERMAL INFORMATION
TPS56121
THERMAL METRIC(1)
PQFN
22 PINS
34.6
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
ψJT
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.9
0.6
°C/W
ψJB
5.0
θJCbot
0.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
TYP MAX UNIT
14
125 °C
VDD VIN Input voltage
TJ Operating junction temperature
V
–40
2
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ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
VOLTAGE REFERENCE
TJ = 25°C, 4.5 V ≤ VVDD ≤ 14 V
597
594
600
600
603
VFB
FB input voltage
mV
–40°C ≤ TJ ≤ 125°C,
4.5 V ≤ VVDD ≤ 14 V
606
INPUT SUPPLY
VVDD
Input supply voltage range
4.5
14
120
5.0
V
IVDDSD
IVDDQ
VUVLO
Shutdown supply current
Quiescent, non-switching
UVLO ON Voltage
VEN/SS = 0.2 V
80
µA
mA
V
Let EN/SS float, VFB = 1 V
2.5
4.0
4.3
VUVLO(HYS) UVLO hysteresis
500
700
mV
ENABLE/SOFT-START
VIH
VIL
ISS
High-level input voltage, EN/SS
0.55
0.27
8
0.70
0.30
10
1.00
0.33
12
V
V
Low-level input voltage, EN/SS
Soft-start source current
µA
Soft-start voltage level – Start of
ramp
VSS
0.4
0.8
1.3
V
BP REGULATOR
VBP
Output voltage
IBP = 10 mA
6.2
6.5
70
6.8
V
Regulator dropout voltage, VVDD
VBP
–
VDO
IBP = 25 mA, VVDD = 4.5 V
125
mV
OSCILLATOR
RCOMP = 40.2 kΩ, 4.5 V ≤ VVDD ≤ 14 V
RCOMP = open, 4.5 V ≤ VVDD ≤ 14 V
RCOMP = 13.3 kΩ, 4.5 V ≤ VVDD ≤ 14 V
270
450
300
500
330
550
1.1
kHz
kHz
MHz
V
fSW
Switching Frequency
Ramp amplitude
0.8
0.95
(1)
VRAMP
VVDD/6.6
VVDD/6 VVDD/5.4
PWM
fsw = 300 kHz, VFB = 0 V,
4.5 V ≤ VVDD ≤ 14 V
93%
90%
85%
fsw = 500 kHz, VFB = 0 V,
4.5 V ≤ VVDD ≤ 14 V
(1)
DMAX
Maximum duty cycle
fsw = 1 MHz, VFB = 0 V,
4.5 V ≤ VVDD ≤ 14 V
(1)
tON(min)
Minimum controllable pulse width
100
ns
ERROR AMPLIFIER
(1)
GBWP
Gain bandwidth product
10
60
24
MHz
dB
(1)
AOL
Open loop gain
Input bias current (current out of FB
pin)
IIB
VFB = 0.6 V
75
nA
IEAOP
IEAOM
POWER GOOD
Output source current
VFB = 0 V
VFB = 1 V
1.5
1.5
mA
mA
Output sink current
Feedback upper voltage limit for
PGOOD
VOV
VUV
655
500
675
525
700
550
mV
Feedback lower voltage limit for
PGOOD
VPGD-HYST
RPGD
PGOOD hysteresis voltage at FB
PGOOD pull down resistance
30
30
45
70
VFB = 0 V, IFB = 5 mA
Ω
550 mV < VFB < 655 mV,
VPGOOD = 5 V
IPGDLK
PGOOD leakage current
10
20
µA
(1) Ensured by design. Not production tested
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ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OUTPUT STAGE
RHI
High-side device resistance
Low side device resistance
TJ = 25°C, (VBOOT – VSW) = 5.5 V
TJ = 25°C
4.5
1.9
6.5
2.7
mΩ
RLO
OVERCURRENT PROTECTION (OCP)
Minimum pulse time during short
(2)
tPSSC(min)
circuit
250
150
ns
Switch leading-edge blanking pulse
time (high-side detection)
(2)
tBLNKH
IOCH
IILIM
OC threshold for high-side FET
ILIM current source
TJ = 25°C, (VBOOT – VSW) = 5.5 V
TJ = 25°C
27
12
34
39
A
10.0
µA
Programmable OC range for low side
FET
(2)
VOCLPRO
tOFF
TJ = 25°C
100
mV
OC retry cycles on EN/SS pin
4
Cycle
BOOT DIODE
VDFWD
Bootstrap diode forward voltage
IBOOT = 5 mA
0.8
V
THERMAL SHUTDOWN
(2)
TJSD
Junction shutdown temperature
Hysteresis
145
20
ºC
ºC
(2)
TJSDH
(2) Ensured by design. Not production tested
4
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DEVICE INFORMATION
DQP PACKAGE
PQFN-22
(TOP VIEW)
1
2
22
21
20
19
18
17
16
15
14
13
12
COMP
FB
PGD
EN/SS
VDD
BP
3
GND
BOOT
GND
SW
4
5
ILIM
VIN
GND
(Thermal Pad)
6
7
SW
VIN
8
SW
VIN
9
SW
VIN
10
11
SW
VIN
SW
VIN
Note: The thermal pad is also an electrical ground connection.
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME
NO.
Gate drive voltage for the high-side FET. A 100-nF capacitor (typical) must be connected between this pin
and the SW pin. To reduce a voltage spike at SW, a BOOT resistance between 5 Ω to 10 Ω may be placed
in series with the BOOT capacitor to slow down start-up of the high-side FET.
BOOT
4
O
O
O
Output bypass for the internal regulator. Connect a low-ESR bypass ceramic capacitor of 1 µF or greater
from this pin to GND.
BP
19
1
Output of the error amplifier and connection node for loop feedback components. Optionally, a 40.2 kΩ
resistor from this pin to GND sets switching frequency to 300KHz instead of the default value of 500KHz;
while a 13.3 kΩ resistor from this pin to GND sets switching frequency to 1 MHz.
COMP
Logic-level input starts or stops the controller via an external user command. Allowing this pin to float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second
non-inverting input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is
controlled by the internal level shifted voltage ramp until that voltage reaches the internal reference voltage
of 600 mV. The voltage ramp of this pin reaches 1.4 V (typical).
EN/SS
21
2
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage.
FB
I
3
5
–
GND
Ground reference for the device
Ground reference for the device. This is also the thermal pad used to conduct heat from the device. This
connection serves two purposes. The first is to provide an electrical ground connection for the device. The
second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied
externally to a ground plane.
Thermal
Pad
GND
–
ILIM
18
22
6
I
A resistor connected from this pin to GND sets the overcurrent threshold for the device (the low-side FET).
Open drain power good output.
PGD
O
7
8
Sense line for the adaptive anti-cross conduction circuitry. Acts as the common connection for the flying
high-side FET driver.
SW
I
I
9
10
11
Power input to the controller. A low-ESR bypass ceramic capacitor of 1 µF should be connected from this
pin close to GND.
VDD
20
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PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME
NO.
12
13
14
15
16
17
VIN
I
Power input to the high-side FET.
FUNCTIONAL BLOCK DIAGRAM
+
10 mA
0.6 VREF + 12.5%
FB
Soft Start
SS
BP
SS
EN/SS
+
+
SD
0.6 VREF –12.5%
BOOT
Fault
Clock
Controller
OC
6-V
VDD
BP
Regulator
References
BP
0.6 VREF
SD
VIN
Calibration
Circuit
COMP
Clock
Anti-Cross
Conduction
and
Oscillator
PWM
Logic
SW
Pre-Bias
Circuit
BP
FB
PWM
+
+
10 mA
0.6 VREF
SS
Thermal
750 kW
Shutdown
OC
ILIM
PGOOD
Threshold
Setting
Fault Controller
TPS56121
OC
PAD
GND
UDG-11050
6
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TYPICAL CHARACTERISTICS
602
601
600
599
598
597
596
595
594
306
fSW = 300 kHz
305
304
303
302
301
300
VVDD = 4.5 V
VVDD = 12 V
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 1. Reference Voltage vs. Junction Temperature
Figure 2. Switching Frequency vs. Junction Temperature
(300 kHz)
504
975
fSW = 500 kHz
fSW = 1 MHz
502
500
498
496
494
492
490
488
950
925
900
875
VVDD = 4.5 V
VVDD = 12 V
VVDD = 4.5 V
VVDD = 12 V
850
−40 −25 −10
−40 −25 −10
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 3. Switching Frequency vs. Junction Temperature
(500 kHz)
Figure 4. Switching Frequency vs. Junction Temperature
(1 MHz)
725
700
675
650
625
600
292.5
292.0
291.5
291.0
290.5
290.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 5. EN Pin High-Level Threshold Voltage vs.
Junction Temperature
Figure 6. EN Pin Low-Level Threshold Voltage vs.
Junction Temperature
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TYPICAL CHARACTERISTICS (continued)
82
80
78
76
74
72
2.44
2.43
2.42
2.41
2.40
2.39
VVDD = 12 V
VVDD = 12 V
70
2.38
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7. Shutdown Current vs. Junction Temperature
Figure 8. Quiescent Current vs. Junction Temperature
10.5
975
950
925
900
875
850
825
800
775
750
725
10.4
10.3
10.2
10.1
10.0
9.9
9.8
9.7
9.6
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 9. Soft-Start Source vs. Junction Temperature
Figure 10. Soft-Start Voltage Level vs. Junction
Temperature
6.0
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
5.5
5.0
4.5
4.0
3.5
VVDD = 4.5 V
VVDD = 12 V
VVDD = 4.5 V
VVDD = 12 V
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 11. High-Side On Resistance vs. Junction
Temperature
Figure 12. Low-Side On Resistance vs. Junction
Temperature
8
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TYPICAL CHARACTERISTICS
The efficiency curve shown in Figure 15 is measured with a 0.5-µH output inductor and a maximum DCR of 0.75 mΩ.
The efficiency curve shown in Figure 16 is measured with a 0.3-µH output inductor and a maximum DCR of 0.54 mΩ.
The power derating curves shown in Figure 17 and Figure 18 are measured on a 4" × 3.25", 0.062" thick FR4 board
with 6 layers and 1 oz. copper.
40
38
36
34
32
30
28
26
750
700
650
600
550
500
450
VVDD = 4.5 V
VVDD = 12 V
VOV
VUV
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 13. High-Side Overcurrent Threshold vs. Junction
Temperature
Figure 14. Power Good Threshold Voltage vs. Junction
Temperature
100
90
100
95
90
80
85
70
VOUT = 0.8 V
80
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 0.8 V
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
fSW = 500 kHz
VVIN = 5 V
TA = 25°C
60
50
fSW = 500 kHz
VVIN = 12 V
TA = 25°C
75
VOUT = 2.5 V
70
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Load Current (A)
Load Current (A)
Figure 15. Efficiency vs. Load Current (VVIN = 12 V)
Figure 16. Efficiency vs. Load Current (VVIN = 5 V)
16
16
14
12
10
8
14
12
10
8
VOUT = 0.8 V
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
6
6
VOUT = 0.8 V
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.8 V
4
4
2
2
VVIN = 12 V
VOUT = 2.5 V
VVIN = 5 V
100 110
0
0
0
10 20 30 40 50 60 70 80 90 100 110
Ambient Temperature (°C)
0
20
40
60
80
Ambient Temperature (°C)
Figure 17. Output Current vs. Ambient Temperature
(VVIN = 12 V)
Figure 18. Output Current vs. Ambient Temperature
(VVIN = 5 V)
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APPLICATION INFORMATION
Introduction
The TPS56121 is a 15-A high performance synchronous buck converter with two integrated N-channel
NexFET™ power MOSFETs. The device implements a voltage-mode control with voltage feed-forward
compensation that responds instantly to input voltage change. Pre-bias capability eliminates concerns about
damaging sensitive loads.
Voltage Reference
The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power
supply.
2.0
V
Calibration
1.6
EN/SS
Time(1.9 ms)
1.3 V
1.2
0.8
0.4
0
0.7 V
V
SS_INT
Time (ms)
Figure 19. Startup Sequence and Timing
Enable Functionality, Startup Sequence and Timing
After input power is applied, an internal 40-μA current source begins to charge the soft-start capacitor connected
from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal BP
regulator followed by a calibration. Total calibration time is approximately 1.9 ms. See Figure 19. During the
calibration, the device performs the following two functions.
COMP Pin Impedance Sensing
The device samples the impedance at the COMP pin and determines the appropriate operating switching
frequency. If there is no resistor connected from the COMP pin to GND, the switching frequency is set to the
default value of 500 kHz. If a resistor of 40.2 kΩ ± 10% is connected from the COMP pin to GND, the switching
frequency is set to 300 kHz. Alternatively, if a resistor of 13.3 K ± 10% is connected from the COMP pin to GND,
the switching frequency is set to 1 MHz.
After a 1.1-ms time period, the COMP pin is then brought low for 0.8 ms. This ensures that the feedback loop is
preconditioned at startup and no sudden output rise occurs at the output of the converter when it is allowed to
start switching.
Overcurrent Protection (OCP) setting
The device sources 10 μA (typical) to the resistor connected from the ILIM pin to GND. The voltage developed
across that resistor multiplied by a factor of 2 is then sampled and latched off internally as the OCP trip level for
the low-side FET until one cycles the input or toggles the EN/SS.
The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
10
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time once calibration is complete. The discharging current is from an internal current source of 140 μA and it
pulls the voltage down to 0.4 V. It then initiates the soft-start by charging up the capacitor using an internal
current source of 10 μA. The resulting voltage ramp on this pin is used as a second non-inverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, the actual soft-start does not take place
until the voltage at this pin reaches 800 mV.
If the EN/SS pin is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270
mV to ensure that the chip is in shutdown mode.
Soft-Start Time
The soft-start time of the TPS56121 is user programmable by selecting a single capacitor. The EN/SS pin
sources 10 μA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
10 μA to charge the capacitor through a 600 mV range. There is some initial lag due to calibration and an offset
(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.
The soft-start is accomplished in a closed-loop, meaning that the error amplifier controls the output voltage at all
times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start
schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and
the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier
controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset
voltage plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
The capacitance required for a given soft-start ramp time for the output voltage is calculated in Equation 1.
æ
ç
è
ö
÷
ø
I
SS
C
=
´ t
SS
SS
V
FB
where
•
•
•
•
CSS is the required capacitance on the EN/SS pin (nF)
ISS is the soft-start source current (10 μA)
VFB is the feedback reference voltage (0.6 V)
tSS is the desired soft-start ramp time (ms)
(1)
Oscillator
The oscillator frequency is internally fixed at 500 KHz if there is no resistor connected from COMP pin to GND.
Optionally, a 40.2-kΩ resistor from the COMP pin to GND sets the frequency to 300 KHz. Alternatively, a 13.3-kΩ
resistor from COMP pin GND sets the frequency to 1 MHz.
Overcurrent Protection (OCP)
Programmable OCP level at ILIM is from 6 mV to 50 mV. With a scale factor of 2, the actual OC trip point across
the low-side FET is in the range of 12 mV to 100 mV.
If the voltage drop across ROCSET reaches 300 mV during calibration (No ROCSET resistor included), it disables
OC protection. Once disabled, there is no low-side or high-side current sensing.
OCP level for the high-side FET is fixed at 34 A (typical). The high-side OCP provides pulse-by-pulse current
limiting.
OCP sensing for the low-side FET is a true inductor valley current detection, using sample and hold. Equation 2
can be used to calculate ROCSET
.
æ
ç
è
ö
÷
ø
I
æ
ç
è
ö
÷
ø
P-P
R
= I
-
´95 + 500
OCSET
OUT max
(
)
2
where
•
•
•
IP-P is the peak-to-peak inductor current (A)
IOUT(max) is the trip point for OCP (A)
ROC(set) is the resistor used for setting the OCP level (Ω)
(2)
11
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An overcurrent (OC) condition is detected by sensing voltage drop across the low-side FET and across the
high-side FET. If the voltage drop across either FET exceeds OC threshold, a count increments one count. If no
OC condition is detected on either FET, the fault counter decrements by one counter. If three OC pulses are
summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode is
defined as four dummy soft-start timeouts followed by a real one if overcurrent condition is encountered during
normal operation; or five dummy soft-start timeouts followed by a real one if overcurrent condition occurs from
the beginning during start. This cycle continues indefinitely until the fault condition is removed.
Input Undervoltage Lockout (UVLO)
The TPS56121 has fixed input under-voltage lockout (UVLO). In order for the device to turn on, the following
conditions must be met:
•
•
the EN/SS pin voltage must be greater than VIH
the input voltage must exceed UVLO on voltage VUVLO
The UVLO has a minimum of 500 mV hysteresis built-in.
Pre-Bias Startup
The TPS56121 contains a unique circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D),
where D is the duty cycle of the converter.
This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup
and ramp to regulation is smooth and controlled.
Power Good
The TPS56121 provides an indication that output is good for the converter. This is an open drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include:
•
•
•
VFB is more than ±12.5% from nominal
soft-start is active
a short circuit condition has been detected
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator
are turned off. Both high-side FET and low-side FET are kept off. When the junction cools to the required level
(125°C typical), the PWM initiates soft start as during a normal power-up cycle.
12
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS56121
TPS56121
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SLUSAH4 –MARCH 2011
DESIGN EXAMPLE
Introduction
This design example describes a 15-A, 12-V to 1.2-V design using the TPS56121 high-current integrated buck
converter. The system specifications are listed in Table 1.
Table 1. TPS56121 Design Example Parameters
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
8.0
14
0.5
V
V
V
VIN(ripple)
VOUT
Input ripple
IOUT = 15 A
Output voltage
Line regulation
Load regulation
Output ripple
0 A ≤ IOUT ≤ 15 A
8 V ≤ VIN ≤ 14 V
0 A ≤ IOUT ≤ 15 A
IOUT= 15 A
1.164
1.2
1.236
0.5%
0.5%
24
VRIPPLE
VOVER
VUNDER
IOUT
mV
mV
mV
A
Output overshoot
Output undershoot
Output current
Soft-start time
Short- circuit current trip point
Efficiency
5 A ≤ IOUT ≤ 10 A
5 A ≤ IOUT ≤ 10 A
8 V ≤ VIN ≤ 14 V
VIN = 12 V
50
50
0
15
tSS
1.5
ms
A
ISCP
20
η
VIN = 12 V, IOUT = 12.5 A
90
%
fSW
Switching frequency
Size
500
kHz
In2
0.6
+
Figure 20. Design Example Schematic
Copyright © 2011, Texas Instruments Incorporated
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Design Procedure
Switching Frequency Selection
To achieve a balance between small size and high efficiency for this design, use switching frequency of 500 kHz.
Inductor Selection (L1)
Synchronous buck power inductors are typically sized for between approximately 20% and 40% peak-to-peak
ripple current (IRIPPLE).
Using this target ripple current, the required inductor size can be calculated as shown in Equation 3.
V
- VOUT
VOUT
1
14V -1.2 V 1.2V
´
0.3´15A
1
IN(max)
L »
´
´
=
´
14V 500kHz
= 487nH
0.3´IOUT
V
fSW
IN(max)
(3)
Selecting a standard 680-nH inductor value, IRIPPLE =7.3A.
The RMS current through the inductor is approximated in Equation 4.
2
2
)
2
)
2
)
2
2
( )
) (12 )
1
1
1
IL rms
=
I
+
´ I
(
=
)
I
(
+
´ I
(
RIPPLE
=
15
+
´ 3.2
= 15.03A
( )
)
RIPPLE
OUT
(
(
(
L avg
(
12
12
(
)
)
(4)
Output Capacitor Selection (C18, C20, C23)
The selection of the output capacitor is typically driven by the output transient response. The selection of the
output capacitor is typically driven by the output transient response.
•
•
•
loop bandwidth delay
inductor slew-rate delay
transient slew-rate
For applications with VIN(min) > 2 × VOUT the calculation is shown in Equation 5.
2
I
´L
I
I
´ t
(
)
´ V
OVER
TRAN(max)
TRAN(max)
TRAN(max) FALL
C
=
+
-
=
OUT min
(
)
3p´BW ´ V
2´ V
(
V
OVER
)
OVER
OUT
2
5
( )
´ 680nH
5
5A ´1ms
+
3p´ 60kHz ´50mV 2´1.2´50mV
-
= 177mF +142mF - 50mF = 269mF
50mV
(5)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated inEquation 6.
æ
ç
è
ö
÷
ø
I
æ
ç
è
ö
÷
ø
3.2A
8´ 269mF´500kHz
3.2A
RIPPLE
V
-
24mV -
RIPPLE(tot)
V
- V
RIPPLE(cap)
8´ C
´ f
SW
RIPPLE(tot)
OUT
ESR
=
=
=
= 6.5mW
(6)
MAX
I
I
RIPPLE
RIPPLE
In order to meet the low ESR and high capacitance requirements of this design, 5 47-µF, 1210, 2 22-µF, 1206,
and 1 10-µF, 0805 ceramic capacitors are selected. The combination of multiple capacitor types and ceramic
capacitors of different sizes provides a wider band to the filtering frequencies of the output capacitors.
14
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SLUSAH4 –MARCH 2011
Inductor Peak Current Rating
With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 7.
V
´ C
1.2V ´ 275mF
OUT
OUT
I
=
=
= 0.22A
CHARGE
t
1.5ms
SS
(7)
(8)
1
(
1
(
IL peak = IOUT(max)
+
´IRIPPLE + I
)
= 15A +
´3.2A + 0.22A = 16.8A
2
)
CHARGE
2
(
)
Table 2. Inductor Requirements Summary
PARAMETER
VALUE
680
UNITS
L
Inductance
nH
A
IL(rms)
IL(peak)
RMS current (thermal rating)
Peak current (saturation rating)
15.03
16.8
A
PG0871.681NL, 680-nH, 2.3-mΩ, 24-A inductor is selected with a 24-A saturation current and 19-ARMS thermal
rating. A physically larger inductor with a lower DCR could be selected for higher efficiency, but this small
inductor better meets the 0.6 maximum PCB area requirement.
Bootstrap Capacitor (C14)
The bootstrap capacitor maintains power to the high-side driver during the high-side switch ON time. Per the
requirements of the integrated MOSFET, the value of CBOOT is 100 nF with a minimum 10-V rating.
Bootstrap Resistor (R2)
The bootstrap resistor slows the rising edge of the SW voltage to reduce ringing and improve EMI. Per the
datasheet recommendation a 5.1-Ω resistor is selected.
VDD Bypass Capacitor (C11)
Per the TPS56221 recommended pin terminations, VDD is bypassed to GND with a 1.0-µF capacitor.
BP5 Bypass Capacitor (C12)
Per the TPS56221 recommended pin terminations, VDD is bypassed to GND with at least 1.0-µF capacitor. For
additional filtering and noise immunity, a 4.7-µF capacitor is selected.
Soft-Start Capacitor (C13)
The soft-start capacitor provides a constant ramp voltage to the error amplifier to provide controlled, smooth
start-up. The soft-start capacitor is sized using Equation 9.
I
10mA
SS
C
=
´ t
=
SS
´1.5ms = 25nF » 22nF
SS
V
0.6V
FB
(9)
Current Limit (R1)
The TPS56221 uses the negative drop across the internal low-side FET at the end of the OFF-time to measure
the valley of the inductor current. Allowing for a minimum of 30% over maximum load, the programming resistor
is selected using Equation 10.
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
I
æ
ç
è
ö
÷
ø
3.2 A
2
æ
ö
RIPPLE
R
= 95´ 1.3´I
-
+ 500 W = 95´ 1.3´15 A -
+ 500 W = 2.20 kW » 2.87 kW
OCSET
OUT(max)
ç
÷
2
è
ø
(10)
Copyright © 2011, Texas Instruments Incorporated
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TPS56121
SLUSAH4 –MARCH 2011
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Feedback Divider (R4, R7)
The TPS56121 converter uses a full operational amplifier with an internally fixed 0.600-V reference. R4 is
selected between 10 kΩand 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 20.5 kΩ,
The output voltage is programmed with a resistor divider given by Equation 11.
VFB ´RFB
0.600V ´ 20.5kW
RBIAS
=
=
= 20.5kW » 20.5kW
V
- VFB
1.2V - 0.600V
(
)
OUT
(11)
Compensation (C15, C16, C17, R3, R6)
Using the TPS40k Loop Stability Tool for 60 kHz of bandwidth and 60 degrees of phase margin with an R4 value
of 20.5 kΩ, the following values are obtained.
•
•
•
•
•
C17 = C_1 = 470 pF
C15 = C_2 = 1000 pF
C16 = C_3 = 22 pF
R6 = R_2 = 1.27 kΩ
R3 = R_3 = 22.1 kΩ
XXX
DESIGN EXAMPLE PERFORMANCE CHARACTERISTICS
Output voltage 12 V to 1.2V at 0-A to 15-A input current.
100
225
180
135
90
94
92
90
88
86
84
82
80
78
76
74
fSW = 500 kHz
80
60
40
20
0
45
0
−20
−45
−90
−135
−40
Gain
Phase
VIN = 8 V
VIN = 12 V
VIN = 14 V
−60
0.1
1
10
100
1000
Frequency (kHz)
0
3
6
9
12
15
Load Current (A)
Figure 21. Efficiency vs Load Current
Figure 22. Loop Response 60 kHz Bandwidth, 54° Phase
Margin
Figure 23. Output Ripple 20 mV/div, 1.0 µs/div, 20 MHz Bandwidth, AC Coupled
16
Copyright © 2011, Texas Instruments Incorporated
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TPS56121
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SLUSAH4 –MARCH 2011
Table 3. List of Materials for TPS56221 Design Example
REFERENCE
DESiGNATOR
QTY
VALUE
DESCRIPTION
SIZE
PART NUMBER
MANUFACTURER
C1
3
1
1
1
4
1
1
1
1
1
1
1
2
1
5
1
22 µF
Capacitor, Ceramic, 25V, X5R, 20%
Capacitor, Aluminum, 16VDC, ±20%
Capacitor, Ceramic, 25V, X7R, 20%
Capacitor, Ceramic, 25V, X7R, 20%
Capacitor, Ceramic, 25V, X7R, 20%
Capacitor, Ceramic, 25V, X5R, 20%
Capacitor, Ceramic, 10V, X5R, 20%
Capacitor, Ceramic, 16V, X7R, 20%
Capacitor, Ceramic, 16V, X7R, 20%
Capacitor, Ceramic, 25V, X7R, 10%
Capacitor, Ceramic, 25V, C0G, 10%
Capacitor, Ceramic, 25V, C0G, 10%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
IND, SMT Power ±15%
1210
Std
Std
C4
100 µF
1.0 µF
3.3 µF
10 µF
D8
EEEFP1C101AP Panasonic
C5
0805
0805
1206
0805
0805
0402
0402
0402
0402
0402
1206
0805
1210
Std
Std
C6
Std
Std
C7
Std
Std
C11
C12
C13
C14
C15
C16
C17
C18
C20
C21
L1
1.0 µF
4.7 µF
22 µF
Std
Std
Std
Std
Std
Std
100 µF
1000 pF
22 pF
Std
Std
Std
Std
Std
Std
470 pF
22 µF
Std
Std
Std
Std
10 µF
Std
Std
47 µF
Std
Vishay
Pulse
320 nH
7.6 x 7.4
mm
PG0871.681NL
R1
R2
R3
R4
R6
R7
1
1
1
1
1
1
2.87 kΩ
5.1 Ω
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
Resistor, Chip, 1/16W, 1%
0402
0402
0402
0402
0402
0402
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
TI
22.1 kΩ
20.5 kΩ
1.27 kΩ
20.5 kΩ
TPS56121
DQP
15 A, 600 kHz, synchronous buck
converter
QFN-22
6 × 5 mm
U1
1
TPS56121DQP
Copyright © 2011, Texas Instruments Incorporated
17
Product Folder Link(s) :TPS56121
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS56121DQPR
TPS56121DQPT
ACTIVE
ACTIVE
SON
SON
DQP
DQP
22
22
2500
250
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
Call TI
TBD
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Mar-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56121DQPR
SON
DQP
22
2500
330.0
12.4
5.3
6.3
1.8
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Mar-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DQP 22
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
TPS56121DQPR
2500
Pack Materials-Page 2
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