TPS56339DDCR [TI]
4.5V 至 24V 输入、3A 输出同步降压转换器 | DDC | 6 | -40 to 125;
| 型号： | TPS56339DDCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5V 至 24V 输入、3A 输出同步降压转换器 | DDC | 6 | -40 to 125 转换器 |
| 文件： | 总32页 (文件大小：1340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
TPS56339 4.5V 至 24V 输入、3A 输出同步降压转换器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
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输入电压范围：4.5V 至 24V
TPS56339 是一款输入电压范围为 4.5V 至 24V 的 3A
同步降压转换器。该器件包含两个集成开关
输出电压范围：0.8V 至 16V
3A 最大连续输出电流
MOSFET、内部回路补偿和 5ms 内部软启动功能，可
降低组件数。通过采用 SOT-23 (6) 封装，该器件实现
了高功率密度，并且在 PCB 上的占用空间非常小。
500kHz 固定开关频率
支持高达 97% 的占空比
集成式 70mΩ 和 35mΩ MOSFET
关断电流典型值为 3μA
TPS56339 采用高级仿真电流模式 (AECM) 控制，可
实现固定频率快速瞬态响应。该器件具有内部自适应环
路调节功能，因此在宽电压输出范围内无需进行外部补
偿。
静态电流典型值为 98μA
内部 5ms 软启动
方便易用的内部环路补偿
用于高侧和低侧 MOSFET 的逐周期电流限制
非锁存 UVP、UVLO 和 TSD 保护
SOT-23 (6) 封装
使用 TPS56339 并借助 WEBENCH® 电源设计器
创建定制设计
高侧逐周期电流限制可在电流过载情况下保护器件，并
通过低侧拉电流限制防止电流失控，增强限制效果。在
欠压和热关断保护情况下将触发断续保护。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TPS56339
SOT-23 (6)
1.60mm × 2.90mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
12V、19V 分布式总线电源
工业 应用
–
–
视频监控和安全系统
设备
•
消费类应用
–
–
数字电视和 LCD 监视器
无线和智能扬声器
TPS56339 效率
简化原理图
100
95
90
85
80
75
70
65
TPS56339
Rboot
Cboot
3
1
5
6
2
VIN
VIN
BOOT
SW
Cin
Lo
GND
VOUT
Rfb1
Rfb2
4
EN
EN
FB
Co
60
Vin=12V, Vout=5V
55
50
45
Vin=19V, Vout=5V
Vin=12V, Vout=3.3V
Vin=19V, Vout=3.3V
0.001
0.01
0.1
Load Current (A)
1
5
Eff-
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEI2
TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 14
7.5 Light-Load Operation .............................................. 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 24
11.1 接收文档更新通知 ................................................. 24
11.2 相关链接................................................................ 24
11.3 社区资源................................................................ 24
11.4 商标....................................................................... 24
11.5 静电放电警告......................................................... 24
11.6 Glossary................................................................ 24
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (November 2018) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“初始发行版”。........................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS56339
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ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
2
3
6
5
4
BOOT
EN
SW
VIN
FB
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
A 30-Ω boot resistor and a 0.1-μF bootstrap cap are required between BOOT and SW. The
voltage on this cap carries the gate drive voltage for the high-side MOSFET.
BOOT
6
O
EN
FB
5
4
I
I
Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Ground pin. Source terminal of low-side MOSFET as well as the ground terminal for
controller circuit. Connect sensitive FB to this GND at a single point.
GND
1
G
SW
VIN
2
3
O
I
Switch node connection between high-side MOSFET and low-side MOSFET.
Input voltage supply pin. The drain terminal of high-side MOSFET.
(1) I = Input, O = Output, G = GND
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3
MAX
26
UNIT
VIN
EN
6
Input voltages
V
BOOT
SW+6
6
FB
BOOT-SW
6
Output voltages
SW
26
V
SW (<10 ns transient)
Operating junction temperature(2)
Storage temperature
26
TJ
–40
–65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN
4.5
NOM
MAX
24
UNIT
V
VIN
Input voltage
EN
–0.1
–0.1
–0.1
–0.1
0
5.5
5.5
5.5
24
V
FB
V
BOOT-SW
V
Output voltage
SW
V
Ouput Current
Temperature
IOUT
3
A
Operating junction temperature, TJ
–40
125
°C
(1) Conditions for which the device is intended to be functional, but do not ensure specific performance limits.
6.4 Thermal Information
TPS56339
THERMAL METRIC(1)
DDC (SOT23)
6 PINS
119.1
UNIT
(2)(3)
RθJA
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
58.1
36.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were simulated on a standard JEDEC board. They do not represent the performance obtained in an actual application.
(3) The real RθJA on TPS56339EVM is about 62.4 ℃/W, test condition: VIN = 19 V, VOUT = 5 V, IOUT = 3 A, TA = 25 ℃.
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS56339
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ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
Thermal Information (continued)
TPS56339
THERMAL METRIC(1)
DDC (SOT23)
6 PINS
9.4
UNIT
ΨJT
ΨJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
36.2
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4.5 V to 24 V.
PARAMETER
POWER SUPPLY (VIN PIN)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operation input voltage
4.5
24
V
First power on with no load, then force
VFB to 1.2 V, VIN = 12 V
IQ
Non switching quiescent current
Shutdown supply current
98
µA
ISHDN
VIN = 12 V, VEN = 0 V
VIN Rising threshold
VIN Falling threshold
3
4.2
3.7
µA
V
VIN_UVLO
VIN_UVLO
3.9
3.5
4.4
3.9
Undervoltage lockout thresholds
V
ENABLE (EN PIN)
VEN_RISE
EN rising threshold
EN falling threshold
VEN = 1.0 V
1.18
1.12
1.2
1.28
V
V
Enable threshold
VEN_FALL
IEN_INPUT
IEN_HYS
1.08
Input current
µA
µA
Hysteresis current
VEN = 1.5 V
3.1
VOLTAGE REFERENCE (FB PIN)
TJ = 25 °C
0.790
0.782
0.802
0.802
0.814
0.822
V
V
VREF Reference voltage
TJ = -40 °C to 125 °C
INTEGRATED MOSFETS
RDS_ON_HS High-side MOSFET On-resistance
RDS_ON_LS Low-side MOSFET On-resistance
CURRENT LIMIT
IHS_LIMIT High-side MOSFET current limit
ILS_LIMIT Low-side MOSFET current limit
TJ = 25 °C, VBOOT-SW = 5 V
TJ = 25 °C, VIN = 12 V
70
35
mΩ
mΩ
3.9
2.7
4.7
3.6
5.4
4.7
A
A
VIN = 12 V
OUTPUT UNDERVOLTAGE PROTECTION
Output UVP threshold
Hiccup detect (H→L)
62.5
5
%
%
VUVP_HYS
Hysteresis
BOOT UVLO
VBOOT-SW
OSCILLATOR
fSW
BOOT UVLO threshold
Switching frequency
2.2
V
420
500
600
KHz
THERMAL SHUTDOWN
(1)
TSHDN
Thermal shutdown threshold
Hysteresis
160
20
°C
°C
(1)
THYS
(1) Not production tested
6.6 Timing Requirements
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
www.ti.com.cn
Timing Requirements (continued)
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4.5 V to 24 V.
conditions apply: VIN = 4.5 V to 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ON TIMER CONTROL
(1)
TON_MIN
Minimum on time
Maximum on time
Minimum off time
55
5
ns
µs
ns
TON_MAX
TOFF_MIN
SOFT START
TSS
115
Internal soft-start time
5
ms
OUTPUT UNDERVOLTAGE PROTECTION
THIC_WAIT
THIC_RE
Hiccup on time
120
38
µs
Hiccup time before restart
ms
(1) Not production tested
6.7 Typical Characteristics
VIN = 12 V (unless otherwise noted)
110
108
106
104
102
100
98
3.3
3.25
3.2
3.15
3.1
3.05
3
96
94
2.95
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
D001
D002
图 1. Quiescent Current VS Junction Temperature
图 2. Shutdown Current VS Junction Temperature
6
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ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
105
100
95
90
85
80
75
70
65
60
55
50
47.5
45
42.5
40
37.5
35
32.5
30
27.5
25
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
D003
D004
图 3. High-side Rds-On VS Junction Temperature
图 4. Low-side Rds-On VS Junction Temperature
0.808
534
531
528
525
522
519
516
513
510
507
504
0.807
0.806
0.805
0.804
0.803
0.802
0.801
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
D005
D006
图 5. Reference Voltage VS Junction Temperature
图 6. Switching Frequency VS Junction Temperature
4.6
4.4
4.2
4
1.28
1.24
1.2
L ç H
H ç L
L ç H
H ç L
1.16
1.12
1.08
3.8
3.6
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
D007
D008
图 7. VIN UVLO Threshold VS Junction Temperature
图 8. EN Threshold VS Junction Temperature
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TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
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Typical Characteristics (接下页)
VIN = 12 V (unless otherwise noted)
4.86
4.84
4.82
4.8
3.65
3.64
3.63
3.62
3.61
3.6
4.78
4.76
4.74
4.72
4.7
3.59
3.58
3.57
3.56
4.68
4.66
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ - Junction Temperature (èC)
TJ - Junction Temperature (èC)
D009
D010
图 9. High-side Current Limit Threshold VS Junction
图 10. Low-side Current Limit Threshold VS Junction
Temperature
Temperature
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
Vin = 4.5 V
Vin = 12 V
Vin = 19 V
Vin = 6.5 V
Vin = 12 V
Vin = 19 V
0.001
0.01
0.1
Load Current (A)
1
5
0.001
0.01
0.1
Load Current (A)
1
5
Eff-
Eff-
图 11. VOUT=1.05 V Efficiency, L=1.5 µH
图 12. VOUT=3.3 V Efficiency, L=4.7 µH
100
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
55
50
Vin = 6.5 V
Vin = 12 V
Vin = 19 V
Vin = 15 V
Vin = 19 V
0.001
0.01
0.1
Load Current (A)
1
5
0.001
0.01
0.1
Load Current (A)
1
5
Eff-
Eff-
图 13. VOUT=5 V Efficiency, L=5.6 µH
图 14. VOUT=12 V Efficiency, L=6.8 µH
8
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TPS56339
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ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
7 Detailed Description
7.1 Overview
The TPS56339 is a 24-V, 3-A, synchronous buck (step-down) converter with two integrated n-channel
MOSFETs. The device implements an AECM control which can get fast transient response with fixed frequency.
The fast transient response results in low voltage drop and the fixed frequency brings a better jitter permanence
and predictable frequency for EMI design. The optimized internal compensation network minimizes the external
component counts and simplifies the control loop design.
The TPS56339 is designed for safe monotonic start-up into pre-biased loads. The default start-up is when VIN is
typically 4.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage
undervoltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to
operate with the internal pull-up current. The total operating current for the device is approximately 98 μA when
not switching and under no load. When the device is disabled, the supply current is approximately 3 μA. The
integrated 70-mΩ high-side MOSFET and 35-mΩ allow for high efficiency power supply designs with continuous
output currents up to 3 A.
The TPS56339 reduces the external component count by integrating the boot recharge circuit. The bias voltage
for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and SW pins. The boot
capacitor voltage is monitored by a BOOT to SW UVLO (BOOT-SW UVLO) circuit allowing SW pin to be pulled
low to recharge the boot capacitor. The device has a on-time extension function with a maximum on time of 5 μs
to keep the boot capacitor voltage higher than the preset BOOT-SW UVLO threshold which is typically 2.2 V.
During low dropout operation, large duty cycle is needed. The high-side MOSFET could turn on up to 5 μs. Then
the high-side MOSFET turns off and the low-side MOSFET turns on with a minimum off time of 115 ns,
supporting a maximum duty cycle of 97%.
The TPS56339 integrates output undervoltage protection. When the regulated output voltage is lower than 62.5%
of the nominal voltage due to over current triggered, the undervoltage comparator is activated. 120 μs deglitch
timer later, both the high-side and low-side MOSFET turn off, the device steps into hiccup mode.
The TPS56339 has internal 5-ms soft-start time to minimize inrush currents.
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TPS56339
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7.2 Functional Block Diagram
EN
VIN
Thermal
Protection
UVLO
Ip
Ih
UV Protection
-
Hiccup
Shutdown
Shutdown
Logic
+
EN Compatator
Boot Charge
HS Current
Sense
BOOT
HS MOSFET
Current Limit
Boot UVLO
FB
Controller
Power Stage
And
Dead time
Control Logic
SW
VIN
0.8V
Voltage
Reference
Regulator
Soft Start
Oscillator
LS Current
Sense
LS MOSFET
Current Limit
GND
10
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ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
7.3 Feature Description
7.3.1 Advanced Emulated Current Mode Control
The TPS56339 uses an Advanced Emulated Current Mode (AECM) control, which is an emulated current control
topology. The TPS56339 uses an internal oscillator to generate clock to trigger high-side MOSFET turn on. Once
the emulated inductor current ramp up trigger internal reference, the high-side MOSFET turns off and the low-
side MOSFET turns on. Until the next clock coming, the low-side MOSFET turns off and the high-side MOSFET
turns on again. The switching frequency is controlled by the oscillator clock and is fixed that provides ease of
filter design to overcome EMI noise. The internal adaptive loop adjustment eliminates the need for external
compensation over a wide voltage output range up to 16V. However, dynamic adjustment output voltage is not
supported.
7.3.2 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the TPS56339 begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the shutdown mode.
The EN pin has an internal pull-up current source which allows the user to float the EN pin to enable the device.
If an application requires control of the EN pin, use open-drain or open-collector output logic to interface with the
pin.
The TPS56339 implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 510 mV.
If an application requires a higher UVLO threshold on the VIN pin, the EN pin can be configured as shown in 图
15. When using the external UVLO function, setting the hysteresis at a value greater than 510 mV is
recommended.
The EN pin has a small pull-up current, Ip, which sets the default state of the EN pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih when the EN pin crosses the enable threshold. Use 公式 1 , and 公式 2 to
calculate the values of R1 and R2 for a specified UVLO threshold. Once R1, R2 were settled down, the VEN
voltage can be calculated by 公式 3, which should be lower than 5.5V with max VIN.
VIN
Device
R1
R2
Ip
Ih
EN
图 15. Adjustable VIN Undervoltage Lockout
- VSTOP
VEN_FALL
VEN_RISE
VEN_FALL
VEN_RISE
VSATART
R1 =
≈
’
Ip 1-
+ I
h
∆
÷
÷
◊
∆
«
(1)
11
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Feature Description (接下页)
R1 ∂ VEN_FALL
R2 =
VSTOP - VEN_FALL + R ∂ I +I
1
p
h
(2)
R2 ∂ V +R1R2 I +I
(
)
IN
p
h
VEN
=
R1+R2
where
•
•
•
•
•
•
Ip = 1.2 µA
Ih = 3.1 µA
VEN_FALL = 1.12 V
VEN_RISE = 1.18 V
VSATRT, the input voltage enabling the device
VSTOP, the input voltage disabling the device
(3)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS56339 has an internal 5-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS56339 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
During monotonic pre-biased startup, both high-side and low-side MOSFET are not allowed to be turned on until
the internal soft-start voltage is higher than FB pin voltage. This scheme ensures that the converters ramp up
smoothly into regulation point.
7.3.4 Voltage Reference
The voltage reference system produces a precise ±2.5% voltage reference over full temperature by scaling the
output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.802 V.
7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
Minimum ON-time, TON_MIN, is the smallest duration of time that the high-side MOSFET can be on. TON_MIN is
typically 55ns in the TPS56339. Minimum OFF-time, TOFF_MIN, is the smallest duration that the high-side
MOSFET can be off. TOFF_MIN is typically 115 ns in the TPS56339. In CCM operation, TON_MIN and TOFF_MIN limit
the voltage conversion range given a fixed switching frequency.
The minimum duty cycle allowed is:
DMIN = TON_MIN × fSW
(4)
And the maximum duty cycle allowed is:
DMAX = 1 – TOFF_MIN × fSW
(5)
In the TPS56339, a frequency foldback scheme is employed to extend the maximum duty cycle when TOFF_MIN is
reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. With the
duty increase, the on time will increase, until up to the Maximum ON-time, 5 μs. Wide range of frequency
foldback allows the TPS56339 output voltage stay in regulation with a much lower supply voltage VIN. This leads
to a lower effective dropout voltage.
Given an output voltage, the maximum operation supply voltage can be found by:
VOUT
V
=
IN_MAX
fSW ∂ TON_MIN
(6)
At lower supply voltage, the switching frequency decreases once TOFF_MIN is triggered. The minimum VIN without
frequency foldback can be approximated by:
12
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Feature Description (接下页)
VOUT
V
=
IN_MIN
(1-fSW ∂TOFF _MIN
)
(7)
Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in 公式 6. With frequency foldback, VIN_MIN is lowered by decreased fSW, as shown in 图 16 .
540
Iout = 0.5 A
Iout = 1.5 A
Iout = 3 A
510
480
450
420
390
360
330
300
270
240
210
180
4
4.25 4.5 4.75
5 5.25 5.5 5.75
Input Voltage (V)
6
6.25 6.5
Freq
图 16. Frequency Foldback at Dropout (VOUT = 5 V)
7.3.6 Overcurrent and Undervoltage Protection
The TPS56339 is protected from overcurrent conditions by cycle-by-cycle current limiting on both the peak and
valley of the inductor current.
During the on time of the high-side MOSFET switch, the inductor current flow through high-side FET and
increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. The high-side
switch current is sensed when the high-side is turned on after a set blanking time and then compared with the
high-side MOSFET current limit every switching cycle. If the cross-limit event detected after the minimum On-
time, the high-side MOSFET is turned off immediately and the high-side MOSFET current is limited by a clamped
maximum peak current threshold IHS_LIMIT which is constant.
The current going through low-side MOSFET is also sensed and monitored. When the low-side MOSFET turns
on, the inductor current begins to ramp down. The low-side MOSFET is not turned OFF at the end of a switching
cycle if its current is above the low-side current limit ILS_LIMIT. The low-side MOSFET is kept ON for the next cycle
so that inductor current keeps ramping down, until the inductor current ramps below the low-side current limit
ILS_LIMIT and the subsequent switching cycle comes, the low-side MOSFET is turned OFF, and the high-side
MOSFET is turned on after a dead time.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it.
The device will shut down after the UVP delay time (typically 120 μs) and re-start after the hiccup time (typically
38 ms). The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions.
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.7 Thermal Shutdown
The internal thermal shutdown circuitry forces the TPS56339 to stop switching if the junction temperature
exceeds 160°C typically. The device reinitiates the power-up sequence when the junction temperature drops
below 140°C typically.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the device. When VEN is below 1.12 V (typical), the
TPS56339 is in shutdown mode with a shutdown current of 3 μA (typical). The device also employs VIN UVLO
protection. If VIN voltage is below their respective UVLO level, the regulator is turned off.
7.4.2 Active Mode
The TP56339 is in active mode when VEN is above the precision enable threshold, VIN is above its respective
UVLO level. The simplest way to enable the device is to float the EN pin. This allows self startup when the input
voltage is in the operating range 4.5 V to 24 V.
In active mode, depending on the load current, the device is in one of there modes:
1. Continuous Conduction Mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple.
2. Discontinuous Conduction Mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation.
3. Pulse Frequency Modulation Mode (PFM) when switching frequency is decreased at very light load.
7.4.3 CCM Operation
CCM operation is employed in the TPS56339 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in
this mode, and the maximum continuous output current of 3 A can be supplied by the TPS56339.
7.5 Light-Load Operation
The light load running includes Discontinuous Conduction Mode (DCM) and Pulse Frequency Modulation Mode
(PFM).
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to point that its rippled valley touches zero level, which is the boundary between CCM and DCM. The low-
side MOSFET is turned off when the zero inductor current is detected. As the load current further decreases, the
converter runs into DCM.
At even lighter current loads, PFM is activated to maintain high efficiency operation. The On-time is kept almost
the same as it was in the CCM so that it takes longer time to discharge the output capacitor with smaller load
current to the level of the reference voltage. This makes the switching frequency lower, proportional to the load
current, and keeps the light load efficiency high. The transition point to the light load operation IOUT(LL) current can
be calculated in 公式 8.
0.752
(VIN - VOUT )∂ VOUT
IOUT(LL)
=
∂
2∂L1 ∂ fsw
V
IN
(8)
14
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS56339 is a highly-integrated, synchronous, step-down, DC-DC converter. This device is used to convert
a higher DC input voltage to a lower DC output voltage, with a maximum output current of 3 A.
8.2 Typical Application
The application schematic of 图 17 was developed to meet the requirements of the device. This circuit is
available as the TPS56339EVM evaluation module. The design procedure is given in this section.
VIN= 4.5V to 24V
VOUT = 5V, 3A Max
TP8 J3
U1
VIN
L1
J1
TP1
VIN
TP6
BST
C4
R3
1
2
3
5
6
2
2
VOUT
BOOT
SW
1
30.0
5.6uH
TP5
SW
0.1uF
TP7
LOOP
R1
174k
R5
49.9
EN
R4
DNP
0
J2
R6
52.3k
3
2
1
4
1
FB
C1
10uF
C2
10uF
C3
0.1uF
DNP C5
C6
22uF
C7 DNP C8
22uF 22uF
10pF
GND
TP4
EN
TPS56339DDCR
R2
R7
36.5k
10.0k
TP2
GND
TP3
GND
TP9
GND
GND
Copyright © 2019, Texas Instruments Incorporated
图 17. TPS56339 5-V, 3-A Reference Design
8.2.1 Design Requirements
表 1 shows the design parameters for this application.
表 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage
12 V nominal, 5.5 V to 24 V
Output voltage
5 V
3 A
Output current rating
Transient response, 2A load step
Output ripple voltage
ΔVOUT / VOUT = ±5%
30 mV
Input ripple voltage
300 mV
Start Input Voltage (Rising Vin)
Stop Input Voltage (Falling Vin)
Operating frequency
6.6 V
5.7 V
500 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS56339 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%
tolerance or better divider resistors. Referring to the application schematic of 图 17, start with a 10 kΩ for R7 and
use 公式 9 to calculate R6. To improve efficiency at light loads consider using larger value resistors. If the values
are too high the regulator is more susceptible to noise and voltage errors from the FB input current are
noticeable.
VOUT - VREF
VREF
R6 =
∂R7
(9)
表 2 shows the recommended components value for common output voltages.
8.2.2.3 Output Inductor Selection
To calculate the value of the output inductor, use 公式 10. KIND is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer. For this part, TI recommends the range of
KIND from 30% to 50%.
V
- VOUT
VOUT
IN_MAX
LMIN
=
∂
V
KIND ∂IOUT ∂ fSW
IN_MAX
where
•
IOUT = 3 A, the rated output current of the device
(10)
For this design example, use KIND = 50% and the inductor value is calculated to be 5.28 μH. For this design, a
nearest standard value was chosen: 5.6 μH. For the output filter inductor, it is important that the RMS current and
saturation current ratings not be exceeded. The inductor peak-to-peak ripple current, peak current and RMS
current are calculated using 公式 11, 公式 12, and 公式 13.
V
- VOUT
VOUT
IN_MAX
IRIPPLE
=
∂
V
L1 ∂ fSW
IN_MAX
(11)
(12)
IRIPPLE
ILPEAK = IOUT
+
2
1
2
2
ILRMS
=
IOUT
+
IRIPPLE
12
(13)
For this design example, the calculated peak current is 4 A and the calculated RMS current is 3.03 A. The
chosen inductor is a Vishay-Dale IHLP3232DZER5R6M11 5.6-μH. It has a saturation current rating of 7.6 A and
a RMS current rating of 7.4 A.
16
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.4 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. The LC filter used as the output filter has
double pole at:
1
fP =
2p L1 ∂COUT _E
(14)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. A high frequency zero introduced by internal circuit that reduces
the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The
inductor and capacitor for the output filter must be selected so that the double pole of 公式 14 is located below
the high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement, make sure that the L1·COUT_E value meets
the range of L1·COUT_E value recommended in 表 2.
表 2. Recommended Component Values
Range of
L1·COUT_E
(μH×μF)
OUTPUT VOLTAGE(1)
(V)
R6(2)
(kΩ)
R7
(kΩ)
L1(3)
(µH)
COUT
(µF)
(4)
(5)
1.05
1.8
2.5
3.3
5
3.16
12.4
21.5
31.6
52.3
140
10.0
10.0
10.0
10.0
10.0
10.0
1.5
2.2
3.3
4.7
5.6
6.8
2×22
2×22
2×22
2×22
2×22
3×22
48 to 188
64 to 250
87 to 334
107 to 404
93 to 334
45 to 137
12
(1) Please use the recommended L1 and COUT combination of the higher and closest output rail for the
unlisted output rails.
(2) R6 = 0 Ω for VOUT = 0.8 V.
(3) Inductance values are calculated based on VIN=19V, but they can also be used for other input
voltages. Users can calculate their preferred inductance value per 公式 10.
(4) The COUT is the sum of nominal output capacitance. Two 22-uF, 0805, 16V capacitors are
recommended for VOUT ≤ 5V, three 22-uF, 0805, 25VDC capacitors are recommended for VOUT > 5V.
(5) The COUT_E is the effective value after derating, the value of L1·COUT_E should be within in the range.
The capacitor value and ESR determines the amount of output voltage ripple. TheTPS56339 is intended for use
with ceramic or other low ESR capacitors. Use 公式 15 to determine the required RMS current rating for the
output capacitor.
VOUT ∂(V
- VOUT )
IN_MAX
ICORMS
=
12 ∂ VIN_MAX ∂L1 ∂ fSW
(15)
For this design two Murata GRM21BR61C226ME44 22-uF, 0805, 16-V output capacitors are used. From the
data sheet the estimated DC derating of 51.8% at room temperature with AC voltage of 0.2V. The total output
effective capacitance is approximately 22.8 μF. The value of L1·COUT_E is 127.7 μH×μF, which is within the
recommended range.
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8.2.2.5 Input Capacitor Selection
The TPS56339 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from VIN pin to ground is recommended to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage. The capacitor must also have a
ripple current rating greater than the maximum input current ripple of the TPS56339. The input ripple current can
be calculated using 公式 16.
V
IN_MIN - VOUT
VOUT
ICIRMS = IOUT
∂
∂
V
V
IN_MIN
IN_MIN
(16)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at
least a 35-V voltage rating is required to support the maximum input voltage. For this example, two Murata
GRM21BR6YA106KE43L (10-μF, 35-V, 0805, X5R) capacitors have been selected. The effective capacitance
under input voltage of 12 V for each one is 0.269 × 10 = 2.69 μF. The input capacitance value determines the
input ripple voltage of the regulator. The input voltage ripple can be calculated using 公式 17. Using the design
example values, IOUT_MAX = 3 A, CIN_E = 2 × 2.69 = 5.38 μF, fSW = 500 kHz, yields an input voltage ripple of 279
mV and a RMS input ripple current of 1.48 A.
IOUT _MAX ∂ 0.25
DV
=
+ (IOUT _MAX ∂RESR _MAX )
IN
CIN ∂ fSW
where
•
RESR_MAX is the maximum series resistance of the input capacitor
(17)
8.2.2.6 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or
higher voltage rating. In addition, TI recommends in series one boot resistor to make the device more robust, so
a 30-Ω of R3 are required to be used between BOOT to bootstrap capacitor, C4.
8.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is
connected between VIN and the EN pin of the TPS56339 and R2 is connected between EN and GND . The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching when the input voltage increases above 6.6 V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 5.7 V (UVLO stop or disable). 公式 1 and
公式 2 can be used to calculate the values for the upper and lower resistor values. For the stop voltages
specified the nearest standard resistor value for R1 is 174 kΩ and for R2 is 36.5 kΩ.
18
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8.2.4 Application Curves
VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
5.3
5.2
5.1
5
4.9
4.8
4.7
Vin = 6.5 V
Vin = 12 V
Vin = 19 V
Vin = 6.5 V
Vin = 12 V
Vin = 19 V
0.001
0.01
0.1
Load Current (A)
1
5
0.001
0.01
0.1
Load Current (A)
1
5
Eff-
Load
图 18. Efficiency
图 19. Load Regulation
5.15
5.1
5.05
5
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
4.95
4.9
Iout = 0.5 A
Iout = 1.5 A
Iout = 3 A
Iout = 0.03 A
Iout = 3 A
6
8
10
12
14 16
Input Voltage (V)
18
20
22
24
4
4.25 4.5 4.75
5 5.25 5.5 5.75
Input Voltage (V)
6
6.25 6.5
Line
Drop
图 20. Line Regulation
图 21. Dropout Curve
70
65
60
55
50
45
40
35
30
Vin(AC) = 200 mV/div
Vout(AC) = 50 mV/div
SW = 10 V/div
IL = 1 A/div
Vin = 12 V
Vin = 19 V
Time = 4 ms/div
0.5 0.75
1
1.25 1.5 1.75 2
Load Current (A)
2.25 2.5 2.75
3
Case
图 23. Steady State Waveforms, IOUT = 0 A
图 22. Case Temperature Rise vs Load Current
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VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted)
Vin(AC) = 200 mV/div
Vout(AC) = 20 mV/div
Vin(AC) = 200 mV/div
Vout(AC) = 20 mV/div
IL = 2 A/div
IL = 1 A/div
SW = 10 V/div
SW = 10 V/div
Time = 1 µs/div
Time = 2 µs/div
图 25. Steady State Waveforms, IOUT = 3 A
图 24. Steady State Waveforms, IOUT = 0.3 A
Vout(AC) = 100 mV/div
Vout(AC) = 100 mV/div
Iout = 2 A/div
Iout = 2 A/div
Time = 100 ꢀs/div
Time = 100 ꢀs/div
图 27. Transient Response 0.3 to 2.7 A
图 26. Transient Response 1.5 to 3 A
Vin = 10 V/div
Vout = 5 V/div
Vin = 10 V/div
Vout = 5 V/div
IL = 2 A/div
IL = 2 A/div
SW = 5 V/div
SW = 5 V/div
Time = 2 ms/div
Time = 800 µs/div
图 28. Startup Relative to VIN
图 29. Shutdown Relative to VIN
20
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VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted)
Ven = 5 V/div
Vout = 5 V/div
Ven = 5 V/div
Vout = 5 V/div
IL = 2 A/div
IL = 2 A/div
SW = 10 V/div
SW = 10 V/div
Time = 2 ms/div
Time = 200 µs/div
图 30. Enable Relative to EN
图 31. Disable Relative to EN
Vin = 10 V/div
Vout = 5 V/div
Vin = 10 V/div
Vout = 5 V/div
IL = 5 A/div
IL = 5 A/div
SW = 10 V/div
SW = 10 V/div
Time = 20 ms/div
Time = 20 ms/div
图 33. Short Recovery
图 32. Short Protection
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 24 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device or converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitor. An electrolytic capacitor
with a value of 47 μF is a typical choice. The 0.1-µF ceramic bypass capacitor should be as close as possible to
VIN and GND pins.
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. The 0.1-µF ceramic bypass capacitor should be as close as possible to VIN and GND pins.
4. Provide sufficient vias for the input capacitor and output capacitor.
5. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
6. Do not allow switching current to flow under the device.
7. A separate VOUT path should be connected to the upper feedback resistor.
8. Make a Kelvin connection to the GND pin for the feedback path.
9. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
10. The trace of the VFB node should be as small as possible to avoid noise coupling.
11. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
图 34. TPS56339 Top Layout Example
22
版权 © 2018–2019, Texas Instruments Incorporated
TPS56339
www.ti.com.cn
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
Layout Example (接下页)
图 35. TPS56339 Bottom Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
23
TPS56339
ZHCSJ24A –NOVEMBER 2018–REVISED MAY 2019
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS56339DDCR
TPS56339DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
T6339
T6339
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56339DDCR
TPS56339DDCT
SOT-23-
THIN
DDC
DDC
6
6
3000
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23-
THIN
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS56339DDCR
TPS56339DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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