TPS565201DDCT [TI]
采用 SOT23 封装的 4.5V 至 17V 5A 同步降压稳压器 | DDC | 6 | -40 to 125;
| 型号： | TPS565201DDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT23 封装的 4.5V 至 17V 5A 同步降压稳压器 | DDC | 6 | -40 to 125 PC 开关 光电二极管 输出元件 稳压器 |
| 文件： | 总27页 (文件大小：3708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS565201
ZHCSGS9 –SEPTEMBER 2017
TPS565201 4.5V 至 17V 输入、5A 同步降压稳压器
1 特性
3 说明
1
•
•
•
•
•
•
5A 最大输出电流
TPS565201 是一款简单易用的 5A 同步降压转换器。
集成 31mΩ 和 16mΩ FET
该器件经过优化，最大限度地减少了运行所需的外部组
件并可实现低待机电流。
D-CAP2™模式控制，具有快速动态响应特性
输入电压范围：4.5V 至 17V
此开关模式电源 (SMPS) 器件采用 D-CAP2™控制，
此控制方式无需外部补偿组件即可实现快速瞬态响应。
D-CAP2 还支持使用低等效串联电阻 (ESR) 专用聚合
物电容器和陶瓷输出电容器。
输出电压范围：0.76V 至 7V
可在轻负载条件下利用跳脉冲的方式实现高效率
Eco-mode™
•
•
•
•
•
•
•
500kHz 开关频率
关断电流 ≤ 1µA
TPS565201 能够以脉冲跳跃模式运行，从而能在轻负
载运行期间保持高效率。
1% 反馈电压精度
从预偏置输出电压启动
逐周期电流限制
TPS565201 器件采用 6 引脚 1.6mm × 2.9mm SOT
(DDC) 封装，可在 –40°C 至 125°C 的结温范围下运
行。
断续模式过流保护
非锁存 UVP、UVLO 和 TSD 保护
器件信息(1)
2 应用
器件型号
TPS565201
封装
DDC (6)
封装尺寸（标称值）
•
•
•
•
•
数字电视电源
1.60mm x 2.90mm
高清 蓝光™光盘播放器
网络家庭终端设备
数字机顶盒 (STB)
安全监控
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
空白
空白
简化电路原理图
TPS565201 效率
CBST
100%
90%
80%
70%
60%
50%
40%
TPS565201
1
2
6
5
GND
SW
VBST
EN
LO
EN
VOUT
CO
3
4
VOUT
VIN
VFB
VIN
RFB1
RFB2
CIN
Copyright © 2016, Texas Instruments Incorporated
30%
20%
10%
0
VOUT = 1.05 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
0.001
0.01
0.1
1
5
Output Current (A)
D017
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSE71
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 接收文档更新通知 ................................................. 19
11.2 社区资源................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
日期
修订版本
说明
2017 年 9 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
2
3
6
5
4
VBST
EN
SW
VIN
VFB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Ground pin. Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
GND
1
—
SW
VIN
VFB
EN
2
3
4
5
O
I
Switch node connection between high-side NFET and low-side NFET.
Input voltage supply pin. The drain terminal of high-side power NFET.
Converter feedback input. Connect to output voltage with feedback resistor divider.
Enable input control. Active high and must be pulled up to enable the device.
I
I
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
VBST
6
O
Copyright © 2017, Texas Instruments Incorporated
3
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
19
UNIT
V
VIN, EN
VBST
25
V
VBST (10 ns transient)
27
V
Input voltage
VBST (vs SW)
6.5
6.5
19
V
VFB
V
SW
V
SW (10 ns transient)
–3.5
–40
–55
21
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
17
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3.5
–40
23
VBST (10 ns transient)
26
VBST (vs SW)
6.0
17
VI
Input voltage range
EN
V
VFB
5.5
17
SW
SW (10 ns transient)
20
TJ
Operating junction temperature
125
°C
6.4 Thermal Information
TPS565201
DDC (SOT)
6 PINS
95.9
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.6
16.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.4
ψJB
16.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
Operating – non-switching
supply current
IVIN
VIN current, EN = 5 V, VFB = 1 V
VIN current, EN = 0 V
320
0.8
510
5
µA
µA
IVINSDN
Shutdown supply current
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
1.6
120
753
V
V
EN low-level input voltage
EN pin resistance to GND
0.8
VEN = 12 V
245
400
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
VFB input current
760
0
767
mV
µA
IVFB
VFB = 0.8 V. TA = 25°C
±0.1
MOSFET
RDS(on)h
RDS(on)l
High-side switch resistance
Low-side switch resistance
TA = 25°C, VBST – VSW = 5.5 V
TA = 25°C
31
16
mΩ
mΩ
CURRENT LIMIT
IOCL
Current limit
5.3
6.7
8
A
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
172
38
Thermal shutdown
threshold(1)
TSDN
°C
ON-TIME TIMER CONTROL
tOFF(MIN)
SOFT START
tSS
Minimum off time
VFB = 0.61 V
236
1.0
280
ns
ms
Soft-start time
Internal soft-start time
VIN = 12 V, VO = 5 V, CCM mode
FREQUENCY
Fsw
Switching frequency
500
kHz
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
Hiccup detect (H > L)
65
1.8
%
THICCUP_WAIT Hiccup on time
ms
ms
THICCUP_RE
Hiccup time before restart
14.9
UVLO
Wake up VIN voltage
Shutdown VIN voltage
Hysteresis VIN voltage(1)
4.0
3.6
0.4
4.3
UVLO
UVLO threshold
3.3
V
(1) Not production tested.
Copyright © 2017, Texas Instruments Incorporated
5
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.763
0.762
0.761
0.76
0.45
0.4
0.35
0.3
0.25
0.759
0.2
0.758
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D001
D002
Figure 1. TPS565201 Supply Current vs Junction
Temperature
Figure 2. VFB Voltage vs Junction Temperature
1.23
1.2
1.45
1.42
1.39
1.36
1.33
1.3
1.17
1.14
1.11
1.08
1.05
1.02
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D004
D003
Figure 3. EN Pin UVLO Low Voltage vs Junction
Temperature
Figure 4. TPS565201 EN Pin UVLO High Voltage vs Junction
Temperature
60
55
50
45
40
35
30
25
20
28
24
20
16
12
-50
-30
-10
10
30
50
70
90
110 130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D042
D006
Figure 5. TPS565201 High-Side Rds-On vs Junction
Temperature
Figure 6. Low-Side Rds-On vs Junction Temperature
6
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
600
600
500
400
300
200
100
0
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
580
560
540
520
500
480
VOUT = 1.05V
VOUT = 3.3V
VOUT = 5V
4
6
8
10
12
14
16
18
0.001
0.01
0.1
1
5
Input Voltage (V)
Output Current (A)
D018
D046
Figure 7. TPS565201 Switching Frequency
vs Input Voltage
Figure 8. TPS565201 Switching Frequency
vs Output Current
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.001
0.01
0.1
1
5
0.001
0.01
0.1
1
5
Output Current (A)
Output Current (A)
D040
D019
VOUT = 1.05 V
L = 2.2 µH
VOUT = 1.5 V
L = 2.2 µH
Figure 9. TPS565201 Efficiency vs Output Current
Figure 10. TPS565201 Efficiency vs Output Current
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
0.001
0.01
0.1
1
5
0.001
0.01
0.1
1
5
Output Current (A)
Output Current (A)
D020
D041
VOUT = 1.8 V
L = 2.2 µH
VOUT = 3.3 V
L = 2.2 µH
Figure 11. TPS565201 Efficiency vs Output Current
Figure 12. TPS565201 Efficiency vs Output Current
Copyright © 2017, Texas Instruments Incorporated
7
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
VIN = 9 V
VIN = 12 V
VIN = 15 V
0
0.001
0.01
0.1
1
5
Output Current (A)
D021
VOUT = 5 V
L = 3.3 µH
Figure 13. TPS565201 Efficiency vs Output Current
8
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
7 Detailed Description
7.1 Overview
The TPS565201 is a 5-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports
low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without
complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the
output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
3
VIN
VUVP
+
Hiccup
VREG5
UVP
Control Logic
Regulator
UVLO
+
OVP
VOVP
4
VFB
VBST
SW
6
2
+
+
PWM
Voltage
Reference
+
SS
Soft Start
HS
+
Internal Ramp
One-Shot
TSD
XCON
VREG5
LS
Ripple Injection
OCL
threshold
OCL
+
1
GND
+
ZC
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
9
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS565201 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with low-ESR ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN,
and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An ripple is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.
7.3.2 Pulse Skip Mode
The TPS565201 is designed with Eco-mode™ to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in Equation 1.
(VIN - VOUT )´ VOUT
1
IOUT(LL)
=
´
2´L ´ ¦SW
V
IN
(1)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS565201 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converter ramps up smoothly into regulation point.
10
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
Feature Description (continued)
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The
inductor current is monitored during the OFF state by measuring the low-side FET drain to source voltage, which
is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, and the output inductor value. During the on time of the low-side FET switch, this current decreases
linearly. The average value of the switch current is the load current IOUT. If the monitored current is above the
OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage
feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles,
the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-starts after the hiccup time (typically 14.9 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors input voltage. When the voltage is lower than UVLO threshold voltage, the device is
shut off. This protection is non-latching.
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS565201 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS565201 operates at a quasi-fixed frequency of 500
kHz.
7.4.2 Eco-mode™ Operation
When the TPS565201 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS565201
begins operating in pulse skipping eco-mode. Each switching cycle is followed by a period of energy saving sleep
time. The sleep time ends when the VFB voltage falls below the eco-mode threshold voltage. As the output
current decreases, the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS565201 is operating in either normal CCM or Eco-mode™, it may be placed in standby by
asserting the EN pin low.
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ZHCSGS9 –SEPTEMBER 2017
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with
a maximum available output current of 5 A. The following design procedure can be used to select component
values for the TPS565201. Alternately, the WEBENCH® software may be used to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic in Figure 14 shows the TPS565201 4.5-V to 17-V input, 1.05-V output converter
design meeting the requirements for 5-A output. This circuit is available as the evaluation module (EVM). The
sections provide the design procedure.
C7 0.1 ꢁF
TPS565201
1
2
6
5
GND
SW
VBST
EN
VOUT = 1.05 V / 5
A
L1
R3 10 kꢀ
EN
VOUT
2.2 ꢁH
C9
22 ꢁF
C8
22 ꢁF
3
4
VIN
VFB
VOUT
R1 3.74 kꢀ
R2
10 kꢀ
C4
1
C1
C2
C3
10 ꢁF
10 ꢁF 0.1 ꢁF
1
Not Installed
VIN
VIN = 4.5 V to 17 V
Copyright © 2016, Texas Instruments Incorporated
Figure 14. TPS565201 1.05-V, 5-A Reference Design
12
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TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 17 V
1.05 V
Output voltage
Transient response, 1-A/us slew rate
Input ripple voltage
ΔVout = ±5%
400 mV
Output ripple voltage
Output current rating
Operating frequency
20 mV
5 A
550 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of
resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will
be more noticeable.
R1
æ
ö
VOUT = 0.760 ´ 1 +
ç
÷
R2
è
ø
(2)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
=
2p LOUT ì COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
L1 (µH)
TYP
2.2
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
C8 + C9 (µF)
MIN
1.0
1.0
1.0
1.5
1.5
2.2
2.2
3.3
3.3
MAX
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
1
1.05
1.2
1.5
1.8
2.5
3.3
5
3.09
3.74
5.76
9.53
13.7
22.6
33.2
54.9
75
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
20 to 68
2.2
2.2
2.2
2.2
2.2
2.2
3.3
6.5
3.3
Copyright © 2017, Texas Instruments Incorporated
13
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 550 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 7.
V
IN(MAX)- VOUT
VOUT
IP-P
IPEAK = IO +
ILO(RMS)
=
ì
V
LO ì fSW
IN(MAX)
(4)
(5)
IIP-P
1
2
2
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 5.4 A and the calculated RMS current is 5 A. The
inductor used is a WE 744311220 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS565201 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7
to determine the required RMS current rating for the output capacitor.
VOUT ì V - VOUT
(
)
IN
ICO(RMS)
=
12 ì V ì LO ì fSW
IN
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.229 A.
8.2.2.3 Input Capacitor Selection
The TPS565201 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
14
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
8.2.3 Application Curves
3%
2%
1%
0
3%
2%
1%
0
-1%
-2%
-3%
-1%
-2%
-3%
0
1
2
3
4
5
0
1
2
3
4
5
Output Current (A)
Output Current (A)
D050
D051
VIN = 5 V
VOUT = 1.05 V
VIN = 12 V
VOUT = 1.05 V
Figure 15. Load Regulation, VIN = 5 V
Figure 16. Load Regulation, VIN = 12 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
1.05
1.048
1.046
1.044
1.042
1.04
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
1.038
1.036
4
6
8
10
12
14
16
18
0.001
0.01
0.1
1
5
Input Voltage (V)
Output Current (A)
D045
D040
VOUT = 1.05 V
Figure 17. Line Regulation
Figure 18. Efficiency vs Output Current
1 µs/div
1 µs/div
Figure 19. TPS565201 Input Voltage Ripple
Figure 20. TPS565201 Output Voltage Ripple, No Load
Copyright © 2017, Texas Instruments Incorporated
15
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
1 µs/div
1 µs/div
Figure 22. TPS565201 Output Voltage Ripple, IOUT 5 A
Figure 21. TPS565201 Output Voltage Ripple, IOUT 2.5 A
100 µs/div
100 µs/div
Figure 23. TPS565201 Transient Response 0.1 to 2.5 A
Figure 24. TPS565201 Transient Response, 1.25 to 3.75 A
100 µs/div
2 ms/div
Figure 25. TPS565201 Transient Response, 2.5 to 5 A
Figure 26. TPS565201 Startup Relative to VIN
16
Copyright © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
20 ms/div
400 µs/div
Figure 28. TPS565201 Shutdown Relative to VIN
Figure 27. TPS565201 Startup Relative to EN
400 µs/div
Figure 29. TPS565201 Shutdown Relative to EN
9 Power Supply Recommendations
The TPS565201 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 83%. Using that criteria, the minimum recommended input voltage is VO / 0.83.
Copyright © 2017, Texas Instruments Incorporated
17
TPS565201
ZHCSGS9 –SEPTEMBER 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
Trace on the
GND
bottom layer
VOUT
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
BOOST
CAPACITOR
GND
SW
VBST
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
EN
OUTPUT
INDUCTOR
VFB
VIN
VIN
GND trace under IC
On top layer
INPUT BYPASS
CAPACITOR
GND
Figure 30. TPS565201 Layout Example
18
版权 © 2017, Texas Instruments Incorporated
TPS565201
www.ti.com.cn
ZHCSGS9 –SEPTEMBER 2017
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
蓝光 is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS565201DDCR
TPS565201DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
5201
5201
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS565201DDCR
TPS565201DDCT
SOT-
23-THIN
DDC
DDC
6
6
3000
250
180.0
9.5
3.17
3.1
1.1
4.0
8.0
Q3
SOT-
180.0
9.5
3.17
3.1
1.1
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS565201DDCR
TPS565201DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
184.0
184.0
184.0
184.0
19.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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