TPS566231 [TI]
TPS56623x 3-V to 18-V Input, 6-A Synchronous Step-Down Voltage Regulator;
| 型号： | TPS566231 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS56623x 3-V to 18-V Input, 6-A Synchronous Step-Down Voltage Regulator |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS566231, TPS566238
SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
TPS56623x 3-V to 18-V Input, 6-A Synchronous Step-Down Voltage Regulator
1 Features
3 Description
•
Configured for rugged applications
– Input voltage range: 3 V to 18 V
– Output voltage range: 0.6 V to 7 V
– 6-A continuous output current
– 0.6-V ±1% reference voltage (25°C)
– 98% maximum duty cycle
– 600-kHz switching frequency
– Non-latched for OC, OV, UV, and OT
protections
The TPS56623x are simple, easy to use, high-
efficiency, 6-A synchronous buck converters in a QFN
9-pin 1.5-mm x 2.0-mm package.
The devices operate with wider supply input voltage
ranging from 3 V to 18 V. The D-CAP3™ control mode
was adopted to provide a fast transient response,
good line and load regulation, no requirement for
external compensation, and to support low-ESR
output capacitors.
– Built-in output discharge function
Numerous pin-compatible options
– TPS566231 and TPS566238 with SS pin for
adjustable soft-start time
– TPS566231P and TPS566238P with PG pin for
power good indicator
The TPS566231 and TPS566231P operate in Eco-
Mode™ for high efficiency during light load operation,
and are designed with ULQ™ (Ultra Low Quiescent)
feature, achieving 50-uA quiescent current to enable
long battery life in low-power applications. The
TPS566238 and TPS566238P operate in continuous
current mode, which maintains lower output ripple
during all load conditions.
•
– TPS566231 and TPS566231P for auto-skip
mode
The TPS566231 and TPS566238 soft-start time can
be adjusted through the SS pin. The TPS566231P
and TPS566238P indicate power good through the
PG pin.
– TPS566238 and TPS566238P for continuous
current mode
Small solution size and ease of use
– Integrated power MOSFET with RDS(on) 20.8
mΩ and 10.6 mΩ
– D-CAP3™ architecture control for fast transient
response and internal compensation
– 1.5-mm × 2.0-mm HotRod™ QFN package
– Create a custom design with the WEBENCH®
Power Designer
•
The TPS56623x can support up to 98% duty cycle
operation, and integrate complete protection through
OVP, OCP, UVLO, OTP, and UVP with hiccup. They
are each available in a 9-pin 1.5-mm x 2.0-mm
HotRod™ package and the junction temperature is
specified from -40°C to 125°C.
Device Information
2 Applications
PART NUMBER
TPS566231
PACKAGE(1)
BODY SIZE (NOM)
•
•
•
Digital TV, set-top box, gaming consoles
Server, storage and networking point-of-load
Industrial PC, IP camera, and factory automation
applications
TPS566238
VQFN (9)
1.50 mm × 2.00 mm
TPS566231P
TPS566238P
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
L
100
95
90
85
80
75
70
TPS566231/8
TPS566231P/8P
VIN
VOUT
R1
SW
VIN
CIN
CBST
COUT
BST
FB
EN
R2
65
VCC
SS/PG
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
60
55
PGND
C1
0.001
0.01
0.1
I-Load (A)
1
10
12VI
Typical Application
TPS566231 Efficiency Versus Output Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS566231, TPS566238
SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Receiving Notification of Documentation Updates..23
11.2 Support Resources................................................. 23
11.3 Trademarks............................................................. 23
11.4 Electrostatic Discharge Caution..............................23
11.5 Glossary..................................................................23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2020) to Revision A (January 2021)
Page
•
•
Changed device status from Advance Information to Production Data.............................................................. 1
Updated the numbering format for tables, figures and cross-references throughout the document...................1
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5 Pin Configuration and Functions
BST
7
VIN
6
VIN
5
BST
7
VIN
6
VIN
5
8
8
SW
SS
SW
PG
9
4
PGND
9
4
PGND
3
3
1
2
1
2
FB
EN
FB
EN
VCC
VCC
Figure 5-1. TPS566231/TPS566238 Package (Top Figure 5-2. TPS566231P/TPS566238P Package (Top
View) View)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor. If VVIN is lower than 5 V, VCC will follow the VIN voltage.
VCC
1
O
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
ground.
FB
EN
2
3
Enable pin of buck converter. The EN pin is a digital input pin, so it decides to turn on or turn off the buck
converter. If the EN pin is open, the internal pullup current occurs to enable converter.
I
Ground pin. Power ground return for the switching circuit. Connect sensitive SS and FB returns to PGND at
a single point.
PGND
VIN
4
5, 6
7
G
P
Input voltage supply pin. Connect the input decoupling capacitors between VIN and PGND.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW. 0.1 μF is recommended.
BST
SW
O
8
O
O
Switch node terminal. Connect the output inductor to this pin.
TPS566231 and TPS566238 soft-start control pin. Connecting an external capacitor sets the soft-start time.
SS/PG
9
TPS566231P and TPS566238P open-drain power good indicator. It is asserted low if output voltage is out
of PG threshold, over voltage, or if the device is under thermal shutdown, EN shutdown, or during soft start.
O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
-0.3
MAX
20
UNIT
V
VIN
BST
26
V
BST (10-ns transient)
28
V
BST-SW
Input voltage
–0.3
7
V
VIN-SW
22
V
VIN-SW (10-ns transient)
25.5
6
V
SS, FB, EN, PG
PGND
–0.3
–0.3
–2
V
0.3
20
V
SW
V
Output voltage
SW (10-ns transient)
VCC
–5.5
–0.3
–40
–55
22
V
6
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
18
UNIT
VIN
3
–0.1
–0.1
–0.1
–0.1
–1
V
V
BST
23.5
5.5
5.5
0.1
18
Input voltage
BST-SW
SS, FB, EN, PG
PGND
SW
V
V
V
V
Output voltage
Output current
VCC
–0.1
0
5.5
6
V
IOUT
TJ
A
Operating junction temperature
–40
125
°C
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6.4 Thermal Information
TPS56623x
THERMAL METRIC(1)
RQF (VQFN)
9 PINS
89.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA_effective
RθJC(top)
RθJB
Junction-to-ambient thermal resistance with TI EVM
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44
72.2
25
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
ΨJB
24.8
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY VOLTAGE
VIN
IVIN
Input voltage range
VIN Supply Current
VIN Shutdown Current
VIN
3
18
75
V
No load, VEN = 5 V, non-switching
(TPS566231/TPS566231P)
25
50
µA
No load, VEN = 5 V, non-switching
(TPS566238/TPS566238P)
275
375
3.2
475
5
µA
µA
IINSDN
No load, VEN = 0 V
UVLO
Wake up VIN voltage
Shut down VIN voltage
Hysteresis VIN voltage
2.62
2.44
2.74
2.54
200
2.86
2.64
V
V
VUVLOVIN
VIN UVLO threshold
mV
VCC OUTPUT
VIN = 12 V
VIN = 3 V
VIN = 12 V
VIN = 3 V
4.7
5
3
5.2
V
V
VCC
VCC Output Voltage
VCC Current Limit
20
5
mA
mA
ICC
FEEDBACK VOLTAGE
TJ = 25°C
594
591
600
600
606
609
mV
mV
VFB
FB voltage
TJ = -40°C to 125°C
MOSFET
RDS (ON)HI
TJ = 25°C, VIN ≥ 5 V
TJ = 25°C, VIN = 3 V
TJ = 25°C, VIN ≥ 5 V
TJ = 25°C, VIN = 3 V
Valley current set point
20.8
25.8
10.6
13
mΩ
mΩ
mΩ
mΩ
A
High-side MOSFET Rds(on)
Low-side MOSFET Rds(on)
RDS (ON)LO
IOCL
Over Current threshold
6.1
2
7.4
8.9
5.3
INOCL
Negative Over Current threshold
3.4
A
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching Frequency
Minimum On-time(1)
Minimum Off-time(1)
TJ = 25°C, VVOUT = 1.0 V
TJ = 25°C
600
50
kHz
ns
TON(MIN)
TOFF(MIN)
90
VFB = 0.5 V
100
ns
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TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOGIC THRESHOLD
VEN(ON)
VEN(OFF)
VENHYS
IEN
EN Threshold High-level
EN Threshold Low-level
EN Hysteresis
1.13
1.01
1.19
1.08
110
2
1.25
1.16
V
V
mV
uA
EN Pull up Current
VEN = 1.0 V
OUTPUT DISCHARGE and SOFT START
RDIS
ISS
Discharge resistance
Soft-start Charge Current
Internal Soft-start Time
TJ = 25°C, VVOUT = 0.5 V, VEN = 0 V
TPS566231/TPS566238
114
6.5
1.9
Ω
5
8.5
2.9
uA
ms
TSS
TPS566231P/TPS566238P
0.93
POWER GOOD (TPS566231P/TPS566238P)
PG from low-to-high
PG from high-to-low
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
IOL = 4 mA
1
32
ms
us
%
TPGDLY
PG Start-up Delay
PG Threshold
80
85
85
90
95
90
%
VPGTH
110
105
115
110
120
115
0.4
1
%
%
VPG_L
IPGLK
PG Sink Current Capability
PG Leak Current
V
VPGOOD = 5.5 V
uA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP Trip Threshold
OVP Prop deglitch
UVP Trip Threshold
UVP Prop deglitch
110
55
115
32
120
65
%
us
%
tOVPDLY
VUVP
tUVPDLY
tUVPDEL
TJ = 25°C
60
256
256
us
us
Output Hiccup delay relative to SS time UVP detect
Output Hiccup enable delay relative to
tUVPEN
tUVPEN
UVP detect (TPS566231/TPS566238)
7
cycles
ms
SS time
Output Hiccup enable delay relative to
SS time
UVP detect (TPS566231P/
TPS566238P)
19
THERMAL PROTECTION
TOTP
OTP Trip Threshold(1)
OTP Hysteresis(1)
160
25
°C
°C
TOTPHSY
(1) No production test, specified by design.
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6.6 Typical Characteristics
TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
60
415
400
385
370
355
340
55
50
45
40
35
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D001
D002
VEN = 5 V
TPS566231
VEN = 5 V
TPS566238
Figure 6-1. Supply Current vs Junction
Temperature
Figure 6-2. Supply Current vs Junction
Temperature
4.5
615
610
605
600
595
590
4
3.5
3
2.5
2
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D002
D003
VEN = 0 V
Figure 6-3. Shutdown Current vs Temperature
Figure 6-4. Feedback Voltage vs Junction
Temperature
1.22
1.21
1.2
1.12
1.11
1.1
1.19
1.18
1.17
1.09
1.08
1.07
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D004
D005
Figure 6-5. Enable On Voltage vs Junction
Temperature
Figure 6-6. Enable Off Voltage vs Junction
Temperature
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30
27
24
21
18
15
16
14
12
10
8
6
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D006
D007
VIN = 12 V
VIN = 12 V
Figure 6-7. High-Side RDS(on) vs Junction
Temperature
Figure 6-8. Low-Side RDS(on) vs Junction
Temperature
35
32
29
26
23
20
20
18
16
14
12
10
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D006
D007
VIN = 3 V
VIN = 3 V
Figure 6-9. High-Side RDS(on) vs Junction
Temperature
Figure 6-10. Low-Side RDS(on) vs Junction
Temperature
120
118
116
114
112
110
65
63
61
59
57
55
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D009
D010
Figure 6-11. OVP Threshold vs Junction
Temperature
Figure 6-12. UVP Threshold vs Junction
Temperature
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170
8
7.8
7.6
7.4
7.2
7
150
130
110
90
70
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D008
D011
Figure 6-13. Discharge Resistor vs Junction
Temperature
Figure 6-14. Valley Current Limit vs Junction
Temperature
7
6.6
6.2
5.8
5.4
5
2.5
2.3
2.1
1.9
1.7
1.5
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature(OC)
Junction Temperature(OC)
D012
D013
TPS566231 and TPS566238
TPS566231P and TPS566238P
Figure 6-15. Soft-Start Charge Current Iss vs
Junction Temperature
Figure 6-16. Soft-Start Time vs Junction
Temperature
115
110
105
100
95
100
90
80
70
60
50
40
30
20
10
0
90
85
Nat Conv
80
100 LFM
200 LFM
75
400 LFM
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
70
0
1
2
3
4
Output Current (A)
5
6
7
0.001
0.01
0.1
I-Load (A)
1
10
SOA_
D100
VIN = 12 V
VIN = 12 V
VOUT = 1.0 V
Figure 6-18. TPS566238 and TPS566238P
Efficiency
Figure 6-17. Safe Operating Area
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700
800
700
600
500
400
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
600
500
400
300
200
100
0
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
12VI
D102
Figure 6-19. TPS566231 and TPS566231P FSW Load Figure 6-20. TPS566238 and TPS566238P FSW Load
Regulation
Regulation
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7 Detailed Description
7.1 Overview
The TPS56623x is an 6-A integrated FET synchronous buck converter that operates from 3-V to 18-V input
voltage (VIN) and 0.6-V to 7-V output voltage. The proprietary D-CAP3™ mode enables low external component
count, ease of design, and optimization of the power design for cost, size, and efficiency. The key feature of the
TPS566231 and TPS566231P is ultra-low quiescent current (ULQ™) mode. This feature enables long battery life
in system standby mode and high efficiency under light load conditions. The devices employ D-CAP3 mode
control that provides fast transient response with no external compensation components and an accurate
feedback voltage. The control topology provides a seamless transition between CCM operating mode in heavier
load conditions and DCM operation in lighter load conditions.
This Eco-mode™ allows the TPS566231 and TPS566231P to maintain high efficiency at light load. The
TPS566238 and TPS566238P work in continuous current mode to maintain lower output ripple in all load
conditions. The soft-start time of the TPS566231 and TPS566238 can be adjusted through the SS pin. The
TPS566231P and TPS566238P indicate power good through the PG pin. The devices are able to adapt to both
low equivalent series resistance (ESR) output capacitors such as POS-CAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
7.2 Functional Block Diagram
PG high
threshold
PG
+
+
UV threshold
Delay
+
UV
PG low
threshold
+
OV
VIN
OV threshold
FB
+
LDO
VCC
0.6 V
VREGOK
2.74 V /
2.54 V
+
+
PWM
+
+
PG
Control Logic
On/Off time
BST
VIN
SS/PG
SS
Internal Ramp
ñ
ñ
ñ
ñ
ñ
ñ
ñ
Minimum On/Off
Light load Operation
OVP/UVP/OCP/TSD
Soft-Start
Internal SS
Ripple injection
SW
XCON
SW
Large Duty Operation
Power Good
PGND
One Shot
+
OCL
EN
+
+
+
EN Threshold
ZC
+
THOK
160°C /25°C
NOCL
Discharge control
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports
a proprietary D-CAP3 mode control. D-CAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56623x also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to the reference voltage for emulating the output ripple. This enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the devices is a low-pass L-C circuit. This L-C filter has a double-pole frequency described
in Equation 1.
1
fp =
2ìpì LOUTìCOUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS56623x. The low-frequency L-C double pole has a 180 degree drop in-phase. At the output filter
frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain rolloff from –40-dB to –20-dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is about 45 kHz.
The inductor and capacitor selected for the output filter is recommended such that the double pole is located
close to 1/3 the high-frequency zero so that the phase boost provided by this high-frequency zero provides
adequate phase margin for the stability requirement. The crossover frequency of the overall system should
usually be targeted to be less than one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS566231 and TPS566238 have an external SS pin is provided for setting soft-start time. When the EN
pin becomes high, the soft start function begins ramping up the reference voltage to the PWM comparator.
If the application needs a longer soft start time than 0.5 ms, it can be set by connecting a capacitor on the SS
pin. When the EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor
(CSS) connected between SS and ground. The devices tracks the lower of the internal soft-start voltage or the
external soft-start voltage as the reference. The estimated equation for the soft-start time (TSS) is shown in
Equation 2:
1.4 × %OO (J() × 84'( (8)
6 (IO) =
OO
:
;
Q#
+
OO
(2)
where
•
•
VREF is 0.6 V
ISS is 6.5 μA
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7.3.3 Power Good
The TPS566231P and TPS566238P have the PG pin as a power good indicator. The PG pin is an open-drain
output. Once the VFB is between 90% and 110% of the internal reference voltage (VREF), the PG is de-asserted
and floats after a 1-ms de-glitch time. A 100-kΩ pullup resistor is recommended to pull the voltage up to VCC.
The PG pin is pulled low when:
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage,
the device an OVP, UVP, or thermal shutdown event,
or during the soft-start period.
7.3.4 Large Duty Operation
The TPS56623x can support large duty operations by smoothly dropping down the switching frequency. When
VIN / VOUT < 1.6 and the VFB is lower than internal VREF, the switching frequency is allowed to smoothly drop to
make TON extended to implement the large duty operation and also improve the performance of the load
transient performance. The minimum switching frequency is limited with about 165 kHz with typical minimum off-
time of 100 ns. The TPS56623x can support up to 98% duty cycle operation.
7.3.5 Overcurrent Protection and Undervoltage Protection
The TPS56623x has overcurrent protection and undervoltage protection. The output overcurrent limit (OCL) is
implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state by
measuring the low-side FET drain-to-source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited. The output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it and the device will shut off after a wait time of 256 μs and then restart after the hiccup time (typically 7
× Tss). When the overcurrent condition is removed, the output will be recovered.
7.3.6 Overvoltage Protection
The TPS56623x has the overvoltage protection feature. When the output voltage becomes higher than 115% of
the target voltage, the OVP is triggered. The output will be discharged after a wait time of 32 µs, and both the
high-side MOSFET driver and the low-side MOSFET driver turnoff. When the overvoltage condition is removed,
the output voltage will be recovered.
7.3.7 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS56623x has the discharge function by using internal MOSFET of about 114-Ω RDS(on), which discharges
the output VOUT through the SW node during any event like output overvoltage protection, output undervoltage
protection, TSD, if VCC voltage below the UVLO, and when the EN pin voltage (VEN) is below the turnon
threshold. The discharge is slow due to the lower current capability of the MOSFET.
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7.3.9 Thermal Shutdown
The TPS56623x monitors the internal die temperature. If the temperature exceeds the threshold value (typically
160°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
7.4 Device Functional Modes
7.4.1 Advanced Eco-mode Control
The TPS566231 and TPS566231P operate in advanced Eco-mode mode, which maintains high light load
efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced and
eventually comes to a point where the rippled valley touches zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero
inductor current is detected. As the load current further decreases, the converter runs into discontinuous
conduction mode. The on-time is kept almost the same as it was in continuous conduction mode so that it takes
longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. This
makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high.
The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can be calculated from
Equation 3.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.2 Force CCM Mode
The TPS566238 and TPS566238P operate in Force CCM (FCCM) mode, which keeps the converter operating in
continuous current mode during light-load conditions and allows the inductor current to become negative. During
FCCM mode, the switching frequency (FSW) is maintained at an almost constant level over the entire load range,
which is suitable for applications requiring tight control of the switching frequency and output voltage ripple at the
cost of lower efficiency under light load.
7.4.3 Standby Operation
The TPS56623x can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 3.2 µA when in standby condition. The EN pin is pulled high internally. When floating, the part is
enabled by default.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 8-1 shows a typical application for TPS566231 with 1-V output. This design converts an
input voltage range of 3 V to 18 V down to 1 V with a maximum output current of 6 A.
8.2 Typical Application
Figure 8-1. 1-V, 6-A Reference Design
8.2.1 Design Requirements
Table 8-1 lists the design parameters for this example.
Table 8-1. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNIT
V
VOUT
IOUT
Output voltage
Output current
6
A
ΔVOUT
VIN
Transient response
Input voltage
0.1 A - 6 A load step, 2.5 A/μs
CCM condition
±50
12
14
600
25
mV
V
3
18
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
Ambient temperature
mV(P-P)
kHz
°C
TA
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor, you can change the output voltage above 0.6 V. See Equation 4.
RUPPER
VOUT = 0.6 ì (1+
)
RLOWER
(4)
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8.2.2.1.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 8-2 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 5 and Equation 6. It is
important that the inductor is rated to handle these currents.
2
≈
∆
’
÷
≈
∆
∆
«
’
÷
÷
◊
VOUT ì(V
- VOUT )
1
IN(max)
IL
=
I2
+
ì
OUT
(
RMS
)
∆
∆
«
÷
÷
◊
12
V
ìLOUT ìFSW
IN(max)
(5)
(6)
IL(ripple)
IL(peak) = IOUT
+
2
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In D-CAP3, the regulator reacts within
one cycle to the change in duty cycle so the good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in Table 8-2. It is not
recommended to choose the combination of minimum inductance and minimum capacitance or maximum
inductance and maximum capacitance.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
.
Table 8-2. Recommended Component Values
LOUT (µH)
COUT (µF)
RUPPER
(kΩ)
VOUT (V)
RLOWER (kΩ)
CFF (PF)
MIN
0.68
0.68
1
TYP
1
MAX
4.7
4.7
4.7
4.7
4.7
4.7
MIN
44
44
44
44
44
44
MAX
220
220
220
220
220
220
0.6
1
10
30
20
20
20
30
0
20
20
40
90
220
-
-
1
1.2
1.8
3.3
5.0
1.2
1.5
2.2
2.2
-
1
0-50
10-100
10-100
1.5
1.5
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8.2.2.1.4 Input Capacitor Selection
The devices require input decoupling capacitors on power supply input VIN and the bulk capacitors are needed
depending on the application. The minimum input capacitance required is given in Equation 7.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(7)
TI recommends using high-quality X5R or X7R input decoupling capacitors of 30 µF on the input voltage pin VIN.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by Equation 8:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
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8.2.3 Application Curves
Figure 8-2 through Figure 8-25 apply to the circuit of Figure 8-1. VIN = 12-V. TA = 25°C unless otherwise
specified.
95
90
85
80
75
70
65
60
55
100
90
80
70
60
50
40
30
20
10
0
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D101
1Vou
Figure 8-3. TPS566238 Efficiency Curve
Figure 8-2. TPS566231 Efficiency Curve
1
1
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
1Vlo
D106
Figure 8-4. TPS566231 Load Regulation
Figure 8-5. TPS566238 Load Regulation
700
800
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
600
500
400
300
200
100
0
700
600
500
400
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
1VFs
D103
Figure 8-6. TPS566231 FSW vs Output Load
Figure 8-7. TPS566238 FSW vs Output Load
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800
1
0.8
0.6
0.4
0.2
0
700
600
500
400
300
-0.2
-0.4
-0.6
-0.8
-1
200
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VIN (V)
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VIN (V)
1V6A
1V_l
IOUT = 6 A
IOUT = 0.1 A
Figure 8-8. Switching Frequency vs Input Voltage
Figure 8-9. TPS566231 Line Regulation
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VIN (V)
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VIN (V)
D104
1V_l
IOUT = 0.1 A
IOUT = 6 A
Figure 8-10. TPS566238 Line Regulation
Figure 8-11. Line Regulation
Vout=20mV/div (AC coupled)
Vout=10mV/div (AC coupled)
SW=5V/div
SW=5V/div
2us/div
10us/div
IOUT = 0.01 A
IOUT = 0.01 A
Figure 8-13. TPS566238 Output Voltage Ripple
Figure 8-12. TPS566231 Output Voltage Ripple
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VIN=5V/div
EN=2V/div
Vout=20mV/div (AC coupled)
SW=5V/div
Vout=500mV/div
2us/div
1ms/div
Figure 8-14. Output Voltage Ripple, IOUT = 6 A
Figure 8-15. Start-Up Through EN, IOUT = 3 A
VIN=5V/div
VIN=5V/div
EN=2V/div
EN=2V/div
Vout=500mV/div
Vout=500mV/div
200us/div
4ms/div
Figure 8-16. Shut-down Through EN, IOUT = 3 A
Figure 8-17. Start-up with VIN Rising, IOUT = 3 A
VIN=5V/div
EN=2V/div
Vout=50mV/div (AC coupled)
Vout=500mV/div
Iout=5A/div
4ms/div
200us/div
0.6 A to 5.4 A
Slew Rate = 2.5 A/μs
Figure 8-18. Start-up with VIN Falling, IOUT = 3 A
Figure 8-19. TPS566231 Transient Response
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Vout=50mV/div (AC coupled)
Vout=50mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200us/div
200us/div
0.6 A to 5.4 A
Slew Rate = 2.5 A/μs
0.1 A to 6 A
Slew Rate = 2.5 A/μs
Figure 8-21. TPS566238 Transient Response
Figure 8-20. TPS566231 Transient Response
Vout=50mV/div (AC coupled)
Vout=1V/div
SW=10V/div
IL=10A/div
80us/div
Iout=5A/div
200us/div
0.1 A to 6 A
Slew Rate = 2.5 A/μs
Figure 8-23. TPS566231 Normal Operation to
Output Hard Short
Figure 8-22. TPS566238 Transient Response
Vout=1V/div
SW=10V/div
Vout=200mV/div
SW=10V/div
IL=10A/div
IL=10A/div
80us/div
10ms/div
Figure 8-24. TPS566238 Normal Operation to
Output Hard Short
Figure 8-25. Output Hard Short Hiccup
9 Power Supply Recommendations
The TPS56623x is intended to be powered by a well-regulated dc voltage. The input voltage range is 3 V to 18
V. The input supply voltage must be greater than the desired output voltage for proper operation. Input supply
current must be appropriate for the desired output current. If the input voltage supply is located far from the
TPS56623x circuit, additional input bulk capacitance is recommended. Typical values are 100 μF to 470 μF.
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10 Layout
10.1 Layout Guidelines
•
A four-layer PCB for good thermal performance and with maximum ground plane is recommended. 55-mm ×
60-mm, four-layer PCB with 2-1-1-2 oz copper is used as example.
•
•
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place an output inductor and capacitors with IC at the same layer. SW routing should be as short as possible
to minimize EMI, and should be a width plane to carry big current. Enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible.
•
Place a BST resistor and capacitor with IC at the same layer, close to BST and SW plane. 15-mil width trace
is recommended to reduce line parasitic inductance.
•
•
•
Feedback must be routed away from the switching node, BST node, or other high frequency signal.
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and PGND and near input capacitors to reduce parasitic
inductance and improve thermal performance.
10.2 Layout Example
Figure 10-1 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 8-1. Resistor divider for EN is not used in the circuit of Figure 8-1, but are shown in the
layout for reference.
GND
To Other
GND Layer
Additional Vias to
the GND plane
To Enable
Control
Additional Vias to
the GND plane
C
C
GND
C
C
PGND
SS
SW
C
C
C
VOUT
C
VIN
R
Figure 10-1. Top-Layer Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
D-CAP3™, HotRod™, Eco-Mode™, ULQ™, Eco-mode™, and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS566231PRQFR
TPS566231RQFR
TPS566238PRQFR
TPS566238RQFR
XTPS566231RQFR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
RQF
RQF
RQF
RQF
RQF
9
9
9
9
9
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1ID
1H4
1IE
1H5
ACTIVE
VQFN-HR
3000
RoHS (In
work) & Green
(In work)
XTPS566238RQFR
ACTIVE
VQFN-HR
RQF
9
3000
RoHS (In
work) & Green
(In work)
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQF0009A
2.1
1.9
B
A
1.6
1.4
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
PKG
(0.1) TYP
4
4X 0.5
PKG
3
5
7
0.9
0.7
2X
1
1.2
1
1
PIN 1 ID
C0.15
0.3
9X
9
8
0.2
3X 0.25
0.1
C A B
C
0.4
0.3
7X
0.05
4225248/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQF0009A
(1.85)
3X (0.25)
9
8
7X (0.55)
9X (0.25)
1
7
(0.675)
(1.3)
4X (0.5)
(0.3)
PKG
2X
(1)
(0.45)
5
3
(1)
(R0.05) TYP
4
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225248/A 09/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQF0009A
(1.85)
3X (0.25)
9
8
7X (0.55)
9X (0.25)
1
7
(0.675)
(1.3)
4X (0.5)
(0.3)
PKG
2X
(1)
(0.45)
5
3
(1)
(R0.05) TYP
4
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 30X
4225248/A 09/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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