TPS56C215 [TI]
具有 D-CAP3 控制功能的 3.8V 至 17V、12A 同步 SWIFT™ 降压转换器;
| 型号： | TPS56C215 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 D-CAP3 控制功能的 3.8V 至 17V、12A 同步 SWIFT™ 降压转换器 转换器 |
| 文件： | 总39页 (文件大小：2008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS56C215
ZHCSEU8D –MARCH 2016 –REVISED FEBRUARY 2021
TPS56C215 3.8V 至17V 输入、12A 同步降压SWIFT™ 转换器
1 特性
2 应用
• 集成式13.5mΩ和4.5mΩMOSFET
• 支持12A 持续IOUT
• 4.5V 启动（没有5.0V 外部偏置）
• 整个温度范围内的基准电压为0.6V ±1%
• 0.6V 至5.5V 输出电压范围
• 服务器、云计算、存储
• 电信和网络、负载点(POL)
• IPC、工厂自动化、PLC、测试测量
• 高端DTV
3 说明
• 支持陶瓷输出电容器
• D-CAP3™ 控制模式，用于快速瞬态响应
• 可选强制持续导通模式(FCCM)，用于实现窄输出
电压纹波，或自动跳跃Eco-Mode，用于实现高轻
负载效率
• 400kHz、800kHz 和1.2MHz 的可选FSW
• 单调启动至预偏置输出
• 具有断续重启功能的两个可调节电流限制设置
• 可选5V 外部偏置，可提升效率
• 可调节软启动，默认软启动时间为1ms
• –40°C 至150°C 的工作结温范围
• 小型3.5mm x 3.5mm HotRod™ QFN 封装
• 在WEBENCH® 设计工具中受支持
TPS56C215 是 TI 旗下最小的一款单片 12A 同步降压
转换器，具有自适应导通时间 D-CAP3 控制模式。该
器件集成了低 RDS(on) 功率 MOSFET，简单易用且高
效，只需极少的外部组件，适合空间受限的电源系统。
具有竞争力的特性包括非常精确的基准电压、快速负载
瞬态响应、自动跳跃模式运行以实现轻负载效率、可调
节的电流限制和无需外部补偿。强制持续导通模式有助
于满足高性能 DSP 和 FPGA 的严格电压调节精度要
求。TPS56C215 采用热增强型 18 引脚 HotRod QFN
封装，并且设计为在 -40°C 至 150°C 的结温范围内运
行。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS56C215
VQFN (18)
3.5mm x 3.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
95
90
85
80
75
VREG5
RM_H
VIN
MODE
VREG5
VIN
RM_L
CIN
PGOOD
BOOT
SW
PGOOD
TPS56C215
LOUT
VOUT
EN
SS
COUT
RUPPER
FB
CSS
AGND
PGND
RLOWER
VIN=4.5V,VOUT=1.2V,400kHz
70
V =12V, VOUT=1.2V, 400kHz
IN
V =17V, VOUT=1.2V, 400kHz
IN
典型应用
65
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
C001
效率与输出电流间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD05
TPS56C215
ZHCSEU8D –MARCH 2016 –REVISED FEBRUARY 2021
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................29
11.1 Device Support........................................................29
11.2 接收文档更新通知................................................... 30
11.3 支持资源..................................................................30
11.4 Trademarks............................................................. 30
11.5 静电放电警告...........................................................30
11.6 术语表..................................................................... 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Typical Characteristics................................................7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................19
Information.................................................................... 31
12.1 Package Marking.................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (November 2017) to Revision D (February 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
• 更正了整个文档中的拼写和语法错误.................................................................................................................. 1
• Added VIN-SW, VIN-SW, and BOOT –SW (10-ns transient)..............................................................................4
• Changed SW (10-ns transient) min value from -3 V to -5 V............................................................................... 4
Changes from Revision B (July 2016) to Revision C (November 2017)
Page
• 添加了特性项“4.5V 启动（没有5.0V 外部偏置）”......................................................................................... 1
• 添加了特性项“4.5V 启动（没有5.0V 外部偏置）”......................................................................................... 1
• 更改了典型应用图像中的VREG5 引脚处的接地符号。....................................................................................1
• Changed from "5% resistors" to "1% resistors" in the 节7.3.4 description ......................................................15
• Changed Power-Up Sequence image for 图7-2.............................................................................................. 15
• Changed Adjustable VIN Undervoltage Lock Out image for 图7-3. ................................................................17
• Added Ih term to 方程式5 Definition List ......................................................................................................... 17
• Added 节12.1 information................................................................................................................................31
Changes from Revision A (March 2016) to Revision B (May 2016)
Page
• 将节1 从“支持14A 持续IOUT”更改为“支持12A 持续IOUT”......................................................................1
• 向典型应用原理图添加了组件名称......................................................................................................................1
• Deleted IOCL spec for "ILIM+1 option, Valley Current" condition.........................................................................5
• Changed From: "...up to 14 A" To: "...up to 12 A" in first sentence of 节7.1.................................................... 12
• Deleted four rows in Mode Pin Resistor Settings table for IOUT of 14 A........................................................... 15
Changes from Revision * (March 2016) to Revision A (March 2016)
Page
• 添加了完整量产数据表的内容.............................................................................................................................1
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5 Pin Configuration and Functions
BOTTOM VIEW
TOP VIEW
AGND 12
VIN 11
1 BOOT
2 VIN
BOOT 1
VIN 2
12 AGND
11 VIN
PGND 10
PGND 9
PGND 8
3 PGND
4 PGND
5 PGND
PGND 3
PGND 4
PGND 5
10 PGND
9 PGND
8 PGND
7
6
6
7
SW
SW
图5-1. RNN Package 18-Pin VQFN
表5-1. Pin Functions
PIN
I/O DESCRIPTION
NAME
NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BOOT and SW.
BOOT
1
I
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
VIN
2,11
P
G
3, 4, 5,
8, 9, 10
PGND
Power GND terminal for the controller circuit and the internal circuitry. Connect to AGND with a short trace.
SW
6, 7
12
O
G
I
Switch node terminal. Connect the output inductor to this pin.
AGND
FB
Ground of internal analog circuitry. Connect AGND to PGND plane with a short trace.
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND.
13
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the converter starts up in 1 ms.
SS
14
15
16
17
18
O
I
Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input
UVLO by connecting to the center tap of the resistor divider between VIN and EN.
EN
Open-drain power good indicator, it is asserted low if output voltage is out of PGOOD threshold, overvoltage,
or if the device is under thermal shutdown, EN shutdown or during soft start.
PGOOD
VREG5
MODE
O
I/O
I
4.7-V internal LDO output which can also be driven externally with a 5-V input. This pin supplies voltage to the
internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor.
Switching frequency, current limit selection and light load operation mode selection pin. Connect this pin to a
resistor divider from VREG5 and AGND for different MODE options shown in 表7-3.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–2
MAX
20
UNIT
VIN
SW
19
SW (10-ns transient)
VIN-SW
25
–5
22
VIN-SW (10-ns transient)
25
6.5
6.5
7.5
Input Voltage
V
EN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
BOOT –SW
BOOT –SW (10 ns transient)
BOOT
25.5
6.5
6
SS, MODE, FB
VREG5
Output Voltage
PGOOD
6.5
14
V
A
Output Current(2) IOUT
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
–40
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) In order to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current
should not exceed 14A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction
temperature or longer power-on hours are achievable at lower than 14A continuos output current.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.8
NOM
MAX
17
UNIT
VIN
V
V
V
V
A
SW
17
–1.8
–0.1
–0.1
0
Input Voltage
BOOT
VREG5
ILOAD
23.5
5.2
12
Output Current
Operating junction
temperature
TJ
-40
150
°C
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6.4 Thermal Information
RNN PACKAGE
UNIT
THERMAL METRIC(1)
18 PINS
RθJA
Junction-to-ambient thermal resistance
29.5
17.0
8.6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJT
8.6
ψJB
RθJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
IIN
VIN supply current
TJ = 25°C, VEN=5 V, non switching
TJ = 25°C, VEN=0 V
600
7
700
µA
µA
IVINSDN
VIN shutdown current
LOGIC THRESHOLD
VENH
VENL
EN H-level threshold voltage
1.175
1.025
1.225
1.104
0.121
1.91
1.3
V
V
EN L-level threshold voltage
1.15
VENHYS
IENp1
V
VEN = 1.0 V
VEN = 1.3 V
0.35
3
2.95
5.5
µA
µA
EN pull-up current
IENp2
4.197
FEEDBACK VOLTAGE
TJ = 25°C
598
597.5
594
600
600
600
600
602
602.5
602.5
606
mV
mV
mV
mV
TJ = 0°C to 85°C
TJ = –40°C to 85°C
TJ = –40°C to 150°C
VFB
FB voltage
594
LDO VOLTAGE
VREG5
LDO Output voltage
4.58
100
4.7
4.83
200
V
TJ = –40°C to 150°C
TJ = –40°C to 150°C
ILIM5
LDO Output Current limit
150
mA
MOSFET
RDS(on)H
RDS(on)L
High side switch resistance
Low side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
TJ = 25°C, VVREG5 = 4.7 V
13.5
4.5
mΩ
mΩ
SOFT START
Iss
Soft start charge current
TJ = -40°C to 150°C
4.9
6
7.1
µA
CURRENT LIMIT
ILIM-1 option, Valley Current
ILIM option, Valley Current
Valley Current
9.775
11.73
11.5
13.8
4
13.225
15.87
A
A
A
IOCL
Current Limit (Low side sourcing)
Current Limit (Low side negative)
PGOOD threshold
POWER GOOD
VPGOODTH
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
84%
93%
116%
107%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
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MAX UNIT
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
121% x
VFB
VOVP
VUVP
Output OVP threshold
Output UVP threshold
OVP detect
68% x
VFB
Hiccup detect
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
160
15
°C
°C
°C
°C
TSDN
Thermal shutdown threshold
TSDN VREG5
VREG5 thermal shutdown threshold
Shutdown temperature
Hysteresis
171
18
UVLO
VREG5 rising voltage
4.3
3.57
730
3.32
3.26
60
V
V
UVLO
UVLO threshold
VREG5 falling voltage
VREG5 hysteresis
mV
V
VIN rising voltage, VREG5=4.7V
VIN falling voltage, VREG5=4.7V
VIN hysteresis, VREG5=4.7V
UVLO,
VREG5=4.7V
UVLO threshold, VREG5=4.7V
V
mV
6.6 Timing Requirements
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ON-TIME TIMER CONTROL
tON
SW On Time
VIN = 12 V, VOUT=3.3 V, FSW = 800 kHz
VIN = 17 V, VOUT=0.6 V, FSW= 1200 kHz
25°C, VFB=0.5 V
310
340
54
380
310
ns
ns
ns
tON min
tOFF
SOFT START
tSS Soft start time
SW Minimum on time
SW Minimum off time
Internal soft-start time
1.045
ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL
tUVPEN
Output Hiccup delay relative to SS time
UVP detect
UVP detect
1
7
cycle
cycle
Output Hiccup enable delay relative to
SS time
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6.7 Typical Characteristics
1000
900
800
700
600
500
400
300
200
20
18
16
14
12
10
8
6
4
VIN =12V
2
VIN =12V
0
-50
0
50
100
150
0
50
100
150
œ50
TJ - Junction Temperature(°C)
TJ - Junction Temperature(°C)
C002
C003
图6-1. Quiescent Current vs Temperature
图6-2. Shutdown Current vs Temperature
0.606
30
0.604
0.602
0.6
25
20
15
0.598
0.596
V
=12V
V
=12V
IN
IN
0.594
10
-50
0
50
100
150
0
50
100
150
œ50
TJ - Junction Temperature(°C)
TJ - Junction Temperature(°C)
C004
C005
图6-3. Feedback Voltage vs Temperature
图6-4. High-side RDS(on) vs Temperature
10
9
8
8
7
6
5
7
6
5
4
3
2
V
=12V
1
0
IN
V
IN
=12V
4
-50
0
50
100
150
0
50
100
150
œ50
TJ - Junction Temperature(°C)
TJ - Junction Temperature(°C)
C006
C008
图6-5. Low-side RDS(on) vs Temperature
图6-6. Soft-Start Charge Current vs Temperature
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3
2.5
2
6
5.5
5
4.5
4
1.5
1
3.5
3
V
IN
=12V
V =12V
IN
0
50
100
150
0
50
100
150
œ50
œ50
TJ - Junction Temperature(°C)
TJ - Junction Temperature(°C)
C009
C010
图6-7. Enable Pullup Current, VEN = 1.0 V
图6-8. Enable Pullup Current, VEN = 1.3 V
120
115
110
105
18
ILIM option
17
ILIM-1 option
16
15
14
13
12
11
10
V
FB rising
100
95
V
falling
rising
falling
FB
V
FB
V
FB
90
85
80
1
2
3
4
5
6
7
8
9
10
0
50
100
150
œ50
TJ - Junction Temperature(°C)
TJ - Junction Temperature(°C)
C011
C012
图6-9. PGOOD Threshold vs Temperature
图6-10. Current Limit vs Temperature
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
V
OUT =1.2V,FSW= 400kHz
OUT=1.2V,FSW = 800kHz
OUT=1.2V,FSW = 1200kHz
VOUT=1.2V,FSW= 400kHz
=1.2V,FSW= 800kHz
20
10
0
V
V
OUT
V
VOUT=1.2V,FSW= 1200kHz
10
0
0
0
1
10
0.001
0.01
0.1
1
Output Current(A)
Output Current(A)
C013
C014
图6-11. Efficiency with Internal VREG5 = 4.7 V, VIN 图6-12. Efficiency with External VREG5 = 5 V, VIN
= 12 V 12 V
=
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100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
VIN =12V,VOUT=1.2V
VIN =12V,VOUT=3.3V
VIN =12V,VOUT=5.5V
V
=12V,VOUT=1.2V
IN
VIN =12V,VOUT=3.3V
VIN =12V,VOUT=5.5V
0.001
0.01
0.1
1
10
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current(A)
C015
C016
图6-13. Efficiency, Mode = DCM, FSW = 400 kHz
图6-14. Efficiency, Mode = FCCM, FSW = 400 kHz
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VIN =12V,VOUT=1.2V
20
10
0
VIN =12V,VOUT =1.2V
VIN =12V,VOUT=3.3V
20
VIN =12V,VOUT=3.3V
10
VIN =12V,VOUT =5.5V
V
=12V,VOUT=5.5V
IN
0
0.001
0.01
0.1
1
10
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current(A)
C017
C018
图6-15. Efficiency, Mode = DCM, FSW = 1200 kHz
图6-16. Efficiency, Mode = FCCM, FSW = 1200 kHz
1.206
500
450
400
350
300
250
VIN =4.5V,VOUT=1.2V
V
=12V,VOUT=1.2V
IN
1.203
1.2
VIN =17V, VOUT=1.2V
1.197
1.194
200
VIN =4.5V,VOUT =1.2V
150
100
V
=7V,VOUT=1.2V
=17V,VOUT =1.2V
IN
V
IN
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current(A)
C019
C021
图6-17. Load Regulation, FSW = 800 kHz
图6-18. FSW Load Regulation, Mode = DCM, FSW =
400 kHz
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900
800
700
600
500
1400
1300
1200
1100
1000
900
800
V
=4.5V,VOUT=1.2V
IN
VIN =4.5V, VOUT=1.2V
VIN =7V,VOUT=1.2V
=17V, VOUT=1.2V
400
300
700
V
=7V,VOUT=1.2V
=17V,VOUT=1.2V
IN
V
V
IN
IN
600
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current
C022
C023
图6-19. FSW Load Regulation, Mode = DCM, FSW = 图6-20. FSW Load Regulation, Mode = DCM, FSW
800 kHz 1200 kHz
=
600
500
400
300
200
1000
900
800
700
600
500
400
V
=4.5V, VOUT=1.2V
VIN =4.5V,VOUT=1.2V
VIN =12V,VOUT =1.2V
IN
VIN =12V, VOUT=1.2V
VIN =17V,VOUT=1.2V
V
=17V,VOUT =1.2V
IN
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current(A)
C024
C025
图6-21. FSW Load Regulation, Mode = FCCM, FSW = 图6-22. FSW Load Regulation, Mode = FCCM, FSW
400 kHz 800 kHz
=
1400
1300
1200
1100
1000
900
600
500
400
300
200
V
=4.5V,V =1.2V
V
=12V, VOUT=1.2V
=12V, VOUT=3.3V
=12V,VOUT=5.5V
IN
IN
OUT
IN
V
=12V,VOUT=1.2V
=17V,VOUT=1.2V
V
IN
IN
V
V
IN
800
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
Output Current(A)
C026
C027
图6-23. FSW Load Regulation, Mode = FCCM, FSW = 图6-24. FSW Load Regulation, Mode = FCCM, FSW
1200 kHz 400 kHz
=
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1400
1300
1200
1100
1000
900
V
=12V,VOUT=1.2V
IN
VIN =12V,V =3.3V
OUT
VIN =12V,VOUT=5.5V
800
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
C028
图6-25. FSW Load Regulation, Mode = FCCM, FSW = 1200 kHz
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7 Detailed Description
7.1 Overview
The TPS56C215 is a high density synchronous step down buck converter which can operate from 3.8-V to 17-V
input voltage (VIN). It has 13.5-mΩand 4.5-mΩintegrated MOSFETs that enable high efficiency up to 12 A. The
device employs D-CAP3 mode control that provides fast transient response with no external compensation
components and an accurate feedback voltage. The control topology provides seamless transition between
FCCM operating mode at higher load condition and DCM/Eco-mode operation at lighter load condition. DCM/
Eco-mode allows the TPS56C215 to maintain high efficiency at light load. The TPS56C215 is able to adapt to
both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
The TPS56C215 has three selectable switching frequencies (FSW) (400 kHz, 800 kHz, and 1200 kHz), which
gives the flexibility to optimize the design for higher efficiency or smaller size. There are two selectable current
limits. All these options are configured by choosing the right voltage on the MODE pin.
The TPS56C215 has a 4.7-V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin which improves the efficiency of the
converter. The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal
circuitry from low input voltages. The device has an internal pullup current source on the EN pin which can
enable the device even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage, and overtemperature conditions.
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7.2 Functional Block Diagram
PG rising threshold
TPS56C215
+
PGOOD
PGOOD Logic
UV
UV
threshold
+
+
Delay
VREG5
UVP / OVP Logic
PG falling threshold
+
OV threshold
OV
LDO
VIN
UVLO
BOOT
Internal Ramp
+
BOOT
t
VREF
t
+
Error Amp
Control Logic
+
+
FB
t
SW
SW
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On Time
Min On Time/Off Time
FCCM/SKIP
Soft-Start
XCON
Internal SS
Power Good
Internal/External VREG5
UVP/TSD
One shot
VREG5
SS
PGND
Light Load Operation/
Current Limit/Switching
Frequency
MODE
TSD 160C/171C
SW
OCL
+
Ip1
Ip2
EN
+
ZC
+
Enable Threshold
NOCL
+
7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The TPS56C215 operates using the adaptive on-time PWM control with a proprietary D-CAP3 control which
enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle, the high-side MOSFET is turned on for an on-time
set by an internal one shot timer. This on-time is set based on the input voltage of the conveter, output voltage of
the converter, and the pseudo-fixed frequency, hence this type of control topology is called an adaptive on-time
control. The one-shot timer resets and turns on again once the feedback voltage (VFB) falls below the internal
reference voltage (VREF). An internal ramp is generated which is fed to the FB pin to simulate the output voltage
ripple. This enables the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No
external current sense network or loop compensation is required for DCAP3 control topology.
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The TPS56C215 includes an error amplifier that makes the output voltage very accurate. This error amplifier is
absent in other flavors of DCAP3. For any control topology that is compensated internally, there is a range of the
output filter it can support. The output filter used with the TPS56C215 is a low-pass L-C circuit. This L-C filter has
double pole that is described in 方程式1.
1
¦
=
P
2´ p´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56C215. The low frequency L-C double pole has a 180 degree in-phase. At the output filter
frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40-dB to –20-dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in 表 7-1. The inductor
and capacitor selected for the output filter must be such that the double pole is located close enough to the high-
frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase margin
for the stability requirement. The crossover frequency of the overall system should usually be targeted to be less
than one-fifth of the switching frequency (FSW).
表7-1. Ripple Injection Zero
SWITCHING FREQUENCY (kHz)
ZERO LOCATION (kHz)
400
800
7.1
14.3
21.4
1200
表7-2 lists the inductor values and part numbers that are used to plot the efficiency curves in 节6.7.
表7-2. Inductor Values
WÜRTH PART
VOUT(V)
FSW(kHz)
LOUT(μH)
NUMBER(1)
744325120
744311068
744314047
744325240
7443552150
744325120
744325330
744325240
7443552150
400
800
1.2
0.68
0.47
2.4
1.2
1200
400
3.3
5.5
800
1.5
1200
400
1.2
3.3
800
2.4
1200
1.5
(1) See Third-Party Products disclaimer.
7.3.2 Eco-mode Control
The TPS56C215 is designed with Eco-mode control to increase efficiency at light loads. This option can be
chosen using the MODE pin as shown in 表 7-3. As the output current decreases from heavy load condition, the
inductor current is also reduced. If the output current is reduced enough, the valley of the inductor current
reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The low-side MOSFET is turned off when a zero inductor current is detected. As the load current further
decreases the converter runs into discontinuous conduction mode. The on-time is kept approximately the same
as it is in continuous conduction mode. The off-time increases as it takes more time to discharge the output with
a smaller load current. The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can
be calculated from 方程式2.
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(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(2)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(ma×) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.3.3 4.7-V LDO
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage
that is above the internal output voltage of the LDO can override the internal LDO, switching it to the external rail
once a higher voltage is detected. This enhances the efficiency of the converter because the quiescent current
now runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5 pin
voltage and disables the output when VREG5 falls below the UVLO threshold. When using an external bias on
the VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand that
if there is a discharge path on the VREG5 rail that can pull a current higher than the internal current limit of the
LDO (ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of TPS56C215.
If such condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage switches over to
the internal LDO voltage which is 4.7 V typically in a few nanoseconds. 图 7-1 shows this transition of the
VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V when the external bias to
VREG5 is disabled while the output of TPS56C215 remains unchanged.
VREG5
VOUT
图7-1. VREG5 Transition
7.3.4 MODE Selection
The TPS56C215 has a MODE pin that can offer 12 different states of operation as a combination of current limit,
switching frequency, and light load operation. The device can operate at two different current limits ILIM-1 and
ILIM to support an output continuous current of 10 A and 12 A, respectively. The TPS56C215 is designed to
compare the valley current of the inductor against the current limit thresholds so it is important to understand that
the output current will be half the ripple current higher than the valley current. For example, with the ILIM current
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limit selection, the OCL threshold is 11.73 A minimum which means that a pk-pk inductor ripple current of 0.54 A
minimum is needed to be able to draw 12 A out of the converter without entering an overcurrent condition. The
TPS56C215 can operate at three different frequencies of 400 kHz, 800 kHz, and 1200 kHz and also can choose
between Eco-mode and FCCM mode. The device reads the voltage on the MODE pin during start-up and
latches onto one of the MODE options listed in 表 7-3. The voltage on the MODE pin can be set by connecting
this pin to the center tap of a resistor divider connected between VREG5 and AGND. A guideline for the top
resistor (RM_H) and the bottom resistor (RM_L) in 1% resistors is shown in 表 7-3. It is important that the voltage
for the MODE pin is derived from the VREG5 rail only since internally this voltage is referenced to detect the
MODE option. The MODE pin setting can be reset only by a VIN power cycling.
表7-3. MODE Pin Resistor Settings
LIGHT LOAD
OPERATION
CURRENT LIMIT
FREQUENCY
(kHz)
RM_L (kΩ)
RM_H (kΩ)
5.1
10
20
20
51
51
51
51
51
51
51
51
300
200
160
120
200
180
150
120
91
FCCM
FCCM
FCCM
FCCM
FCCM
FCCM
DCM
ILIM-1
ILIM
400
400
ILIM-1
ILIM
800
800
ILIM-1
ILIM
1200
1200
400
ILIM-1
ILIM
DCM
400
DCM
ILIM-1
ILIM
800
82
DCM
800
62
DCM
ILIM-1
ILIM
1200
1200
51
DCM
图 7-2 shows the typical start-up sequence of the device once the EN pin voltage crosses the EN turnon
threshold. After the voltage on VREG5 pin crosses the rising UVLO threshold, it takes 100 μs to read the first
MODE setting and approximately 100 μs from there to finish the last MODE setting. The output voltage starts
ramping after the MODE setting reading is completed.
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EN threshold
1.2 V
EN
VREG5 UVLO
4.3 V
VREG5
MODE
MODE16
MODE1
200 µs
tss(1ms)
100 µs
SS
图7-2. Power-Up Sequence
7.3.5 Soft Start and Pre-biased Soft Start
The TPS56C215 has an adjustable soft start time that can be set by connecting a capacitor on SS pin. When the
EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 方程式3:
CSS × VREF
TSS(S)
=
ISS
(3)
where
• VREF is 0.6 V and ISS is 6 µA
If the output capacitor is pre-biased at start-up, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.6 Enable and Adjustable UVLO
The EN pin controls the turnon and turnoff of the device. When EN pin voltage is above the turnon threshold
which is around 1.2 V, the device starts switching and when the EN pin voltage falls below the turnoff threshold,
which is around 1.1 V, it stops switching. If the user application requires a different turnon (VSTART) and turnoff
thresholds (VSTOP) respectively, the EN pin can be configured as shown in 图7-3 by connecting a resistor divider
between VIN and EN. The EN pin has a pullup current Ip1 that sets the default state of the pin when it is floating.
This current increases to Ip2 when the EN pin voltage crosses the turnon threshold. The UVLO thresholds can be
set by using 方程式4 and 方程式5.
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TPS56C215
Ih
VIN
EN
Ip1
R1
R2
图7-3. Adjustable VIN Undervoltage Lock Out
æ
ç
è
ö
VENFALLING
VSTART
- VSTOP
÷
VENRISING
ø
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+ I
p1 ç
h
VENRISING
è
(4)
(5)
R1´ VENFALLING
STOP - VENFALLING +R1 Ip2
R2 =
V
where
• Ip2 = 4.197 μA
• Ip1 = 1.91 μA
• Ih = 2.287 μA
• VENRISING = 1.225 V
• VENFALLING = 1.104 V
7.3.7 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the FB pin voltage is between 93% and 107% of
the internal reference voltage (VREF), the PGOOD is de-asserted and floats after a 200-µs de-glitch time. A
pullup resistor of 10 kΩ is recommended to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin
voltage is lower than VUVP or greater than VOVP threshold, in an event of thermal shutdown, or during the soft-
start period
7.3.8 Overcurrent Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. During the on-time of the high-side FET switch, the switch current increases at
a linear rate determined by input voltage, output voltage, the on-time, and the output inductor value. During the
on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the
load current IOUT. If the measured drain-to-source voltage of the low-side FET is above the voltage proportional
to current limit, the low-side FET stays on until the current level becomes lower than the OCL level which
reduces the output current available. When the current is limited the output voltage tends to drop because the
load demand is higher than what the converter can support. When the output voltage falls below 68% of the
target voltage, the UVP comparator detects it and shuts down the device after a wait time of 1 ms, the device re-
starts after a hiccup time of 7 ms. In this type of valley detect control, the load current is higher than the OCL
threshold by one half of the peak-to-peak inductor ripple current. When the overcurrent condition is removed, the
output voltage returns to the regulated value. If an OCL condition happens during start-up, then the device
enters hiccup-mode immediately without a wait time of 1 ms.
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7.3.9 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault.
OOB protection operates as an early no-fault overvoltage protection mechanism. During the OOB operation, the
controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET
beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall
quickly toward the setpoint. During the operation, the cycle-by cycle negative current limit is also activated to
ensure the safe operation of the internal FETs.
7.3.10 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.11 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C), the device shuts off. This is a non-latch protection. During start-up, if the device
temperature is higher than 160°C, the device does not start switching and does not load the MODE settings. If
the device temp goes higher than TSDN threshold after start-up, it stops switching with SS reset to ground and an
internal discharge switch turns on to quickly discharge the output voltage. The device re-starts switching when
the temperature goes below the thermal shutdown threshold but the MODE settings are not re-loaded again.
There is a second higher thermal protection on the device TSDN VREG5 which protects it from overtemperature
conditions not caused by the switching of the device itself. This threshold is at typically 170°C. Even under non-
switching condition of the device after exceeding TSDN threshold, if it still continues to heat up the VREG5 output
shuts off once temperature goes beyond TSDN VREG5, thereby shutting down the device completely.
7.3.12 Output Voltage Discharge
The device has a 500-Ω discharge switch that discharges the output VOUT through SW node during any event of
fault like output overvoltage, output undervoltage, TSD, if VREG5 voltage below the UVLO and when the EN pin
voltage (VEN) is below the turnon threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (FSW) is maintained at an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in DCM/Eco-mode, the device enters pulse skip mode after the valley of the inductor ripple
current crosses zero. The Eco-mode maintains higher efficiency at light load with a lower switching frequency.
7.4.2 Standby Operation
The TPS56C215 can be placed in standby mode by pulling the EN pin low. The device operates with a shut-
down current of 7 μA when in standby condition.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The schematic of 图8-1 shows a typical application for TPS56C215. This design converts an input voltage range
of 4.5 V to 17 V down to 1.2 V with a maximum output current of 12 A.
8.2 Typical Application
VIN = 4.5 V - 17 V
V
IN
U1
TPS56C215
C1
0.1µF
C2
0.1µF
C3
22µF
C4
22µF
C5
22µF
C6
22µF
L
OUT
C9
V
= 1.2 V, 12 A
OUT
2
1
VIN
VIN
BOOT
VOUT
C14
11
470nH
R4 10.0k
0.1µF
6
SW
SW
FB
C11
47µF
C12
47µF
C13
47µF
7
13
47µF
14
15
16
17
18
SS
EN
C7
0.047µF
3
C10
PGND
PGND
PGND
PGND
PGND
PGND
EN
4
PGOOD
R1
5
PGOOD
VREG5
MODE
56pF
8
10.0k
9
R5
10.0k
10
R2
52.3k
C8
4.7µF
12
AGND
R3
49.9k
图8-1. Application Schematic
8.2.1 Design Requirements
表8-1. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
VOUT
Output voltage
Output current
1.2
12
40
12
20
IOUT
A
Transient response
Input voltage
9-A load step
mV
V
ΔVOUT
VIN
4.5
17
VOUT(ripple)
Output voltage ripple
mV(P-P)
V
Internal
UVLO
Start input voltage
Input voltage rising
Input voltage falling
Internal
UVLO
Stop input voltage
V
FSW
Switching frequency
1.2
DCM
25
MHz
Operating Mode
TA
Ambient temperature
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See 方程式6.
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æ
ö
RUPPER
VOUT = 0.6´ 1+
ç
÷
RLOWER ø
è
(6)
8.2.2.1.2 Switching Frequency and MODE Selection
Switching Frequency, current limit, and switching mode (DCM or FCCM) are set by a voltage divider from
VREG5 to GND connected to the MODE pin. See 表 7-3 for possible MODE pin configurations. Switching
frequency selection is a tradeoff between higher efficiency and smaller system solution size. Lower switching
frequency yields higher overall efficiency but relatively bigger external components. Higher switching frequencies
cause additional switching losses which impact efficiency and thermal performance. For this design, 1.2 MHz is
chosen as the switching frequency, the switching mode is DCM and the output current is 12 A.
8.2.2.1.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表8-2 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 方程式 7 and 方程式 8. It is important
that the inductor is rated to handle these currents.
æ
2 ö
÷
÷
÷
ø
æ
ç
ö
÷
VOUT × V
- VOUT
(
× LOUT × FSW
IN(max)
)
1
IN(max)
ç 2
I
IL(rms)=
+
×
OUT
ç
ç
è
÷
ø
12
V
ç
è
(7)
(8)
IOUT(ripple)
I
= IOUT
+
L(peak)
During transient/short circuit conditions the inductor current can increase up to the current limit of the device so it
is safe to choose an inductor with a saturation current higher than the peak current under current limit condition.
8.2.2.1.4 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. In DCAP3, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in 表8-2
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
.
表8-2. Recommended Component Values
VOUT (V)
FSW (kHz)
LOUT (µH)
0.68
0.47
0.33
1.2
COUT(min) (µF)
COUT(max) (µF)
500
CFF (pF)
RLOWER (kΩ)
RUPPER (kΩ)
400
300
100
88
–
–
0.6
10
0
800
500
1200
400
500
–
100
88
500
–
1.2
3.3
10
800
0.68
0.47
2.4
500
–
1200
400
88
500
–
88
500
100–220
100–220
100–220
100–220
100–220
100–220
45.3
800
1.5
88
500
1200
400
1.2
88
500
3.3
88
500
5.5
82.5
800
2.4
88
500
1200
1.5
88
700
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8.2.2.1.5 Input Capacitor Selection
The minimum input capacitance required is given in 方程式9.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(9)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by 方程式10:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(10)
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8.2.3 Application Curves
Efficiency through Transient Response apply to the circuit of 图 8-1. VIN = 12 V. Ta = 25°C unless otherwise
specified.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
2 3 45 7 1015
0
1
2
3
4
5
6
7
Output Current (A)
8
9
10 11 12
D102
D101
图8-3. Light Load Efficiency
图8-2. Efficiency
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
1
2
3
4
5
Output Current (A)
6
7
8
9
10 11 12
0
1
2
3
4
5
Output Current (A)
6
7
8
9
10 11 12
D103
D104
图8-4. Load Regulation, VIN = 5 V
图8-5. Load Regulation, VIN = 12 V
60
50
180
150
120
90
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
40
30
20
60
10
30
0
0
-10
-20
-30
-40
-50
-60
-30
-60
-90
-120
-150
-180
Gain (dB)
Phase (Deg)
100 200 500 1000
10000
Frequency (Hz)
100000
500000
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
D106
D105
图8-7. Loop Response, IOUT = 6 A
图8-6. Line Regulation, IOUT = 6 A
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VIN = 100 mV / div (ac coupled)
VIN = 100 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 50 µsec / div
Time = 500 nsec / div
图8-9. Input Voltage Ripple, IOUT = 800 mA
图8-8. Input Voltage Ripple, IOUT = 10 mA
VOUT = 20 mV / div (ac coupled)
VIN = 100 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 500 nsec / div
Time = 50 µsec / div
图8-10. Input Voltage Ripple, IOUT = 12 A
图8-11. Output Voltage Ripple, IOUT = 10 mA
VOUT = 20 mV / div (ac coupled)
VOUT = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 500 nsec / div
Time = 500 nsec / div
图8-12. Output Voltage Ripple, IOUT = 800 mA
图8-13. Output Voltage Ripple, IOUT = 12 A
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VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
EN = 5 V / div
VOUT = 500 mV / div
PGOOD = 5 V / div
VOUT = 500 mV / div
PGOOD = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
图8-14. Start Up Relative to VIN Rising
图8-15. Start Up Relative to EN Rising
VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
EN = 5 V / div
VOUT = 500 mV / div
VOUT = 500 mV / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
图8-16. Shut Down Relative to VIN Falling
图8-17. Shut Down Relative to EN Falling
VOUT = 50 mV / div (ac coupled)
IOUT = 2 A / div
Load step = 3 A - 9 A, slew rate = 1 A / µsec
Time = 200 µsec / div
图8-18. Transient Response
9 Power Supply Recommendations
The TPS56C215 is intended to be powered by a well regulated dc voltage. The input voltage range is 3.8 to 17
V. TPS56C215 is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS56215 circuit, some additional input bulk capacitance is recommended. Typical
values are 100 µF to 470 µF.
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10 Layout
10.1 Layout Guidelines
• Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
x 3", four-layer PCB with 2-oz. copper used as example.
• Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.
• Inner layer 1 will be ground with the PGND to AGND net tie
• Inner layer2 has VIN copper pour that has vias to the top layer VIN. Place multiple vias under the device
near VIN and PGND and near input capacitors to reduce parasitic inductance and improve thermal
performance
• Bottom later is GND with the BOOT trace routing.
• Feedback should be referenced to the quite AGND and routed away from the switch node.
• VIN trace must be wide to reduce the trace impedance.
10.2 Layout Example
图 10-1 shows the recommended top side layout. Component reference designators are the same as the circuit
shown in 图 8-1. Resistor divider for EN is not used in the circuit of 图 8-1, but are shown in the layout for
reference.
PGOOD
OUTPUT
R1
BOOT
VIN
AGND
VIN
PGND
PGND
PGND
PGND
PGND
PGND
C1
C2
C3
C4
C5
C6
L1
C11
C12
C13
C14
图10-1. Top Side Layout
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图 10-2 shows the recommended layout for the first internal layer. It is comprised of a large PGND plane and a
smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating currents.
AGND
SINGLE POINT
AGND TO PGND
CONNECTION
PGND PLANE
图10-2. Mid Layer 1 Layout
图 10-3 shows the recommended layout for the second internal layer. It is comprised of a large PGND plane, a
smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper fill area.
VIN
PGND PLANE
VOUT
图10-3. Mid Layer 2 Layout
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图 10-4 shows the recommended layout for the bottom layer. It is comprised of a large PGND plane and a trace
to connect the BOOT capacitor to the SW node.
PGND PLANE
图10-4. Bottom Layer Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
The evaluation module for system validation in shown in 图11-1.
图11-1. System Validation EVM Board
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11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
D-CAP3™, HotRod™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Marking
TI =
YM =
S =
TI Letters
Year Month Date Code
Assembly Site Code
Assembly Lot Code
LLLL =
56C215
TI YMS
LLLL
Y : Year Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0)
M : Month Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0, A, B, C)
图12-1. Symbolization
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PACKAGE OPTION ADDENDUM
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24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS56C215RNNR
TPS56C215RNNT
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RNN
RNN
18
18
3000 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR
-40 to 125
-40 to 125
56C215
56C215
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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24-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56C215RNNR
TPS56C215RNNT
TPS56C215RNNT
VQFN-
HR
RNN
RNN
RNN
18
18
18
3000
250
330.0
180.0
180.0
12.4
12.4
12.4
3.75
3.75
3.75
3.75
3.75
3.75
1.15
1.15
1.15
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS56C215RNNR
TPS56C215RNNT
TPS56C215RNNT
VQFN-HR
VQFN-HR
VQFN-HR
RNN
RNN
RNN
18
18
18
3000
250
346.0
210.0
213.0
346.0
185.0
191.0
33.0
35.0
35.0
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNN0018A
VQFN-HR - 1 mm max height
SCALE 3.200
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
3.6
3.4
30.000
ALTERNATE PIN 1 ID SHAPE
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
0.6
1.0
0.9
8X
0.35
0.25
2X
(0.2) TYP
7
6
8
5
4X 0.55
0.3
0.2
6X
2.5
2X
2X 0.65
2.3
PKG
2X
0.925
0.45
0.35
12
8X
2X
1
2X 0.575
SEE ALTERNATE
PIN 1 ID DETAIL
18
13
0.3
0.2
SYMM
0.45
0.35
7X
0.1
0.05
C B A
5X 0.5
2.5
0.45
0.35
C
ALL PADS
4222688/E 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RNN0018A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
2X (1.65)
5X (0.5)
SYMM
18
13
8X (0.6)
(1.65)
8X (0.25)
(R0.05) TYP
1
EXPOSED METAL
TYP
12
2X (0.925)
2X (0.4)
11
2X (0.35)
2
PKG
0.000
2X
(2.6)
2X (0.3)
(0.65)
2X (0.85)
8
2X (1.4)
5
6X (0.25)
8X (1.15)
6
7
2X (0.3)
2X (0.3)
8X (1.375)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
SOLDER MASK
OPENING
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
SOLDER MASK DETAILS
(PREFERRED)
4222688/E 03/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
RNN0018A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
(1.65)
5X (0.5)
SYMM
13
18
8X (0.6)
(1.65)
8X (0.25)
1
EXPOSED
METAL, TYP
2X (0.925)
2X (0.36)
12
6X (0.3)
2
11
2X (0.35)
(0.2825)
PKG
0.000
6X
(0.733)
2X (0.3)
(0.651)
2X (0.85)
2X (1.4)
8
5
(1.585)
6X (0.25)
8X (1.15)
EXPOSED METAL
TYP
EXPOSED METAL
TYP
7
6
8X (1.375)
(R0.05) TYP
(0.3) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 6 & 7: 83% - PADS 2 & 11: 90%
SCALE:30X
4222688/E 03/2021
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
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重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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