TPS57112C-Q1 [TI]
汽车 2.95V 至 6V、2A、2MHz 同步降压转换器;
| 型号： | TPS57112C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车 2.95V 至 6V、2A、2MHz 同步降压转换器 转换器 |
| 文件： | 总40页 (文件大小：2495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS57112C-Q1
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
TPS57112C-Q1 汽车类 2.95V 至 6V、2A、2MHz 同步降压转换器
1 特性
3 说明
1
•
符合汽车类 应用要求
TPS57112C-Q1 器件是一款具有两个集成 MOSFET
的全功能 6V、2A 同步降压电流模式转换器。
•
具有符合 AEC-Q100 标准的下列特性：
–
器件温度等级 1：–40°C 至 +125°C 的环境工作
温度范围
TPS57112C-Q1 器件集成了 MOSFET，通过实施电流
模式控制来减少外部组件数量，通过启用高达 2MHz
的开关频率来减小电感器尺寸，并借助小型 3mm ×
3mm 热增强型 QFN 封装最大限度减小 IC 尺寸，从而
实现小型设计。
–
–
器件 HBM ESD 分类等级 H2
器件 CDM ESD 分类等级 C3B
•
两个可在 2A 负载下获得高效率的 12mΩ（典型
值）MOSFET
•
•
200kHz 至 2MHz 开关频率
TPS57112C-Q1 器件可在工作温度范围内以 ±1% 的
电压基准 (Vref) 为多种负载提供精确调节。
在工作温度范围（–40°C 至 +150°C）内具有 0.8V
± 1% 电压基准
集成式 12mΩ MOSFET 和 515μA（典型值）的电源电
流，可最大限度提升效率。使用使能引脚进入关断模
式，可将电源电流降低至 5.5µA（典型值）。
•
•
•
•
•
•
与外部时钟同步
可调缓启动和排序
欠压 (UV) 和过压 (OV) 电源正常输出
–40°C 至 +150°C 的工作结温范围
热增强型 3mm × 3mm 16 引脚 WQFN 封装
与 TPS54418 引脚兼容
内部欠压锁定设置为 2.45V，但通过使能引脚上的电阻
器网络来设定阈值，可提高该设置。缓启动引脚可控制
输出电压启动斜升。一个开漏电源正常信号表示输出处
于其标称电压值的 93% 至 107% 之内。
2 应用
频率折返和热关断功能负责在过流情况下保护器件。
•
•
•
•
•
信息娱乐系统音响主机
混合仪表组
器件信息
器件型号
封装
封装尺寸（标称值）
远程信息处理控制单元
ADAS 摄像头模块
TPS57112C-Q1
WQFN (16)
3.00mm × 3.00mm
针对高性能 DSP、FPGA、ASIC 和微处理器的负
载点调节
1. 如需了解所有可用封装，请参阅数据表末尾的可订
购产品附录。
效率与输出电流间的关系
简化原理图
100
C(BOOT)
V(VIN) = 3 V
TPS57112C-Q1
95
V(VIN)
C(I)
VIN
BOOT
PH
90
V(VIN) = 5 V
R4
R5
L(O)
85
EN
VO
80
75
C(O)
R1
R2
70
65
PWRGD
VSENSE
SS/TR
RT/CLK
COMP
60
f(SW) = 500 kHZ
55
C(SS)
Rt
GND
VO = 1.8 V
50
AGND
R3
C1
0
0.5
1
1.5
2
Output Current (A)
Thermal Pad
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDU5
TPS57112C-Q1
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
Power Supply Recommendations...................... 31
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics Curves ................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 器件和文档支持 ..................................................... 34
11.1 器件支持................................................................ 34
11.2 文档支持................................................................ 34
11.3 接收文档更新通知 ................................................. 34
11.4 支持资源................................................................ 34
11.5 商标....................................................................... 34
11.6 静电放电警告......................................................... 34
11.7 Glossary................................................................ 34
12 机械、封装和可订购信息....................................... 35
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2018) to Revision A
Page
•
首次公开发布数据表 ............................................................................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TPS57112C-Q1
www.ti.com.cn
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN With Thermal Pad
Top View
16
15
14
13
VIN
VIN
1
2
3
4
12
11
10
9
PH
PH
Exposed Thermal Pad
GND
GND
PH
SS/TR
5
6
7
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AGND
NO.
5
—
Connect analog ground electrically to GND close to the device.
There is a requirement for a bootstrap capacitor between BOOT and PH. A voltage on this capacitor
that is below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor
recharges.
BOOT
13
O
Error amplifier output, and input to the output-switch current comparator. Connect frequency-
compensation components to this pin.
COMP
EN
7
O
I
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. One can use this
pin to set the on-off threshold (adjust UVLO) with two additional resistors.
15
3
GND
PH
—
O
Power ground. Connect this pin electrically to the thermal pad directly under the IC.
4
10
11
12
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
An open-drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent,
overvoltage, undervoltage, or EN shutdown.
PWRGD
RT/CLK
SS/TR
14
8
O
I
Resistor-timing or external-clock input pin
Slow-start and tracking. An external capacitor connected to this pin sets the output-voltage rise time.
Another use of this pin is for tracking.
9
I
1
2
VIN
I
Input supply voltage, 2.95 V to 6 V.
16
6
VSENSE
I
Inverting node of the transconductance (gm) error amplifier
Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any
internal PCB ground plane using multiple vias for good thermal performance.
Thermal pad
—
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS57112C-Q1
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
VIN
–0.3
7
EN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–2
7
BOOT
PH + 7
3
VSENSE
Input voltage
V
COMP
3
PWRGD
SS/TR
7
3
RT/CLK
BOOT-PH
7
7
Output voltage
Source current
Sink current
PH
7
V
PH 10-ns transient
EN
10
100
100
100
10
100
150
150
µA
RT/CLK
COMP
µA
mA
µA
°C
PWRGD
SS/TR
Junction temperature, TJ
Storage temperature, Tstg
–40
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
All pins
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 4, 5, 8, 9, 12, 13, 16)
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
6
UNIT
V(VIN)
TA
Input voltage
2.95
–40
V
Operating ambient temperature
125
°C
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS57112C-Q1
www.ti.com.cn
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
6.4 Thermal Information
TPS57112C-Q1
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
43.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
15.5
ψJT
0.7
ψJB
15.5
RθJC(bot)
3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN UVLO START (output turns on, device starts
switching)
2.45
2.28
2.6
2.5
Internal undervoltage lockout threshold
V
VIN UVLO STOP (output turns off, device stops
switching)
Shutdown supply current
Quiescent current – I(q)
V(EN) = 0 V, 25°C, 2.95 V ≤ V(VIN) ≤ 6 V
5.5
15
μA
μA
V(VSENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ
515
750
ENABLE AND UVLO (EN PIN)
Rising
1.25
1.18
Enable threshold
Input current
V
Falling
Enable threshold + 50 mV
Enable threshold – 50 mV
–3.2
μA
–1.65
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
2.95 V ≤ V(VIN) ≤ 6 V, –40°C <TJ < +150°C
0.79
0.8
0.811
V
MOSFET
BOOT-PH = 5 V
BOOT-PH = 2.95 V
V(VIN) = 5 V
12
16
13
17
30
30
30
30
High-side switch resistance
Low-side switch resistance
mΩ
mΩ
V(VIN) = 2.95 V
ERROR AMPLIFIER
Input current
2
nA
µS
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
245
Error amplifier transconductance (gm)
during slow start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
V(VSENSE) = 0.4 V
79
µS
Error amplifier source or sink
COMP to high-side FET current gm
CURRENT LIMIT
V(COMP) = 1 V, 100-mV overdrive
±20
14
μA
S
Current-limit threshold
THERMAL SHUTDOWN
Thermal shutdown
2.9
5.3
A
168
20
°C
°C
Hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using Rt
mode
200
400
2000
600
kHz
kHz
Switching frequency
Rt = 400 kΩ
500
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS57112C-Q1
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switching frequency range using CLK
mode
300
2000
kHz
RT/CLK voltage
Rt = 400 kΩ
0.5
1.6
V
V
RT/CLK high threshold
2.5
Delay from RT/CLK falling edge to PH Measure at 500 kHz with Rt resistor in series with
90
ns
rising edge
device pin
BOOT (BOOT PIN)
BOOT charge resistance
BOOT-PH UVLO
V(VIN) = 5 V
16
Ω
V(VIN) = 2.95 V
2.1
V
SLOW START AND TRACKING (SS/TR PIN)
Charge current
V(SS/TR) = 0.4 V
2
54
μA
mV
V
SS/TR to VSENSE matching
SS/TR to reference crossover
SS/TR discharge voltage (overload)
SS/TR discharge current (overload)
V(SS/TR) = 0.4 V
98% of nominal reference voltage
V(VSENSE) = 0 V
1.1
60
mV
µA
V(VSENSE) = 0 V, V(SS/TR) = 0.4 V
350
SS discharge current (UVLO, EN,
thermal fault)
V(VIN) = 5 V, V(SS/TR) = 0.5 V
1.9
mA
POWER GOOD (PWRGD PIN)
V(VSENSE) falling (Fault)
V(VSENSE) rising (Good)
V(VSENSE) rising (Fault)
V(VSENSE) falling (Good)
V(VSENSE) falling
91
93
VSENSE threshold
%Vref
109
107
2
Hysteresis
%Vref
nA
Ω
Output-high leakage
On-resistance
V(VSENSE) = Vref, V(PWRGD) = 5.5 V
7
56
100
1.5
Output low
I(PWRGD) = 3 mA
0.3
0.65
V
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
V
6.6 Timing Requirements
TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum CLK pulse duration
75
ns
6.7 Switching Characteristics
TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK low threshold
0.4
0.6
42
V
PLL lock-in time
Measure at 500 kHz
μs
PH (PH PIN)
Measured at 50% points on PH, IO = 2 A
Measured at 50% points on PH, V(VIN) = 6 V, IO = 0 A
Prior to skipping off pulses, BOOT-PH = 2.95 V, IO = 2 A
V(VIN) = 6 V, IO = 2 A
75
120
60
Minimum on-time
ns
Minimum off-time
Rise time
ns
2.25
2
V/ns
V/ns
Fall time
V(VIN) = 6 V, IO = 2 A
6
Copyright © 2018–2019, Texas Instruments Incorporated
TPS57112C-Q1
www.ti.com.cn
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
6.8 Typical Characteristics Curves
525
520
515
510
505
500
495
490
485
0.025
0.023
High-Side rDS(on), V(VIN) = 3.3 V
Low-Side rDS(on), V(VIN) = 3.3 V
0.021
0.019
0.017
0.015
0.013
0.011
0.009
0.007
0.005
High-Side rDS(on), V(VIN) = 5 V
Low-Side rDS(on), V(VIN) = 5 V
480
475
–50
–25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
Rt = 400 kΩ
V(VIN) = 5 V
图 2. Frequency versus Temperature
图 1. High-Side and Low-Side rDS(on) versus Temperature
0.807
8
0.805
0.803
0.801
0.799
0.797
0.795
0.793
0.791
7.5
V(VIN) = 2.95 V
7
V(VIN) = 3.3 V
6.5
6
5.5
5
V(VIN) = 6 V
4.5
V(VIN) = 5 V
4
-50
-25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
图 4. Voltage Reference versus Temperature
图 3. High-Side Current-Limit versus Temperature
100
75
2000
1800
1600
1400
1200
1000
800
V(VSENSE) Falling
V(VSENSE) Rising
50
25
0
600
400
200
80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
180
380
480
580
680
780
880
980
280
V(VSENSE) (V)
Resistance (kΩ)
图 5. Switching Frequency versus Rt Resistance, Low-
图 6. Switching Frequency versus VSENSE
Frequency Range
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TPS57112C-Q1
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Typical Characteristics Curves (接下页)
105
100
95
310
290
270
250
230
210
90
85
80
75
70
65
190
170
60
55
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
V(VIN) = 3.3 V
图 7. Transconductance versus Temperature
图 8. Transconductance (Slow Start) versus Junction
Temperature
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
–3
–3.1
V(VIN) = 3.3 V, rising
–3.2
–3.3
–3.4
–3.5
–3.6
–3.7
–3.8
V(VIN) = 3.3 V, falling
1.19
1.18
1.17
1.16
1.15
–3.9
–4
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 5 V
V(EN) = Threshold + 50 mV
图 9. EN Pin Voltage versus Temperature
图 10. EN Pin Current versus Temperature
–1
–1.2
–1.4
–1.6
–1.8
–2
–1.4
–1.6
–1.8
–2
–2.2
–2.4
–2.6
–2.2
–2.4
–2.6
–2.8
–3
–2.8
–3
–50
–25
0
25
50
75
100
125
150
–50 –30
–10 10
30
50
70
90
110
130 150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 5 V
V(EN) = Threshold – 50 mV
V(VIN) = 5 V
图 11. EN Pin Current versus Temperature
图 12. Charge Current versus Temperature
8
版权 © 2018–2019, Texas Instruments Incorporated
TPS57112C-Q1
www.ti.com.cn
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
Typical Characteristics Curves (接下页)
8
7
6
5
4
3
2
2.8
2.7
2.6
UVLO Start Switching
2.5
2.4
2.3
UVLO Stop Switching
2.2
1
0
2.1
2
–50
–25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 3.3 V
图 13. Input Voltage versus Temperature
图 14. Shutdown Supply Current versus Temperature
8
800
7
6
5
4
3
2
700
600
500
400
300
200
1
0
3
3.5
4
4.5
5
5.5
6
–50
–25
0
25
50
75
100
125
150
Input Voltage (V)
Junction Temperature (°C)
TJ = 25ºC
V(VIN) = 3.3 V
图 15. Shutdown Supply Current versus Input Voltage
图 16. VIN Supply Current versus Junction Temperature
800
110
108
106
700
600
500
400
V(VSENSE) Rising,
104
V(VSENSE) Falling,
PWRGD Deasserted
PWRGD Asserted
102
100
98
96
94
92
90
88
V(VSENSE) Rising,
PWRGD Asserted
V(VSENSE) Falling,
PWRGD Deasserted
300
200
3
3.5
4
4.5
5
5.5
6
–50 –25
0
25 75
Junction Temperature (°C)
50
100
125
150
Input Voltage (V)
TJ = 25ºC
V(VIN) = 5 V
图 17. VIN Supply Current versus Input Voltage
图 18. PWRGD Threshold versus Temperature
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TPS57112C-Q1
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www.ti.com.cn
Typical Characteristics Curves (接下页)
100
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
10
0
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
V(VIN) = 5 V
V(SS/TR) = 0.4 V
V(VIN) = 5 V
图 20. SS/TR-to-VSENSE Offset versus Temperature
图 19. PWRGD On-Resistance versus Temperature
10
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7 Detailed Description
7.1 Overview
The TPS57112C-Q1 device is a 6-V, 2-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients, the device implements a constant-
frequency, peak-current-mode control which reduces output capacitance and simplifies external frequency-
compensation design. The wide switching-frequency range of 200 kHz to 2000 kHz allows for efficiency and size
optimization when selecting the output-filter components. The switching-frequency adjustment uses a resistor to
ground on the RT/CLK pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that
synchronizes the power-switch turnon to the falling edge of an external system clock.
The TPS57112C-Q1 device has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup
current source that one can use to adjust the undervoltage lockout (UVLO) of the input voltage with two external
resistors. In addition, the pullup current provides a default condition that allows the device to operate when the
EN pin is floating. The total operating current for the TPS57112C-Q1 device is typically 515 μA when not
switching and under no load. When the device is disabled, the supply current is typically 5.5 μA.
The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents
up to 2 A.
The TPS57112C-Q1 device reduces the external component count by integrating the boot recharge diode. The
bias-voltage supply for the integrated high-side MOSFET is from a capacitor between the BOOT and PH pins. A
UVLO circuit monitors the boot-capacitor voltage and turns off the high-side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS57112C-Q1 device to operate approaching 100%
duty cycle. The lower limit for stepping down the output voltage is the 0.8-V reference.
The TPS57112C-Q1 device has a power-good comparator (PWRGD) with 2% hysteresis.
The TPS57112C-Q1 device minimizes excessive output overvoltage transients by taking advantage of the
overvoltage power-good comparator. The regulated output voltage exceeding 109% of the nominal voltage
activates the overvoltage comparator, turning off the high-side MOSFET and masking it from turning on until the
output voltage is lower than 107% of the nominal voltage.
A use of the SS/TR (slow-start or tracking) pin is to minimize inrush currents or provide power-supply sequencing
during power up. Couple a small-value capacitor to the pin for slow start. The SS/TR pin discharges before the
output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault, or disabled condition.
The use of a frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault
conditions to help limit the inductor current.
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7.2 Functional Block Diagram
PWRGD
EN
VIN
i(1)
i(hys)
Thermal
Shutdown
Shutdown
UVLO
Enable
Comparator
91%
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
109%
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
COMP Clamp
Current
Sense
ERROR
AMPLIFIER
PWM
Comparator
VSENSE
SS/TR
BOOT
Logic and PWM
Latch
Shutdown
Logic
Slope
Compensation
S
PH
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
With PLL
GND
TPS57112C-Q1 Block Diagram
AGND
Thermal Pad
RT/CLK
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS57112C-Q1 device uses an adjustable fixed-frequency peak-current-mode control. External resistors on
the VSENSE pin compare the output voltage to an internal voltage reference by an error amplifier that drives the
COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device performs a
comparison of the error-amplifier output to the high-side power-switch current. When the power-switch current
reaches the COMP voltage level, the high-side power switch turns off and the low-side power switch turns on.
The COMP pin voltage increases and decreases as the output current increases and decreases. The device
implements a current limit by clamping the COMP pin voltage to a maximum level, and also implements a
minimum clamp for improved transient-response performance.
7.3.2 Slope Compensation and Output Current
The TPS57112C-Q1 device adds a compensating ramp to the switch-current signal. This slope compensation
prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant
over the full duty-cycle range.
12
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Feature Description (接下页)
7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
The TPS57112C-Q1 device has an integrated boot regulator and requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic
capacitor should be 0.1 μF. TI recommends a ceramic capacitor with a voltage rating of 10 V or higher, and an
X7R or X5R grade dielectric because of the stable characteristics over temperature and voltage.
To improve dropout, the TPS57112C-Q1 device operates at 100% duty cycle as long as the BOOT-to-PH pin
voltage is greater than 2.2 V. A UVLO circuit turns off the high-side MOSFET, allowing for the low-side MOSFET
to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the
BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh
the capacitor; thus, the effective duty cycle of the switching regulator is high.
7.3.3.1 Error Amplifier
The TPS57112C-Q1 device has a transconductance amplifier that it uses as its error amplifier. The error
amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage
reference. The transconductance of the error amplifier is 245 μS during normal operation. When the voltage of
the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is typically greater
than 79 μS, but less than 245 μS. Placement of the frequency-compensation components is between the COMP
pin and ground.
7.3.4 Voltage Reference
The voltage-reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable band-gap circuit. The band-gap and scaling circuits produce 0.8 V at the non-inverting
input of the error amplifier.
7.4 Device Functional Modes
7.4.1 Adjusting the Output Voltage
A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using divider
resistors with 1% tolerance or better. Start with 100 kΩ for the R1 resistor and use 公式 1 to calculate R2. To
improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is
more susceptible to noise, and voltage errors from the VSENSE input current are noticeable.
æ
ç
è
ö
÷
ø
0.8 V
R2 = R1´
VO - 0.8 V
(1)
TPS57112C-Q1
V
O
R1
R2
VSENSE
-
0.8 V
+
图 21. Voltage-Divider Circuit
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Device Functional Modes (接下页)
7.4.2 Enable Functionality and Adjusting Undervoltage Lockout
The VIN pin voltage falling below 2.6 V disables the TPS57112C-Q1 device. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in to adjust the input voltage UVLO by using two external
resistors. TI recommends using the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6 V. Set the
rising threshold (VSTART) to provide enough hysteresis to allow for any input supply variations. The EN pin has an
internal pullup current source that provides the default condition of the TPS57112C-Q1 device operating when
the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 μA of hysteresis is added. Pulling
the EN pin below 1.18 V removes the 1.6 μA. This additional current facilitates input voltage hysteresis.
TPS57112C-Q1
I(hys)
VIN
1.6 mA
I(1)
R1
1.6 mA
+
EN
R2
-
图 22. Adjustable Undervoltage Lockout
æ
ç
ç
è
ö
÷
÷
ø
V
(ENFALLING)
V
- V
(STOP)
(START)
V
(ENRISING)
R1 =
æ
ç
(1) ç
è
ö
÷
÷
ø
V
(ENFALLING)
I
1-
+ I
(hys)
V
(ENRISING)
(2)
R1´ V
(ENFALLING)
R2 =
V
(STOP) - V(ENFALLING) + R1´(I(1) + I(hys))
where
•
•
•
•
I(hys) = 1.6 µA
I(1) = 1.6 µA
V(ENRISING) = 1.25 V
V(ENFALLING) = 1.18 V
(3)
7.4.3 Slow-Start or Tracking Pin
The TPS57112C-Q1 device regulates to the lower of the SS/TR pin or the internal reference voltage. A capacitor
on the SS/TR pin to ground implements a slow-start time. The TPS57112C-Q1 device has an internal pullup
current source of 2 μA that charges the external slow-start capacitor. 公式 4 calculates the required slow-start
capacitor value where t(SS/TR) is the desired slow-start time in ms, I(SS/TR) is the internal slow-start charging
current of 2 μA, and Vref is the internal voltage reference of 0.8 V.
t(SS/TR) (ms) ´ I(SS/TR) (mA)
C(SS/TR) (nF) =
V
(V)
ref
(4)
If during normal operation, VIN goes below UVLO, the EN pin goes below 1.2 V, or a thermal shutdown event
occurs, the TPS57112C-Q1 device stops switching. On VIN going above UVLO, the release of pulling high of
EN, or exit from a thermal shutdown, SS/TR discharges to below 60 mV before reinitiating a powering-up
sequence. The VSENSE voltage follows the SS/TR pin voltage with a 54-mV offset up to 85% of the internal
voltage reference. When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
14
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Device Functional Modes (接下页)
7.4.4 Sequencing
One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD
pins. Implementation of the sequential method uses an open-drain or open-collector output of a power-on-reset
pin of another device. shows the sequential method. Coupling power-good to the EN pin on the TPS57112C-Q1
device enables the second power supply once the primary supply reaches regulation.
Ratiometric start-up is achieved by connecting the SS/TR pins together. The regulator outputs ramp up and
reach regulation at the same time. When calculating the slow-start time, double the pullup current source in 公式
4. illustrates the ratiometric method.
TPS57112C-Q1
PWRGD
EN
EN
EN1
SS
SS
EN2
PWRGD
VO(1)
VO(2)
图 23. Sequential Start-Up Sequence
图 24. Sequential Start-up Using EN and PWRGD
TPS57112C-Q1
EN1
EN
SS
SS/TR1
PWRGD1
VO(1)
TPS57112C-Q1
EN2
VO(2)
SS/TR2
PWRGD2
图 25. Schematic for Ratiometric Start-Up
图 26. Ratiometric Start-up With VO(1) Leading VO(2)
Sequence
One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of
R1 and R2 shown in to the output of the power supply that requires tracking, or to another voltage reference
source. Using 公式 5 and 公式 6, one can calculate the tracking resistors to initiate VO(2) slightly before, after, or
at the same time as VO(1). VO(1) – VO(2) is 0 V for simultaneous sequencing. Including V(ssoffset) and I(SS/TR) as
variables in the equations minimizes both the effect of the inherent SS/TR-to-VSENSE offset (V(ssoffset)) in the
slow-start circuit, and the offset created by the pullup current source (I(SS)) and tracking resistors. Because of the
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Device Functional Modes (接下页)
requirement to pull the SS/TR pin below 40 mV before starting after an EN, UVLO, or thermal shutdown fault,
one must carefully select the tracking resistors to ensure the device can restart after a fault. Make sure the
calculated R1 value from 公式 5 is greater than the value calculated in 公式 7 to ensure the device can recover
from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(ssoffset) becomes
larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The
SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference, as shown
in 图 26.
VO(1)
V
(ssoffset)
R1 =
´
V
I(SS/TR)
ref
(5)
V
´ R1
ref
R2 =
VO(1) - V
ref
(6)
(7)
R1 > 2930´ VO(1) - 145 ´ (VO(1) - VO(2)
)
TPS57112C-Q1
BOOT1
EN1
PH1
EN1
SS2
VO(1)
SS/TR1
PWRGD1
VO(1)
VO(2)
TPS57112C-Q1
BOOT2
R1
R2
EN2
PH2
VO(2)
SS/TR2
VSENSE2
PWRGD2
图 27. Schematic for Ratiometric and Simultaneous 图 28. Ratiometric Start-Up Using Coupled SS/TR
Start-Up Sequence
Pins
7.4.5 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS57112C-Q1 device is adjustable over a wide range from 200 kHz to 2000
kHz by placing a resistor on the RT/CLK pin with a value calculated by 公式 8. An internal amplifier holds this pin
at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in 图 5 or 公式
8.
247 530 (MW/s)
1.0533
Rt kW =
( )
f(SW)
kHz
( )
(8)
131 904 (MW/s)
0.9492
f
kHz =
( )
(SW)
Rt
kW
( )
(9)
To reduce the solution size, set the switching frequency as high as possible, but consider tradeoffs of the
efficiency, maximum input voltage, and minimum controllable on-time.
The minimum controllable on-time is typically 65 ns at full-current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
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Device Functional Modes (接下页)
7.4.6 Overcurrent Protection
The TPS57112C-Q1 device implements a cycle-by-cycle current limit. During each switching cycle, a comparison
occurs between a voltage derived from the high-side switch current and the voltage on the COMP pin. When the
instantaneous switch-current voltage intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
increasing the switch current. An internal clamp on the error amplifier output functions as a switch-current limit.
7.4.7 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS57112C-
Q1 device implements a frequency shift. Without the frequency shift, during an overcurrent condition the low-side
MOSFET may not turn off long enough to reduce the current in the inductor, causing a current runaway. With
frequency shift, an overcurrent condition reduces the switching frequency from 100% to 50%, then 25%, as the
voltage decreases from 0.8 V to 0 V on the VSENSE pin. The frequency shift allows the low-side MOSFET to be
off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the
voltage on VSENSE increases from 0 V to 0.8 V. See 图 6 for details.
7.4.8 Reverse Overcurrent Protection
The TPS57112C-Q1 device implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
7.4.9 Synchronize Using the RT/CLK Pin
The RT/CLK pin can synchronize the converter to an external system clock. See . To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns.
If the square wave pulls the pin above the PLL upper threshold, a mode change occurs, and the pin becomes a
synchronization input. The CLK mode disables the internal amplifier, and the pin is a high-impedance clock input
to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the mode returns to the
frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher
than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of PH
synchronizes to the falling edge of the RT/CLK pin.
TPS57112C-Q1
SYNC Clock = 2 V/div
RT/CLK
PLL
PH = 2 V/div
Clock
Rt
Source
Time = 500 ns/div
图 29. Synchronizing to a System Clock
图 30. Plot of Synchronizing to System Clock
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Device Functional Modes (接下页)
7.4.10 Power Good (PWRGD Pin)
The PWRGD pin output is an open-drain MOSFET. The output goes low when the VSENSE voltage enters the
fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a
2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or
falls below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends using
a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. PWRGD is in a
valid state once the VIN input voltage is greater than 1.1 V.
7.4.11 Overvoltage Transient Protection
The TPS57112C-Q1 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold,
which is 109% of the internal voltage reference. A VSENSE pin voltage greater than the OVTP threshold
disables the high-side MOSFET, preventing current from flowing to the output and minimizing output overshoot.
The VSENSE voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on during
the next clock cycle.
7.4.12 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 148°C, the device reinitiates the power-up sequence
by discharging the SS pin to below 60 mV. The thermal shutdown hysteresis is 20°C.
7.4.13 Small-Signal Model for Loop Response
图 31 shows an equivalent model for the TPS57112C-Q1 control loop, which one can model in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μS. One can model the error amplifier using an ideal voltage-
controlled current source. Resistor R0 and capacitor C0 model the open-loop gain and frequency response of the
amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the
frequency-response measurements. Plotting a over c vs frequency shows the small-signal response of the
frequency compensation. Plotting a over b vs frequency shows the small-signal response of the overall loop. One
can check the dynamic loop response by replacing R(L) with a current source with the appropriate load-step
amplitude and step rate in a time-domain analysis.
PH
VO
Power Stage
14 S
a
b
R(ESR)
R1
R(L)
COMP
c
VSENSE
0.8 V
C(OUT)
R3
C1
C0
gm
245 µS
R0
C2
R2
图 31. Small-Signal Model for Loop Response
18
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Device Functional Modes (接下页)
7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
图 31 is a simple small-signal model that one can use to understand how to design the frequency compensation.
A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load
resistor approximates the TPS57112C-Q1 power stage. 公式 10 shows the control-to-output transfer function,
which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current
and the change in COMP pin voltage (node c in 图 31) is the power-stage transconductance. The gm for the
TPS57112C-Q1 device is 14 S. The low-frequency gain of the power-stage frequency response is the product of
the transconductance and the load resistance, as shown in 公式 11. As the load current increases and
decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem
problematic at first glance, but the dominant pole moves with load current [see 公式 12]. The dashed line in the
right half of 图 32 highlights the combined effect. As the load current decreases, the gain increases and the pole
frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it
easier to design the frequency compensation.
VO
V(C)
A(dc)
R(ESR)
f(p)
R(L)
gm(ps)
C(OUT)
f(z)
图 32. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
ö
s
1+
1+
ç
ç
è
÷
÷
ø
2p × f(z)
VO
= A(dc)
´
V
æ
ç
ç
è
ö
÷
÷
ø
(C)
s
2p × f(p)
(10)
(11)
A(dc) = gm(ps) ´ R(L)
1
f(p)
=
C
(OUT) ´ R(L) ´ 2p
(12)
(13)
1
f(z)
=
C
(OUT) ´ R(ESR) ´ 2p
7.4.15 Small-Signal Model for Frequency Compensation
The TPS57112C-Q1 device uses a transconductance amplifier for the error amplifier and readily supports two of
the commonly used frequency-compensation circuits. 图 33 shows the compensation circuits. The most likely
implementation of Type 2B circuits is in high-bandwidth power-supply designs using low-ESR output capacitors.
Type 2A includes one additional high-frequency pole to attenuate high-frequency noise.
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Device Functional Modes (接下页)
VO
R1
VSENSE
Type 2A
Type 2B
gm(ea)
COMP
Vref
R3
C1
R3
C1
R2
C0
5pF
R0
C2
图 33. Types of Frequency Compensation
20
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Device Functional Modes (接下页)
The design guidelines for TPS57112C-Q1 loop compensation are as follows:
1. Calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using 公式 14 and 公式 15. Derating the
output capacitor (C(OUT)) may be necessary if the output voltage is a high percentage of the capacitor rating.
Use the capacitor manufacturer information to derate the capacitor value. Use 公式 16 and 公式 17 to
estimate a starting point for the crossover frequency, f(c). 公式 16 is the geometric mean of the modulator
pole and the ESR zero, and 公式 17 is the mean of modulator pole and the switching frequency. Use the
lower value of 公式 16 or 公式 17 as the maximum crossover frequency.
IO(max)
f(p,mod)
=
2p´ VO ´ C(OUT)
(14)
1
f(z,mod)
=
2p´R(ESR) ´ C(OUT)
(15)
(16)
f(c)
=
f
(p,mod) ´ f(z,mod)
f(SW)
f(c)
=
f(p,mod)
´
2
(17)
2. Use 公式 18 to calculate the value of R3.
2p´ f(c) ´ VO ´ C(OUT)
R3 =
g
m(ea) ´ V ´ gm(ps)
ref
where
•
•
gm(ea) is the amplifier gain (245 μS)
gm(ps) is the power-stage gain (14 S)
(18)
1
f(p)
=
C
(OUT) ´ R(L) ´ 2p
3. Place a compensation zero at the dominant pole
4. Use 公式 19 to calculate the value of C1.
R
(L) ´ C(OUT)
C1 =
R3
(19)
(20)
5. The use of C2 is optional. If using C2 is necessary, use it to cancel the zero from the ESR of C(OUT)
.
R
(ESR) ´ C(OUT)
C2 =
R3
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Details on how to use this device in automotive applications appear throughout this device specification. The
following sections provide the typical application use case with equations and methods on selecting the external
components, as well as layout guidelines.
8.2 Typical Application
TPS57112C-Q1
2
图 34. High-Frequency, 1.8-V Output Power-Supply Design With Adjusted UVLO
8.2.1 Design Requirements
This example details the design of a high-frequency switching-regulator design using ceramic output capacitors.
A few parameters must be known to start the design process. These parameters are typically determined at the
system level. For this example, use the following known parameters:
PARAMETER
VALUE
Output voltage
1.8 V
Transient response for load step from 1 A to 2 A
Maximum output current
Input voltage
ΔV(OUT) = 5%
2 A
5 V nominal, 3 V to 6 V
< 30 mV p-p
1000 kHz
Output-voltage ripple
Switching frequency (f(SW)
)
22
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8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, one wants to choose the highest
switching frequency possible, because this produces the smallest solution size. The high switching frequency
allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a
lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the
performance of the converter. The converter is capable of running from 200 kHz to 2 MHz. Unless a small
solution size is an ultimate goal, select a moderate switching frequency of 1 MHz to achieve both a small solution
size and high-efficiency operation. Using 公式 8, calculate the value of R5 to be 180 kΩ. The choice for the
design is a standard 1% 182-kΩ value.
8.2.2.2 Output Inductor Selection
The inductor selected works for the entire TPS57112C-Q1 input-voltage range. To calculate the value of the
output inductor, use 公式 21. The k(IND) coefficient represents the amount of ripple current in the inductor relative
to the maximum output current. The output capacitor filters the inductor ripple current. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a
ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, k(IND) is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use k(IND) = 0.3; the calculated value of the inductor is 2.2 µH. For this design, the
choice is a nearest standard value of 1.5 μH. For the output-filter inductor, it is important not to exceed the rms
current and saturation current ratings. Use 公式 23 and 公式 24 to find the rms and peak inductor currents.
For this design, the rms inductor current is 2 A and the peak inductor current is 2.42 A. The chosen inductor is a
Coilcraft XLA4020-152ME_. It has a saturation current rating of 9.6 A and an rms current rating of 7.5 A.
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch-current limit rather than the peak inductor current.
VI(max) - VO
VO
L1 =
´
IO ´ k(IND)
V
I(max) ´ f(SW)
(21)
(22)
VI(max) - VO
VO
I(ripple)
=
´
L1
V
I(max) ´ f(SW)
æ
ö2
÷
÷
ø
VO ´ (VI(max) - VO )
VI(max) ´ L1 ´ f(SW)
1
2
I(Lrms)
=
IO
+
´ ç
ç
è
12
(23)
(24)
I(ripple)
I(Lpeak) = IO +
24
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8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for
the regulator where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after removal of the input power. The regulator is temporarily not able to supply sufficient output
current if there is a large, fast increase in the current needs of the load, such as transitioning from no load to a
full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load
current and output voltage and adjust the duty cycle to react to the change. Sizing of the output capacitor must
be adequate to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a
tolerable amount of droop in the output voltage. 公式 25 shows the minimum output capacitance necessary to
meet this requirement.
For this example, the transient load response is specified as a 5% change in VO for a load step from 0 A (no
load) to 1.5 A (50% load). For this example, ΔIO = 1.5 A – 0 A = 1.5 A and ΔVO = 0.05 × 1.8 = 0.09 V. Using
these numbers gives a minimum capacitance of 33 μF. This value does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation.
公式 26 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this
case, the maximum output-voltage ripple is 30 mV. Under this requirement, 公式 26 yields 2.3 µF.
2 ´ DIO
C(OUT)
>
f
(SW) ´ DVO
where
•
•
•
ΔIO is the change in output current
f(SW) is the switching frequency of the regulator
ΔVO is the allowable change in the output voltage
(25)
1
1
C(OUT)
>
´
VO(ripple)
8´ f(SW)
I(ripple)
where
•
•
•
f(SW) is the switching frequency
VO(ripple) is the maximum allowable output voltage ripple
I(ripple) is the inductor ripple current
(26)
公式 27 calculates the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. 公式 27 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Factor in additional capacitance de-ratings for aging, temperature, and dc bias, which increase this minimum
value. For this example, use two 22-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR.
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Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets
specify the root-mean-square (RMS) value of the maximum ripple current. One can use 公式 28 to calculate the
rms ripple current the output capacitor must support. For this application, 公式 28 yields 333 mA.
VO(ripple)
R(ESR)
<
I(ripple)
VO ´ (VI(max) - VO )
12 ´ VI(max) ´ L1 ´ f(SW)
(27)
I(Co,rms)
=
(28)
8.2.2.4 Input Capacitor
The TPS57112C-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at
least 4.7 μF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance
includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple-current rating greater than the maximum input ripple current of the
TPS57112C-Q1 device. Calculate the input ripple current using 公式 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. Minimize the capacitance variations due to temperature by selecting a dielectric material that is stable
over temperature. The usual selection for power regulator capacitors is an X5R or X7R ceramic dielectric,
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor selection must also take the dc bias into account. The capacitance value of a capacitor decreases as
the dc bias across a capacitor increases.
This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum
input voltage. The selection for this example is one 10-μF capacitor in parallel with one 0.1-μF capacitor, both
with 10-V ratings. The input capacitance value determines the input ripple voltage of the regulator. Use 公式 30
to calculate the input voltage ripple.
V
(
- VO
)
VO
I(min)
I(Ci,rms) = IO ´
´
VI(min)
VI(min)
(29)
(30)
I
O(max) ´ 0.25
DVI =
C(IN) ´ f(SW)
Using the design example values, IO(max) = 2 A, C(IN) = 10 μF, f(SW) = 1 MHz, yields an input voltage ripple of 50
mV and an RMS input ripple current of 0.98 A.
8.2.2.5 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. Slow start is useful if a load requires a controlled voltage-slew rate.
Another use for slow start is if the output capacitance is large and would require large amounts of current to
charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor
may make the TPS57112C-Q1 device reach the current limit, or excessive current draw from the input power
supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these
problems.
One can calculate the slow-start capacitor value using 公式 31. For the example circuit, the slow-start time is not
too critical because the output-capacitor value is 44 μF which does not require much current to charge to 1.8 V.
The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10 nF capacitor. In
the TPS57112C-Q1 device, I(SS/TR) is 2.2 μA and Vref is 0.8 V.
t(SS) (ms) ´ I(SS/TR) (mA)
C(SS) (nF) =
V
(V)
ref
(31)
26
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ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
8.2.2.6 Bootstrap Capacitor Selection
Connect a 0.1-μF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends using
a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage
rating.
8.2.2.7 Output Voltage and Feedback Resistor Selection
For the example design, the R6 selection is 100 kΩ. Using 公式 32, the calculated value of R7 is 80 kΩ. The
nearest standard 1% resistor is 80.5 kΩ.
V
ref
R7 =
´ R6
VO - V
ref
(32)
Because of the internal design of the TPS57112C-Q1 device, any given input voltage has a minimum output
voltage limit. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by 公式 33
V
O(min) = t(ONmin) ´ f(SWmax) ´ VI(max) - IO(min) ´ 2´ rDS(on) - I
(
´ R(L) + rDS(on)
O(min)
)
(
)
where
•
•
•
•
•
•
•
VO(min) = minimum achievable output voltage
t(ONmin) = minimum controllable on-time (65 ns typical. 120 ns no load)
f(SWmax) = maximum switching frequency, including tolerance
VI(max) = maximum input voltage
IO(min) = minimum load current
rDS(on) = minimum high-side MOSFET on-resistance (15 mΩ–19 mΩ)
R(L) = series resistance of output inductor
(33)
There is also a maximum achievable output voltage which is limited by the minimum off-time. The maximum
output voltage is given by 公式 34
VO(max) = 1- t(OFFmax) ´ f(SWmax) ´ V
(
- IO(max) ´ 2´rDS(on) - I
)
´ R(L) + rDS(on)
O(max)
) ( I(min)
(
)
where
•
•
•
•
•
•
•
VO(max) = maximum achievable output voltage
t(OFFmax) = maximum off-time (60 ns typical)
f(SWmax) = maximum switching frequency, including tolerance
VI(min) = minimum input voltage
IO(max) = maximum load current
rDS(on) = maximum high-side MOSFET on-resistance (19 mΩ–30 mΩ)
R(L) = series resistance of output inductor
(34)
8.2.2.8 Compensation
There are several industry techniques used to compensate dc-dc regulators. The method presented here is easy
to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60
and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS57112C-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually
lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more-accurate
design.
To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using 公式 35 and 公式 36. For
C(OUT), derating the capacitor is not needed, as the 1.8-V output is a small percentage of the 10-V capacitor
rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the
capacitor to derate the capacitor value. Use 公式 37 and 公式 38 to estimate a starting point for the crossover
frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. 公式 37 is the geometric mean
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of the modulator pole and the ESR zero, and 公式 38 is the mean of modulator pole and the switching frequency.
公式 37 yields 85.3 kHz and 公式 38 gives 54.9 kHz. Use the lower value of 公式 37 and 公式 38 as the
approximate crossover frequency. For this example, f(c) is 56 kHz. Next, calculate the compensation components.
Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel with these two
components forms the compensating pole (if needed).
IO(max)
f(p,mod)
=
2p´ VO ´ C(OUT)
(35)
1
f(z,mod)
=
2p´R(ESR) ´ C(OUT)
(36)
(37)
f(c)
=
f
(p,mod) ´ f(z,mod)
f(SW)
f(c)
=
f(p,mod)
´
2
(38)
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use 公式 39 to calculate the resistor value for the compensation
network. In this example, the anticipated crossover frequency (f(c)) is 56 kHz. The power-stage gain (gmps) is
14 S, and the error-amplifier gain (gmea) is 245 μS.
2p´ f(c) ´ VO ´ C(OUT)
R3 =
g
m(ea) ´ Vref ´ gm(ps)
(39)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the
capacitor for the compensation network from 公式 40.
R0´ C0
C3 =
R3
(40)
3. An extra pole can be added to attenuate high-frequency noise. In this application, the extra pole is not
necessary.
From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.
8.2.2.9 Power-Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous-conduction-mode (CCM)
operation. The power dissipation of the IC (PT) includes conduction loss (P(con)), dead-time loss (P(d)), switching
loss (P(SW)), gate-drive loss (P(gd)), and supply-current loss (P(q)).
2
P
= IO ´ rDS(on)(Temp)
(con)
where
•
IO is the output current (A)
•
rDS(on)(Temp) is the on-resistance of the high-side MOSFET with given temperature (Ω)
(41)
(42)
P
= f(SW)´ IO ´0.7´ 60´10-9
(d)
where
•
f(SW) is the switching frequency (Hz)
P
= 1/2 ´ VI ´ IO ´ f(SW) ´8´10-9
(SW)
where
•
VI is the input voltage (V)
(43)
(44)
(45)
P
= 2 ´ VI ´ f(SW) ´ 2´10-9
(gd)
P
= VI ´ 515´10-6
(q)
Therefore:
PT = P(con) + P(d) + P(SW) + P(gd) + P
(q)
28
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where
•
PT is the total device power dissipation (W)
(46)
For a given TA:
TJ = TA + RqJA ´ PT
where
•
•
•
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RθJA is the thermal resistance of the package (°C/W)
(47)
(48)
For a given TJ(max)
:
TA(max) = TJ(max) - RqJA ´ PT
where
•
•
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
Additional power losses occur in the regulator circuit because of the inductor ac and dc losses and trace
resistance that impact the overall efficiency of the regulator.
8.2.3 Application Curves
100
90
80
70
60
50
40
30
20
100
90
V(VIN) = 3.3 V
80
70
60
50
40
30
20
10
0
V(VIN) = 3.3 V
V(VIN) = 5 V
V(VIN) = 5 V
10
0
0
0.5
1
1.5
2
0.01
0.1
1
10
Output Current (A)
Output Current (A)
图 36. Efficiency versus Load Current
图 35. Efficiency versus Load Current
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VO = 1.8 V
VO = 1.05 V
VO = 1.8 V
VO = 1.05 V
VO = 3.3 V
55
50
55
50
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Current (A)
Output Current (A)
f(SW) = 1 MHz
V(VIN) = 3.3 V
f(SW) = 1 MHz
TA = 25ºC
V(VIN) = 5 V
TA = 25ºC
图 37. Efficiency versus Load Current
图 38. Efficiency versus Load Current
1 MHz, 3.3 VIN, TA = 25°C
1 MHz, 5 VIN, TA = 25°C
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V
= 2 V/div
V
= 2 V/div
(VIN)
(VIN)
EN = 1 V/div
EN = 1 V/div
SS/TR = 1 V/div
SS/TR = 1 V/div
V
= 1 V/div
O
V
= 1 V/div
O
Time = 5 ms/div
Time = 500 ms/div
图 39. Power-Up VO, V(VIN)
图 40. Power-Down VO, V(VIN)
V(VIN) = 5 V/div
VO = 100 mV/div (ac-coupled)
VO = 2 V/div
IO = 1 A/div (0-A to 1.5-A load step)
EN = 2 V/div
PWRGD = 5 V/div
Time = 5 ms/div
Time = 200 µs/div
图 42. Power-Up VO, V(VIN)
图 41. Transient Response, 1.5-A Step
V(VIN) = 5 V/div
VO = 20 mV/div (ac-coupled)
VO = 2 V/div
PH = 2 V/div
EN = 2 V/div
PWRGD = 5 V/div
Time = 500 ns/div
图 44. Output Ripple, 2 A
Time = 5 ms/div
图 43. Power-Up VO, EN
30
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ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
60
50
180
150
120
90
40
V(VIN) = 100 mV/div (ac coupled)
30
20
60
10
30
0
0
PH = 2 V/div
–10
–20
–30
–40
–50
–60
–30
–60
–90
–120
–150
Gain
Phase
–180
1M
10
100
1000
10k
100k
Frequency - Hz
Time = 400 ns/div
图 45. Input Ripple, 2 A
图 46. Closed-Loop Response, V(VIN) (5 V), 2 A
0.4
0.3
0.4
0.3
0.2
0.1
0
0.2
0.1
0
V(VIN) = 5 V
V(VIN) = 3.3 V
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
0.5
1
1.5
2
3
3.5
4
4.5
5
5.5
6
Output Current (A)
Input Voltage (V)
IO = 2 A
图 47. Load Regulation versus Load Current
图 48. Regulation versus Input Voltage
9 Power Supply Recommendations
By design, the TPS57112C-Q1 device works with an analog supply voltage range of 2.95 V to 6 V. Ensure good
regulation for the input supply, and connect the supply to the VIN pins with the appropriate input capacitor as
calculated in the Input Capacitor section. If the input supply is located more than a few inches from the
TPS57112C-Q1 device, the design may require extra capacitance in addition to the recommended value.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. There are several signal paths that conduct fast-
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass capacitor
connections and the VIN pins. See 图 49 for a PCB layout example. Tie the GND pins and AGND pin directly to
the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias
directly under the IC. One can use additional vias to connect the top-side ground area to the internal planes near
the input and output capacitors. For operation at full-rated load, the top-side ground area, along with any
additional internal ground planes, must provide adequate heat dissipating area.
Locate the input bypass capacitor as close to the IC as possible. Route the PH pins to the output inductor.
Because the PH connection is the switching node, locate the output inductor close to the PH pins, and minimize
the area of the PCB conductor to prevent excessive capacitive coupling. Also locate the boot capacitor close to
the device. Connect the sensitive analog ground connections for the following to a separate analog ground trace
as shown:
•
•
•
•
Feedback voltage divider
Compensation components
Slow-start capacitor
Frequency-set resistor
The RT/CLK pin is particularly sensitive to noise, so locate the RT resistor as close as possible to the IC and
route traces to minimize their lengths. One can place the additional external components approximately as
shown. It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout,
meant as a guideline, demonstrably produces good results.
32
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TPS57112C-Q1
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ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
BOOT
CAPACITOR
VIN
INPUT
OUTPUT
VIN
VIN
PH
PH
PH
SS
VOUT
BYPASS
CAPACITOR
INDUCTOR
OUTPUT
FILTER
EXPOSED
POWERPAD
AREA
CAPACITOR
GND
GND
PH
SLOW START
CAPACITOR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
图 49. PCB Layout Example
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11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
要获得更多 SWIFT™文档，请访问 TI 网站 www.ti.com.cn/swift。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
德州仪器 (TI)，为 TPS57112-Q1 启用功能和调节欠压锁定
德州仪器 (TI)，使用低阻抗外部时钟驱动器连接 TPS57xxx-Q1、TPS65320-Q1 系列以及 TPS65321-Q1 器件
德州仪器 (TI)，TPS57112-Q1 高频 (2.35MHz) 运行
德州仪器 (TI)，TPS57112EVM 用户指南
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
SWIFT, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
34
版权 © 2018–2019, Texas Instruments Incorporated
TPS57112C-Q1
www.ti.com.cn
ZHCSKI0A –APRIL 2018–REVISED NOVEMBER 2019
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS57112CQRTERQ1
ACTIVE
WQFN
RTE
16
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
7112Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS57112CQRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS57112CQRTERQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
重要声明和免责声明
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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Copyright © 2023，德州仪器 (TI) 公司
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