TPS59603QDSGRQ1 [TI]
适用于汽车应用中高频 CPU 内核电源的同步降压 FET 驱动器 | DSG | 8 | -40 to 125;
| 型号： | TPS59603QDSGRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车应用中高频 CPU 内核电源的同步降压 FET 驱动器 | DSG | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总22页 (文件大小：1695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
适用于汽车应用高频 CPU 内核电源的 TPS59603-Q1 同步降压 FET
驱动器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
TPS59603-Q1 驱动器针对高频 CPU VCORE 应用进行
了优化，具有 降低 死区时间驱动和自动零交越等高级
特性，可用于在整个负载范围内优化效率。
–
–
–
器件温度等级 1：-40°C 至 125°C
器件人体放电模式静电放电 (ESD) 分类等级 H2
器件的组件充电模式 ESD 分类等级 C3B
SKIP 引脚提供 CCM 操作选项，以支持输出电压的受
控管理。此外，TPS59603-Q1 支持两种低功耗模式。
借助于脉宽调制 (PWM) 输入三态，静态电流被减少至
130µA，并支持立即响应。当 SKIP 被保持在三态时，
电流被减少至 8µA（恢复切换通常需要 20µs）。此驱
动器与合适的德州仪器 (TI) 控制器配对使用，能够成
为出色的高性能电源系统。
•
•
针对已优化连续传导模式 (CCM) 的精简死区时间
驱动电路
针对已优化断续传导模式 (DCM) 效率的自动零交
叉检测
•
•
•
针对已优化轻负载效率的多个低功耗模式
为了实现高效运行的经优化信号路径延迟
集成 BST 开关驱动强度针对低 RdsON FET 进行
了优化
TPS59603-Q1 器件采用节省空间的耐热增强型 8 引
脚、2mm x 2mm 可湿性侧面 WSON 封装，工作温度
范围为 -40°C 至 125°C。
•
•
•
针对 5V FET 驱动器进行了优化
转换输入电压范围 (VIN)：2.5V 至 28V
具有可湿性侧面和散热焊盘的 2mm × 2mm、8 引
脚、WSON 封装
器件信息(1)
器件型号
封装
WSON (8)
封装尺寸（标称值）
TPS59603-Q1
2.00mm × 2.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
使用高频 CPU 的汽车后座娱乐 (RSE) 平板电脑
汽车 ADAS 处理器内核电源
简化应用
VIN
R1
C3
TPS59603-Q1
L1
Q1
1
2
3
4
BST
DRVH
SW
8
7
6
5
PWM
SKIP
VDD
PWM
SKIP
VDD
GND
DRVL
Q2
C1
C2
C4
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDL0
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
Power Supply Recommendations...................... 13
Layout ................................................................... 13
9.1 Layout Guidelines ................................................... 13
9.2 Layout Recommendation ........................................ 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 器件和文档支持 ..................................................... 14
10.1 器件支持................................................................ 14
10.2 文档支持................................................................ 14
10.3 社区资源................................................................ 14
10.4 商标....................................................................... 14
10.5 静电放电警告......................................................... 14
10.6 Glossary................................................................ 14
11 机械、封装和可订购信息....................................... 14
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (January 2020) to Revision A
Page
•
已更改 更改了“相关文档”部分的超链接................................................................................................................................. 14
2
Copyright © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
5 Pin Configuration and Functions
DSG Package
8-Pin WSON
Top View
1
8
7
6
5
BST
DRVH
PWM
2
3
4
SW
SKIP
VDD
GND
DRVL
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
BST
NO.
1
I
High-side N-channel FET bootstrap voltage input; power supply for high-side driver
High-side N-channel gate drive output
DRVH
DRVL
GND
8
O
O
G
5
Synchronous low-side N-channel gate drive output
6
Synchronous low-side N-channel gate drive return and device reference
PWM input. A tri-state voltage on this pin turns off both the high-side (DRVH) and low-side drivers
(DRVL)
PWM
2
3
I
When SKIP is LO, the zero crossing comparator is active. The power chain enters discontinuous
conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing
comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts
the driver into a very-low power state.
SKIP
I
SW
7
4
I/O
I
High-side N-channel gate drive return. Also, zero-crossing sense input
5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater
Tie to system GND plane with multiple vias
VDD
Thermal Pad
G
(1) I = Input, O = Output, G = Ground
Copyright © 2020, Texas Instruments Incorporated
3
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1) (2)
over operating free-air temperature (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
6
UNIT
VDD
Input voltage
V
PWM, SKIP
6
BST
35
38
6
BST (transient <20 ns)
BST to SW; DRVH to SW
Output voltage
SW
V
30
38
6
DRVH, SW (transient <20 ns)
DRVL
–5
–0.3
–0.3
–40
–55
Ground pins
GND to PAD
0.3
125
150
V
Operating junction temperature, TJ
Storage temperature range, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
5.5
5.5
34
UNIT
VDD
5
Input voltage
V
PWM, SKIP
–0.1
–0.1
–0.1
–1
BST
BST to SW; DRVH to SW
5.5
28
Output voltage
Ground pins
V
SW
DRVL
–0.1
–0.1
–40
5.5
0.1
125
GND to PAD
V
Operating junction temperature, TJ
°C
6.4 Thermal Information
TPS59603-Q1
THERMAL METRIC(1)
WSON (DSG)
8 PINS
63.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
74.1
34.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.0
ψJB
34.9
RθJC(bot)
11.7
(1) 有关传统和新热指标的更多信息，请参见应用报告《半导体和 IC 封装热指标》（文献编号：SPRA953）。
4
版权 © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
6.5 Electrical Characteristics
These specifications apply for –40°C ≤ TJ ≤ 125°C, and VVDD = 5 V unless otherwise specified.
PARAMETER
VDD INPUT SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSKIP = VVDD or VSKIP = 0 V,
PWM = High
160
250
600
VSKIP = VVDD or VSKIP = 0 V,
PWM = Low
ICC
Supply current (operating)
µA
VSKIP = VVDD or VSKIP = 0 V,
PWM = Float
130
8
VSKIP = Float
VDD UNDERVOLTAGE LOCKOUT (UVLO)
Rising threshold
Falling threshold
4.19
VUVLO
UVLO threshold
UVLO hysteresis
V
V
3.65
VUVHYS
0.2
PWM AND SKIP I/O SPECIFICATIONS
Pullup to VDD
1.7
MΩ
kΩ
V
RI
Input impedance
Pulldown (to GND)
800
VIL
Low-level input voltage
High-level input voltage
Hysteresis
0.6
2.0
VIH
2.70
1.3
V
VIHH
VTS
0.2
V
Tri-state voltage
V
Tri-state activation time (falling)
PWM
tTHOLD(off1)
tTHOLD(off2)
tTSKF
60
60
1
ns
ns
µs
µs
Tri-state activation time (rising)
PWM
Tri-state activation time (falling)
SKIP
Tri-state activation time (rising)
SKIP
tTSKR
1
t3RD(PWM)
t3RD(SKIP)
Tri-state exit time PWM
Tri-state exit time SKIP
100
50
ns
µs
HIGH-SIDE GATE DRIVER (DRVH)
DRVH rising, CDRVH = 3.3 nF; 20%
to 80%
tR(DRVH)
Rise time
30
40
ns
ns
tRPD(DRVH)
Rise time propogation delay
CDRVH = 3.3 nF
Source resistance,
RSRC
Source resistance
(VBST– VSW) = 5 V,
2
4
Ω
high state, (VBST – VDRVH) = 0.1 V
tF(DRVH)
Fall time
DRVH falling, CDRVH = 3.3 nF
CDRVH = 3.3 nF
8
ns
ns
tFPD(DRVH)
Fall-time propagation delay
25
Sink resistance,
RSNK
Sink resistance
(VBST – VSW) forced to 5 V,
low state (VDRVH – VSW) = 0.1 V
0.5
1.6
Ω
RDRVH
DRVH to SW resistance(1)
100
kΩ
(1) Specified by design. Not production tested.
版权 © 2020, Texas Instruments Incorporated
5
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
Electrical Characteristics (接下页)
These specifications apply for –40°C ≤ TJ ≤ 125°C, and VVDD = 5 V unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW-SIDE GATE DRIVER (DRVL)
DRVL rising, CDRVL = 3.3 nF; 20% to
80%
tR(DRVL)
Rise time
15
35
ns
ns
tRPD(DRVL)
Rise time propagation delay
CDRVL = 3.3 nF
Source resistance, (VVDD–GND) = 5
V,
RSRC
Source resistance
1.5
3
Ω
high state, (VVDD – VDRVL) = 0.1 V
tF(DRVL)
Fall time
DRVL falling, CDRVL = 3.3 nF
CDRVL= 3.3 nF
10
15
ns
ns
tFPD(DRVL)
Fall-time propagation delay
Sink resistance, (VVDD– GND) = 5 V,
low state, (VDRVL – GND) = 0.1 V
RSNK
Sink resistance
0.4
1.6
Ω
RDRVL
DRVL to GND resistance(1)
100
kΩ
GATE DRIVER DEAD-TIME
tR(DT)
tF(DT)
Rising edge
Falling edge
0
0
20
10
40
25
ns
ns
ZERO CROSSING COMPARATOR
VZX Zero crossing offset
BOOTSTRAP SWITCH
SW voltage rising
–2.25
0
120
12
2.00
mV
VFBST
IRLEAK
RDS(on)
Forward voltage
IF = 10 mA
240
2
mV
µA
Ω
Reverse leakage
On-resistance
(VBST – VVDD) = 25 V
24
6
版权 © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
6.6 Typical Characteristics
图 1. PWM High to DRVL Low
图 2. PWM Low to DRVH Low
图 3. DRVL Low to DRVH High
图 4. DRVH Low to DRVL High
图 5. PWM Low to Tri-State
图 6. PWM Tri-State to Low
版权 © 2020, Texas Instruments Incorporated
7
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
Typical Characteristics (接下页)
图 7. SKIP Mode Entry
图 8. SKIP Mode Exit
图 9. Very-Low-Power Mode Entry
图 10. Very-Low-Power Mode Exit
VIN = 8 V
VIN = 20 V
图 11. SW Node-Ringing
图 12. SW Node-Ringing
8
版权 © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
7 Detailed Description
7.1 Overview
The TPS59603-Q1 device is a synchronous-buck MOSFET driver designed to drive both high-side and low-side
MOSFETs. It allows high-frequency operation with current driving capability matched to the application. The
integrated boost switch is internal. The TPS59603-Q1 device employs dead-time reduction control and shoot-
through protection, which helps avoid simultaneous conduction of high-side and low-side MOSFETs. Also, the
drivers improve light-load efficiency with integrated DCM-mode operation using adaptive crossing detection.
Typical applications yield a steady-state duty cycle of 60% or less. For high steady-state duty cycle applications,
including a small external Schottky diode may help to ensure sufficient charging of the bootstrap capacitor.
7.2 Functional Block Diagram
VDD
+
DRVL
1
8
BST
+
Level Shift
DRVH
VUVLO
+
+
+
VDD
7
SW
1 V
1.7 MW
Tri-State
Logic
SKIP
3
800 kW
VDD
+
1 V
1.7 MW
4
5
VDD
Tri-State
Logic
PWM
2
DRVL
800 kW
6
GND
7.3 Feature Description
7.3.1 UVLO Protection
The UVLO comparator evaluates the VDD voltage level. As VVDD rises, both DRVH and DRVL hold actively low
at all times until VVDD reaches the higher UVLO threshold (VUVLO_H). Then, the driver becomes operational and
responds to PWM and SKIP commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H
–
Hysteresis), the device disables the driver and drives the outputs of DRVH and DRVL actively low. 图 13 shows
this function.
CAUTION
Do not start the driver in the very low power mode (SKIP = Tri-state).
版权 © 2020, Texas Instruments Incorporated
9
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
Feature Description (接下页)
V
UVLO_H
V
UVLO_L
V
VDD
Driver On
UDG-12218
图 13. UVLO Operation
7.3.2 PWM Pin
The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when
PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin
incorporates a weak pullup to maintain the voltage within the tri-state window during low-power modes.
Operation into and out of a tri-state condition follows the timing diagram outlined in 图 14.
When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The
window is defined as the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The
device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3-V
(typical) and 5-V (typical) PWM drive signals.
When the PWM exits the tri-state condition, the driver enters CCM for a period of 4 µs, regardless of the state of
the SKIP pin. Typical operation requires this time period in order for the auto-zero comparator to resume.
VIH
High-Z Window
High-Z Window
VIL
PWM
HDR
LDR
t3RD1
tFPD-DRVH
tHOLD_OFF1
tHOLD_OFF2
t3RD2
tFPD-DRVL
tR-DT
tF-DT
UDG-12225
Time
图 14. PWM Tri-State Timing Diagram
10
版权 © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
Feature Description (接下页)
7.3.3 SKIP Pin
The SKIP pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP is
low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current
is less than the critical current. When SKIP is high, the ZX comparator disables, and the converter enters FCCM
mode. When the SKIP pin is in a tri-state condition, typical operation forces the gate driver outputs low and the
driver enters a very-low-power state. In the low-power state, the UVLO comparator remains off to reduce
quiescent current. When the SKIP pin voltage is pulled either low or high, the driver wakes up and is able to
accept PWM pulses in less than 50 µs.
表 1 shows the logic functions of UVLO, PWM, SKIP, DRVH, and DRVL.
表 1. Logic Functions
UVLO
Active
PWM
—
SKIP
—
DRVL
Low
High(1)
High
Low
DRVH
Low
Low
Low
High
Low
Low
MODE
Disabled
DCM(1)
FCCM
Inactive
Inactive
Inactive
Inactive
Inactive
Low
Low
Low
High
High
Tri-state
—
H or L
H or L
Tri-state
Low
Low power
Low
Very-low power
(1) Until zero crossing protection occurs.
7.3.3.1 Zero Crossing (ZX) Operation
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy
load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,
which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects
the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the
rectifying MOSFET.
7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
The driver utilizes an anti-shoot-through and adaptive dead-time control to minimize low-side body diode
conduction time and maintain high efficiency. When the PWM input voltage becomes high, the low-side MOSFET
gate voltage begins to fall after a propagation delay. At the same time, DRVL voltage is sensed, and high-side
driving voltage starts to increase after DRVL voltage is lower than a proper threshold.
2.65 V
0.6 V
PWM
t
R-DRVL
t
RPD-DRVL
90%
4.0 V
DRVL
4.0 V
t
FPD-DRVL
1.0 V
10%
1.0 V
t
F-DRVL
90%
4.0 V
t
R-DRVL
4.0 V
t
t
F-DRVH
FPD-DRVH
t
RPD-DRVH
1.0 V
10%
1.0 V
DRVH
UDG-12226
Time
图 15. Rise and Fall Timing and Propagation Delay Definitions
版权 © 2020, Texas Instruments Incorporated
11
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
Typical operation manages to near zero the dead-time between the low-side gate turn-off to high-side gate
voltage turn-on, and high-side gate turn-off to low-side gate turn-on, in order to avoid simultaneous conduction of
both MOSFETs, as well as to reduce body diode conduction and recovery losses. This operation also reduces
ringing on the leading edge of the SW waveform.
PWM
DRVL
1.0 V
1.0 V
t
R-DT
t
F-DT
1.0V
DRVH
Time
UDG-12227
图 16. Dead-Time Definitions
7.3.5 Integrated Boost-Switch
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and BST pin is replaced by a FET, which is gated by the DRVL signal.
7.4 Device Functional Modes
The TPS59603-Q1 device operates in CCM mode when the SKIP pin is high, and it enters DCM mode when the
SKIP pin is low. When both the SKIP pin and the PWM pin are in a tri-state condition, it forces the gate driver
outputs low and the driver enters a very-low-power state.
12
版权 © 2020, Texas Instruments Incorporated
TPS59603-Q1
www.ti.com.cn
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
8 Power Supply Recommendations
The voltage range for the VDD pin is between 4.5 V and 5.5 V. A 5-V power supply is recommended for the VDD
pin of the TPS59603-Q1 device.
9 Layout
9.1 Layout Guidelines
To improve the switching characteristics and design efficiency, these layout rules must be considered:
•
•
•
Locate the driver as close as possible to the MOSFETs.
Locate the VDD and bootstrap capacitors as close as possible to the driver.
Pay special attention to the GND trace. Use the thermal pad of the package as the GND by connecting it to
the GND pin. The GND trace or pad from the driver goes directly to the source of the MOSFET, but should
not include the high current path of the main current flowing through the drain and source of the MOSFET.
•
•
Use a similar rule for the switch-node as for the GND.
Use wide traces for DRVH and DRVL closely following the related SW and GND traces. A width of between
80 and 100 mils is preferable where possible.
•
•
Place the bypass capacitors as close as possible to the driver.
Avoid PWM and enable traces going close to the SW and pad where high dV/dT voltage can induce
significant noise into the relatively high-impedance leads.
A poor layout can decrease the reliability of the entire system.
9.2 Layout Recommendation
图 17 above shows the primary current loops in each phase, numbered in order of importance.
The most important loop to minimize the area of is loop 1, the path from the input capacitor through the high and
low-side FETs, and back to the capacitor through ground.
Loop 2 is from the inductor through the output capacitor, ground, and Q2. The layout of the low-side gate drive
(Loops 3a and 3b) is important. The guidelines for the gate drive layout are:
•
•
•
Make the low-side gate drive length as short as possible (1 inch or less preferred).
Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.
If changing layers is necessary, use at least two vias.
VBAT
CB
CIN
1
Q1
4b
DRVH
4a
L
VCORE
LL
2
Q2
CD
DRVL
3a
COUT
3b
PGND
UDG-12191
图 17. Layout recommendations to minimize major Current loops
版权 © 2020, Texas Instruments Incorporated
13
TPS59603-Q1
ZHCSKR9A –JANUARY 2020–REVISED MARCH 2020
www.ti.com.cn
10 器件和文档支持
10.1 器件支持
10.1.1 开发支持
有关 Power Stage Designer，请转到常用开关模式电源的 Power Stage Designertm 工具
10.2 文档支持
10.2.1 相关文档
《适用于汽车 ADAS 应用的 TPS59632-Q1 2.5V 至 24V、三相/两相/单相降压无驱动器控制器》数据表
10.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 商标
E2E is a trademark of Texas Instruments.
10.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
14
版权 © 2020, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS59603QDSGRQ1
TPS59603QDSGTQ1
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
603Q
603Q
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008B
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.1 MIN
(0.05)
PIN 1 INDEX AREA
S
C
A
L
E
3
0
.
A
2.1
1.9
SECTION A-A
TYPICAL
0.3
0.2
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
A
A
2X
1.5
9
1.6 0.1
8
1
0.3
8X
0.2
0.4
0.2
PIN 1 ID
8X
0.1
0.05
C A B
C
4222124/E 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222124/E 05/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222124/E 05/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明