TPS59632QRHBTQ1 [TI]

2.5V 至 24V、三相/两相/单相降压无驱动器控制器

| RHB | 32 | -40 to 125;


型号：	TPS59632QRHBTQ1
厂家：	TEXAS INSTRUMENTS
描述：	2.5V 至 24V、三相/两相/单相降压无驱动器控制器 \| RHB \| 32 \| -40 to 125 驱动控制器开关驱动器
文件：	总56页 (文件大小：2872K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

适用于汽车 ADAS 应用的 TPS59632-Q1 2.5V 至 24V、三相/两相/单相降

压无驱动器控制器

1 特性

2 应用

•

符合面向汽车应用的 AEC-Q100 标准

•

高级驾驶辅助系统 (ADAS)

条件式自动驱动控制器

–

温度等级 1：–40°C 至 125°C

人体放电模型 ESD 分类等级 H2

带电器件模型 ESD 分类等级 C3B

汽车信息娱乐系统和仪表组

3 说明

•

可选相位数：3、2 或 1

TPS59632-Q1 器件是一款三相降压无驱动器控制器，

具有许多高级功能，例如具有输出电压过冲衰减

(OSR) 和下冲衰减 (USR) 功能的 D-CAP+™控制架

构，可实现极快的瞬态响应、超低的输出电容和高效

率。该器件支持 I²C 接口，能够实现输出电压动态控

制、可优化效率的相位管理以及电流监控器遥测。

TPS59603-Q1 MOSFET 栅极驱动器专用于与此控制

器配合工作，以驱动同步降压转换器功率级

转换电压范围：2.5V 至 24V（相位数、开关频率和

最大输出电压限制适用）

•

7 位 DAC 电压范围：0.50V 至 1.52V

支持预设引导，DAC 电压 0.800V

精确、可调节的直流负载线（压降）或零斜率负载

线

•

D-CAP+™控制，可实现快速瞬态响应

已获专利的 AutoBalance™相位均衡技术

8 种开关频率设置（300kHz 至 1MHz）

MOSFET。TPS59632-Q1 器件采用节省空间的 5mm

× 5mm、热增强型 32 引脚 QFN 封装（间距为

0.5mm），额定工作温度范围为 –40°C 至 125°C。

8 级独立的输出电压过冲衰减 (OSR) 和下冲衰减

(USR)

•

可选 8 级电流限制

器件信息⁽¹⁾

负载电流监视器（模拟和数字）

可选 8 级电压压摆率

器件型号

封装

封装尺寸（标称值）

TPS59632-Q1

VQFN (32)

5mm × 5mm

优化了轻负载和重负载条件下的效率

I²C 接口适用于 VID 控制、相位管理和遥测（具有

8 个器件地址）

•

采用 5mm x 5mm、32 引脚、间距为 0.5mm 的

QFN 封装（具有电源板和可湿性侧面）

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化应用

High-Side

Low-Side

MOSFETs

TPS59603-Q1 Gate Drive

TPS59632-Q1

PWM1

I²C BUS

High-Side

Low-Side

MOSFETs

PWM2

VOUT

TPS59603-Q1 Gate Drive

PWM3

SKIP

High-Side

Low-Side

MOSFETs

TPS59603-Q1 Gate Drive

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDL4

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

8.1 Application Information............................................ 29

8.2 Typical Application .................................................. 29

Power Supply Recommendations...................... 38

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 9

6.7 Switching Characteristics.......................................... 9

6.8 Typical Characteristics............................................ 11

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

7.4 User Selections....................................................... 25

7.5 I²C Interface Operation ........................................... 25

7.6 I²C Register Maps................................................... 27

Applications and Implementation ...................... 29

10 Layout................................................................... 39

10.1 Layout Guidelines ................................................. 39

10.2 Layout Example ................................................... 39

10.3 Current Sensing Lines .......................................... 40

10.4 Feedback Voltage Sensing Lines ......................... 40

10.5 PWM And SKIP Lines........................................... 40

10.6 Power Chain Symmetry ........................................ 40

10.7 Component Location............................................. 40

10.8 Grounding Recommendations .............................. 41

10.9 Decoupling Recommendations ............................. 41

10.10 Conductor Widths................................................ 41

11 器件和文档支持 ..................................................... 42

11.1 文档支持................................................................ 42

11.2 商标....................................................................... 42

11.3 静电放电警告......................................................... 42

11.4 Glossary................................................................ 42

12 机械、封装和可订购信息....................................... 43

13 Package Option Addendum ............................... 44

13.1 Packaging Information .......................................... 44

13.2 Tape And Reel Information................................... 45

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2020 年 2 月

初始发行版

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

5 Pin Configuration and Functions

RHB Package

32-Pin QFN

(Top View)

SDA

VDD

VFB

GFB

PGOOD

PWM3

PWM2

PWM1

SKIP

CSN3

CSP3

CSP2

CSN2

CSN1

CSP1

Thermal

Pad

(Not to scale)

Pin Functions

I/O

DESCRIPTION

NAME

COMP

NO.

Error amplifier summing node. Resistors from VREF to COMP (R_COMP) and COMP to DROOP (R_DROOP) set

the droop gain.

CSP1

CSP2

CSP3

CSN1

CSN2

CSN3

Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR

sense network. Tie CSP3, CSP2, or CSP1 (in that order) to 3.3 V to disable the phase.

Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR

sense network. CSN1 has a secondary OVP comparator and includes the soft-stop pulldown transistor.

Error amplifier output. A resistor pair from VREF to COMP to DROOP sets the droop gain. A_DROOP= 1 +

DROOP

R_DROOP/ R_COMP

Enable; 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when brought

low.

R to GND sets the per phase switching frequency. MUST connect a resistor to VREF to ensure this pin

voltage is above 0.8 V for proper operation.

FREQ-P

GFB

Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when µP is not

populated.

GND

–

Analog circuit reference; tie to a quiet point on the ground plane.

IMON

Analog current monitor output. V_IMON= Σ V_ISENSE× (1 + R_IMON/ R_OCP).

Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). R to GND (R_OCP) selects 1 of 8

OCP levels (per phase, latched at start-up).

OCP-I

I/O

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Voltage divider to the VREG pin. Connect a resistor to GND to select the pulse-truncation level and OSR

level. Voltage at O-USR selects the USR level.

O-USR

Provides pullup resistance to VREF through 10-kΩ resistor.

PAD

GND

–

Thermal pad; tie to the ground plane with multiple vias.

Power Good output; Open-drain. PGOOD can be configured to go low when the current reaches 70% of the

OCP setting value.

PGOOD

PWM1

PWM2

PWM3

PWM controls for the external driver; 5-V logic level. Controller forces signal to the 3-state level when

needed.

Voltage divider to VREF. Connect a resistor to GND to set the ramp setting voltage. The RAMP setting can

override the factory ramp setting.

RAMP

NC No connect. Leave pins floating.

l²C digital clock line.

I/O I²C digital data line.

SCL

SDA

This pin is active high to operate synchronous buck MOSFETs in Forced Continuous Conduction Mode

SKIP

(FCCM) active low for skip mode operation. This pin must be connected to the corresponding pin of the

drivers for this function.

The voltage sets the 3 LSBs of the I²C address. The resistance to GND selects 1 of 8 slew rates. The start-

up slew rate (EN transitions high) is SLEWRATE / 2. The ADDRESS and SLEWRATE values are latched at

start-up.

SLEWA

VINTF

V5A

Input voltage to power I²C interface logic. Can be tied to VDD if 3.3-V logic signals are needed.

5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥ 1-µF

ceramic capacitor

VBAT

VDD

10-kΩ resistor to VBAT provides VBAT information to the on-time circuits for both converters.

3.3-V digital power input; bypass to GND with ≥ 1-µF capacitor.

Voltage sense line. Tie directly to V_OUTsense point of processor. Tie to V_OUTon PCB with a 10-Ω resistor to

VFB

provide feedback when the microprocessor is not populated. The resistance between VFB and GFB is > 1

MΩ.

VREF

1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V5A

–0.3

6.0

VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3,

VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC

-0.3

3.6

Input voltage

VBAT

–0.3

–0.2

–0.3

–40

3.6

0.2

3.6

6.0

150

COMP

GFB

PGOOD, IMON, VREF, DROOP

PWM3, PWM2, PWM1, SKIP

Output voltage

Junction temperature range, T_J

Storage Temperature T_stg

°C

–55

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC-Q100 Classification

Level H2

±2000

V_(ESD)

Electrostatic Discharge

Charged device model (CDM), per AEC-Q100 Classification

Level C3B

±750

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V5A

–0.1

5.5

VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3,

VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC

-0.1

3.5

Input voltage

VBAT

–0.1

–40

3.5

0.1

3.5

5.5

125

COMP

GFB

PGOOD, IMON, VREF, DROOP

PWM3, PWM2, PWM1, SKIP

Output voltage

Operating junction temperature, T_J

°C

6.4 Thermal Information

TPS59632-Q1

THERMAL METRIC⁽¹⁾

RSM (VQFN)

32 PINS

37.2

UNITS

R_θJA

Junction-to-ambient thermal resistance

R_θJCtop

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31.9

8.1

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

7.9

R_θJCbot

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

6.5 Electrical Characteristics

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_OUT, 0.7 < VFREQ-

P ≤ V_VREF(unless otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET

I_V5-3P

V5A supply current, 3-phase

VDD supply current, 3-phase

V5A supply current, 1-phase

VDD supply current, 1-phase

V_VDAC< V_VFB< (V_VDAC+ 100 mV), EN = ‘HI’

3.6

0.2

3.5

0.2

6.0

0.8

6.0

0.8

V_VDAC< V_VFB< (V_VDAC+ 100 mV) , EN = ‘HI’; digital

buses idle

I_VDD-3P

I_V5-1P

VDAC < VFB < (V_VDAC+ 100 mV) EN = ‘HI’

VDAC < VFB < (V_VDAC+ 100 mV), EN = ‘HI’; digital

buses idle

I_VDD-1P

I_V5STBY

I_VDDSTBY

I_VINTF

V5A standby current

VDD standby current

VINTF supply current

EN = ‘LO’

125

200

EN = ‘LO’

µA

All conditions; digital buses idle

1.7

5.0

V_VFB< 200 mV. Ramp up; V_VDD> 3 V; EN = ’HI’;

Switching begins.

V_UVLOH

V_UVLOL

V_5POR

V5A UVLO ‘OK’ threshold

V5A UVLO fault threshold

V5A fault latch reset threshold

VDD UVLO ‘OK’ threshold

Fault threshold

4.2

4.00

1.2

4.4

4.2

1.9

2.8

2.6

4.52

4.35

2.5

Ramp down; EN = ’HI’; V_VDD> 3 V; V_VFB= 100 mV.

Switching stops

Ramp down. EN = ‘HI’; V_VDD> 3 V. Can restart if

V5A rises to V_UVLOH, and no other faults present.

V_VFB< 200 mV. Ramp up; V_V5A> 4.5 V; EN = ’HI’;

Switching begins.

V_3UVLOH

V_3UVLOL

2.5

3.0

Ramp down; EN = ’HI’; V5A > 4.5 V; VFB = 100

mV. Switching stops.

2.4

2.8

Ramp down. EN = ‘HI’; V5A > 4.5 V. Can restart if

VDD goes up to V_3UVLOH, and no other faults

present.

V_3POR

VDD fault latch

1.2

1.9

2.5

V_INTFUVLOH

V_INTFUVLOL

VINTF UVLO OK

Ramp up; EN = ’HI’; V5A > 4.5 V; VFB = 100 mV.

1.4

1.3

1.5

1.4

1.6

1.5

Ramp down; EN = ’HI’; V5A > 4.5 V; VFB = 100

mV.

VINTF UVLO falling

REFERENCES: VDAC, VREF, BOOT Voltage

V_VIDSTP

V_DAC1

VID step size

Change VID0 HI to LO to HI

1.36 V ≤ V_VFB≤ 1.52 V, I_OUT= 0 A

1.0 V ≤ V_VFB≤ 1.35 V; I_OUT= 0 A

0.5 V ≤ V_VFB≤ 0.99 V; I_OUT= 0 A

VREF output 4.5 V ≤ V_V5A≤ 5.5 V, I_VREF= 0 A

0 A ≤ I_REF≤ 500 µA, HP-2

–9

–8

V_DAC2

VFB tolerance

V_DAC3

–7

V_VREF

VREF output

1.66

–4

1.700

–3

1.74

V_VREFSRC

V_VREFSNK

V_VBOOT

VREF output source

VREF output sink

–500 A ≤ I_REF≤ 0 A, HP-2

Internal VFB initial boot voltage Initial DAC boot voltage

0.8

DIFFERENTIAL VOLTAGE SENSE: VFB AND GFB

Not in fault, disable, or UVLO, V_VFB= V_DAC= 1.5 V

V_GFB= 0 V, measure from VFB to GFB

R_VFB

VFB/GFB Input resistance

MΩ

V_DELGND

GFB Differential

GND to GFB

±100

ERROR AMPLIFIER, CURRENT AMPLIFIER, CURRENT SHARE

Error amplifier total voltage

A_V-EA

VFB to DROOP

gain⁽¹⁾

I_{EA_SR}

I_{EA_SK}

I_CS

Error amplifier source current

Error amplifier sink current

CS pin input bias current

I_DROOP, V_VFB= V_DAC+ 50 mV, R_COMP= 1 kΩ

I_DROOP, V_VFB= V_DAC–50 mV, R_COMP= 1 kΩ

CSPx and CSNx

–1

–500

5.8

0.2

500

6.2

Gain from CSPx – CSNx to PWM comparator,

R_SKIP= Open

A_CSINT

Internal current sense gain

6.0

V/V

V_DAC= 1.70 V, V_CSP1– V_CSN1= V_CSP2– V_CSN2

V_CSP3– V_CSN3= V_{OCPP_MIN}

I_{BAL_TOL}

Internal current share tolerance

–3%

+3%

(1) Specified by design. Not production tested.

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

Electrical Characteristics (continued)

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_OUT, 0.7 < VFREQ-

P ≤ V_VREF(unless otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

RAMP SETTINGS

V_RAMP

R_RAMP= 20 kΩ +/- 1%

R_RAMP= 30 kΩ +/- 1%

R_RAMP= 39 kΩ +/- 1%

Compensation ramp amplitude

100

R_RAMP≥ 150 kΩ +/- 1%

SLEW SETTINGS

SL_SET

R_SLEW= 20 kΩ +/- 1%

R_SLEW= 24 kΩ +/- 1%

R_SLEW= 30 kΩ +/- 1%

R_SLEW= 39 kΩ +/- 1%

EN goes high, R_SLEW= 20 kΩ

Slew rate setting for VID

change

mV/µs

(2)

SL_START

Slew rate setting for start-up

ADDRESS SETTINGS

V_SLEWA≤ 0.25 V

000b

001b

010b

011b

100b

101b

110b

111b

0.35 V ≤ V_SLEWA≤ 0.45 V

0.55 V ≤ V_SLEWA≤ 0.65 V

0.75 V ≤ V_SLEWA≤ 0.85 V

0.95 V ≤ V_SLEWA≤ 1.05 V

1.15 V ≤ V_SLEWA≤ 1.25 V

1.35 V ≤ V_SLEWA≤ 1.45 V

1.55 V ≤ V_SLEWA≤ V_VREF

Address setting 3 LSB of I²C

Address (ADDR = 100 0xxx)

ADDR

OVERSHOOT REDUCTION (OSR) SETTINGS

R_O-USR= 20 kΩ +/- 1%

R_O-USR= 24 kΩ +/- 1%

R_O-USR= 30 kΩ +/- 1%

R_O-USR= 39 kΩ +/- 1%

R_O-USR= 56 kΩ +/- 1%

R_O-USR= 75 kΩ +/- 1%

R_O-USR= 100 kΩ +/- 1%

R_O-USR= 150 kΩ +/- 1%

100

150

200

250

300

400

500

OFF

Overshoot Reduction (OSR)

Voltage set

V_OSR

(3)

UNDERSHOOT REDUCTION (USR) SETTINGS

V_O-USR< 0.25 V

0.35 < V_O-USR< 0.45 V

0.55 < V_O-USR< 0.65 V

0.75 < V_O-USR< 0.85 V

0.95 < V_O-USR< 1.05 V

1.15 < V_O-USR< 1.25 V

1.35 < V_O-USR< 1.45 V

1.55 < V_O-USR< V_VREF

120

160

200

240

OFF

Undershoot Reduction (USR)

Voltage set

V_USR

(4)

OVER CURRENT PROTECTION (OCP) SETTINGS

(2) Specified by design. Not production tested.

(3) Specified by design. Not production tested.

(4) Specified by design. Not production tested.

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_OUT, 0.7 < VFREQ-

P ≤ V_VREF(unless otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

R_OCP-I= 20 kΩ +/- 1%

5.0

7.0

9.0

R_OCP-I= 24 kΩ +/- 1%

R_OCP-I= 30 kΩ +/- 1%

R_OCP-I= 39 kΩ +/- 1%

R_OCP-I= 56 kΩ +/- 1%

R_OCP-I= 75 kΩ +/- 1%

R_OCP-I= 100 kΩ +/- 1%

R_OCP-I= 150 kΩ +/- 1%

7.0

10.0

14.0

19.0

25.0

32.0

40.0

49.0

13.0

18.0

23.0

29.0

36.0

44.0

53.0

10.0

15.0

21.0

28.0

36.0

45.0

OCP voltage (valley current limit

at CSPx – CSNx)

V_OCP

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

Electrical Characteristics (continued)

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_OUT, 0.7 < VFREQ-

P ≤ V_VREF(unless otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT MONITOR (IMON)

∑∆CS = 0 mV, A_IMON= 3.867

00h

12h

79h

FAh

00h

19h

80h

FFh

03h

20h

87h

FFh

∑∆CS = 4.5 mV, A_IMON= 3.867

∑∆CS = 22 mV, A_IMON= 3.867

∑∆CS = 44 mV, A_IMON= 3.867

Each phase, CSPx – CSNx

VAL_ADC

IMON ADC output

IMON linear range

LR_IMON

PROTECTION: OVP, UVP, PGOOD

V_OVPH

Fixed OVP voltage

V_CSN1> V_OVPHfor 1 µs

Connected to CSN1

1.60

1.70

100

1.80

200

R_SFTSTP

Soft-stop transistor resistance

Measured at the VFB pin with respect to VID code,

device latches OFF

V_PGDH

V_PGDL

PGOOD high threshold

PGOOD low threshold

185

245

Measured at the VFB pin with respect to VID code,

device latches OFF

–348

–280

PWM AND SKIP OUTPUTS: I/O VOLTAGE AND CURRENT

V_{P-S_L}

PWMx / SKIP – Low

PWMx / SKIP – High

PWMx / SKIP 3-state

I_LOAD= ± 1 mA

I_LOAD= ± 100 µA

0.15

1.7

0.3

1.8

V_{P-S_H}

4.2

1.6

V_PW-SKLK

LOGIC INTERFACE: VOLTAGE AND CURRENT

R_VRTTL

SDA, V = 0.31 V

–2

Pulldown resistance

R_VRPG

µA

PGOOD, V = 0.31 V

I_VRTTLK

V_IL,I2C

V_IH,I2C

V_IL,EN

V_IH,EN

I_ENH

Logic leakage current

Low-level input voltage

High-level input voltage

EN Low-level input voltage

EN High-level input voltage

I/O leakage, EN

SDA, SCL = 1.8 V, PGOOD = 3.3 V

0.2

0.6

SCL, SDA, VINTF = 1.8 V

1.2

1.3

0.5

Leakage current , V_EN= 1.8 V

µA

VBAT INPUT RESISTANCE

EN = HI

550

kΩ

R_VBAT

VBAT resistance

EN = LOW

MΩ

6.6 Timing Requirements

The device, TPS59632Q1, requires the ENABLE signal on Pin 8 to go from low to high only after the V5A (5-V

supply), the VDD (3.3-V supply) and the VBAT rails have gone high.

6.7 Switching Characteristics

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_CORE(unless

otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

TIMERS: START-UP, PWM ON-TIME AND I/O TIMING

V_BOOT> 0V , EN = high, time from UVLO to

VOUT ramp, C_REF= 0.33 µF

t_START-CB

t_STBY-E

t_PGDDGLTO

t_PGDDGLTU

Cold boot time

1.2

µs

Time from EN assertion until PGOOD goes

high. V_VID= 1.28 V, R_SLEW= 39 kΩ

STBY exit time

250

Time from VFB out of 250 mV VDAC

boundary to PGOOD low.

PGOOD deglitch time

µs

Time from VFB out of –300 mV VDAC

boundary to PGOOD low.

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Switching Characteristics (continued)

Over recommended temperature range, 4.5 V ≤ V_V5A≤ 5.5 V, 3.0 V ≤ V_VDD≤ 3.6 V, V_GFB= GND, V_VFB= V_CORE(unless

otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

R_F= 24 kΩ, V_BAT= 12 V, V_VFB= 1 V (400

kHz)

230

R_F= 39 kΩ, V_BAT= 12 V, V_VFB= 1 V (600

kHz)

164

140

122

t_ON

PWM ON-time

R_F= 75 kΩ, V_BAT= 12 V, V_VFB= 1 V (800

kHz)

R_F= 150 kΩ, V_BAT= 12 V, V_VFB= 1 V (1

MHz)

t_{OFF_MIN}

t_{ON_MIN}

Controller minimum OFF time

Controller minimum ON time

Fixed value

R_CF= 150 kΩ, V_BAT= 20 V, V_VFB= 0 V

ACK of VID change command to start of

voltage ramp

t_VCCVID

t_PG2

VID change to VFB change⁽¹⁾

µs

PGOOD low after enable goes low

Low-state time after EN goes low.

225

250

275

PWM OUTPUTS: I/O VOLTAGE AND CURRENT

t_{P-S_H-L}

t_{P-S_TRI}

PWMx H-L transition time

PWMx 3-state transition

10 to 90%, both edges

10 or 90% to 3-state level, both edges

(1) Specified by design. Not production tested.

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6.8 Typical Characteristics

Figure 1. 3-phase start up behavior showing EN input and

PGOOD output. Input Voltage = 5V, Load current = 10A.

Figure 2. 3-phase start up behavior showing switching at

startup. Input Voltage = 5V, Load current = 10A.

Figure 4. 3-phase switching ripple at Input Voltage = 5 V,

Load current = 50A, Switching Frequency = 800kHz. Single

mode.

Figure 3. 3-phase switching ripple at Input Voltage = 5 V,

Load current = 50A, Switching Frequency = 800kHz.

Persistence mode.

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Typical Characteristics (continued)

Figure 6. Load transient with a droop of 0.6mΩ load-line

Figure 5. Load transient with a droop of 0.6mΩ load-line

slope. Load transient = 14A to 50A. Single mode.

slope. Load transient = 36A to 0A. Single mode.

Figure 7. Load transient with a droop of 0.6mΩ load-line

Figure 8. Load transient with a droop of 0.6mΩ load-line

slope. Load transient = 0A to 36A. Persistence mode

slope. Load transient = 14A to 50A. Persistence mode

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7 Detailed Description

7.1 Overview

The TPS59632-Q1 device is a DCAP+ mode adaptive on-time controller. The DAC outputs a reference in

accordance with the 8-bit VID code, as defined in Table 3. This DAC sets the output voltage.

In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to

maintain a nearly constant frequency during steady-state conditions. With conventional voltage-mode constant

on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in

the TPS59632-Q1 device, the cycle begins when the current feedback reaches an error voltage level, which

corresponds to the amplified difference between the DAC voltage and the feedback output voltage. In the case of

2-phase or 3-phase operation, the device sums the current feedback from all the phases at the output of the

internal current-sense amplifiers.

This approach has two advantages:

•

The amplifier DC gain sets an accurate linear load-line slope, which is required for CPU core applications.

The device filters the error voltage input to the PWM comparator to improve the noise performance.

In addition, the difference between the DAC-to-output voltage and the current feedback goes through an

integrator to give an approximately linear load-line slope even at light loads where the inductor current is in

discontinuous conduction mode (DCM).

During a steady-state condition, the phases of the TPS59632-Q1 device switch 180° phase-displacement for 2-

phase mode and 120° phase-displacement for 3-phase mode. The phase displacement is maintained both by the

architecture and current ripple. The architecture does not allow the high-side gate drive outputs of more than one

phase to be ON in any condition except transients. The current ripple forces the pulses to be spaced equally.

The controller forces current-sharing adjusting the ON time of each phase. Current balancing requires no user

intervention, compensation, or extra components.

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7.2 Functional Block Diagram

GND

COMP

VREF

VDD

V5A

VBAT

DROOP

Power supply UVLO

and

Enable Logic

POWER ON

FREQ

Differential

Amplifier

ON Time

GENERATOR

Voltage

Amplifier

VFB

GFB

VOUT

RAMP

Ramp

Generator

PWM1

PWM2

PWM3

VDAC

Current Sense

Amplifier

Phase 1

PWM

PWM1

PWM2

PWM3

SKIP

CSP1

PWM

Comparator

IS1

I_AMP

CLK

Phase

Manager

CSN1

CSP2

Phase 2

PWM

Error

Amplifier

Integrator

BLANK

IS2

IS3

Current

Sharing

Circuitry

I_AMP

ISHARE

⁺S

Phase 3

PWM

CSN2

CSP3

Power

State

PS0, 1, 2

ISUM

I_AMP

CSN3

DIGITAL SECTION

DROOP

USR

OSR

VOUT

VDAC

ISUM

VREF

OSR

USR

OCP

Protection Block

(OCP, OVP, etc.)

VINTF

SCL

ISUM

IS1

IS2

PGOOD

Logic

PS0, 1, 2

PGOOD

I2C

Interface

(write)

USR

IS3

OSR

SDA

Digital

Registers

VDAC

DAC

ADC

FREQ

OCP

SLEW

ADDR

I2C

Pin-Strap Detection

Interface

(Telemetry

read)

RAMP

Current

Monitor

TPS59632-Q1

7.3 Feature Description

7.3.1 PWM Operation

The functional block diagram and Figure 9 shows how the converter operates in CCM.

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Feature Description (continued)

CORE

SUM

DROOP

SW_CLK

Phase 1

Phase 2

Phase 3

UDG-12192

Time

Figure 9. D-Cap+ Mode Basic Waveforms

Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current

feedback (I_SUM) is higher than the error amplifier output (V_DROOP). I_SUMfalls until it hits V_DROOP, which contains a

component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and

triggers the on-time generator, which generates the internal SW_CLK signal. Each SW_CLK signal corresponds

to one switching ON pulse for one phase.

During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, I_SUM

voltage corresponds to a single-phase inductor current only.

During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.

Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives

the required interleaving of 360 / n, where n is the number of phases.

7.3.2 Current Sensing

The TPS59632-Q1 provides independent channels of current feedback for every phase, to increase the system

accuracy and reduce the dependence of circuit performance on layout compared to an externally summed

architecture. The design can use inductor DCR sensing to yield the best efficiency or resistor current sensing to

yield the most accuracy across wide temperature ranges. As inductor DCR sensing is not suitable for automotive

applications due to wide variation in current sensing across temperature, resistor sensing is recommended. This

sense resistor must be connected in series with the inductor and requires Kelvin sensing terminals for improved

current sense accuracy.

The pins CSP1, CSN1, CSP2, CSN2, CSP3, and CSN3 are the inductor current sensing pins for the each of the

three phases of the converter.

7.3.3 Load-line (Droop)

The TPS59632-Q1 features programmable droop enabling significant reduction of output capacitors. Figure 10

shows the output voltage droop with increasing load current.

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Feature Description (continued)

VID

Slope of Loadline R

= R x I

DROOP LL CC

DROOP

UDG-12193

Figure 10. Load-Line Slope

R_{CS eff}´ A_CS´I_CC

( )

V_DROOP= R_LL´I_CC

A_DROOP

where

•

R_CS(eff)is the effective current sense resistance, when using either a sense resistor or inductor DCR

A_CSis the gain of the current sense amplifier

I_CCis the load current

A_DROOPis the DROOP gain (see Equation 2)

(1)

(2)

DROOP

= 1+

DROOP

COMP

where

•

resistor, R_DROOPis connected between the DROOP pin and the COMP pin

resistor R_COMPis connected between the COMP pin and the VREF pin

This load-line aids in the transient performance as discussed in the following section.

7.3.4 Load Transients

When the load increases suddenly, the output voltage immediately drops. This voltage drop is reflected as a

rising voltage on the DROOP pin. This rising voltage forces the PWM to pulse sooner and more frequently, which

causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-

state operating condition is reached and the PWM switching resumes the steady-state frequency. Similarly, when

the load releases suddenly, the output voltage rises. This rise is reflected as a falling voltage on the DROOP pin.

This rising voltage forces a delay in the PWM pulses until the inductor current reaches the new load current,

when the switching resumes and steady-state switching continues.

For simplicity, neither Figure 11 or Figure 12 show the ripple on the output V_COREnor the DROOP waveform.

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Feature Description (continued)

LOAD

V_CORE

I_SUM

DROOP

I_SUM

DROOP

SW_CLK

Phase

Time

UDG-12194

UDG-12195

Figure 11. Operation During Load Transient

(Insertion)

Figure 12. Operation During Load Transient

(Release)

7.3.5 Overshoot Reduction (OSR)

The problem of overshoot in synchronous buck converters results from the output inductor having a small voltage

(V_OUT) with which to respond to a transient load release.

With overshoot reduction feature enabled, when the output voltage increases beyond a value that corresponds to

a voltage difference between the ISUM voltage and the DROOP pin voltage exceeding the specified OSR

voltage (as specified in the Electrical Characteristics table), at the instant that the low-side drivers are turned

OFF. When the low-side driver is turned OFF, the energy in the inductor is partially dissipated by the body

diodes. As the overshoot reduces, the low-side drivers are turned ON again. Figure 13 shows overshoot

reduction by turning off the low-side MOSFET during load transient release.

V_DAC

V_OUT

ISUM

OSR

DROOP

V_OSR

–

ISUM

OSR

Comparator

V_DROOP

External

Setting

OSR Threshold

OSR

Phase 1

Phase 2

Phase 3

UDG-12237

Time

Figure 13. Overshoot Reduction

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Feature Description (continued)

7.3.6 Undershoot Reduction (USR)

When the transient load increase becomes quite large, it is difficult to meet the energy demanded by the load

especially at lower input voltages. Then it is necessary to quickly increase the energy in the inductors during the

transient load increase. This increase is achieved by enabling pulse overlapping. In order to maintain the

interleaving of the multi-phase configuration while maintaining pulse-overlapping during load-insertion, the

undershoot reduction (USR) mode is entered only when necessary. This device enters this mode is when the

difference between DROOP voltage and ISUM voltage exceeds the USR voltage level specified in the Electrical

Characteristics table.

Figure 14 shows the undershoot reduction operation. This feature allows for the use of reduced output

capacitance while continuing to meet the specification. The device achieves undershoot reduction by overlapping

of pulses on all the phases.

V_DAC

DROOP

V_OUT

USR

V_USR

V_DROOP

–

ISUM

USR

Comparator

External

Setting

ISUM

USR threshold

USR

Phase 1

Phase 2

Phase 3

UDG-12238

Time

Figure 14. Undershoot Reduction

When the transient condition is completed, the interleaving of the phases is resumed.

It should be noted that single-phase mode there is no USR mode of operation.

7.3.7 Autobalance Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of

each phase to equalize the current in each phase.

The PWM comparator (not shown) starts a pulse when the feedback voltage equals the reference voltage. The

VBAT voltage charges C_t(on)through the resistor R_t(on). The pulse is terminated when the voltage at capacitor

C_t(on)matches the on-time (t_ON) reference, usually the DAC voltage (V_DAC).

A current sharing circuit is shown in Figure 15. For example, assume that the 5-µs-averaged value of I1 = I2 = I3.

In this case, the PWM modulator terminates at V_DAC, and the typical pulse width is delivered to the system. If

instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for phase one is shortened,

reducing the current in phase one to compensate. If I1 < I_AVG, then a longer pulse is produced, again

compensating on a pulse-by-pulse basis.

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Feature Description (continued)

VBAT

Rt_(on)

V_DAC

CSP1

K x (I1-I_AVG

)

PWM1

5 ms

Filter

Current

Amplifier

CSN1

Ct_(on)

I_AVG

Rt_(on)

V_DAC

CSP2

K x (I2-I_AVG

PWM2

5 ms

Filter

Current

Amplifier

CSN2

Ct_(on)

I_AVG

Rt_(on)

Averaging

Circuit

I_AVG

V_DAC

CSP3

K x (I3-I_AVG

PWM3

5 ms

Filter

Current

Amplifier

CSN3

Ct_(on)

I_AVG

UDG-12197

Figure 15. Autobalance Current Sharing

7.3.8 PWM And SKIP Signals

The PWM and SKIP signals are outputs of the controller and serve as input to the MOSFET gate driver or

DrMOS-type devices. Both signals are 5-V logic signals. The PWM signals are logic high to allow the high-side

drive of the external gate driver to turn ON. The PWM signal must be low for the low-side drive of the external

gate driver to turn ON. To drive both the signals are OFF, the PWM is set to tri-state. The SKIP signal is active

low to set all the phases in Continuous Conduction Mode (CCM) of operation. If SKIP signal is high then the

external gate driver turns OFF the Low-side drive to operate in the boundary of CCM and Discontinuous

Conduction Mode (DCM).

7.3.9 Bias Power (V5A, VDD, And VINTF) UVLO

The TPS59632-Q1 device continuously monitors the voltage on the V5A, VDD, and VINTF pin to ensure a value

high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The

converter starts with approximately 4.4 V and has a nominal 200 mV of hysteresis. Once the 5VA,VDD, or VINTF

goes below the V_UVLOL, the corresponding voltage must fall below V_POR(1.5 V) to reset the device.

The input (V_BAT) does not include a UVLO function, so the circuit runs with power inputs as low as approximately

3 × V_OUT

7.3.10 Start-Up Sequence

The TPS59632-Q1 device initializes when all of the supplies rise above the UVLO thresholds. This function is

also know as a cold boot. The device then reads all of the various settings (such as frequency and overcurrent

protection). This process takes less than 1.2 ms. During this time, the VSR initializes to the BOOT voltage. The

output voltage rises to the VSR level when the EN pin (enable) goes high. Once the BOOT sequence completes,

PGOOD is HIGH and the I²C interface can be used to change the voltage select register (VSR). The current VSR

value is held when EN goes low and returns to a high state This function is also known as a warm boot.

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Feature Description (continued)

7.3.11 Power Good Operation

PGOOD is an open-drain output pin that is designed to be pulled-up with an external resistor to a voltage 3.6 V

or less. Normal PGOOD operation (exclusive of activation of any faults) is shown in Figure 16. On initial power-

up PGOOD happens within 6 µs of the DAC reaching its target value. When EN is brought low, PGOOD is also

brought low for 250 µs, then is allowed to float. The TPS59632-Q1 device pulls down the PGOOD signal when

the EN signal subsequently goes high and returns high again within 6 µs of the end of the DAC ramp. The delay

period between EN going high and PGOOD going low in this case is less than 1 µs. Figure 16 shows the power

good operation at initial start-up and with falling and rising EN.

For applications where it is undesirable to have PGOOD high when EN is low, an alternate method of pulling up

the open-drain PGOOD signal is possible. In this method, the PGOOD is pulled up to EN logic signal. This

ensures that the PGOOD is low when EN goes low.

VBIAS

VOUT

1 ms

PGOOD

1.2 ms

6 ms

250 ms

UDG-13096

Figure 16. Power Good Operation

7.3.12 Analog Current Monitor, IMON, And Corresponding Digital Output Current

The TPS59632-Q1 device includes a current monitor function. The current monitor supplies an analog voltage,

proportional to the load current, on the IMON pin.

The current monitor function is related to the OCP selection resistors. The R_OCPis the resistor between the OCP-

I pin and GND and R_CIMONis the resistor between the IMON pin to the OCP-I pin that sets the current monitor

gain. Equation 3 shows the calculation for the current monitor gain.

;

ìÜØß×æ

H Í 8_¼Ìá1ÛÛÛ. 8

4_ÂÆÈÇ

ÂÆÈÇ

L sr H s E

;

4_È¼É

where

•

Σ V_CSis the sum of the DC voltages at the inputs to the current sense amplifiers

(3)

To ensure stable current monitor operation, and at the same time, provide a fast dynamic response, connect a

4.7-nF to 10-nF capacitor from the IMON pin to GND. Connecting higher capacitance will reduce the response

time accordingly.

The analog current monitor should be set so that at the maximum processor current (I_CC(max)) the IMON voltage

should be 1.7 V. This setting corresponds to a digital output current value of ‘FF’ in the telemetry register 03H

through I2C. For any other IMON voltage output in the range of 0 to 1.7 V, the digital output varies linearly.

7.3.13 Fault Behavior

TPS59632-Q1 device has a complete suite of fault detection and protection functions, including input under-

voltage lockout on all power inputs, over voltage and over current limiting, and output under voltage detection.

The protection limits are given in the tables above. The converter suspends switching when the limits are

exceeded and PGOOD goes low. In this state, the fault register 14h can be read. To exit fault protection mode,

the bias power (V5A, VDD and VINTF) must be cycled as described in Bias Power (V5A, VDD, And VINTF)

UVLO.

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Feature Description (continued)

7.3.14 Output Under Voltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Over Current

Protection (OCP) section. If V_OUTdrops below the low PGOOD voltage threshold, then the PWM is tri-stated. The

device stays off until the V5A, VDD or VINTF power is cycled and EN goes high.

7.3.15 Output Over Voltage Protection (OVP)

An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than

VDAC. V_OUT> + V_PGDHgreater than VDAC. In this case, the controller device sets PGOOD inactive, and keeps

all the PWM signals low so as to keep the low-side driver ON at the converter. The converter remains in this

state until the controller device is reset by cycling V5A, VDD or VINTF. This is the first level of OVP. This first

level of OVP is inactive during VID transitions. There is a second OVP level fixed at V_OVPHwhich is always

active. If the fixed OVP condition is detected, the PGOOD is forced inactive and the PWM signals are kept low

and the operation is similar to the first level of OVP detection

7.3.16 Over Current Protection (OCP)

The TPS59632-Q1 device uses a inductor valley current limiting scheme, so the ripple current must be

considered. The DC current value at OCP is the OCP limit value plus half of the ripple current. Current limiting

occurs on a phase-by-phase and pulse-by-pulse basis. Generally, the current is sensed using the sense resistor

in series with the inductor for automotive applications giving a voltage between the CSPx and CSNx pins. If this

sensed voltage is above the OCP limit, the converter delays the next ON pulse until that voltage difference drops

below the OCP limit.

In OCP mode, the voltage drops until the UVP limit is reached. When UVP limit is reached the operation follows

as described in the Output Under Voltage Protection (UVP).

7.3.17 Over Current Warning

I²C programming enables this function. The TPS59632-Q1 device pulls down the voltage on the PGOOD pin

whenever the valley current reaches 70% of the OCP value (or higher). PGOOD resumes normal function when

the value falls below 65% of the OCP value.

7.3.18 Input Voltage Limits

The minimum input voltage is limited by the number of input phases, the switching frequency and the output

voltage. The minimum input voltage increases with required maximum output voltage and switching frequency.

See Table 1 for limits in 3-phase operating mode and Table 2 for limits in 2-phase operating mode . In 1-phase

mode, the operation is limited by controller's capability to 2.5 V for all output voltages and switching frequency.

Table 1. Minimum Input Voltage (V_{IN, MIN}) Limits Versus Switching Frequency

(F_SW) and Maximum Output Voltage (V_{OUT, MAX}) in 3-phase operation

V_OUT,MAX(V)

F_SW(kHz)

800

V_{IN, MIN}(V)

3.6

4.0

4.5

5.0

0.8

1000

800

0.9

1.0

1000

800

1000

Table 2. Minimum Input Voltage (V_{IN, MIN}) Limits Versus Switching Frequency

(F_SW) and Maximum Output Voltage (V_{OUT, MAX}) in 2-phase operation

V_OUT,MAX(V)

F_SW(kHz)

1000

V_{IN, MIN}(V)

0.8

0.9

1.0

2.5

2.8

1000

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7.3.19 VID Table

The Table 3 shows the VID table for all the programmable DAC voltage levels.

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Table 3. TPS59632-Q1 VID Table

VID6

VID5

VID4

VID3

VID2

VID1

VID0

HEX

VOLTAGE

0.5000

0.5100

0.5200

0.5300

0.5400

0.5500

0.5600

0.5700

0.5800

0.5900

0.6000

0.6100

0.6200

0.6300

0.6400

0.6500

0.6600

0.6700

0.6800

0.6900

0.7000

0.7100

0.7200

0.7300

0.7400

0.7500

0.7600

0.7700

0.7800

0.7900

0.8000

0.8100

0.8200

0.8300

0.8400

0.8500

0.8600

0.8700

0.8800

0.8900

0.9000

0.9100

0.9200

0.9300

0.9400

0.9500

0.9600

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Table 3. TPS59632-Q1 VID Table (continued)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

HEX

VOLTAGE

0.9700

0.9800

0.9900

1.0000

1.0100

1.0200

1.0300

1.0400

1.0500

1.0600

1.0700

1.0800

1.0900

1.1000

1.1100

1.1200

1.1300

1.1400

1.1500

1.1600

1.1700

1.1800

1.1900

1.2000

1.2100

1.2200

1.2300

1.2400

1.2500

1.2600

1.2700

1.2800

1.2900

1.3000

1.3100

1.3200

1.3300

1.3400

1.3500

1.3600

1.3700

1.3800

1.3900

1.4000

1.4100

1.4200

1.4300

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Table 3. TPS59632-Q1 VID Table (continued)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

HEX

VOLTAGE

1.4400

1.4500

1.4600

1.4700

1.4800

1.4900

1.5000

1.5100

1.5200

7.4 User Selections

After the V5A, VDD, and VINTF voltages are applied to the controller and all these voltage levels are above their

respective UVLO levels, the following information is latched and cannot be changed during operation. The

defines the values of the selections.

•

Operating Frequency. The resistor from FREQ-P pin to GND sets the switching frequency. See the Detailed

Design Procedure for the resistor settings corresponding to each frequency selection. Note that the operating

frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage (at the

VBAT pin) and output voltage (set by VID). The OFF time varies based on various factors such as load and

power-stage components.

•

Overcurrent Protection (OCP) Level. The resistor from OCP-I to GND sets the OCP level of the CPU

channel. See the Detailed Design Procedure for the resistor settings corresponding to each OCP level.

IMON Gain. The resistors from IMON to OCP-I and OCP-I to GND set the DC load current monitor (IMON)

gain.

Slew Rate. The SetVID fast slew rate is set by the resistor from SLEWA pin to GND. See the Detailed Design

Procedure for the resistor settings corresponding to each slew rate setting.

•

Base Address. The voltage on SLEWA pin sets the device base address.

Ramp Selection. The resistor from RAMP to GND sets the ramp compensation level. See the Detailed

Design Procedure for the resistor settings corresponding to each ramp level.

•

Overshoot Reduction (OSR) Level. The resistor from O-USR to GND sets the OSR level. Detailed Design

Procedure provides all the possible selections for OSR.

Undershoot Reduction Level (USR) The voltage on O-USR pin sets the USR level. Detailed Design

Procedure provides all the possible selections for USR.

Active Phases. Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode,

tie the CSP3 pin to a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and

CSP3 pins to a 3.3-V supply and tie the CSN2 and CSN3 pins to GND.

7.5 I²C Interface Operation

The TPS59632-Q1 device includes a slave I²C interface accessed via the SCL (serial clock) and SDA (serial

data) pins. The interface sets the base VID value, receives IMON telemetry, and controls functions described in

this section. It operates with EN = low, with the bias supplies in regulation. It is compliant with I²C specification

UM10204, Revision 3.0; characteristics are detailed as following:

•

Addressing

–

7-bit addressing; address range is 100 0xxx (binary)

Last three bits are determined by the voltage on SLEWA pin at start-up

•

Byte read and byte write protocols only (see the following figures)

Frequency

–

100 kHz

400 kHz

1 MHz

3.4 MHz

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I²C Interface Operation (continued)

•

Logic inputs are 1.8-V logic levels (3.3-V tolerant)

The TPS59632-Q1 device can be configured for eight different device addresses by setting a voltage on the

SLEWA pin. Configure a resistor divider on SLEWA from VREF to GND. Once the slew rate resistor is selected,

the resistor from the VREF pin to the SLEWA pin can be chosen based on the required device address. For a

device address of 40h, the VREF to SLEWA resistor can be left open.

7.5.1 Key For Protocol Examples

Master Drives SDA

ACK

Slave Drives SDA

NAK

Start

Stop

Write

Read

UDG-13045

7.5.2 Protocol Examples

The good byte read transaction the controller ACKs and the master terminates with a NAK/stop

Slave Address

Reg Address

Slave Address

Reg data

UDG-13046

Figure 17. Good Byte Read Transaction

The controller NAKs a read with an invalid register address.

Slave Address

Reg Address

UDG-13047

Figure 18. NAK Invalid Register Address

A good byte write is illustrated in Figure 19.

Slave Address

Reg Address

Reg Data

UDG-13048

Figure 19. Good Byte Write

The controller NAKs a write with an invalid register address.

Slave Address

Reg Address

UDG-13049

Figure 20. Invalid NAK Register Address

The controller will NAK a write for the condition of invalid data.

Slave Address

Reg Address

Reg Data

UDG-13050

Figure 21. Invalid NAK Register Data

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7.6 I²C Register Maps

The I²C interface shall support 400 kHz, 1 MHz, and 3.4-MHz clock frequencies. The I²C interface shall be

accessible even when EN is low. The following registers are accessible via I²C.

7.6.1 Voltage Select Register (VSR) (Address = 00h)

•

Type: read and write

Power-up value: BOOT[6:0]

EN rising (after power-up): prior programmed value

See Table 3 for exact values

A command to set VSR < 19h (minimum VID) generates an NAK and the VBR remains at the prior value

—

VID6

—

VID0

7.6.2 IMON Register (Address = 03h)

•

Type: read only

Power-up value: 00h

EN rising (after power-up):00h

MSB

—

LSB

7.6.3 VMAX Register (Address = 04h)

•

Type: read or write (see the following bit definitions)

Power-up value: 7Fh

EN rising (after power-up): last written value

Lock

MSB

—

LSB

Bit definitions:

Table 4.

BIT

NAME

DEFINITION

0 - 6

VMAX

Maximum VID setting

Access protection of the VMAX register

0: No protection, R/W access to bits 0-6

Lock

1: Access is read only; reset after UVLO event.

7.6.4 Power State Register (Address = 06h)

•

Type: read and write

Power-up value: 00h

EN rising (after power-up): 00h

—

MSB

LSB

Bit definitions:

VALUE

DEFINITION

b1 = 0, b0 Multi-phase CCM

= 0

b1 = 0, b0 Single-phase CCM

= 1

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VALUE

DEFINITION

b1 = 1, b0 Single-phase DCM

= 0

7.6.5 Slew Register (Address = 07h)

•

Type: read and write (see below)

Power-up value: defined by SLEWA pin at power-up

EN rising (after power-up): last written value

Write only a single 1 for the minimum SLEW rate desired for voltage changes. The start-up slew rate is half of

the normal voltage change slew rate.

48 mV/µs

42 mV/µs

36 mV/µs

30 mV/µs

24 mV/µs

18 mV/µs

12 mV/µs

6 mV/µs

7.6.6 Lot Code Registers (Address = 10-13h)

•

Type: 8 bits, read only

Power-up value: programmed at factory

7.6.7 Fault Register (Address = 14h)

•

Type: 8 bits; read only

Power-up value: 00h

—

Device thermal

shutdown

OVP

UVP

OCP

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8 Applications and Implementation

8.1 Application Information

The TPS59632Q1 device has a very simple design procedure. A Microsoft Excel^®-based component value

calculation tool is available. Please contact your local TI representative to get a copy of the spreadsheet.

8.2 Typical Application

8.2.1 3-Phase D-CAP+™, Step-Down Application

VREF

10 nF

IMON

DNP

487 kΩ

V_IN

75 kΩ

CSP1

CSN1

3 x 22 µF

133 kΩ

1 mF

DNP

0.22 µF

TPS59603-Q1

1 Ω

39 kΩ

75 kΩ

150 kΩ

56 kΩ

0.1 uH

Rs1

1 mW

20 kΩ

BST

DRVH

VINTF

V_OUT

PWM1

PWM

SKIP

VDD

10 kΩ

V_IN

GND

DRVL

SKIP

COUT

15 x 100 uF +

24 x 22 uF

5V_DRV

2.2 µF

17 CSP1

18 CSN1

19 CSN2

20 CSP2

21 CSP3

22 CSN3

23 GFB

CSP1

ENABLE

SKIP

CSN1

CSN2

CSP2

CSP3

CSN3

GFB

SKIP

PWM1

PWM2

PWM1

PWM2

TPS59632-Q1

3 x 22 µF

V_IN

CSP2

CSN2

PWM3

10 kΩ

ENABLE

0.22 µF

TPS59603-Q1

PGOOD

VDD

PGOOD

3.3 V

0.1uH

BST

DRVH

Rs2

1 mW

Thermal Pad

V_OUT

VFB

24 VFB

1 Ω

PWM2

PWM

SKIP

VDD

SDA

GND

DRVL

SKIP

30 31 32

1 mF

5V_DRV

2.2 µF

4.7 p

19.6 kΩ

1.96 kΩ

1 kΩ

3 x 22 µF

V_IN

CSP3

CSN3

VINTF

1 kΩ

560 p

3 k

0.1 mF

0.22 µF

TPS59603-Q1

0.1 uH

0.33 mF

BST

DRVH

Rs3

1 mW

V_OUT

PWM3

PWM

SKIP

VDD

10 Ω

1 mF

5 V

GND

DRVL

SKIP

0 Ω

5V_DRV

562 Ω

2.2 µF

VFB

GFB

VCPU_SENSE

From processor

GND_SENSE

To controller

10 kΩ

NOTE: Current-sense and Voltage feedback sense may need additional filtering to reduce noise.

Figure 22. 3-Phase D-CAP+™, Step-Down Application with Power Stages

8.2.1.1 Design Requirements

Design example specifications:

•

Number of phases, N_ph: 3

Conversion Input voltage, V_INrange: 5 V +/- 10%

Converter Output Voltage V_OUT= 0.875 +/- 3% V (including DC and AC)

Load Current, I_CC(max)= 50 A

Voltage Rise time (at start-up) > 100µs

Load Transient step = 36A

Load Transient Slew rate = 36A/µs

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Typical Application (continued)

•

Effective Switching Frequency > 2.0 MHz

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Step 1: Select Switching Frequency

The switching frequency is selected by a resistor (R_F) between the FREQ_P pin and GND. The frequency is

approximate and expected to vary based on load and input voltage.

Table 5. TPS59632-Q1 Device Frequency Selection

Table

SELECTION

RESISTOR (R_F) VALUE (kΩ)

OPERATING FREQUENCY

(f_SW) (kHz)

300

400

500

600

700

800

900

1000

100

150

For this design, choose a switching frequency of 800 kHz so that the effective switching frequency in 3-phase

operation = 2.4 MHz. So, R_F= 75 kΩ.

NOTE

The voltage on the FREQ-P pin MUST be set higher than 0.7V for proper operation of the

device, TPS59632Q1. This can easily be achieved by connecting a resistor of the same

value as R_Ffrom FREQ-P to VREF (1.7 V).

As per the note above, in this design, a resistor of value 75 kΩ is connected from FREQ-P to VREF.

8.2.1.2.2 Step 2: Set The Slew Rate

A resistor to GND (R_SLEWA) on SLEWA pin sets the slew rate. For a minimum start-up time of 100 µs, the

maximum allowed slew rate would be VOUT/100 µs. This would mean a maximum start-up slew rate of 8.8

mV/µs. Hence, from Table 6 the maximum start-up slew rate setting of 5mV/µs is chosen. It should be noted that

the slew rate corresponding to start-up rate is half of the slew rate during voltage changes due to VID changes

as specified in the EC table. The table below provides the minimum and maximum start-up slew rate for each

resistor selection. The resistor selection chosen for this design is R_SLEWA= 20 kΩ.

Table 6. Slew Rate Versus Selection Resistor

SELECTION RESISTOR

MINIMUM START-UP SLEW

MAXIMUM START-UP SLEW RATE

(mV/µs)

R_SLEWA(kΩ)

RATE

(mV/µs)

8.2.1.2.3 Step 3: Set The I²C Address

The voltage on the SLEWA pin also sets the I²C address for the device. For an I2C address of 40, the SLEWA

pin should only have a resistor, RSLEW to GND and the SLEW pin to VREF pin should be left open. For other

I²C addresses, a resistor must be connected between the SLEWA pin and the VREF pin (1.7 V). This resistor

can be calculated to set the corresponding voltage for the required address listed in Table 7.

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Table 7. I²C Address Selection

SLEWA

I²C

VOLTAGE

ADDRESS

V_SLEWA≤ 0.30 V

0.35 V ≤ V_SLEWA≤ 0.45 V

0.55 V ≤ V_SLEWA≤ 0.65 V

0.75 V ≤ V_SLEWA≤ 0.85 V

0.95 V ≤ V_SLEWA≤ 1.05 V

1.15 V ≤ V_SLEWA≤ 1.25 V

1.35 V ≤ V_SLEWA≤ 1.45 V

1.55 V ≤ V_SLEWA≤ 1.65 V

8.2.1.2.4 Step 4: Determine Inductor Value And Choose Inductor

Applications with smaller inductor values have better transient performance but also have higher voltage ripple

and lower efficiency. Applications with higher inductor values have the opposite characteristics. Choice of

inductance is a trade off between transient, ripple, size, efficiency, cost and availability.

For this design, we chose an inductance value of 0.1 µH. The chosen inductor should have the following

characteristics:

•

As flat as an inductance versus current curve as possible.

Either high saturation or soft saturation. A saturation current of at least the per phase maximum current of

I_CC(max)/ N_ph+ I_ripple/2

•

Low DCR for high efficiency.

8.2.1.2.5 Step 5: Current Sensing Resistance

The TPS59632 device supports both resistor sensing and inductor DCR sensing. However, inductor DCR

sensing is not suitable for automotive applications due to wide variation in current sensing across temperature.

The sense resistance, R_Smust be chosen large enough to give sufficient current signal to the controller and

small enough to keep the power dissipation low. Choosing max power dissipation to about 0.5W per phase, we

get R_S= 1 mΩ.

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8.2.1.2.6 Step 6: Select Over Current Protection (OCP) Setting

The OCP level is chosen such that it is 30% above the maximum load current, I_CC(max). In the equation, here R_CS

is the current sense resistor.Equation 4. I_VALLEYis the load current less half the ripple.

_VALLEY´R_{CS eff}= V_{CS ocp}

( )

(

)

(4)

Set the OCP threshold level just greater than the calculated I_VALLEYfor the required OCP level. Equation 4. In this

design, the minimum required OCP is 65A. Therefore, an OCP selection resistor of 56k is chosen to meet the

requirement.

Table 8 shows the minimum OCP level for all the selection resistors.

Table 8. OCP Selection⁽¹⁾

SELECTION RESISTOR

Minimum V_CS(OCP)

(mV)

R_OCP(kΩ)

100

150

(1) If a corresponding match is not found, then select the next higher

setting.

8.2.1.2.7 Step 7: Current Monitor (IMON) Setting

Set the analog current monitor so that at I_CC(max)the IMON pin voltage is 1.7 V. This corresponds to a digital I_OUT

value of ‘FF’ in I²C register 03H. The voltage on the IMON pin is shown in Equation 5.

IMON

1.7 = 10´ 1+

´R

´I

CS eff CC max

( )

(

)

OCP

(5)

where, I_CC(max)is 50 A; R_CS(eff)is 1.0 mΩ and R_OCPis 56 kΩ

Solving, R_IMON= 133 kΩ. R_IMONis connected from IMON pin to OCP-I pin.

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8.2.1.2.8 Step 8: Set the Load-Line Slope

Setting a load line slope is effective in significantly reducing the output capacitors. Therefore, although the design

requirement does not call for a load-line, we use the output voltage tolerance specification to determine an

appropriate load-line. Figure 23 shows how we first determine the load-line window.

Max limit

Max limit - Controller TOL

Min limit - Controller TOL - AC ripple

Nominal DC Load-line Window

Nominal

Min limit + Controller TOL + AC ripple

Min limit + Controller TOL

Min limit

Figure 23. Determination of Nominal DC Load-line window

This nominal DC load-line window is now used to set the load-line slope across the range of load current from 0

to I_cc,maxas shown in Figure 24.

VOUT at

zero load

Slope of Loadline

R _LL

Nominal

DROOP

cc,max

Figure 24. Determination of the Slope of the Load-line

The load-line slope R_LLis first determined as shown in Figure 24 using the equation in Equation 6. In the device,

TPS59632-Q1, the load-line is determined by the current sense resistance, R_CS, the current sense amplifier gain,

A_CS, and the gain of the droop amplifier (A_DROOP) as shown in Equation 7.

(6)

(7)

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The gain of the droop amplifier, (A_DROOPcan therefore be determined by Equation 7. This gain is set by the

external resistors R_DROOP(between the DROOP pin and the COMP pin) and resistor R_COMP(between the COMP

pin and the VREF pin) as shown in Equation 8. We fix the value of R_DROOPto 19.6 kΩ, and thereby R_COMPis

calculated to 1.87 kΩ.

(8)

8.2.1.2.9 Step 9: Voltage Feedback Resistor Calculation

In the device TPS59632-Q1, the internal DAC voltage is set to 0.80 V. To adjust the output voltage above or

below this voltage we need to use feedback resistor divider setting. Since we are sensing the voltage using

differential remote sense we adopt the circuit shown in Figure 25 to increase the voltage above 0.80 V and the

and circuit shown in Figure 26 to decrease the voltage below 0.80 V.

VFB

To Controller

GFB

Vout_Sense+

From Output

Vout_Sense-

Figure 25. Feedback resistor divider circuit to increase the output voltage above internal DAC voltage

In this design, we need to calculate the feedback resistor values, R1 and R2, to increase the voltage above the

DAC, the equation shown in Equation 9 is used. Here, V_DAC= 0.80 V, and Va from load-line setting is determined

as 0.890 V. R2 is set to 10 kΩ and R1 is calculated to 562.

(9)

Vref

Vout_Sense+

VFB

To Controller

GFB

From Output

Vout_Sense-

GND

Figure 26. Feedback resistor divider circuit to decrease the output voltage above internal DAC voltage

To calculate the feedback resistor values, R1 and R2, to decrease the voltage below the DAC, the equation

shown in Equation 10 is used. Here, V_DAC= 0.80 V, and Va from load-line setting for the specific application. Vref

is the TPS59632-Q1 reference voltage at Pin 27 (VREF) which is nominally 1.7 V. Using this, and setting R2 to

10 kΩ, R1 can be determined.

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(10)

8.2.1.2.10 Step 10: Ramp Compensation Selection

The Ramp compensation is selected to minimize the jitter. Higher ramp gives lower jitter but can worsen the

transient response. The ramp compensation selection is a trade off between transient response and jitter.

Table 9 shows the available ramp selections.

Table 9. Ramp Compensation Selection

SELECTION RESISTOR

RAMP COMPENSATION

VOLTAGE

R_RAMP(kΩ)

(mV)

100

150

8.2.1.2.11 Step 11 Overshoot Reduction (OSR) selection

The OSR level selection is based on the load-transient performance and amount of actual output capacitance to

get the best performance with least output capacitance. The suggested method is to begin with OSR OFF and

perform the load transient test based on a calculated amount of output capacitance. If the overshoot is higher

then specified voltage limits, the OSR can be enabled by lowering the OSR threshold level. If the overshoot is

acceptable with OSR OFF, then e reduction in output capacitance can be made and then an appropriate OSR

level can be selected to meet the load transient specification. While reducing the output capacitance, other

considerations like output ripple, undershoot, stability, and so on needs to be considered simultaneously.

Table 10 shows the available OSR selections.

Table 10. OSR Selection

SELECTION RESISTOR

OSR THRESHOLD LEVEL

(mV)

R_OSR(kΩ)

100

150

200

250

300

400

500

OFF

100

150

8.2.1.2.12 Step 12: Undershoot Reduction (USR) selection

Once the the R_OSRvalue is fixed, then the USR level can be set by the voltage on the O-USR pin. The resistor

R_USR(between the O-USR pin and the VREF pin) sets the voltage.

Table 11. USR Selection

V_O-USRSELECTION

VOLTAGE (V)

V_USR

UNDERSHOOT

REDUCTION LEVEL

(mV)

LEVEL

MIN

MAX

0.25

0.45

0.65

0.85

0.35

0.55

0.75

120

180

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Table 11. USR Selection (continued)

V_O-USRSELECTION

VOLTAGE (V)

V_USR

UNDERSHOOT

REDUCTION LEVEL

(mV)

LEVEL

MIN

MAX

0.95

1.15

1.35

1.55

1.05

1.25

240

420

480

540

1.45

V_VREF

The USR level is also selected similar to the OSR setting. First, begin with least undershoot reduction and lower

the level until pulse-overlap between two phases happens sufficiently to meet the load insertion transient

requirement. The USR level can be approximately estimated by multiplying one-third of the droop voltage for the

specified load transient with the A_DROOPdetermined in Step 8: Set the Load-Line Slope. The actual level needs to

be tuned based on measurement. In this design, OSR is set to OFF and USR is set to 90-mV level. Therefore

R_OSR= 150k and R_USR= 487k.

8.2.1.2.13 Step 13: Loop Compensation

The controller device TPS59632-Q1 does not require any additional loop compensation for stability as the load-

line setting droop amplifier gain automatically stabilizes the DCAP+ control loop. However, to further increase the

response time to fast load transients, an additional resistor (3 kΩ) in series with a capacitor (560 pF) is placed

from COMP to VREF. Frequency response is measured to ensure the stability while meeting the transient

requirements. Some key results for this design are given in Application Performance Plots.

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8.2.1.3 Application Performance Plots

0.92

0.91

0.9

0.89

0.88

0.87

0.86

0.85

0.84

Load Current (A)

D001

Figure 27. Output Voltage vs Output Current

100%

95%

90%

85%

80%

75%

70%

65%

60%

I_OUT(A)

D004

Figure 28. Efficiency and Power Loss Vs. Load Current

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150

120

-10

-20

-30

-40

-50

-30

-60

-90

-120

-150

500000 1000000

10000 20000

50000 100000 200000

Frequency (Hz)

D002

Figure 29. Control-loop Gain-Phase measurement Vs. frequency

9 Power Supply Recommendations

This device is designed to operate from a supply voltage at the V5A pin (5-V power input for analog circuits) from

4.5 V to 5.5 V and a supply voltage at the VDD pin (3.3-V digital power input) from 3.1 V to 3.5 V, and a supply

voltage at VINTF from 1.7 V to 3.5 V. Use only a well-regulated supply. The VBAT input must be connected to

the conversion input voltage and must not exceed 28 V. Proper bypassing of the V5A, VDD, and VINTF input

supplies is critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in

the Layout section.

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10 Layout

10.1 Layout Guidelines

•

Confirm the pinout of the controller on schematic against the pinout of the data sheet.

Have a component value calculator tool ready to check component values.

Carefully check the choice of inductor and sense resistor.

Carefully check the choice of output capacitors.

Because the voltage and current feedback signals are fully differential, double check their polarity.

–

CSP1 / CSN1

CSP2 / CSN2

CSP3 / CSN3

VOUT_SENSE to VFB / GND_SENSE to GFB

•

Make sure the pull up on the SDA, SCL lines are correct. Check if there is a bypass capacitor close to the

device on the pull up VINTF rail to GND of the device.

TI strongly recommends that the device GND be separate from the system and Power GND.

NOTE

Make sure to separate noisy driver interface lines. This is a critical layout rule.

The driver (TPS59603-Q1) is outside of the device. All gate-drive and switch-node traces must be local to the

inductor and MOSFETs.

10.2 Layout Example

1.8V and IMON to GND

decoupling cap

PWM

signals

Differential routing

of CSP and CSN in

quiet internal layers.

V5A, VREF, VCCIO

and VDD decoupling

Caps to Analog GND.

Differential routing

of VFB and GFB

I2C Interface

signals

Compensation

Network

Figure 30. Example Layout

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10.3 Current Sensing Lines

Given the physical layout of most systems, the current feedback (CSPx and CSNx) may have to pass near the

power chain. Clean current feedback is required for good load-line, current sharing, and current limiting

performance of the TPS59632-Q1 device, so take the following precautions:

•

Ensure all vias in the CSPx and CSNx traces are isolated from all other signals.

TI recommends dotted signal traces be run in internal planes.

If possible, change the name of the CSNx trace if possible to prevent automatic ties to the V_COREplane.

Run CSPx and CSNx as a differential pair in a quiet layer to the device.

Isolate the lines from noisy signals by a voltage or ground plane.

Make a Kelvin connection to the pads of the resistor used for current sensing.

Place any noise filtering capacitors directly under or near the TPS59632-Q1 device and connect to the CS

pins with the shortest trace length possible.

10.4 Feedback Voltage Sensing Lines

The voltage feedback coming from the CPU socket must be routed as a differential pair all the way to the VFB

and GFB pins of the TPS59632-Q1 device. Care should be taken to avoid routing over switch-node and gate-

drive traces.

10.5 PWM And SKIP Lines

The PWM and SKIP lines should be routed from the TPS59632-Q1 device to the MOSFET gate driver without

crossing any switch-node or the gate drive signals.

10.6 Power Chain Symmetry

The TPS59632-Q1 device does not require special care in the layout of the power chain components because

independent isolated current feedback is provided. Lay out the phases in a symmetrical manner, if possible. The

rule is: the current feedback from each phase needs to be clean of noise and have the same effective current-

sense resistance.

10.7 Component Location

Place components as close to the device in the following order:

1. CS pin noise filtering components

2. COMP pin and DROOP pin compensation components

3. Decoupling capacitors for VREF, VDD, V5A

4. Decoupling cap for VINTF rail, which is pullup voltage for the digital lines. This decoupling should be placed

near the device to have good signal integrity.

5. OCP-I resistors, FREQ-P resistors, SLEWA resistors, RAMP resistors, and O-USR resistors

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

10.8 Grounding Recommendations

The TPS59632-Q1 device has an analog ground and a thermal pad. The usual procedure for connecting these

is:

•

Keep the analog GND of the device and the power GND of the power circuit separate. The device analog

GND and the power circuit power GND can be connected at one single quiet point in the layout.

The thermal pad does not have an electrical connection to device. But, the thermal pad must be connected to

pin 29 GND of the device to give good ground shielding. Do not connect this to system GND.

Tie the thermal pad to a ground island with at least 4 vias. All the analog components can connect to this

analog ground island.

The analog ground can be connected to any quiet spot on the system ground. A quiet spot is defined as a

spot where no power supply switching currents are likely to flow. Use a single point connection from analog

ground to the system ground.

•

Make sure the bottom FET source connection and the input decoupling capacitors have plenty of vias.

10.9 Decoupling Recommendations

•

Decouple V5A and VDD to GND with a ceramic capacitor (with a value of at least 1 µF).

Decouple VINTF to GND with a capacitor (with a value of at least 0.1 µF) to GND.

10.10 Conductor Widths

•

Maximize the widths of power, ground, and drive signal connections.

For conductors in the power path, be sure there is adequate trace width for the amount of current flowing

through the traces.

•

Make sure there are sufficient vias for connections between layers. Use 1 via minimum per ampere of current.

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

《适用于汽车应用高频 CPU 内核电源的 TPS59603-Q1 同步降压 FET 驱动器》数据表

11.2 商标

D-CAP+, AutoBalance, D-CAP+ are trademarks of Texas Instruments.

Excel is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

11.3 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

13 Package Option Addendum

13.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

(1)

(2)

(3)

Orderable Device

Status

Pins

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking⁽⁴⁾⁽⁵⁾

GREEN

TPS59632QRHBRQ1

PREVIEW

QFN

RHB

3000

250

(RoHS and no

Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

–40 to 125

TPS59632Q

GREEN

(RoHS and no

Sb/Br)

TPS59632QRHBTQ1

PREVIEW

QFN

CU NIPDAU

–40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TPS59632-Q1

www.ti.com.cn

ZHCSKX0 –FEBRUARY 2020

13.2 Tape And Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS59632QRHBRQ1

TPS56632QRHBTQ1

QFN

RHB

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

TPS59632-Q1

ZHCSKX0 –FEBRUARY 2020

www.ti.com.cn

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

35.0

TPS59632QRHBRQ1

TPS59632QRHBTQ1

QFN

RHB

367.0

210.0

367.0

185.0

35.0

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS59632QRHBRQ1

TPS59632QRHBTQ1

ACTIVE

VQFN

RHB

3000 RoHS & Green

250 RoHS & Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 125

TPS

59632

Samples

ACTIVE

RHB

NIPDAU | SN

TPS

59632

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

Addendum-Page 2

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032P

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

0.5

0.3

0.2

PIN 1 INDEX AREA

DETAIL

OPTIONAL TERMINAL

TYPICAL

5.1

4.9

0.1 MIN

(0.05)

SECTION A-A

SCALE 25.000

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.7 0.1

2X 3.5

(0.2) TYP

EXPOSED

THERMAL PAD

SEE TERMINAL

DETAIL

SYMM

3.5

0.3

0.2

32X

28X 0.5

0.1

C A B

SYMM

PIN 1 ID

(OPTIONAL)

0.05

0.5

0.3

32X

4223198/A 08/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032P

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.7)

SYMM

32X (0.6)

32X (0.25)

(1.6)

(R0.05)

TYP

SYMM

(1.26) TYP

(4.8)

28X (0.5)

(

0.2) TYP

VIA

(1.26) TYP

4X (1.6)

(4.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223198/A 08/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032P

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.26) TYP

9X ( 1.06)

32X (0.6)

32X (0.25)

(R0.05) TYP

(1.26)

TYP

SYMM

(4.8)

28X (0.5)

METAL

TYP

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33

74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223198/A 08/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RHB0032U

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

3.7 0.1

2X 3.5

(0.2) TYP

EXPOSED

THERMAL PAD

28X 0.5

(0.16) TYP

SYMM

3.5

0.3

0.2

32X

0.1

C A B

0.05

PIN 1 ID

(45 X 0.3)

SYMM

0.5

0.3

(0.25)

TYP

32X

4225709/C 01/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032U

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.7)

SYMM

32X (0.6)

32X (0.25)

(0.97)

28X (0.5)

(0.63)

TYP

SYMM

(4.8)

(

0.2) TYP

VIA

(R0.05)

TYP

(0.63) TYP

(0.97)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225709/C 01/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032U

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9X ( 1.06)

(1.26)

(R0.05) TYP

32X (0.6)

32X (0.25)

28X (0.5)

(1.26)

SYMM

(4.8)

METAL

TYP

(R0.05) TYP

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4225709/C 01/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS59632QRHBTQ1 [TI]

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