TPS61022RWUT [TI]
具有 0.5V 超低输入电压的 8A 升压转换器 | RWU | 7 | -40 to 125;
| 型号： | TPS61022RWUT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 0.5V 超低输入电压的 8A 升压转换器 | RWU | 7 | -40 to 125 升压转换器 |
| 文件： | 总33页 (文件大小：2156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61022
ZHCSJB0D –JANUARY 2019 –REVISED JULY 2021
具有0.5V 超低输入电压的TPS61022 8A 升压转换器
1 特性
3 说明
• 输入电压范围：0.5V 至5.5V
• 启动时的最小输入电压为1.8V
• 输出电压设置范围：2.2V 至5.5V
• 两个12mΩ(LS)/18mΩ(HS) MOSFET
• 8A 谷值开关电流限制
• VIN = 3.6V、VOUT = 5V 且IOUT = 3A 时效率为
94.7%
• VIN > 1.5V 时开关频率为1MHz，VIN < 1V 时开关
频率为0.6MHz
• 在–40°C 至+125°C 温度范围内，基准电压精度
为±2.5%
• 轻负载运行时引脚可选自动PFM 工作模式或强制
PWM 工作模式
• VIN > VOUT 时切换为直通模式
• 在关断期间真正断开输入域输出之间的连接
• 输出过压和热关断保护
• 输出短路保护
• 2mm × 2mm VQFN 7 引脚封装
TPS61022 可以为由多种电池和超级电容器供电的便携
式设备和物联网设备提供电源解决方案。在整个温度范
围内， TPS61022 的谷值开关电流限制最小值为
6.5A。在 0.5V 至 5.5V 的宽输入电压范围内，
TPS61022 支持超级电容器备用电源应用，这可能导致
超级电容器深度放电。
当输入电压高于 1.5V 时，TPS61022 的工作频率为
1MHz。当输入电压低于1.5V 甚至降至1V 时，开关频
率逐渐降至0.6MHz。在轻负载条件下，MODE 引脚将
TPS61022 工作模式设定为省电模式或强制 PWM 模
式。在轻负载条件下，TPS61022 仅消耗 VOUT 处的
26µA 静态电流。关断期间，负载与输入电源完全断
开。TPS61022 还具有 5.7V 输出过压保护、输出短路
保护和热关断保护。
TPS61022 采用 2mm × 2mm VQFN 封装，更大限度
地减少了外部元件的数量，因而拥有非常小巧的解决方
案尺寸。
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
TPS61022
• USB 端口
• 备用超级电容器
• GPRS 电源
VQFN (7)
2.00mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
L1
VIN
GND
1 µH
VOUT
C1
FB
VOUT
VIN
SW
EN
SW
GND
VOUT
MODE
VOUT
GND
GND
VIN
C2
VIN
R1
R2
PWM
ON
TPS61022
PFM
OFF
FB
MODE
EN
GND
典型应用电路
需要一个陶瓷输出电容器，并且它必须靠近TPS61022 的
VOUT 引脚和GND 引脚
布局示例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDX7
TPS61022
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ZHCSJB0D –JANUARY 2019 –REVISED JULY 2021
Table of Contents
8.1 Application Information............................................. 13
8.2 Typical Application ................................................... 13
8.3 System Examples..................................................... 18
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
10.3 Thermal Considerations..........................................21
11 Device and Documentation Support..........................23
11.1 Device Support .......................................................23
11.2 接收文档更新通知................................................... 23
11.3 支持资源..................................................................23
11.4 Trademarks............................................................. 23
11.5 Electrostatic Discharge Caution..............................23
11.6 术语表..................................................................... 23
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................13
Information.................................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (June 2021) to Revision D (July 2021)
Page
• Added IQ into VIN typical value...........................................................................................................................5
• Changed ISD test conditions from 5.5 V to 5.0 V................................................................................................ 5
• Changed ISD, TJ maximum value from 3.0 μA to 3.5 μA..................................................................................5
Changes from Revision B (January 2020) to Revision C (June 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
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5 Pin Configuration and Functions
VIN
MODE
EN
GND
SW
VOUT
FB
图5-1. 7-Pin VQFN with Thermal Pad RWU Package (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Ground pin of the IC. The GND pad of output capacitor must be close to the GND pin.
Layout example is shown in Layout Example.
1
GND
PWR
PWR
The switch pin of the converter. It is connected to the drain of the internal low-side power
MOSFET and the source of the internal high-side power MOSFET.
2
SW
Boost converter output. The VOUT pad of output capacitor must be close to the VOUT pin.
Layout example is shown in Layout Example.
3
4
5
VOUT
FB
PWR
I
I
Voltage feedback of adjustable output voltage.
Enable logic input. Logic high voltage enables the device. Logic low voltage disables the
device and turns it into shutdown mode.
EN
Operation mode selection in the light load condition. When it is connected to logic high
voltage, the device works in forced PWM mode. When it is connected to logic low voltage,
the device works in auto PFM mode.
6
7
MODE
VIN
I
I
IC power supply input.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–40
–65
MAX
7
UNIT
V
Voltage range at terminals(2)
Operating junction temperature, TJ
Storage temperature, Tstg
VIN, EN, FB, MODE, SW, VOUT
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.5
0.5
2.2
0.33
4.7
30
NOM
MAX
4.8
UNIT
V
Output voltage pre biased < 0.7V before start-up
Output voltage pre biased > 0.7V before start-up
VIN
Input voltage range
5.5
V
VOUT
L
Output voltage setting range
Effective inductance range
5.5
V
1.0
10
30
30
30
2.9
µH
µF
µF
µF
µF
°C
CIN
Effective input capacitance range
IOUT >= 3A
1000
1000
1000
125
COUT
Effective output capacitance range
Operating junction temperature
1.5A < IOUT < 3A
IOUT <= 1.5A
20
10
TJ
–40
6.4 Thermal Information
TPS61022
TPS61022
THERMAL METRIC(1)
RWU (VQFN) - 7 PINS
RWU (VQFN) - 7 PINS
UNIT
Standard
108.2
70.2
EVM(2)
50.9
N/A
RθJA
RθJC
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
37.1
N/A
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.6
1.6
36.7
20.0
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on TPS61022EVM-034, 4-layer, 2oz copper 58mm×46mm PCB.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 3.6 V and VOUT = 5.0 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
0.5
5.5
1.8
1.6
0.5
V
V
V
V
VIN rising at VOUT = 0 V
1.7
1.3
0.4
VIN_UVLO
Under-voltage lockout threshold
VIN rising at VOUT > 2.2 V, TJ up to 85°C
VIN falling
IC enabled, No load, No switching VIN
=
Quiescent current into VIN pin
Quiescent current into VOUT pin
1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up
to 85°C
0.9
27
3.0
32
µA
µA
IQ
IC enabled, No load, No switching VOUT
2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up
to 85°C
=
IC disabled, VIN = 1.8 V to 5.0 V, TJ =
25°C
0.25
0.25
0.6
3.5
µA
µA
ISD
Shutdown current into VIN and SW pin
IC disabled, VIN = 1.8 V to 5.0 V, TJ up to
85°C
OUTPUT
VOUT
Output voltage setting range
2.2
585
590
5.5
5.5
V
mV
mV
V
PWM mode
PFM mode
600
606
5.7
0.1
615
VREF
Reference voltage at the FB pin
VOVP
Output over-voltage protection threshold VOUT rising
Over-voltage protection hysteresis
6.0
VOVP_HYS
IFB_LKG
V
Leakage current at FB pin
20
3
nA
IC disabled, VIN = 0 V, VSW = 0 V, VOUT
5.5 V,TJ up to 85°C
=
IVOUT_LKG
Leakage current into VOUT pin
Soft startup time
1
µA
From active EN to VOUT regulation.
VIN = 2.5 V, VOUT = 5.0 V, COUT_EFF
=
tSS
700
μs
30μF, IOUT = 0
POWER SWITCH
High-side MOSFET on resistance
Low-side MOSFET on resistance
VOUT = 5.0 V
18
12
mΩ
mΩ
MHz
MHz
ns
RDS(on)
VOUT = 5.0 V
VIN = 3.6 V, VOUT = 5.0 V, PWM mode
VIN = 1.0 V, VOUT = 5.0 V, PWM mode
1.0
0.6
80
fSW
Switching frequency
tOFF_min
Minimum off time
150
10
ILIM_SW
Valley current limit
VIN = 3.6 V, VOUT = 5.0 V
VIN = 1.8 - 4.8 V, VOUT < 0.4 V
VIN = 2.4 V, VOUT > 0.4 V
6.5
400
2
8
A
ILIM_CHG
ILIM_CHG_max
Pre-charge current
700
2.4
mA
A
Maximum pre-charge current
LOGIC INTERFACE
VEN_H
EN logic high threshold
VIN > 1.8 V or VOUT > 2.2 V
VIN > 1.8 V or VOUT > 2.2 V
VIN > 1.8 V or VOUT > 2.2 V
VIN > 1.8 V or VOUT > 2.2 V
1.2
0.45
1.2
V
V
VEN_L
EN logic low threshold
0.35
0.4
0.42
VMODE_H
VMODE_L
PROTECTION
TSD
MODE logic high threshold
MODE logic low threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
150
20
°C
°C
TSD_HYS
TJ falling below TSD
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6.6 Typical Characteristics
VIN = 3.6 V, VOUT = 5 V, TJ = 25°C, unless otherwise noted
100
95
90
85
80
100
95
90
85
80
75
70
65
75
VIN=1.8V
VIN=3.0V
VIN=3.6V
VIN=4.2V
VOUT=3.3V
VOUT=3.8V
VOUT=4.0V
VOUT=5.0V
70
65
0.0001
0.001
0.01
Output Current (A)
0.1
1
5
0.0001
0.001
0.01
Output Current (A)
0.1
1
5
effi
effi
VIN = 1.8 V, 3 V, 3.6 V, 4.2 V; VOUT = 5 V
VIN = 1.8 V; VOUT = 3.3 V, 3.8 V, 4 V, 5 V
图6-1. Load Efficiency With Different Input in Auto
图6-2. Load Efficiency With Different Output in
PFM
Auto PFM
100
80
100
80
60
60
40
40
VIN=1.8V
VIN=3.0V
VOUT=3.3V
VOUT=3.8V
20
20
VIN=3.6V
VIN=4.2V
VOUT=4.0V
VOUT=5.0V
0
0.0001
0
0.0001
0.001
0.01
Output Current (A)
0.1
1
5
0.001
0.01
Output Current (A)
0.1
1
5
effi
effi
VIN = 1.8 V, 3 V, 3.6 V, 4.2 V; VOUT = 5 V
VIN = 1.8 V; VOUT = 3.3 V, 3.8 V, 4 V, 5 V
图6-3. Load Efficiency With Different Input in
图6-4. Load Efficiency With Different Output in
Forced PWM
Forced PWM
5.1
5.05
5
5.04
5.02
5
4.98
4.96
4.95
VIN=1.8V
VIN=1.8V
VIN=3.0V
VIN=3.6V
VIN=4.2V
VIN=3.0V
VIN=3.6V
VIN=4.2V
4.94
4.9
0.0001
4.92
0.0001
0.001
0.01
Output Current (A)
0.1
1
5
0.001
0.01
Output Current (A)
0.1
1
5
regu
regu
VIN = 1.8 V, 3 V, 3.6 V, 4.2 V; VOUT = 5 V
VIN = 1.8 V, 3 V, 3.6 V, 4.2 V; VOUT = 5 V
图6-5. Load Regulation in Auto PFM
图6-6. Load Regulation in Forced PWM
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5
4.5
4
600
599
598
597
596
595
3.5
3
2.5
2
1.5
1
Tj=-40èC
Tj=25èC
Tj=125èC
0.5
0.5
1
1.5
2 2.5
Output Voltage (V)
3
3.5
4
-60
-30
0
30
60
90
120
150
Temperature (èC)
prec
refe
VIN = 5 V; VOUT = 0.5 V to 4 V
VIN = 3.6 V; VOUT = 5 V, TJ = –40°C to +125°C
图6-7. Pre-charge Current vs Output Voltage
图6-8. Reference Voltage vs Temperature
2
29
28
27
26
25
24
VIN=1.8V
VIN=3.6V
VIN=4.5V
1.5
1
0.5
23
VOUT=2.2V
VOUT=3.6V
VOUT=5V
22
21
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
iqvi
iqvo
VIN = 1.8 V, 3.6 V 4.5 V; VOUT = 5 V, TJ = –40°C to +85°C, No
VIN = 1.8 V; VOUT = 2.2 V, 3.6 V, 5 V, TJ = –40°C to +85°C,
switching
No switching
图6-9. Quiescent Current into VIN vs Temperature
图6-10. Quiescent Current into VOUT vs
Temperature
1.4
1.14
1.11
1.08
1.05
1.02
0.99
0.96
0.93
0.9
VIN=1.8V
VIN=3.6V
1.2
VIN=4.5V
VIN=5V
1
0.8
0.6
0.4
0.2
0
0.87
0.84
-40
-20
0
20
40
60
80
100
1.8
2.1
2.4
2.7
3 3.3
Input Voltage (V)
3.6
3.9
4.2
4.5
Temperature (èC)
shut
freq
VIN = VSW = 1.8 V, 3.6 V, 4.5 V, 5 V; TJ = –40°C to +85°C
VIN = 1.8 V to 4.5 V; VOUT = 5 V
图6-11. Shutdown Current vs Temperature
图6-12. Switching Frequency vs Input Voltage
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1.05
1
0.48
0.45
0.42
0.39
0.36
0.33
VIN=1.8V
VIN=2.4V
VIN=3.6V
VIN=4.5V
0.95
0.9
0.85
0.8
0.75
VIN=1.8V
VIN=2.4V
VIN=3.6V
VIN=4.5V
0.7
0.65
-40
-20
0
20
40
60
80
100 120 140
-60
-30
0
30
60
90
120
150
Temperature (èC)
Temperature (èC)
enri
enfa
VIN = 1.8 V, 2.4 V, 3.6 V, 4.5 V; VOUT = 5 V; TJ = –40°C to
VIN = 1.8 V, 2.4 V, 3.6 V, 4.5 V; VOUT = 5 V; TJ = –40°C to
+125°C
+125°C
图6-13. EN Rising Threshold vs Temperature
图6-14. EN Falling Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TPS61022 synchronous step-up converter is designed to operate from an input voltage supply range
between 0.5 V and 5.5 V with 6.5-A (minimum) valley switch current limit. The TPS61022 typically operates at a
quasi-constant frequency pulse width modulation (PWM) at moderate to heavy load currents. The switching
frequency is 1 MHz when the input voltage is above 1.5 V. The switching frequency reduces down to 0.6 MHz
gradually when the input voltage goes down from 1.5 V to 1 V and keeps at 0.6 MHz when the input voltage is
below 1 V. The MODE pin sets the TPS61022 converter operating in power-save mode with pulse frequency
modulation (PFM) or forced PWM mode in light load conditions. During PWM operation, the converter uses
adaptive constant on-time valley current mode control scheme to achieve excellent line regulation and load
regulation and allows the use of a small inductor and ceramic capacitors. Internal loop compensation simplifies
the design process while minimizing the number of external components.
7.2 Functional Block Diagram
SW
2
VIN
VOUT
Undervoltage
Lockout
VIN
VOUT
7
3
EN
5
6
Valley Current
Sense
Gate Driver
Logic
MODE
GND
1
Thermal
Shutdown
PWM Control
Overvoltage
FB
4
Soft Start-up
Protection and
Short-Circuit
Protection
VOUT
EA
VREF
7.3 Feature Description
7.3.1 Undervoltage Lockout
The TPS61022 has a built-in undervoltage lockout (UVLO) circuit to ensure the device working properly. When
the input voltage is above the UVLO rising threshold of 1.8 V, the TPS61022 can be enabled to boost the output
voltage. After the TPS61022 starts up and the output voltage is above 2.2 V, the TPS61022 works with input
voltage as low as 0.5 V.
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7.3.2 Enable and Soft Start
When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2 V, the
TPS61022 is enabled and starts up. At the beginning, the TPS61022 charges the output capacitors with a
current of about 700 mA when the output voltage is below 0.4 V. When the output voltage is charged above 0.4
V, the output current is changed to having output current capability to drive 1-Ω resistance load. After the output
voltage reaches the input voltage, the TPS61022 starts switching, and the output voltage ramps up further. The
typical start-up time is 700 µs accounting from EN high to output reaching target voltage for the application with
input voltage is 2.5 V, output voltage is 5 V, output effective capacitance is 30 µF and no load. When the voltage
at the EN pin is below 0.4 V, the internal enable comparator turns the device into shutdown mode. In the
shutdown mode, the device is entirely turned off. The output is disconnected from input power supply.
7.3.3 Switching Frequency
The TPS61022 switches at a quasi-constant 1-MHz frequency when the input voltage is above 1.5 V. When the
input voltage is lower than 1.5 V, the switching frequency is reduced gradually to 0.6 MHz to improve the
efficiency and get higher boost ratio. When the input voltage is below 1 V, the switching frequency is fixed at a
quasi-constant 0.6 MHz.
7.3.4 Current Limit Operation
The TPS61022 uses a valley current limit sensing scheme. Current limit detection occurs during the off-time by
sensing of the voltage drop across the synchronous rectifier.
When the load current is increased such that the inductor current is above the current limit within the whole
switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before
the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached, the output
voltage decreases during further load increase.
The maximum continuous output current (IOUT(LC)), before entering current limit (CL) operation, can be defined
by 方程式1.
1
≈
’
IOUT(CL) = 1-D ì I
+
DIL P-P
(
)
LIM
∆
÷
◊
(
)
2
«
(1)
where
• D is the duty cycle
• ΔIL(P-P) is the inductor ripple current
The duty cycle can be estimated by 方程式2.
V
IN ì h
D = 1-
VOUT
(2)
where
• VOUT is the output voltage of the boost converter
• VIN is the input voltage of the boost converter
• ηis the efficiency of the converter, use 90% for most applications
The peak-to-peak inductor ripple current is calculated by 方程式3.
V ìD
L ì fSW
IN
DIL P-P
=
(
)
(3)
where
• L is the inductance value of the inductor
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• fSW is the switching frequency
• D is the duty cycle
• VIN is the input voltage of the boost converter
7.3.5 Pass-Through Operation
When the input voltage is higher than the setting output voltage, the output voltage is higher than the target
regulation voltage. When the output voltage is 101% of the setting target voltage, the TPS61022 stops switching
and fully turns on the high-side PMOS FET. The device works in pass-through mode. The output voltage is the
input voltage minus the voltage drop across the DCR of the inductor and the RDS(on) of the PMOS FET. When
the output voltage drops below the 97% of the setting target voltage as the input voltage declines or the load
current increases, the TPS61022 resumes switching again to regulate the output voltage.
7.3.6 Overvoltage Protection
The TPS61022 has an output overvoltage protection (OVP) to protect the device if the external feedback resistor
divider is wrongly populated. When the output voltage is above 5.7 V typically, the device stops switching. Once
the output voltage falls 0.1 V below the OVP threshold, the device resumes operating again.
7.3.7 Output Short-to-Ground Protection
The TPS61022 starts to limit the output current when the output voltage is below 1.8 V. The lower the output
voltage reaches, the smaller the output current is. When the VOUT pin is short to ground, and the output voltage
becomes less than 0.4 V, the output current is limited to approximate 700 mA. Once the short circuit is released,
the TPS61022 goes through the soft start-up again to the regulated output voltage.
7.3.8 Thermal Shutdown
The TPS61022 goes into thermal shutdown once the junction temperature exceeds 150°C. When the junction
temperature drops below the thermal shutdown recovery temperature, typically 130°C, the device starts
operating again.
7.4 Device Functional Modes
The TPS61022 operates at a quasi-constant frequency pulse width modulation (PWM) in moderate-to heavy
load condition. Based on the input voltage to output voltage ratio, a circuit predicts the required on-time of the
switching cycle. At the beginning of each switching cycle, the low-side NMOS FET switch, shown in Functional
Block Diagram, is turned on. The input voltage is applied across the inductor and the inductor current ramps up.
In this phase, the output capacitor is discharged by the load current. When the on-time expires, the main switch
NMOS FET is turned off, and the rectifier PMOS FET is turned on. The inductor transfers its stored energy to
replenish the output capacitor and supply the load. The inductor current declines because the output voltage is
higher than the input voltage. When the inductor current hits a value that is the error amplifier's output, the next
switching cycle starts again. The error amplifier compares the feedback voltage of the output voltage with an
internal reference voltage; its output determines the inductor valley current in every switching cycle.
In light load condition, the TPS61022 implements two operation modes (power-save mode with PFM and forced
PWM mode) to meet different application requirements. The operation modes are set by the status of the MODE
pin. When the MODE pin is connected to logic low, the device works in the PFM mode. When the MODE pin is
connected to logic high, the device works in the forced PWM mode.
7.4.1 Forced PWM Mode
In the forced PWM mode, the TPS61022 keeps the switching frequency constant in light load condition. When
the load current decreases, the output of the internal error amplifier decreases as well to keep the inductor
current down and deliver less power from input to output. When the output current further reduces, the current
through the inductor decreases to zero during the off-time. The high-side P-MOSFET is not turned off even if the
current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to zero. The
power flow is from output side to input side. The efficiency is low in this mode. But with the fixed switching
frequency, there is no audible noise and other problems which might be caused by low switching frequency in
light load condition.
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7.4.2 Power-Save Mode
The TPS61022 integrates a power-save mode with PFM to improve efficiency at light load. When the load
current decreases, the inductor valley current set by the output of the error amplifier no longer regulates the
output voltage. When the inductor valley current hits the low limit of 150 mA, the output voltage exceeds the
setting voltage as the load current decreases further. When the FB voltage hits the PFM reference voltage, the
TPS61022 goes into the power-save mode. In the power-save mode, when the FB voltage rises and hits the
PFM reference voltage, the device continues switching for several cycles because of the delay time of the
internal comparator — then it stops switching. The load is supplied by the output capacitor, and the output
voltage declines. When the FB voltage falls below the PFM reference voltage, after the delay time of the
comparator, the device starts switching again to ramp up the output voltage.
Output
Voltage
PFM mode at light load
1.01 x VOUT_NOM
VOUT_NOM
PWM mode at heavy load
图7-1. Output Voltage in PWM Mode and PFM Mode
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS61022 is a synchronous boost converter designed to operate from an input voltage supply range
between 0.5 V and 5.5 V with a minimum 6.5-A valley switch current limit. The TPS61022 typically operates at a
quasi-constant 1-MHz frequency PWM at moderate-to-heavy load currents when the input voltage is above 1.5
V. The switching frequency changes to 0.6 MHz gradually with the input voltage changing from 1.5 V to 1 V for
better efficiency and high step-up ratio. When the input voltage is below 1 V, the switching frequency is fixed at a
quasi-constant 0.6 MHz. At light load currents, when the MODE pin is set to low logic level, the TPS61022
converter operates in power-save mode with PFM to achieve high efficiency over the entire load current range.
When the MODE pin is set to high logic level, the TPS61022 converter operates in forced PWM mode to keep
the switching frequency constant.
8.2 Typical Application
The TPS61022 provides a power supply solution for portable devices powered by batteries or backup
applications powered by super-capacitors. With minimum 6.5-A switch current capability, the TPS61022 can
output 5 V and 3 A from a single-cell Li-ion battery.
L1
2.7 V to 4.35 V
1 µH
C1
10 µF
VIN
SW
5 V
VOUT
GND
C2
3 x 22 µF
R1
PWM
TPS61022
732 kꢀ
PFM
OFF
FB
MODE
EN
R2
100 kꢀ
ON
图8-1. Li-ion Battery to 5-V Boost Converter
8.2.1 Design Requirements
The design parameters are listed in 表8-1.
表8-1. Design Parameters
PARAMETERS
Input voltage
VALUES
2.7 V to 4.35 V
5 V
Output voltage
Output current
3 A
Output voltage ripple
±50 mV
8.2.2 Detailed Design Procedure
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8.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider (R1, R2 in Li-ion Battery to 5-V Boost Converter). When
the output voltage is regulated, the typical voltage at the FB pin is VREF. Thus the resistor divider is determined
by 方程式4.
≈
∆
«
’
VOUT
VREF
R1=
-1 ìR2
÷
◊
(4)
where
• VOUT is the regulated output voltage
• VREF is the internal reference voltage at the FB pin
For best accuracy, keep R2 smaller than 300 kΩ to ensure the current flowing through R2 is at least 100 times
larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity against noise
injection. Changing the R2 towards a higher value reduces the quiescent current for achieving highest efficiency
at low load currents.
8.2.2.2 Inductor Selection
Because the selection of the inductor affects steady-state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications, inductor value, saturation current, and dc resistance (DCR).
The TPS61022 is designed to work with inductor values between 0.33 µH and 2.9 µH. Follow 方程式 5 to 方程式
7 to calculate the inductor peak current for the application. To calculate the current in the worst case, use the
minimum input voltage, maximum output voltage, and maximum load current of the application. To have enough
design margins, choose the inductor value with –30% tolerances, and low power-conversion efficiency for the
calculation.
In a boost regulator, the inductor dc current can be calculated by 方程式5.
VOUT ìIOUT
IL DC
=
(
)
V ì h
IN
(5)
where
• VOUT is the output voltage of the boost converter
• IOUT is the output current of the boost converter
• VIN is the input voltage of the boost converter
• ηis the power conversion efficiency, use 90% for most applications
The inductor ripple current is calculated by 方程式6.
V ìD
L ì fSW
IN
DIL P-P
=
(
)
(6)
where
• D is the duty cycle, which can be calculated by 方程式2
• L is the inductance value of the inductor
• fSW is the switching frequency
• VIN is the input voltage of the boost converter
Therefore, the inductor peak current is calculated by 方程式7.
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DIL P-P
(
)
IL P = IL DC
+
(
)
(
)
2
(7)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The
saturation current of the inductor must be higher than the calculated peak inductor current. 表 8-2 lists the
recommended inductors for the TPS61022.
表8-2. Recommended Inductors for the TPS61022
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
PART NUMBER
L (µH)
SIZE (LxWxH)
VENDOR
XAL7030-102MEC
XAL6030-102MEC
XEL5030-102MEC
744316100
1
1
1
1
5.00
6.18
8.40
5.23
28
23
8 × 8 × 3.1
6.36 × 6.56 × 3.1
5.3 × 5.5 × 3.1
5.6 × 5.3 × 4.3
Coilcraft
Coilcraft
16.9
11.5
Coilcraft
Wurth Elecktronik
8.2.2.3 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple
voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a ceramic
capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by 方程
式8.
IOUT ìDMAX
fSW ì VRIPPLE
COUT
=
(8)
where
• DMAX is the maximum switching duty cycle
• VRIPPLE is the peak-to-peak output ripple voltage
• IOUT is the maximum output current
• fSW is the switching frequency
The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are
used. The output peak-to-peak ripple voltage caused by the ESR of the output capacitors can be calculated by
方程式9.
VRIPPLE(ESR) = IL(P) ìRESR
(9)
Take care when evaluating the derating of a ceramic capacitor under dc bias voltage, aging, and ac signal. For
example, the dc bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than 50%
of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure adequate
capacitance at the required output voltage. Increasing the output capacitor makes the output ripple voltage
smaller in PWM mode.
TI recommends using the X5R or X7R ceramic output capacitor in the range of 10-μF to 50-μF effective
capacitance. The output capacitor affects the small signal control loop stability of the boost regulator. If the
output capacitor is below the range, the boost regulator can potentially become unstable. Increasing the output
capacitor makes the output ripple voltage smaller in PWM mode.
8.2.2.4 Loop Stability, Feedforward Capacitor Selection
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop may be unstable.
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The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the stability of the converters.
Without any ringing, the loop has usually more than 45° of phase margin.
A feedforward capacitor (C3 in the 图 8-2) in parallel with R1 induces a pair of zero and pole in the loop transfer
function. By setting the proper zero frequency, the feedforward capacitor can increase the phase margin to
improve the loop stability. For large output capacitance more than 40 μF application, TI recommends a
feedforward capacitor to set the zero frequency (fFFZ) to 2 kHz. As for the input voltage lower than 2-V
application, TI recommends setting the zero frequency (fFFZ) to 20 kHz when the effective output capacitance is
less than 40 μF. The value of the feedforward capacitor can be calculated by 方程式10.
1
C3 =
2pì fFFZ ìR1
(10)
where
• R1 is the resistor between the VOUT pin and FB pin
• fFFZ is the zero frequency created by the feedforward capacitor
L1
VIN
1 µH
C1
VIN
SW
VOUT
C2
VOUT
GND
C3
R1
R2
PWM
ON
TPS61022
PFM
OFF
FB
MODE
EN
图8-2. TPS61022 Circuit With Feedforward Capacitor
8.2.2.5 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are excellent choices for input decoupling of the step-up converter as
they have extremely low ESR and are available in small footprints. Input capacitors must be located as close as
possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be
used to reduce input current ripple without limitations. Take care when using only ceramic input capacitors.
When a ceramic capacitor is used at the input and the power is being supplied through long wires, a load step at
the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part. In this circumstance, place additional bulk capacitance (tantalum or
aluminum electrolytic capacitor) between ceramic input capacitor and the power source to reduce ringing that
can occur between the inductance of the power source leads and ceramic input capacitor.
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8.2.3 Application Curves
VIN = 3.6 V, VOUT = 5 V, IOUT = 100 mA , MODE = low
VIN = 3.6 V, VOUT = 5 V, IOUT = 3 A
图8-4. Switching Waveform at Light Load
图8-3. Switching Waveform at Heavy Load
VIN = 3.6 V, VOUT = 5 V, 1.6-Ωresistance load
VIN = 3.6 V, VOUT = 5 V, 1.6-Ωresistance load
图8-5. Start-up Waveform
图8-6. Shutdown Waveform
VIN = 3.6 V, VOUT = 5 V, IOUT = 1 A to 3 A with 20-μs slew
VIN = 2.7 V to 4.35 V with 50-μs slew rate, VOUT = 5 V,
rate
IOUT = 3 A
图8-7. Load Transient
图8-8. Line Transient
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VIN = 3.6 V, VOUT = 5 V, IOUT = 0 A to 3 A Sweep, MODE = low
VIN = 0 V to 4.35 V Sweep, VOUT = 5 V, IOUT = 1 A
图8-9. Load Sweep
图8-10. Line Sweep
VIN = 3.6 V, VOUT = 5 V, IOUT = 1 A
VIN = 3.6 V, VOUT = 5 V, IOUT = 1 A
图8-11. Output Short Protection (Entry)
图8-12. Output Short Protection (Recover)
8.3 System Examples
For those applications with input voltage higher than 4.8 V, TI suggests adding a diode between the VIN pin and
the VOUT pin to pre-bias the output before the TPS61022 is enabled. As an example shown in 图8-13, the input
voltage is from a USB port in the range of 4.5 V to 5.25 V. The target output voltage is 5 V to 5.25 V.
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L1
4.75V ~ 5.25V
C1
1.0µH
D1
10µF
VIN
SW
5.0V
C2
VOUT
GND
R1
PWM
3 x 22µF
TPS61022
732kꢀ
PFM
OFF
FB
MODE
R2
EN
100kꢀ
ON
图8-13. TPS61022 Circuit for VIN > 4.8-V Application
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 0.5 V to 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or
aluminum electrolytic capacitor with a value of 100 µF. Output current of the input power supply must be rated
according to the supply voltage, output voltage, and output current of the TPS61022.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If the layout is not carefully done, the regulator could suffer from instability
and noise problems. To maximize efficiency, switch rise and fall time are very fast. To prevent radiation of high
frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin, and always use a ground plane under the switching
regulator to minimize interplane coupling. The input capacitor needs not only to be close to the VIN pin, but also
to the GND pin in order to reduce input supply ripple.
The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then
the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise
and fall time and must be kept as short as possible. Therefore, the output capacitor not only must be close to the
VOUT pin, but also to the GND pin to reduce the overshoot at the SW pin and VOUT pin.
10.2 Layout Example
GND
VOUT
FB
VOUT
EN
SW
GND
MODE
GND
VIN
VIN
GND
Note: A ceramic output capacitor is needed and must be close to VOUT pin and GND pin of the TPS61022
图10-1. Layout Example
10.3 Thermal Considerations
Restrict the maximum IC junction temperature to 125°C under normal operating conditions. Calculate the
maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal to PD(max). The
maximum-power-dissipation limit is determined using 方程式11.
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125 - TA
RqJA
PD max
=
(
)
(11)
where
• TA is the maximum ambient temperature for the application
• RθJA is the junction-to-ambient thermal resistance given in Thermal Information
The TPS61022 comes in a VQFN package. This package includes three power pads that improves the thermal
capabilities of the package. The real junction-to-ambient thermal resistance of the package greatly depends on
the PCB type, layout, and thermal pad connection. Using larger and thicker PCB copper for the power pads
(GND, SW, and VOUT) to enhance the thermal performance. Using more vias connects the ground plate on the
top layer and bottom layer around the IC without solder mask also improves the thermal capability.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61022RWUR
TPS61022RWUT
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RWU
RWU
7
7
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
(1UNF, 2GZH)
(1UNF, 2GZH)
Samples
Samples
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61022RWUR
TPS61022RWUT
VQFN-
HR
RWU
RWU
7
7
3000
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61022RWUR
TPS61022RWUT
VQFN-HR
VQFN-HR
RWU
RWU
7
7
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RWU0007A
A
2.1
1.9
B
2.1
1.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.35
1.15
1.05
0.85
2X
(0.1) TYP
0.4
0.3
2X
3X 0.5
4
2X 0.55
3
SYMM
1.5
0.25
0.15
1
7
0.3
0.2
PIN 1 IDENTIFICATION
(OPTIONAL)
SYMM
0.1
0.05
C A B
C
0.3
0.2
4X
4223724/C 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RWU0007A
(0.625)
(0.975)
(0.475)
2X (1.15)
2X (0.35)
7
1
3X
(0.5)
2X
(0.55)
PKG
(1.5)
(0.2)
3
4
PKG
4X (0.25)
4X
(0.45)
(1.45)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223724/C 02/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RWU0007A
(0.675)
(0.288)
(0.975)
4X (0.475)
4X (0.35)
7
1
3X
(0.5)
2X
(0.55)
(0.062)
PKG
(1.5)
2X (0.2)
3
4
4X (0.25)
PKG
2X
(0.625)
4X
(0.45)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1-3: 83%
SCALE: 30X
4223724/C 02/2018
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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