TPS61091 [TI]
SYNCHRONOUS BOOST CONVERTER WITH 2A SWITCH; 具有2A开关同步升压转换器
| 型号： | TPS61091 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS BOOST CONVERTER WITH 2A SWITCH |
| 文件： | 总19页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61090
TPS61091, TPS61092
Actual Size
(4,15 mm x 4,15 mm)
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
SYNCHRONOUS BOOST CONVERTER
WITH 2A SWITCH
FEATURES
DESCRIPTION
•
Synchronous (96% Efficient) Boost Converter
The TPS6109x devices provide a power supply
solution for products powered by either a one-cell
Li-Ion or Li-polymer, or a two-cell alkaline, NiCd or
NiMH battery and required supply currents up to or
higher than 1 A. The converter generates a stable
output voltage that is either adjusted by an external
resistor divider or fixed internally on the chip. It
provides high efficient power conversion and is
capable of delivering output currents up to 0.5 A at 5
V at a supply voltage down to 1.8 V. The im-
plemented boost converter is based on a fixed
frequency, pulse-width- modulation (PWM) controller
using a synchronous rectifier to obtain maximum
efficiency. Boost switch and rectifier switch are con-
nected internally to provide the lowest leakage induct-
ance and best EMI behavior possible. The maximum
peak current in the boost switch is limited to a value
of 2500 mA.
With 500-mA Output Current From 1.8-V Input
Available in a 16-Pin QFN 4 x 4 Package
Device Quiescent Current: 20-µA (Typ)
Input Voltage Range: 1.8-V to 5.5-V
•
•
•
•
Adjustable Output Voltage Up to 5.5-V Fixed
Output Voltage Options
•
Power Save Mode for Improved Efficiency at
Low Output Power
•
•
Low Battery Comparator
Low EMI-Converter (Integrated Antiringing
Switch)
•
•
Load Disconnect During Shutdown
Over-Temperature Protection
APPLICATIONS
The converter can be disabled to minimize battery
drain. During shutdown, the load is completely dis-
connected from the battery. A low-EMI mode is
implemented to reduce ringing and, in effect, lower
radiated electromagnetic energy when the converter
enters the discontinuous conduction mode.
•
All Single Cell Li or Dual Cell Battery, or USB
Powered Operated Products as MP-3 Player,
PDAs, and Other Portable Equipment
The output voltage can be programmed by an exter-
nal resistor divider or is fixed internally on the chip.
The device is packaged in a 16-pin QFN 4 x 4 mm
(16 RSA) package.
L1
e.g. 5 V up to
500 mA
VOUT
SW
6.8 µH
C2
2.2 µF
C3
100 µF
VBAT
R3
R4
R1
R2
1.8 V to 5 V
Input
C1
10 µF
EN
FB
R5
LBI
SYNC
GND
LBO
Low Battery
Output
PGND
TPS6109x
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OUTPUT VOLTAGE OPTIONS(1)
OUTPUT VOLTAGE
(2)
TA
PACKAGE
Part Number
DC/DC
Adjustable
3.3 V
16-Pin QFN 4x4mm
16-Pin QFN 4x4mm
16-Pin QFN 4x4mm
TPS61090RSA
TPS61091RSA
TPS61092RSA
40°C to 85°C
5 V
(1) Contact the factory to check availability of other fixed output voltage versions.
(2) The RSA package is available taped and reeled. Add R suffix to device type (e.g., TPS61090RSAR) to order quantities of 3000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS6109x
Input voltage range on LBI
-0.3 V to 3.6 V
-0.3 V to 7 V
-40°C to 85°C
150°C
Input voltage range on SW, VOUT, LBO, VBAT, SYNC, EN, FB
Operating free air temperature range TA
Maximum junction temperature TJ
Storage temperature range Tstg
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage at VBAT, VI
Inductance, L
1.8
5.5
V
2.2
6.8
10
µH
µF
µF
Input, capacitance, Ci
Output capacitance, Co
22
-40
-40
100
Operating free air temperature, TA
Operating virtual junction temperature, TJ
85 °C
125 °C
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range and over recommended input voltage range (typical values are at an ambient
temperature range of 25°C) (unless otherwise noted)
DC/DC STAGE
PARAMETER
Input voltage range
TEST CONDITIONS
MIN
1.8
TYP MAX UNIT
VI
5.5
5.5
V
VO
VFB
f
TPS61090 output voltage range
TPS61090 feedback voltage
Oscillator frequency
1.8
V
490
500
500
2000
500
600
510
700
700
mV
kHz
kHz
mA
mA
mΩ
mΩ
Frequency range for synchronization
Switch current limit
ISW
VOUT= 5 V
2200 2500
0.4 x ISW
Start-up current limit
Boost switch on resistance
Rectifying switch on resistance
Total accuracy
VOUT= 5 V
VOUT= 5 V
55
55
-3%
3%
Line regulation
0.6%
2
TPS61090
TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
Electrical Characteristics (continued)
over recommended free-air temperature range and over recommended input voltage range (typical values are at an ambient
temperature range of 25°C) (unless otherwise noted)
DC/DC STAGE
PARAMETER
Load regulation
TEST CONDITIONS
MIN
TYP MAX UNIT
0.6%
into
VBAT
IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =5 V
10
25
µA
Quiescent current
Shutdown current
into
VOUT
IO = 0 mA, VEN = VBAT = 1.8 V, VOUT = 5 V
VEN= 0 V, VBAT = 2.4 V
10
20
1
µA
µA
0.1
CONTROL STAGE
PARAMETER
TEST CONDITIONS
VLBI voltage decreasing
VLBI voltage decreasing
MIN
TYP
1.5
MAX UNIT
VUVLO
VIL
Under voltage lockout threshold
LBI voltage threshold
V
490
500
10
510
mV
mV
µA
V
LBI input hysteresis
LBI input current
EN = VBAT or GND
0.01
0.04
100
0.01
0.1
0.4
LBO output low voltage
LBO output low current
LBO output leakage current
EN, SYNC input low voltage
EN, SYNC input high voltage
EN, SYNC input current
Overtemperature protection
Overtemperature hysteresis
VO = 3.3 V, IOI = 100 µA
µA
µA
V
VLBO = 7 V
0.1
VIL
VIH
0.2 × VBAT
0.8 × VBAT
V
Clamped on GND or VBAT
0.01
140
20
0.1
µA
°C
°C
PIN ASSIGNMENTS
RSA Package
(Top View)
VOUT
NC
LBO
EN
SW
SYNC
LBI
SW
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
11
EN
FB
I
I
Enable input. (1/VBAT enabled, 0/GND disabled)
Voltage feedback of adjustable versions
14
3
TPS61090
TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
Pin Assignments (continued)
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
GND
NO.
13
9
I/O
I
Control/logic ground
LBI
LBO
NC
Low battery comparator input (comparator enabled with EN)
Low battery comparator output (open drain)
Not connected
12
2
O
SYNC
10
I
Enable/disable power save mode (1: VBAT disabled, 0: GND enabled, clock signal for
synchronization)
SW
PGND
3, 4
I
I/O
I
Boost and rectifying switch input
Power ground
5, 6, 7
8
VBAT
Supply voltage
VOUT
1, 15, 16
O
DC/DC output
PowerPAD™
Must be soldered to achieve appropriate power dissipation. Should be connected to PGND.
FUNCTIONAL BLOCK DIAGRAM
SW
VOUT
Anti-
Ringing
VBAT
PGND
PGND
Gate
Control
100 kW
PGND
10 pF
Error Amplifier
_
FB
Regulator
+
= 0.5 V
+
V
REF
_
Control Logic
Oscillator
GND
Temperature
Control
EN
SYNC
GND
LBI
Low Battery Comparator
+
_
LBO
+
V
REF
= 0.5 V
_
GND
4
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
L1
VOUT
FB
V
SW
OUT
6.8 µH
Boost Output
C2
2.2 µF
C3
100 µF
VBAT
R3
R4
R1
C1
10 µF
Power
Supply
EN
R5
LBI
R2
SYNC
GND
LBO
Low Battery
Output
PGND
List of Components:
U1 = TPS6109xRSA
TPS6109x
L1 = Sumida CDRH103R-6R8
C1, C2 = X7R/X5R Ceramic
C3 = Low ESR Tantalum
5
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
TYPICAL CHARACTERISTICS
Table of Graphs
DC/DC Converter
Figure
1, 2
3
Maximum output current
vs Input voltage
vs Output current (TPS61090) (VO = 2.5 V, VI = 1.8 V, VSYNC = 0 V)
vs Output current (TPS61091) (VO = 3.3 V, VI = 1.8 V, 2.4 V, VSYNC = 0 V)
vs Output current (TPS61092) (VO = 5.0 V, VI = 2.4 V, 3.3 V, VSYNC = 0 V)
vs Input voltage (TPS61091) (IO = 10 mA, 100 mA, 500 mA, VSYNC = 0 V)
vs Input voltage (TPS61092) (IO = 10 mA, 100 mA, 500 mA, VSYNC = 0 V)
vs Output current (TPS61091) (VI = 2.4 V)
4
Efficiency
5
6
7
8
Output voltage
vs Output current (TPS61092) (VI = 3.3 V)
9
No-load supply current into VBAT
No-load supply current into VOUT
vs Input voltage (TPS61092)
10
11
12
13
14
15
16
vs Input voltage (TPS61092)
Output voltage in continuous mode (TPS61092)
Output voltage in power save mode (TPS61092)
Load transient response (TPS61092)
Waveforms
Line transient response (TPS61092)
DC/DC converter start-up after enable (TPS61092)
TPS61091
TPS61092
MAXIMUM OUTPUT CURRENT
MAXIMUM OUTPUT CURRENT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
2.5
2.5
2
2
1.5
1
1.5
1
0.5
0.5
0
0
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
V
- Input Voltage - V
V
- Input Voltage - V
I
I
Figure 1.
Figure 2.
6
TPS61090
TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
TPS61090
EFFICIENCY
vs
TPS61091
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V = 2.4 V
I
V = 1.8 V
I
V
= 2.5 V
O
10
0
V
= 3.3 V
10
0
O
V = 1.8 V
I
1
10
1
10
100
1000
10000
100
1000
10000
I
O
- Output Current - mA
I
O
- Output Current - mA
Figure 3.
Figure 4.
TPS61092
EFFICIENCY
vs
TPS61091
EFFICIENCY
vs
OUTPUT CURRENT
INPUT VOLTAGE
100
90
100
90
80
70
60
I
= 100 mA
= 500 mA
V = 3.3 V
I
O
V = 2.4 V
I
I
O
= 10 mA
I
O
80
50
40
30
20
10
0
70
60
50
V
= 5 V
O
1.8
2
2.2
2.4
2.6
2.8
3
3.2
1
10
100
1000
10000
V - Input Voltage - V
I
I
O
- Output Current - mA
Figure 5.
Figure 6.
7
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
TPS61092
EFFICIENCY
vs
INPUT VOLTAGE
100
TPS61091
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.35
3.3
I
O
= 100 mA
VBAT = 2.4 V
95
90
85
80
75
70
65
60
I
O
= 500 mA
I
O
= 10 mA
3.25
55
50
3.2
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
10
100
1000
10000
I
O
- Output Current - mA
V - Input Voltage - V
I
Figure 7.
Figure 8.
TPS61092
OUTPUT VOLTAGE
vs
TPS61092
NO-LOAD SUPPLY CURRENT INTO VBAT
vs
OUTPUT CURRENT
INPUT VOLTAGE
5.1
16
14
12
10
8
VBAT = 3.3 V
85°C
25°C
5.05
5
4.95
4.9
-40°C
6
4
4.85
4.8
2
0
10
100
1000
10000
2
3
4
5
I
O
- Output Current - mA
V - Input Voltage - V
I
Figure 9.
Figure 10.
8
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
TPS61092
MINIMUM LOAD RESISTANCE AT STARTUP
NO-LOAD SUPPLY CURRENT INTO VOUT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
25
20
15
10
16
85°C
14
25°C
12
10
-40°C
8
6
4
5
0
2
0
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
V - Input Voltage - V
I
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
V - Input Voltage - V
I
Figure 11.
Figure 12.
TPS61092
TPS61092
OUTPUT VOLTAGE IN CONTINUOUS MODE
OUTPUT VOLTAGE IN POWER SAVE MODE
V = 3.3 V, R = 10 Ω
I
L
V = 3.3 V, R =100 Ω
I
L
Output Voltage
50 mV/Div, AC
Output Voltage
20 mV/Div
Inductor Current
200 mA/Div, DC
Inductor Current
200 mA/Div
Timebase - 1 µs/Div
Figure 13.
Timebase - 100 µs/Div
Figure 14.
9
TPS61090
TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
TPS61092
TPS61092
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
V = 2.5 V, I =200 mA to 400 mA
V = 2.2 V to 2.7 V, R =50 Ω
Input Voltage
500 mV/Div, DC
I
L
I
L
Output Current
500 mA/Div, DC
Output Voltage
20 mV/Div, AC
Output Voltage
50 mV/Div, AC
Timebase - 2 ms/Div
Timebase - 2 ms/Div
Figure 15.
Figure 16.
TPS61092
DC/DC CONVERTER START-UP AFTER ENABLE
Enable
5 V/Div, DC
Output Voltage
2 V/Div, DC
Inductor Current
500 mA/Div, DC
Voltage at SW
2 V/Div, DC
V = 2.4 V,
I
R
L
=50 Ω
Timebase - 200 µs/Div
Figure 17.
10
TPS61090
TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
APPLICATION INFORMATION
DESIGN PROCEDURE
The TPS6109x dc/dc converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery
with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell
Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary
alkaline battery cells can be the power source in systems where the TPS6109x is used.
Programming the Output Voltage
The output voltage of the TPS61090 dc/dc converter section can be adjusted with an external resistor divider.
The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is
5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB
pin. The typical current into the FB pin is 0.01 µA, and the voltage across R4 is typically 500 mV. Based on those
two values, the recommended value for R4 should be lower than 500 kΩ, in order to set the divider current at 1
µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200
kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using
Equation 1:
V
V
O
O
R3 + R4
* 1 + 200 kW
* 1
ǒ Ǔ ǒ Ǔ
V
500 mV
FB
(1)
If as an example, an output voltage of 5.0 V is needed, a 1.8-MΩ resistor should be chosen for R3. If for any
reason the value for R4 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is
recommended. The required capacitance value can be easily calculated using Equation 2
200 kW
R4
ǒ
–1Ǔ
C
+ 10 pF
parR3
(2)
L1
V
OUT
SW
VOUT
FB
Boost Output
C2
C3
VBAT
R3
R4
R1
R2
Power
C1
EN
Supply
R5
LBI
SYNC
GND
Low Battery
Output
LBO
PGND
TPS6109x
Figure 18. Typical Application Circuit for Adjustable Output Voltage Option
Programming the LBI/LBO Threshold Voltage
The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The
typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is
generated on-chip, which has a value of 500 mV. The recommended value for R2is therefore in the range of 500
kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be
calculated using Equation 3.
11
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TPS61091, TPS61092
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SLVS484A–JUNE 2003–REVISED APRIL 2004
APPLICATION INFORMATION (continued)
V
V
BAT
BAT
R1 + R2
* 1 + 390 kW
* 1
ǒ
Ǔ ǒ Ǔ
V
500 mV
LBI*threshold
(3)
The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated
battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with
a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not
exceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND.
Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion. A
boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is
recommended to keep the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. For example, the current limit threshold of the TPS6109x's switch is 2500 mA at an
output voltage of 5 V. The highest peak current through the inductor and the switch depends on the output load,
the input (VBAT), and the output voltage (VOUT). Estimation of the maximum average inductor current can be done
using Equation 4:
V
OUT
0.8
I
+ I
L
OUT
V
BAT
(4)
For example, for an output current of 500 mA at 5 V, at least 1750 mA of average current flows through the
inductor at a minimum input voltage of 1.8 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those
parameters, it is possible to calculate the value for the inductor by using Equation 5:
ǒVOUT BATǓ
V
–V
BAT
L +
DI ƒ V
L
OUT
(5)
Parameter f is the switching frequency and ∆IL is the ripple current in the inductor, i.e., 20% × IL. In this example,
the desired inductor has the value of 5.5 µH. With this calculated value and the calculated currents, it is possible
to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to
higher currents as estimated in equation 4. Also, the losses in the inductor caused by magnetic hysteresis losses
and copper losses are a major parameter for total circuit efficiency.
The following inductor series from different suppliers have been used with the TPS6109x converters:
List of Inductors
VENDOR
Sumida
INDUCTOR SERIES
CDRH6D28
CDRH6D38
CDRH103R
Wurth Elektronik
EPCOS
WE-PD type L
WE-PD type XL
B82464G
12
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SLVS484A–JUNE 2003–REVISED APRIL 2004
Capacitor Selection
Input Capacitor
At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.
Output Capacitor DC/DC Converter
The major parameter necessary to define the minimum value of the output capacitor is the maximum allowed
output voltage ripple in steady state operation of the converter. This ripple is determined by two parameters of
the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the
defined ripple, supposing that the ESR is zero, by using equation Equation 6:
ǒVOUT BATǓ
I
* V
OUT
C
+
min
ƒ DV V
OUT
(6)
Parameter f is the switching frequency and ∆V is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum capacitance of 53 µF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 7:
DV
I
R
ESR
OUT
ESR
(7)
An additional ripple of 40 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple
is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this
example, the total ripple is 50 mV. Additional ripple is caused by load transients. This means that the output
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor
has to completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. With the
calculated minimum value of 53 µF and load transient considerations, a reasonable output capacitance value is
in a 100 µF range. For economical reasons this usually is a tantalum capacitor. Because of this the control loop
has been optimized for using output capacitors with an ESR of above 30 mΩ.
Small Signal Stability
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel to R3 helps to obtain small signal stability with lowest ESR output capacitors. For more
detailed analysis the small signal transfer function of the error amplifier and regulator, which is given is
Equation 8, can be used.
d5(R3 ) R4)
R4 (1 ) i w 2.3 ms)
d
A
+
A
+
REG
REG
V
FB
(8)
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
13
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
APPLICATION INFORMATION
L1
V
5 V
CC
VOUT
FB
SW
6.8 µH
Boost Output
C2
2.2 µF
C3
100 µF
VBAT
Battery
Input
R1
R2
C1
EN
10 µF
R5
LBI
SYNC
GND
LBO
LBO
PGND
TPS61092
List of Components:
U1 = TPS6109xRSA
L1 = Sumida CDRH103R-6R8
C1, C2 = X7R,X5R Ceramic
C3 = Low ESR Tantalum
Figure 19. Power Supply Solution for Maximum Output Power
V
10 V
CC2
C5
Unregulated
Auxiliary Output
DS1
C6
1 µF
0.1 µF
L1
V
5 V
SW
CC1
VOUT
FB
6.8 µH
Boost Main Output
C2
2.2 µF
C3
100 µF
VBAT
EN
Battery
Input
R1
C1
10 µF
LBI
R5
R2
SYNC
GND
LBO
LBO
PGND
TPS61092
List of Components:
U1 = TPS6109xRSA
L1 = Sumida CDRH103R-6R8
C1, C2, C5, C6, = X7R,X5R Ceramic
C3 = Low ESR Tantalum
DS1 = BAT54S
Figure 20. Power Supply Solution With Auxiliary Positive Output Voltage
14
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
Application Information (continued)
V
-5 V
CC2
C5
Unregulated
Auxiliary Output
DS1
C6
1 µF
0.1 µF
L1
V
5 V
SW
CC1
VOUT
6.8 µH
Boost Main Output
C2
2.2 µF
C3
100 µF
VBAT
EN
Battery
Input
R1
C1
10 µF
FB
LBI
R5
R2
SYNC
GND
LBO
LBO
PGND
TPS61092
List of Components:
U1 = TPS6109xRSA
L1 = Sumida CDRH103R-6R8
C1, C2, C5, C6 = X7R,X5R Ceramic
C3 = Low ESR Tantalum
DS1 = BAT54S
Figure 21. Power Supply Solution With Auxiliary Negative Output Voltage
DETAILED DESCRIPTION
Synchronous Rectifier
The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.
Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power
conversion efficiency reaches 96%. To avoid ground shift due to the high currents in the NMOS switch, two
separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS
switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND
pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In
conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in
shutdown and allows current flowing from the battery to the output. This device however uses a special circuit
which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when
the regulator is not enabled (EN = low).
The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of
the converter. No additional components have to be added to the design to make sure that the battery is
disconnected from the output of the converter.
Controller Circuit
The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input
voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So
changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect
and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,
only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output
voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to
generate an accurate and stable output voltage.
The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and
the inductor. The typical peak current limit is set to 2200 mA.
An internal temperature sensor prevents the device from getting overheated in case of excessive power
dissipation.
15
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
Detailed Description (continued)
Device Enable
The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In
shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is
switched off, and the load is isolated from the input (as described in the Synchronous Rectifier Section). This
also means that the output voltage can drop below the input voltage during shutdown. During start-up of the
converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the
battery.
Undervoltage Lockout
An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than typically
1.6 V. When in operation and the battery is being discharged, the device automatically enters the shutdown
mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is
implemented in order to prevent the malfunctioning of the converter.
Softstart
When the device enables the internal startup cycle starts with the first step, the precharge phase. During
precharge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input
voltage. The rectifying switch current is limited in that phase. This also limits the output current under short-circuit
conditions at the output. After charging the output capacitor to the input voltage the device starts switching. Until
the output voltage is reached, the boost switch current limit is set to 40% of its nominal value to avoid high peak
currents at the battery during startup. When the output voltage is reached, the regulator takes control and the
switch current limit is set back to 100%.
Power Save Mode and Synchronization
The SYNC pin can be used to select different operation modes. To enable power save, SYNC must be set low.
Power save mode is used to improve efficiency at light load. In power save mode the converter only operates
when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several
pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. This
power save mode can be disabled by setting the SYNC to VBAT.
Applying an external clock with a duty cycle between 30% and 70% at the SYNC pin forces the converter to
operate at the applied clock frequency. The external frequency has to be in the range of about ±20% of the
nominal internal frequency. Detailed values are shown in the electrical characteristic section of the data sheet.
Low Battery Detector Circuit—LBI/LBO
The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag
when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is
enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI.
During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold.
It is active low when the voltage at LBI goes below 500 mV.
The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider
connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV,
which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the
application section for more details about the programming of the LBI threshold. If the low-battery detection
circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left
unconnected. Do not let the LBI pin float.
16
TPS61090
TPS61091, TPS61092
www.ti.com
SLVS484A–JUNE 2003–REVISED APRIL 2004
Low-EMI Switch
The device integrates a circuit that removes the ringing that typically appears on the SW node when the
converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the
rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the
battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the
inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and
therefore dampens ringing.
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum junction temperature (TJ) of the TPS6109x devices is 150°C. The thermal resistance of the 16-pin
QFN PowerPAD package (RSA) isRΘJA = 38.1 °C/W, if the PowerPAD is soldered and the board layout is
optimized. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore,
the maximum power dissipation is about 1700 mW. More power can be dissipated if the maximum ambient
temperature of the application is lower.
T
* T
J(MAX)
R
A
150°C * 85°C
38.1 kńW
P
+
+
+ 1700 mW
D(MAX)
qJA
If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is
lower. Using the above equation (8) results in 1050 mW power dissipation.
17
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