TPS61096ADSST [TI]
具有 1μA 静态电流的 28V 输出电压升压转换器 | DSS | 12 | -40 to 85;
| 型号： | TPS61096ADSST |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1μA 静态电流的 28V 输出电压升压转换器 | DSS | 12 | -40 to 85 升压转换器 PC 开关 光电二极管 输出元件 |
| 文件： | 总28页 (文件大小：2333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61096A
SLVSE09A –APRIL 2017–REVISED APRIL 2017
TPS61096A 28-V Output Voltage Boost Converter with Ultra-Low Quiescent Current
The TPS61096A integrates a 30-V power switch and
a power diode. It can output up to 28 Volts. The
1 Features
1
•
•
•
•
1 µA ultra-low IQ into VIN pin
TPS61096A uses
a PFM peak current control
Operating Input Voltage from 1.8 V to 5.5 V
Adjustable Output Voltage from 4.5 V to 28 V
Selectable Inductor Peak Current:
scheme to obtain the highest efficiency over a wide
range of input and output load conditions. It only
consumes 1 µA quiescent current and can achieve up
to 70% efficiency under 10-µA load condition.
–
0.25 A and 0.5 A
The TPS61096A can also support selective inductor
peak current. With 250-mA current limit, the
TPS61096A can reduce inductor ripple so that it
reduces external component size for light load
applications. With 500 mA current limit, the
TPS61096A can provide 30 mA output current for a
conversion from 3.3 V to 18 V.
•
•
•
•
•
Integrated Power Diode
Integrated Level Shifters
70% Efficiency at 10 µA load
12-Pin 3-mm x 2-mm WSON Package
Create a Custom Design Using the TPS61096A
With the WEBENCH® Power Designer
The TPS61096A integrates two-channel low-power
level shifters to convert low level signals to output
voltage level signals for specific applications. It only
consumes 1-µA static current per channel and
ensures very low static and dynamic power
consumption across the entire output range.
2 Applications
•
•
•
•
•
Stylus
Memory LCD Bias
Sensor Power
The TPS61096A is available in a 12-pin 3.0-mm x
2.0-mm WSON Package.
General Purpose Bias
RF Mems Relay Power
Device Information(1)
3 Description
PART NUMBER
PACKAGE
BODY SIZE (NOM)
The TPS61096A is a high output voltage boost
converter with ultra-low quiescent current. It is
designed for products that require high efficiency at
light load conditions powered by either two-cell
alkaline, or one-cell Li-Ion or Li-polymer battery.
TPS61096A
WSON (12)
3 mm x 2 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
L
VOUT
SW
VIN
VOUT
4.5 V to 28 V
2.2 µH
COUT
VOSNS
VIN
10 µF
1.8 V to 5.5 V
CIN
4.7 µF
RUP
EN
FB
TPS61096A
RDOWN
ILIM
GND
LVI1
LVI2
HVO1
HVO2
Level Shifter
Level Shifter
/opyright © 2017, Çexas Lnstruments Lncorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61096A
SLVSE09A –APRIL 2017–REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 ESD Ratings ............................................................ 4
6.2 Recommended Operating Conditions....................... 4
6.3 Thermal Information.................................................. 4
6.4 Electrical Characteristics........................................... 5
6.5 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 19
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Device Support .................................................... 20
11.2 Receiving Notification of Documentation Updates 20
11.3 Community Resources.......................................... 20
11.4 Trademarks........................................................... 20
11.5 Electrostatic Discharge Caution............................ 20
11.6 Glossary................................................................ 21
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2017) to Revision A
Page
•
Set status to Production Data ................................................................................................................................................ 1
2
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SLVSE09A –APRIL 2017–REVISED APRIL 2017
5 Pin Configuration and Functions
DSS Package
12-Pin WSON, 3 mm × 2 mm × 0.75 mm
Top View
LV1
LV2
VIN
SW
ILIM
EN
HVO1
HVO2
GND
VOUT
VOSNS
FB
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
LVI1
NO.
1
I
Input of level shifter 1
LVI2
VIN
SW
2
I
I
Input of level shifter 2
IC power supply input
3
4
PWR
Switch pin of the converter. It is connected to inductor.
Inductor peak current limit selection pin. Logic low voltage to select 250mA peak current
limit, logic high voltage to select 500mA peak current limit. Must be actively tied high or low.
Do not leave it floating.
ILIM
5
I
Enable logic input. Logic high voltage enables the device, logic low voltage disables the
device. Must be actively tied high or low. Do not leave it floating.
EN
FB
6
7
8
I
I
Voltage feedback of adjustable output voltage. Connect to the center tap of a resistor divider
to program the output voltage.
Boost converter output voltage sense pin. Connect an external resistor divider between this
pin and FB pin.
VOSNS
I/O
VOUT
GND
9
PWR
PWR
O
Boost converter output
Ground pin
10
11
12
HVO2
HVO1
Output of level shifter 2
Output of level shifter 1
O
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6 Specifications
MIN
–0.3
-0.3
MAX
6
UNIT
V
VIN, EN, ILIM, LVI1, LVI2
FB
3.6
V
Voltage range at terminals
SW, VOUT, VOSNS, HVO1,
HVO2
–0.3
32
V
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.1 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
± 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
4.5
1.0
1.0
10
NOM
MAX
5.5
28
UNIT
V
VIN
VOUT
L
Input voltage
Boost converter output voltage
Inductor
V
2.2
4.7
10
47
µH
µF
µF
°C
CIN
COUT
TJ
Input capacitor
Output capacitor
100
125
Operating junction temperature
–40
6.3 Thermal Information
TPS61096A
DSS (WSON)
12 PINS
65.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
72.4
29.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.5
ψJB
29.7
RθJC(bot)
10.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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SLVSE09A –APRIL 2017–REVISED APRIL 2017
6.4 Electrical Characteristics
-40°C ≤ TJ ≤ 125°C and VIN=3.6V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
1.8
5.5
1.7
0.3
V
V
V
VUVLO
Undervoltage lockout threshold
Hysteresis
Input voltage rising
1.5
0.2
IQ_VIN
Quiescent current into VIN pin
Device enabled, no load, no
switching
1.2
2.5
µA
-40°C ≤ TJ ≤ 85 °C
IQ_VOUT
Quiescent current into VOUT pin
Shutdown current into VIN pin
Device enabled
internal LS main switch on, VOSNS
switch on
VOUT = 20 V, IQ to level shifter
excluded, -40°C ≤ TJ ≤ 85 °C
0.2
0.3
µA
µA
ISD
Device disabled
0.07
1
-40°C ≤ TJ ≤ 85 °C
OUTPUT
VOUT
Output voltage range
4.5
28
V
V
VREF
Internal reference voltage
Leakage current into VOUT pin
0.98
1.02
IOUT_LKG
Device disabled
VOUT = 20 V
0.2
µA
-40°C ≤ TJ ≤ 85 °C
IFB_LKG
VOVP
Leakage current into FB pin
VFB = 1.0 V
0.2
30.6
1.2
µA
V
Output overvoltage protection
threshold
Rising edge at VOUT pin
28.2
0.4
29.4
0.8
VOVP_HYS
Overvoltage protection hysteresis
V
POWER SWITCH AND CURRENT LIMIT
RDS(on)
IILIM
MOSFET on-resistance
Peak switch current limit
VIN = 3.6 V
ILIM = Low
ILIM = High
450
0.25
0.5
1
700
0.35
0.6
mΩ
A
0.15
0.35
A
tSS
Soft-start time
4.5
ms
ISW_LKG
Leakage current into SW pin (from
SW pin to GND)
Device disabled , VSW = 20 V
-40°C ≤ TJ ≤ 85 °C
0.5
1
µA
µA
LEVEL SHIFTER
IQ_LS
Level shifters quiescent current into Both level shifter channel enabled,
VOUT pin
0.5
1.5
LVIx = Low
Both level shifter channel enabled,
LVIx = High
3
µA
kHz
V
fPULSE
VIL
Pulse frequency
CHVOx ≤ 10 pF
200
Low level input voltage threshold at Falling edge
LVIx pin
0.15 ×
Vin
VIH
High level input voltage threshold at Rising edge
LVIx pin
0.8 × Vin
V
V
VOH
High-level output voltage at HVOx
pin
12 V ≤ VOUT ≤ 28 V
IHVOx = 10 µA
VOUT
0.1 V
–
12 V ≤ VOUT ≤ 28 V
IHVOx = 100 µA
VOUT
0.3 V
–
V
VOL
Low-level output voltage at HVOx
12 V ≤ VOUT ≤ 28 V
IHVOx = -10 µA
0.1
0.3
V
12 V ≤ VOUT ≤ 28 V
IHVOx = -100 µA
V
ISRC
ISINK
Level shifter high-side FET sourcing VOUT = 20 V,
800
800
µA
µA
current
VHVOx = 0 V
Level shifter low-side FET sinking
current
VHVOx = 20 V
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Electrical Characteristics (continued)
-40°C ≤ TJ ≤ 125°C and VIN=3.6V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Iin
Input leakage current at LVIx pin
VOUT = 0 V to 28 V
VLVIx = 0 V to 4.5 V
0.5
µA
VOUT = 20 V, CHVOx = 5 pF
From VLVIx rising above 0.8×Vin to
VHVOx rising above 2 V
500
500
ns
ns
Propagation delay from input to
output
tpd
VOUT = 20 V, CHVOx = 5 pF
From VLVIX falling below 0.15×Vin to
VHVOx falling below 18 V
Control Logic
VIL_EN
EN pin low level input voltage
threshold
0.4
0.4
V
V
VIH_EN
EN pin high level input voltage
threshold
1.2
VIL_ILIM
VIH_ILIM
IEN_LKG
IILIM_LKG
ILIM pin low level input voltage
threshold
V
ILIM pin high level input voltage
threshold
1.2
50
50
V
Leakage current into EN pin
VEN = 5 V
-40°C ≤ TJ ≤ 85 °C
nA
nA
Leakage current into ILIM pin
VILIM = 5 V
-40°C ≤ TJ ≤ 85 °C
Protection
TSD
Overtemperature protection
Overtemperature hysteresis
TJ rising
150
25
°C
°C
TSD_HYS
TJ falling below TSD
6
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SLVSE09A –APRIL 2017–REVISED APRIL 2017
6.5 Typical Characteristics
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN = 1.8 V
VIN = 2.7 V
VIN = 3.6 V
VIN = 4.2 V
VOUT = 12 V
VOUT = 18 V
VOUT = 24 V
10m
100m
1m
10m
100m
10m
100m
1m
10m
100m
Output Current (A)
Output Current (A)
D001
D002
VIN =1.8 V, 2.7 V, 3.6 V, 4.2 V
VOUT= 12 V
VIN = 3.6 V
VOUT = 12 V, 18 V, 24 V
Figure 1. Load Efficiency with Different Inputs
Figure 2. Load Efficiency with Different Outputs
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.02
1.015
1.01
1.005
1
0.995
0.99
0.985
0.98
VIN = 1.8 V
VIN = 3.6 V
VIN = 4.5 V
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D004
D005
VIN = 1.8 V, 3.6 V, 4.5 V
No switching
VIN = 3.6 V
TJ= –40°C to 125°C
Figure 3. Quiescient Current into VIN vs Temperature
Figure 4. Reference Voltage vs Temperature
0.7
0.7
0.65
0.6
0.65
0.6
0.55
0.5
0.55
0.5
0.45
0.4
0.45
0.4
0.35
0.3
0.35
0.3
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100
120
Input Voltage (V)
Temperature (èC)
D006
D007
VIN= 1.8 V to 5.5 V
TJ= 25°C
VIN= 3.6 V
TJ = –40°C to 125°C
Figure 5. Current Limit vs VIN with ILIM = H
Figure 6. Current Limit vs Temperature with ILIM = H
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Typical Characteristics (continued)
0.5
0.45
0.4
0.5
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
Temperature (°C)
80
100
125
Input Voltage (V)
D008
D009
VIN= 1.8 V to 5.5 V
TJ = 25°C
VIN= 3.6 V
TJ = –40°C to 125°C
Figure 7. Current Limit vs VIN with ILIM = L
Figure 8. Current Limit vs Temperature with ILIM = L
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
–40
–20
0
20 40
Temperature (ºC)
60
80
100
D010
VIN= 3.6 V into VIN Pin
TJ = –40°C to 85°C
Figure 9. Shutdown Current vs Temperature
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SLVSE09A –APRIL 2017–REVISED APRIL 2017
7 Detailed Description
7.1 Overview
The TPS61096A operates with an input voltage range of 1.8 V to 5.5 V and can generate output voltage up to 28
V. The device operates in a PFM peak current control scheme with selective peak current. This control scheme
consumes very low quiescent current so that it is able to achieve high efficiency at light load condition.
The TPS61096A integrates two-channel low power level shifters to convert low voltage logic signals to output
voltage for specific applications. It only consumes 1µA static current per channel and ensures very low static and
dynamic power consumption across the entire output range.
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7.2 Functional Block Diagram
VIN
SW
Under Voltage
Lockout
VOUT
Gate
VOSNS
Driver
EN
Control Logic
ILIM
GND
FB
Error Comparator
VREF
VOUT
LVI1
HVO1
VOUT
LVI2
HVO2
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7.3 Feature Description
7.3.1 Controller Circuit
The TPS61096A operates in a PFM with peak current control scheme. The converter monitors the output voltage
through feedback pin. As soon as the feedback voltage falls below the reference voltage of typical 1 V, the
internal switch turns on and the inductor current ramps up. The switch turns off as soon as the inductor current
reaches the setting peak current limit. As the switch turns off, the internal power diode is forward biased and
delivers the inductor current to the output. After the inductor current drops to zero, the TPS61096A compares the
feedback voltage with the reference voltage. Once feedback voltage falls below the reference voltage, the switch
turns on again. In this way, the TPS61096A regulates the output voltage at the target value.
Using this PFM peak current control scheme the converter operates in discontinuous conduction mode (DCM)
where the switching frequency depends on the output current. This regulation scheme is inherently stable,
allowing a wide selection range for the inductor and output capacitor.
Discontinuous Conduction Operation
ILIM
Inductor
Current
IOUT
0A
Output
Voltage
VOUT_PP
VREF x (1 + Rup/Rdown
)
Figure 10. PFM Peak Current Control Operation
7.3.2 Current Limit Selection
The TPS61096A supports selectable current limit thresholds. If the ILIM pin is pulled logic high voltage, a high
current limit (500 mA typ.) is selected; if the ILIM pin is connected to logic low voltage, a low current limit (250
mA typ.) is selected. With the low current limit threshold, the TPS61096A allows the use of small size external
components, especially the inductor, for light load applications.
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7.4 Device Functional Modes
7.4.1 Under-Voltage Lockout
An under-voltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the typical UVLO threshold of 1.3 V. A hysteresis of 200 mV is added so that the device cannot be enabled again
until the input voltage goes up to 1.5 V. This function is implemented in order to prevent malfunctioning of the
device when the input voltage is between 1.3 V and 1.5 V.
7.4.2 Enable and Disable
When the input voltage is above maximal UVLO rising threshold of 1.7 V and the EN pin is pulled high, the
TPS61096A is enabled. When the EN pin is pulled low, the device stops switching, the TPS61096A goes into
shutdown mode. In shutdown mode, less than 1-µA input current is consumed.
7.4.3 Soft Start
The TPS61096A begins soft start when the EN pin is pulled high. An internal soft-start circuit increases the peak
inductor current limit to the final value within typical 1 ms. The soft-start function reduces the inrush current
during startup.
7.4.4 Level Shifters
The TPS61096A contains two level shifter channels. Each channel features a logic-level input stage and a high
voltage output stage powered from VOUT. The logic low input must be lower than 0.15 × Vin and logic high input
must be higher than 0.8 × Vin. The level shifters have 200-µA sourcing and sinking capability, and are capable of
generating up to 200 kHz pulses with up to 10pF capacitive load connected to the outputs.
VOUT
Level Shifter
VOUT
LVI1
HVO1
VOUT
VOUT
LVI2
HVO2
Figure 11. Level Shifter Schematic Illustration
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Device Functional Modes (continued)
VI
0.8 x Vin
Level shifter input
0.15 x Vin
GND
tpd
tpd
VOH
90% VHVOx
90% VHVOx
90% VHVOx
Level shifter output
10% VHVOx
10% VHVOx
10% VHVOx
tf
VOL
tr
Figure 12. Level Shifter Timing Diagram
7.4.5 Over-voltage Protection
The TPS61096A has internal output over-voltage protection (OVP) function. When the output voltage exceeds
the OVP threshold of 29.4 V, the device stops switching. Once the output voltage falls 0.8 V below the OVP
threshold, the device resumes operating again.
7.4.6 Thermal Shutdown
The TPS61096A goes into thermal shutdown once the junction temperature exceeds 150°C. When the junction
temperature drops below the thermal shutdown temperature threshold minus the hysteresis, typically 125°C, the
device starts operating again.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61096A is a high output voltage boost converter with ultra-low quiescent current. It is designed for
products powered by either two-cell alkaline, or one cell Li-Ion or Li-polymer battery, for which high efficiency
under light load condition is critical to achieve long battery life operation. It can also support selective inductor
peak current. With lower current limit, the TPS61096A can reduce inductor ripple so as to reduce external
components size for light load applications. With higher current limit, the TPS61096A can have higher output
current capability to meet more application requirements.
The TPS61096A integrates two-channel low-power level shifters to convert low level signals to output voltage
signals for specific applications.
8.2 Typical Application
L
VOUT
SW
VIN
VOUT
12V
2.2 µH
C2
VOSNS
VIN
10 µF
3.6V
C1
4.7 µF
R1
R2
EN
FB
TPS61096A
ILIM
GND
HVO1
HVO2
LVI1
LVI2
/opyright © 2017, Çexas Lnstruments Lncorporated
Figure 13. 12-V Pulse Generation From 3.6-V Input Voltage
8.2.1 Design Requirements
In this typical application, two channel 50-kHz pulse signals of 3.2 V amplitude are output from a controller, and
the signals' amplitude is required to be converted. High efficiency under light load is required.
The TPS61096A converts the 3.6-V input voltage to 12-V output voltage first, and this 12-V output voltage
provides bias to the integrated two level shifters. The level shifters outputs have no load so the boost converter
always works in light load condition.
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Table 1. TPS61096A Design Parameters
PARAMETER
EXAMPLE VALUES
Input voltage
Output voltage
3.6 V
12 V
Input pulse frequency
50 kHz
Input pulse duty cycle
50%
Input pulse amplitude
3.2 V
Output pulse frequency and duty cycle
Output pulse amplitude
Output load of level shifters
Same as input pulse
12 V
No load
8.2.2 Detailed Design Procedure
The following sections describe the selection process of the external components.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61096A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Programming the Output Voltage
By selecting the external resistor divider R1 and R2, as shown in Equation 1, the output voltage is programmed
to the desired value. When the output voltage is regulated, the typical VREF voltage at FB pin is 1.0 V.
R1+ R2
VOUT = VREF
´
R2
(1)
For the best accuracy, the current following through R2 should be 100 times larger than FB pin leakage current.
Changing R2 towards a lower value increases the robustness against noise injection while has little influence on
efficiency at light load, because TPS61096A only samples FB voltage when it is lower than the reference. 110-
kΩ and 10-kΩ resistors are selected for R1 and R2. High accuracy resistors are recommended for better output
voltage accuracy.
8.2.2.3 Maximum Output Current
The maximum output capability of the TPS61096A is determined by the input voltage to output voltage ratio and
the current limit of the boost converter. It can be estimated by Equation 2.
V ´ ILIM ´ h
IN
IOUT(max)
=
2 ´ VOUT
where
•
•
•
•
VIN is the input voltage
VOUT is the output voltage
ILIM is the peak current limit
η is the power conversion efficiency
(2)
15
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If an application requires high output current capability of the boost converter, ILIM pin should be tied to logic
high voltage to enable a higher current limit. Minimum input voltage, maximum boost output voltage and
minimum value of the selected current limit should be used as the worst case condition for the estimation.
In this example, the output load is only the bias current to the level shifters, so it will not reach the maximum
output current value.
8.2.2.4 Inductor Selection
Because the PFM peak current control scheme is inherently stable, the inductor value does not affect the stability
of the regulator. The selection of the inductor together with the nominal load current, input and output voltage of
the application determines the switching frequency of the converter. Depending on the application, inductor
values from 1.0 μH to 47 μH are recommended.
The inductor value determines the maximum switching frequency of the converter. Therefore, select the inductor
value that ensures the maximum switching frequency at the converter maximum load current does not exceed
the required maximum switching frequency. The maximum switching frequency is calculated by Equation 3:
V ´(VOUT - h´ V )
IN
IN
ƒs(max)
=
L ´ VOUT ´ILIM
where
•
L is the selected inductor value
(3)
h × VOUT
Choose the smaller one between VIN(max) and
entire input range.
to calculate the highest switching frequency across the
2
The selected inductor should have a saturation current that is larger than the maximum peak current of the
converter. Use the minimal value of selected current limit for this calculation.
Another important inductor parameter is the dc resistance. The lower the dc resistance, the higher the efficiency
of the converter. Table 2 lists the recommended inductors for the TPS61096A.
Table 2. Recommended Inductors
INDUCTANCE
(µH)
DC RESISTANCE
ISAT (A)
PACKAGE SIZE
PART NUMBER
MANUFACTURER(1)
(mΩ)
2.2
2.2
2.2
1.7
1.5
0.7
117
106
200
2.0 mm × 1.6 mm
3.2 mm × 2.5 mm
2.0 mm × 1.2 mm
DFE201610E-2R2M=P2
74479299222
TOKO
Wurth
Wurth
74479775222A
(1) See Third-Party Products disclaimer
8.2.2.5 Capacitor Selection
For best output and input voltage filtering, low ESR X5R or X7R ceramic capacitors are recommended.
The input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system
rail for the device. An input capacitor value of 4.7 μF is normally recommended to improve transient behavior of
the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor placed as close as possible
to the VIN and GND pins of the IC is recommended.
The selection of output capacitor determines the output voltage ripple. The default hysteresis window of Vout is
30mV, but due to the 10-µs internal comparator delay, output ripple gets larger as load gets heavier. The output
ripple is calculated with Equation 4:
IOUT × tdelay
VRIPPLE
=
+ 30 mV
COUT
where
•
•
•
VRIPPLE refers to the output voltage ripple
tdelay is the internal comparator delay time, typical value 10 µs
COUT is effective output capacitance
(4)
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For the output capacitor of VOUT pin, small ceramic capacitors are recommended. Place the output capacitor as
close as possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of
large capacitors which cannot be placed close to the IC, the use of a small ceramic capacitor with a capacitance
value of 1 μF in parallel to the large one is recommended. This small capacitor should be placed as close as
possible to the VOUT and GND pins of the IC. The recommended typical output capacitor values are 10 μF
(nominal value).
When selecting capacitors, the derating effect of the ceramic capacitor under bias should be considered. Choose
the right nominal capacitance by checking the DC bias characteristics of the capacitor. In this example,
GRM188R6YA106MA73D, a 10-µF ceramic capacitor with high effective capacitance value at DC biased
condition, is selected for the VOUT rail. The performance is shown in the Application Curves section.
8.2.3 Application Curves
Vin=3.6 V, Vout=12 V, Iout=30 mA
Vin=3.6 V, Vout=12 V, Iout=2 mA
Figure 14. Switching Waveform at Heavy Load
Figure 15. Switching Waveform at Light Load
Vin=3.6 V, Vout=12 V, Iout=25 mA
Vin=3.6 V, Vout=12 V, Iout=25 mA
Figure 16. Startup by VIN
Figure 17. Startup by EN
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Vin=3.0 V to 3.6 V, Vout=12 V, Iout=20 mA
Vin=3.6 V, Vout=12 V, Iout=0 mA to 30 mA
Figure 18. Line Transient
Figure 19. Load Regulation
Vout (AC)
200 mV/Div
Vout (AC)
200 mV/Div
IL
Vin
1 V/Div
200 mA/Div
Iout
10 mA/Div
IL
200 mA/Div
Vin=3.6 V, Vout=12 V, Iout=5 mA to 20 mA
Vin=1.8 V to 4.2 V, Vout=12 V, Iout=20 mA
Figure 20. Load Transient
Figure 21. Line Regulation
LVl1
2 V/Div
LVl2
2 V/Div
HVO1
10 V/Div
HVO2
10 V/Div
LVI1 = LVI2 = 3.2 V, HVO1 = HVO2 = 12 V
Figure 22. Level Shifters Function
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9 Power Supply Recommendations
TPS61096A is designed to operate from an input voltage supply range between 1.8 V to 5.5 V. The power supply
can be either two-cell alkaline, or one cell Li-Ion or Li-polymer battery. The input supply must be well regulated
with the rating of TPS61096A. If the input supply is located more than a few inches from the converter, a bulk
capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak current
and high switching frequency. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
paths. The input and output capacitor, as well as inductor should be placed as close as possible to the IC.
10.2 Layout Example
A large ground plane on the bottom layer connects the ground pins of the components on the top layer through
vias.
LVI2
LVI1
HVO1
HVO2
LV1
HVO1
HVO2
GROUND
LV2
VIN
SW
ILIM
EN
GROUND
VOUT
GND
VOUT
VOSNS
FB
VIN
GROUND
ILIM
EN
Figure 23. Example PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61096A device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61096ADSSR
TPS61096ADSST
ACTIVE
ACTIVE
WSON
WSON
DSS
DSS
12
12
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
61096A
61096A
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE OUTLINE
DSS0012B
WSON - 0.8 mm max height
SCALE 4.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
0.35
0.25
PIN 1 INDEX AREA
0.3
0.2
3.1
2.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
1
0.1
(0.2) TYP
SYMM
0.05
0.00
EXPOSED
THERMAL PAD
6
7
SEE TERMINAL
DETAIL
2X
13
SYMM
2.5
2.65 0.1
1
12
10X 0.5
0.3
12X
0.2
0.1
0.05
0.35
0.25
12X
PIN 1 ID
(OPTIONAL)
C A B
C
4218908/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1)
12X (0.5)
SYMM
1
12
12X (0.25)
13
SYMM
(2.65)
10X (0.5)
(R0.05) TYP
(1.075)
(
0.2) VIA
TYP
7
6
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
EXPOSDE METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218908/A 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
EXPOSED METAL
TYP
12X (0.5)
SYMM
1
13
12
12X (0.25)
(0.685)
SYMM
10X (0.5)
2X (1.17)
(R0.05) TYP
7
6
2X (0.95)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13:
83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218908/A 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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