TPS61162A [TI]
适用于智能手机的双通道 WLED 驱动器;
| 型号： | TPS61162A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于智能手机的双通道 WLED 驱动器 手机 驱动 智能手机 驱动器 |
| 文件： | 总28页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
用于智能手机的双通道白光发光二极管 (WLED) 驱动器
查询样片: TPS61162A, TPS61163A
1
特性
说明
2
•
2.7V 至 6.5V 输入电压
TPS61162A 和 TPS61163A 是双通道 WLED 驱动
器，此驱动器为单节锂离子电池供电的智能手机背光提
供高度集成的解决方案。 此器件具有一个带有集成
1.5A/40V 功率 MOSFET 的内置高效升压稳压器并支
持低至 2.7V 的输入电压。 借助于两个高电流匹配能力
的电流吸收稳压器，此器件能够驱动高达十串两并
(10s2p) 的 WLED 二极管。 升压输出能够自动调节至
WLED 正向电压并且可实现极低的电压净空控制，从
而有效提升 LED 灯串的效率。
•
集成型 1.5A/40V 金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
1.2MHz 开关频率
每个通道上高达 30mA 的双电流吸收能力
1% 的典型电流匹配及准确度
可选 26.5V/37.5V 过压保护 (OVP) 阀值
–
–
TPS61162A - 26.5V OVP
TPS61163A - 37.5V OVP
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
自适应升压输出至 WLED 电压
极低电压净空控制 (90mV)
灵活的数字和脉宽调制 (PWM) 亮度控制
1 线制控制接口 (EasyScale)
PWM 亮度调节控制接口
高达 100:1 PWM 调光比
高达 9 位的调光分辨率
TPS61162A 和 TPS61163A 支持 PWM 调光接口和 1
线制数字 EasyScale™ 调光接口并能够实现 9 位亮度
代码编程。
TPS61162A 和 TPS61163A 集成了内置软启动、过压/
过流保护和热关断保护。
此器件采用节省空间的 1.31mm x 1.31mm CSP 封
装。
效率高达 90%
内置软起动功能
典型应用
轻负载下的脉冲频率调制 (PFM) 模式
具有过压保护功能
L1
4.7µH
2.7V ~ 6.5V
VBAT
D1
内置 WLED 开路/短路保护
热关断
R2
10ꢀ
C1
1µF
C2
1µF
SW
VIN
支持 4.7uH 电感器应用
9L 1.31mm x 1.31mm 芯片级封装 (CSP)
C3
1µF
应用范围
Enable /
Disable
EN
•
•
•
•
智能电话
TPS61162A/3A
掌上电脑 (PDA)，手持计算机
GPS 接收器
PWM
Dimming
PWM
IFB1
IFB2
COMP
针对具有单节电池输入的小型、媒体尺寸 LCD 显
示屏的背光
C4
330nF
ISET
R1
63.4kꢀ
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
EasyScale is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC26
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PACKAGE
TJ
PART NUMBER
OPEN LED PROTECTION
PACKAGE
ORDERING(2)
MARKING
TPS61162A
TPS61163A
TPS61162A
TPS61163A
26.5V (typical)
37.5V (typical)
9-ball WSCP
9-ball WSCP
TPS61162AYFF
TPS61163AYFF
–40°C to
125°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The YFF package is available in tape and reel. Add a R suffix (e.g. TPS61162YFFR) to order quantities of 3000 parts.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
MAX
7
VIN, EN, PWM, IFB1, IFB2
COMP, ISET
V
V
Voltage range(2)
ESD rating
3
SW
40
2
V
Human Body Mode – (HBM)
Machine Mode – (MM)
Charge Device Mode – (CDM)
Continuous power dissipation
Operating junction temperature range
Storage temperature range
kV
V
200
750
V
PD
See Thermal Information Table
TJ
–40
–65
150
150
°C
°C
TSTG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TPS61162A/63A
THERMAL METRIC(1)
UNITS
YFF (9-ball WSCP)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
107
0.9
18.1
4.0
18
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
NA
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
VIN
VIN
4.7
1.0
1.0
NOM
MAX UNIT
VIN
Input voltage range
Output voltage range
6.5
27
38
10
V
TPS61162A
TPS61163A
VOUT
V
L
Inductor
µH
µF
CI
Input capacitor
Output capacitor
Compensation capacitor
CO
2.2
µF
CCOMP
FPWM
TJ
330
nF
PWM dimming signal frequency
Operating junction temperature
10
100
125
kHz
°C
–40
ELECTRICAL CHARACTERISTICS
VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TJ = -40°C to +125°C, typical values are at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN Input voltage range
2.7
6.5
2.3
V
V
VIN falling
VIN rising
2.2
VVIN_UVLO Under voltage lockout threshold
2.45
VVIN_HYS
VIN UVLO hysteresis
100
1.2
1
mV
mA
µA
Device enable, switching 1.2 MHz and no
load, VIN = 3.6V
Iq
Operating quiescent current into VIN
Shutdown current
2
2
ISD
EN = low
EN and PWM
VH
VL
VH
VL
EN Logic high
1.2
1.2
V
V
V
V
EN Logic Low
0.4
PWM Logic high
PWM Logic Low
0.4
EN pin and PWM pin internal pull-
down resistor
RPD
400
800
1600
kΩ
tPWM_SD
tEN_SD
PWM logic low width to shutdown
EN logic low width to shutdown
PWM high to low
EN high to low
20
ms
ms
2.5
CURRENT REGULATION
VISET_full
KISET_full
ISET pin voltage
Current multiplier
Full brightness
1.204
1.229
1030
1.253
V
Full brightness
IISET = 20 μA, D = 100%, 0°C to 70°C
IISET = 20 µA, D = 100%, –40°C to 85°C
D = 100%
–2%
2%
2.3%
2%
IFB_avg
Current accuracy
–2.3%
1%
1%
KM
(IMAX – IAVG) / IAVG
D = 25%
IIFB_max
Current sink max output current
IISET = 35 μA, each IFBx pin
30
mA
Copyright © 2013, Texas Instruments Incorporated
3
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TJ = -40°C to +125°C, typical values are at TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
VIN = 3.6 V
VIN = 3.0 V
0.25
0.3
RDS(on)
Switch MOSFET on-resistance
Switch MOSFET leakage current
Ω
ILEAK_SW
VSW = 35 V, TJ = 25°C
1
µA
OSCILLATOR
fSW
Oscillator frequency
1000
89%
1200
95%
1500
kHz
Measured on the drive signal of switch
MOSFET
Dmax
Maximum duty cycle
BOOST VOLTAGE CONTROL
IIFBx = 20mA, measured on IFBx pin
which has a lower voltage
VIFB_reg
IFBx feedback regulation voltage
90
mV
Isink
Isource
Gea
Rea
fea
COMP pin sink current
12
5
µA
µA
COMP pin source current
Error amplifier transconductance
Error amplifier output resistance
Error amplifier crossover frequency
30
1
55
80
2
µmho
MΩ
45.5
1.65
5pF connected to COMP pin
D = Dmax, 0°C to 70°C
MHz
PROTECTION
ILIM
Switch MOSFET current limit
1.5
0.7
5
A
A
ILIM_Start
tHalf_LIM
Switch MOSFET start up current limit D = Dmax
Time window for half current limit
SW pin over voltage threshold
IFBx pin over voltage threshold
ms
TPS61162A
25
36
26.5
37.5
4.5
28
39
5
VOVP_SW
VOVP_IFB
V
V
TPS61163A
Measured on IFBx pin
4.2
EASYSCALE INTERFACE
tes_delay
tes_det
tes_win
tstart
EasyScale detection delay
Measured from EN low to high
EN pin low time
100
µs
µs
ms
µs
µs
µs
µs
µs
µs
µs
µs
V
EasyScale detection time
260
EasyScale detection window(1)
Start time of program stream
End time of program stream
High time of low bit (Logic 0)
Low time of low bit (Logic 0)
High time of high bit (Logic 1)
Low time high bit (Logic 1)
Acknowledge valid time
Measured from EN low to high
1
2
tEOS
2
2
360
180
360
360
180
2
tH_LB
tL_LB
2 x tH_LB
2 x tL_HB
2
tH_HB
tL_HB
tvalACKN
tACKN
VACKNL
Duration of acknowledge condition
Acknowledge output voltage low(2)
512
0.4
Open drain, Rpullup = 15 kΩ to VIN
THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold
Thys Thermal shutdown hysteresis
160
15
°C
°C
(1) To select EasyScale interface, after tes_delay delay from EN low to high, drive EN pin to low for more than tes_det before tes_win expires.
(2) Acknowledge condition active 0, this condition is only applied when the RFA bit is set to 1. To use this feature, master must have an
open drain output, and the data line needs to be pulled up by the master with a resistor load.
4
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
DEVICE INFORMATION
PIN ASSIGNMENT
9 BALL 1.31mm x 1.31mm YFF PACKAGE
Bottom View
Top View
2
1
3
3
2
1
ISET
IFB2
COMP
VIN
IFB1
IFB1
IFB2
ISET
A
B
C
A
B
C
COMP
PWM
EN
GND
SW
GND
SW
PWM
EN
VIN
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NUMBER
NAME
Full-scale LED current set pin. Connecting a resistor to the pin programs the full-scale LED
current
A1
ISET
I
A2
A3
B1
IFB2
IFB1
PWM
I
I
I
Regulated current sink input pin
Regulated current sink input pin
PWM dimming signal input
Output of the transconductance error amplifier. Connect external capacitor to this pin to
compensate the boost loop
B2
COMP
O
B3
C1
C2
C3
GND
EN
O
I
Ground
Enable control, and 1-wire digital signal input
Supply input pin
VIN
SW
I
I
Drain connection of the internal power MOSFET
Copyright © 2013, Texas Instruments Incorporated
5
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
TITLE
DESCRIPTION
FIGURE
Dimming Efficiency
Dimming Efficiency
Dimming Efficiency
Dimming Efficiency
Dimming Efficiency
Dimming Efficiency
Dimming Linearity
Switching Waveform
Switching Waveform
VIN = 3V, 3.6V, 4.2V, 5V; VO = 15V, 5s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 18V, 6s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 24V, 8s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 27V, 9s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 30V, 10s2p, 20mA/string; PWM Freq = 20kHz; L = 10µH
VIN = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s2p; RISET = 63.4kΩ; PWM Freq = 20kHz
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 10µH
1
2
3
4
5
6
7
8, 9
10, 11
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 20kHz, Duty = 10%; L = 10µH
Dimming Transient
Waveform
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 20kHz, Duty = 10% to 80% and back to
10%; L = 10µH
12
Startup Waveform
Startup Waveform
Shutdown Waveform
Shutdown Waveform
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 10µH
13
14
15
16
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 20kHz, Duty = 50%; L = 10µH
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; Duty = 100%; L = 10µH
VIN = 3.6V; VO = 21V, 7s2p, 20mA/string; PWM Freq = 20kHz, Duty = 50%; L = 10µH
DIMMING EFFICIENCY
DIMMING EFFICIENCY
100
100
90
80
70
60
Vo = 18V, 6s2p, 20mA/string
Vo = 15V, 5s2p, 20mA/string
90
80
70
60
VIN = 3V
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
0
20
40
60
80
100
0
20
40
60
80
100
Dimming Duty Cycle (%)
Dimming Duty Cycle (%)
Figure 1.
Figure 2.
DIMMING EFFICIENCY
DIMMING EFFICIENCY
100
90
80
70
60
100
90
80
70
60
Vo = 24V, 8s2p, 20mA/string
Vo = 21V, 7s2p, 20mA/string
VIN = 3V
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
0
20
40
60
80
100
0
20
40
60
80
100
Dimming Duty Cycle (%)
Dimming Duty Cycle (%)
Figure 3.
Figure 4.
6
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
DIMMING EFFICIENCY
DIMMING EFFICIENCY
100
100
90
80
70
60
Vo = 27V, 9s2p, 20mA/string
Vo = 30V, 10s2p, 20mA/string
90
80
70
VIN = 3V
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
60
0
20
40
60
80
100
0
20
40
60
80
100
Dimming Duty Cycle (%)
Dimming Duty Cycle (%)
Figure 5.
Figure 6.
DIMMING LINEARITY
SWITCHING WAVEFORM
50
40
30
20
10
SW
Voltage
20V/div
DC
Output
Voltage
100mV/div
AC
Inductor
Current
200mA/div
DC
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
Output
Current
20mA/div
DC
Duty = 100%
0
0
20
40
60
80
100
t - Time - 1ms/div
Figure 8.
Dimming Duty Cycle (%)
Figure 7.
SWITCHING WAVEFORM
SWITCHING WAVEFORM
SW
Voltage
20V/div
DC
SW
Voltage
20V/div
DC
Output
Voltage
200mV/div
AC
Min
Feedback
Voltage
100mV/div
DC
Inductor
Current
100mA/div
DC
Inductor
Current
200mA/div
DC
Output
Current
5mA/div
DC
Output
Current
20mA/div
DC
Duty = 100%
PWM Freq = 20kHz, Duty = 10%
t - Time - 4ms/div
t - Time - 1ms/div
Figure 9.
Figure 10.
Copyright © 2013, Texas Instruments Incorporated
7
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
SWITCHING WAVEFORM
DIMMING TRANSIENT WAVEFORM
SW
Voltage
20V/div
DC
SW
Voltage
20V/div
DC
Min
Inductor
Current
200mA/div
DC
Feedback
Voltage
100mV/div
DC
Output
Voltage
2V/div
AC
Inductor
Current
100mA/div
DC
Output
Current
20mA/div
DC
Output
Current
2mA/div
DC
PWM Freq = 20kHz,
Duty = 10% - 80% - 10%
PWM Freq = 20kHz, Duty = 10%
t - Time - 4ms/div
t - Time - 400ms/div
Figure 11.
Figure 12.
STARTUP WAVEFORM
STARTUP WAVEFORM
PWM
Voltage
2V/div
DC
PWM
Voltage
2V/div
DC
Inductor
Current
200mA/div
DC
Inductor
Current
200mA/div
DC
Output
Voltage
20V/div
DC
Output
Voltage
20V/div
DC
Output
Current
20mA/div
DC
Output
Current
20mA/div
DC
Duty = 100%
PWM Freq = 20kHz, Duty = 50%
t - Time - 10ms/div
t - Time - 10ms/div
Figure 13.
Figure 14.
SHUTDOWN WAVEFORM
SHUTDOWN WAVEFORM
PWM
Voltage
2V/div
DC
PWM
Voltage
2V/div
DC
Inductor
Current
200mA/div
DC
Inductor
Current
200mA/div
DC
Output
Voltage
20V/div
DC
Output
Voltage
20V/div
DC
Output
Current
20mA/div
DC
Output
Current
20mA/div
DC
PWM Freq = 20kHz, Duty = 50%
Duty = 100%
t - Time - 10ms/div
t - Time - 10ms/div
Figure 15.
Figure 16.
8
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
L1
D1
VBAT
VOUT
R2
10ꢀ
C2
1µF
C1
1µF
VIN
SW
C3
1µF
SW OVP
UVLO /
Internal Regulator
R
S
Q
OSC
OCP
GND
Slope
Compensation
S
Vref
GM
Comp
COMP
120mV
OPAMP
Vclamp
COMP clamp circuit
C4
330nF
IFBx Voltage
Detection / OVP
UVLO
SW OVP
EN
Enable / Disable
Detection
Shutdown
Control
Dual-Channel
Current Sinks
IFB1
EA
PWM
ISET
Duty Decoding
Current Sink 1
Analog Dimming Control
R1
63.4kꢀ
IFB2
Current Sink 2
Copyright © 2013, Texas Instruments Incorporated
9
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
DETAILED DESCRIPTION
NORMAL OPERATION
In order to provide high brightness backlighting for big size or high resolution smart phone panels, more and
more white LED diodes are used. Having all LED diodes in a string improves overall current matching; however,
the output voltage of a boost converter will be limited when input voltage is low, and normally the efficiency will
drop when output voltage goes very high. Thus the LED diodes are arranged in two parallel strings.
The TPS61162A/TPS61163A is a high efficiency, dual-channel white LED driver for such smart phone
backlighting applications. Two current sink regulators of high current-matching capability are integrated in the
TPS61162A/TPS61163A to support dual LED strings connection and to improve the current balance and protect
the LED diodes when either LED string is open or short.
The TPS61162A/TPS61163A has integrated all of the key function blocks to power and control up to 20 white
LED diodes. It includes a 40V/1.5A boost converter, two current sink regulators and protection circuit for over-
current, over-voltage and thermal shutdown protection.
BOOST CONVERTER
The boost converter of the TPS61162A/TPS61163A integrates 40V 1.5A low side switch MOSFET and has a
fixed switching frequency of 1.2MHz. The control architecture is based on traditional current-mode PWM control.
For operation see the block diagram. Two current sinks regulate the dual-channel current and the boost output is
automatically set by regulating IFBx pin’s voltage. The output of error amplifier and the sensed current of switch
MOSFET are applied to a control comparator to generate the boost switching duty cycle; slope compensation is
added to the current signal to allow stable operation for duty cycles larger than 50%.
The forward voltages of two LED strings are normally different due to the LED diode forward voltage
inconsistency, thus the IFB1 and IFB2 voltages are normally different. The TPS61162A/TPS61163A can select
out the IFBx pin which has a lower voltage than the other and regulates its voltage to a very low value (90mV
typical), which is enough for the two current sinks' headroom. In this way, the output voltage of the boost
converter is automatically set and adaptive to LED strings' forward voltages, and the power dissipation of the
current sink regulators can be reduced remarkably with this very low headroom voltage.
In order to improve the boost efficiency at light load, PFM (Pulse Frequency Modulation) mode is automatically
enabled under light load condition. When the load current decreases along with the dimming duty, the output of
gm amplifier - COMP pin voltage decreases until it is clamped at an internal reference voltage. Because COMP
pin voltage controls the inductor peak current, when it is clamped, the inductor peak current is clamped and can't
decrease, too. As a result, more energy than needed is transferred to the output stage and the output voltage
and IFBx pin voltage increase. An internal hysteresis comparator detects the min. IFBx pin voltage. When the
min. IFBx voltage is detected higher than the regulation voltage 90mV by around 120mV, the boost stops
switching. Then the output voltage as well as IFBx pin voltage decrease. When the min. IFBx voltage is lower
than the hysteresis (around 40mV), the boost switches again. So during PFM mode, the boost output trips
between the low and high thresholds. When the load increases along with the dimming duty, the COMP pin
voltage will exit from the clamped status, and the boost will exit the PFM mode and return to the PWM operation,
during which the min. IFBx pin voltage will be regulated at 90mV again. Refer to Figure 10 and Figure 11 for
PFM mode operation.
IFBx PIN UNUSED
If only one channel is needed, a user can easily disable the unused channel by connecting its IFBx pin to
ground. If both IFBx pins are connected to ground, the IC will not start up.
ENABLE AND STARTUP
In order to enable the IC from shutdown mode, three conditions have to be met: 1. POR (Power On Reset, that
is, VIN voltage is higher than UVLO threshold), 2. Logic high on EN pin, 3. PWM signal (logic high or PWM
pulses) on PWM pin. When these conditions are all met, an internal LDO linear regulator is enabled to provide
supply to internal circuits and the IC can start up.
10
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
The TPS61162A/TPS61163A supports two dimming interfaces: 1-wire digital interface (EasyScale interface) and
PWM interface. TPS61162A/TPS61163A begins an EasyScale detection window after startup to detect which
interface is selected. If the EasyScale interface is needed, signals of a specific pattern should be input into EN
pin during the EasyScale detection window; otherwise, PWM dimming interface will be enabled (see details in 1-
Wire Digital Interface (EasyScale Interface) ).
After the EasyScale detection window, the TPS61162A/TPS61163A checks the status of IFBx pins. If one IFBx
pin is detected to connect to ground, the corresponding channel will be disabled and removed from the control
loop. Then the soft-start begins and the boost converter starts switching. If both IFBx pins are shorted to ground,
the TPS61162A/TPS61163A will not start up.
Either pulling EN pin low for more than 2.5ms or pulling PWM pin low for more than 20ms can disable the device
and the TPS61162A/TPS61163A enters into shutdown mode.
SOFTSTART
Soft-start is implemented internally to prevent voltage over-shoot and in-rush current. After the IFBx pin status
detection, the COMP pin voltage starts ramp up and the boost starts switching. During the beginning 5ms
(tHalf_LIM) of the switching, the peak current of the switch MOSFET is limited at ILIM_Start (0.7A typical) to avoid the
input inrush current. After the 5ms, the current limit is changed to ILIM (1.5A typical) to allow the normal operation
of the boost converter.
FULL-SCALE CURRENT PROGRAM
The dual channels of the TPS61162A/TPS61163A can provide up to 30 mA current each. No matter either
EasyScale interface or PWM interface is selected, the full-scale current (current when dimming duty cycle is
100%) of each channel should be programmed by an external resistor RISET at ISET pin according to Equation 1.
V
ISET _ full
IFB _ full
=
´K
ISET _ full
RISET
(1)
Where:
IFB_full, full-scale current of each channel
KISET_full = 1030 (Current multiple when dimming duty cycle = 100%)
VISET_full = 1.229V (ISET pin voltage when dimming duty cycle = 100%)
RISET = ISET pin resistor
BRIGHTNESS CONTROL
The TPS61162A/TPS61163A controls the DC current of the dual channels to realize the brightness dimming.
The DC current control is normally referred to as analog dimming mode. When the DC current of LED diode is
reduced, the brightness is dimmed.
The TPS61162A/TPS61163A can receive either the PWM signals at the PWM pin (PWM interface) or digital
commands at the EN pin (EasyScale interface) for brightness dimming. If the EasyScale interface is selected, the
PWM pin should be kept high; if PWM interface is selected, the EN pin should be kept high.
1-Wire Digital Interface (EasyScale Interface)
The EN pin features a simple digital interface to allow digital brightness control. The digital dimming interface can
save the processor power and battery life as it does not require PWM signals all the time, and the processor can
enter idle mode if possible. In order to enable the EasyScale interface, the following conditions must be satisfied
and the specific digital pattern on the EN pin must be recognized by the IC every time the TPS61162A/
TPS61163A starts up from shutdown mode.
1. VIN voltage is higher than UVLO threshold and PWM pin is pulled high.
2. Pull EN pin from low to high to enable the TPS61162A/TPS61163A. At this moment, the EasyScale detection
window starts.
3. After EasyScale detection delay time (tes_delay, 100µs), drive EN to low for more than EasyScale detection
time (tes_detect, 260µs).
Copyright © 2013, Texas Instruments Incorporated
11
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
The third step must be finished before the EasyScale detection window (tes_win, 1ms) expires, and once this step
is finished, the EasyScale interface is enabled and the EasyScale communication can start. Refer to Figure 17
for a graphical explanation.
Insert battery
PWM Signal
high
PWM
low
Enter ES mode
Programming
code
ES Detection
Window
Programming code
high
low
EN
ES detect time
ES detect delay
Shutdown
delay
EasyScale
mode
Ramp up
Ramp up
Programmed value
(if not programmed, full current default )
IC
Shutdown
Startup delay
Startup delay
IFBx
Figure 17. EasyScale Interface Detection
The TPS61162A/TPS61163A supports 9-bit brightness code programming. By the EasyScale interface, a master
can program the 9-bit code D8(MSB) to D0(LSB) to any of 511 steps with a single command. The default code
value of D8~D0 is “111111111” when the device is first enabled, and the programmed value will be stored in an
internal register and set the dual-channel current according to Equation 2. The code will be reset to default value
when the IC is shut down or disabled.
Code
´
IFBx = IFB_full
511
(2)
Where:
IFB_full: the full-scale LED current set by the RISET at ISET pin
Code: the 9-bit brightness code D8~D0 programmed by EasyScale interface
When the 1-wire digital interface at EN pin is selected, the PWM pin can be connected to either VIN pin or a
GPIO (refer to ADDITIONAL APPLICATION CIRCUITS). If PWM pin is connected to VIN pin, EN pin alone can
enable and disable the IC: pulling EN pin low for more than 2.5ms disables the IC; if PWM pin is connected to a
GPIO, both PWM and EN signals should be high to enable the IC, and either pulling EN pin low for more than
2.5ms or pulling PWM pin low for more than 20ms disables the IC.
EasyScale Programming
EasyScale is a simple but flexible one pin interface to configure the current of the dual channels. The interface is
based on a master-slave structure, where the master is typically a microcontroller or application processor and
the IC is the slave. Figure 18 and Table 2 give an overview of the protocol used by TPS61162A/TPS61163A. A
command consists of 24 bits, including an 8-bit device address byte and a 16-bit data byte. All of the 24 bits
should be transmitted together each time, and the LSB bit should be transmitted first. The device address byte
D7(MSB)~D0(LSB) is fixed to 0x8F. The data byte includes 9 bits D8(MSB)~D0(LSB) for brightness information
and an RFA bit. The RFA bit set to "1" indicates the Request for Acknowledge condition. The Acknowledge
condition is only applied when the protocol is received correctly. The advantage of EasyScale compared with
other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It
can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.
12
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
DATA IN
Data Byte
Address Byte
Bit 11 ~ D0
Bit 15
D1
1
D2
1
D3
1
D4
0
D5
0
D6
0
D7
EOS
1
Start D0
D1
D2
D3
D4
D5
D6
D7
D8 Bit 9 RFA
1
ACK
DATA OUT
Figure 18. EasyScale Protocol Overview
Table 2. EasyScale Bit Description
BIT
NUMBER
TRANSMISSION
DIRECTION
BYTE
NAME
DESCRIPTION
23 (MSB)
22
DA7
DA6
DA7 = 1, MSB of device address
DA6 = 0
21
DA5
DA5 = 0
Device
Address
Byte
20
DA4
DA4 = 0
IN
19
DA3
DA3 = 1
(0x8F)
18
DA2
DA2 = 1
17
DA1
DA1 = 1
16
DA0
DA0 = 1, LSB of device address
No information. Write 0 to this bit.
No information. Write 0 to this bit.
No information. Write 0 to this bit.
No information. Write 0 to this bit.
No information. Write 0 to this bit.
15
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
14
13
12
11
Request for acknowledge. If set to 1, IC will pull low the data line
when it receives the command well. This feature can only be used
when the master has an open drain output stage and the data line
needs to be pulled high by the master with a pullup resistor;
otherwise, acknowledge condition is not allowed and don't set this bit
to 1.
10
RFA
Data Byte
IN
9
Bit 9
D8
D7
D6
D5
D4
D3
D2
D1
D0
No information. Write 0 to this bit.
8
Data bit 8, MSB of brightness code
7
Data bit 7
6
Data bit 6
5
Data bit 5
4
Data bit 4
3
Data bit 3
2
1
Data bit 2
Data bit 1
0 (LSB)
Data bit 0, LSB of brightness code
tstart
Data Byte
Address Byte
Static High
Static High
DATA IN
D0
1
D8
Bit 9
0
RFA
0
Bit 15
0
DA0
1
DA7
1
0
tEOS
Figure 19. EasyScale Timing, with RFA = 0
Copyright © 2013, Texas Instruments Incorporated
13
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
tstart
Data Byte
Address Byte
Static High
Static High
DATA IN
D0
1
D8
0
Bit 9
0
RFA
1
Bit 15
0
DA0
1
DA7
1
tvalACK
Acknowledge
true, Data line
pulled down by
the IC
ACKN
DATA OUT
(ACKN)
Master needs to pull up
Data line via a pullup
resistor to detect ACKN
Acknowledge
false, no pull
down
DATA OUT
(ACK)
ACK
Figure 20. EasyScale Timing, with RFA = 1
tLow
tHigh tLow
tHigh
Low Bit
High Bit
(Logic 0)
(Logic 1)
Figure 21. EasyScale — Bit Coding
The 24-bit command should be transmitted with LSB first and MSB last. Figure 19 shows the protocol without
acknowledge request (Bit RFA = 0), Figure 20 with acknowledge request (Bit RFA = 1). Before the command
transmission, a start condition must be applied. For this, the EN pin must be pulled high for at least tstart (2μs)
before the bit transmission starts with the falling edge. If the EN pin is already at high level, no start condition is
needed. The transmission of each command is closed with an End of Stream condition for at least tEOS (2μs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH (refer to Figure 21). It can be simplified to:
Low Bit (Logic 0): tLOW ≥ 2 x tHIGH
High Bit (Logic 1): tHIGH ≥ 2 x tLOW
The bit detection starts with a falling edge on the EN pin and ends with the next falling edge. Depending on the
relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by setting RFA bit to 1.
• The transmitted device address matches with the device address of the IC.
• Total 24 bits are received correctly.
If above conditions are met, after tvalACK delay from the moment when the last falling edge of the protocol is
detected, an internal ACKN-MOSFET is turned on to pull the EN pin low for the time tACKN, which is 512μs
maximum, then the Acknowledge condition is valid. During the tvalACK delay, the master controller keeps the line
low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge
condition. If it reads back a logic 0, it means the IC has received the command correctly. The EN pin can be
used again by the master when the acknowledge condition ends after tACKN time.
Note that the acknowledge condition can only be requested when the master device has an open drain output.
For a push-pull output stage, the use of a series resistor in the EN line to limit the current to 500μA is
recommended to for such cases as:
• An accidentally requested acknowledge, or
• To protect the internal ACKN-MOSFET.
14
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
PWM Control Interface
The PWM control interface is automatically enabled if the EasyScale interface fails to be enabled during startup.
In this case, the TPS61162A/TPS61163A receives PWM dimming signals on the PWM pin to control the
backlight brightness. When using PWM interface, the EN pin can be connected to VIN pin or a GPIO (refer to
ADDITIONAL APPLICATION CIRCUITS). If EN pin is connected to VIN pin, PWM pin alone is used to enable
and disable the IC: pulling PWM pin high or apply PWM signals at PWM pin to enable the IC and pulling PWM
pin low for more than 20ms to disable the IC; if EN pin is connected to a GPIO, either pulling EN pin low for more
than 2.5ms or pulling PWM pin low for more than 20ms can disable the IC. Only after both EN and PWM signals
are applied, the TPS61162A/TPS61163A can start up. Refer to Figure 22 for a graphical explanation.
Insert battery
Insert battery
EN signal
EN signal
high
high
EN
low
low
PWM signal
PWM signal
high
high
PWM
PWM
low
low
PWM
mode
Startup
delay
Startup
delay
Ramp up
Ramp up
Shutdown delay
Shutdown delay
Full current x PWM Duty
Full current x PWM Duty
Shut down by
PWM signal
Shut down by
EN signal
IFBx
IFBx
t
t
Figure 22. PWM Control Interface Detection
When the PWM pin is constantly high, the dual channel current is regulated to full-scale according to Equation 1.
The PWM pin allows PWM signals to reduce this regulation current according to the PWM duty cycle; therefore,
it achieves LED brightness dimming. The relationship between the PWM duty cycle and IFBx current is given by
Equation 3.
IFBx = IFB_full ´Duty
(3)
Where IFBx is the current of each current sink, IFB_full is the full-scale LED current, Duty is the duty cycle
information detected from the PWM signals.
UNDERVOLTAGE LOCKOUT
An undervoltage lockout circuit prevents the operation of the device at input voltages below undervoltage
threshold (2.2V typical). When the input voltage is below the threshold, the device is shutdown. If the input
voltage rises by undervoltage lockout hysteresis, the IC restarts.
OVERVOLTAGE PROTECTION
Over voltage protection circuitry prevents IC damage as the result of white LED string disconnection or shortage.
The TPS61162A/TPS61163A monitors the voltages at SW pin and IFBx pin during each switching cycle. No
matter either SW OVP threshold VOVP_SW or IFBx OVP threshold VOVP_FB is reached due to the LED string open
or short issue, the protection circuitry will be triggered. Refer to Figure 23 and Figure 24 for the protection
actions.
If one LED string is open, its IFBx pin voltage drops, and the boost output voltage is increased by the control
loop as it tries to regulate this lower IFBx voltage to the target value (90mV typical). For the normal string, its
current is still under regulation but its IFBx voltage increases along with the output voltage. During the process,
either the SW voltage reaches its OVP threshold VOVP_SW or the normal string’s IFBx pin voltage reaches the
IFBx OVP threshold VOVP_FB, then the protection circuitry will be triggered accordingly.
If both LED strings are open, both IFBx pins’ voltages drop to ground, and the boost output voltage is increased
by the control loop until reaching the SW OVP threshold VOVP_SW, the SW OVP protection circuitry is triggered,
and the IC is latched off. Only VIN POR or EN/PWM pin toggling can restart the IC.
Copyright © 2013, Texas Instruments Incorporated
15
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
One LED diode short in a string is allowed for the TPS61162A/TPS61163A. If one LED diode in a string is short,
the normal string’s IFBx voltage is regulated to about 90mV, and the abnormal string’s IFBx pin voltage will be
higher. Normally with only one diode short, the higher IFBx pin voltage does not reach the IFBx OVP threshold
VOVP_FB, so the protection circuitry will not be triggered.
If more than one LED diodes are short in a string, as the boost loop regulates the normal string’s IFBx voltage to
90mV, this abnormal string’s IFBx pin voltage is much higher and will reach VOVP_FB, then the protection circuitry
is triggered.
The SW OVP protection will also be triggered when the forward voltage drop of an LED string exceeds the SW
OVP threshold. In this case, the device turns off the switch FET and shuts down.
Soft Start /
Normal Operation
No
SW > VOVP for 16~32
switching cycles?
Yes
Latch off
Figure 23. SW OVP Protection Action
Normal Operation
IFBx > VIFB_OVP for
24~32 switching
No (caused by transient)
cycles?
Yes
Yes (single string application,
caused by transient)
Another string is no
use?
Boost stops
switching, current
sink(s) keep on
No
No (dual string application,
caused by transient)
Another VIFBx < 0.5V?
Yes (caused by open string or
more than two LED diodes
short in a string)
Boost stops switching,
disable the current sink
with VIFBx < 0.5V
VIFBx < VIFB_OVP_hys?
Yes (to recover boost
switching)
Figure 24. VIFBx OVP Protection Action
16
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
OVER CURRENT PROTECTION
The TPS61162A/TPS61163A has a pulse-by-pulse over-current limit. The boost switch turns off when the
inductor current reaches this current threshold and it remains off until the beginning of the next switching cycle.
This protects the TPS61162A/TPS61163A and external component under overload conditions.
THERMAL SHUTDOWN
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The device is released from shutdown automatically when the junction temperature decreases by 15°C.
Copyright © 2013, Texas Instruments Incorporated
17
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
APPLICATION INFORMATION
INDUCTOR SELECTION
Because the selection of inductor affects power supply’s steady state operation, transient behavior, loop stability
and the boost converter efficiency, the inductor is one of the most important components in switching power
regulator design. There are three specifications most important to the performance of the inductor: inductor
value, DC resistance, and saturation current. The TPS61162A/TPS61163A is designed to work with inductor
values from 4.7µH to 10µH to support all applications. A 4.7µH inductor is typically available in a smaller or lower
profile package, while a 10µH inductor produces lower inductor ripple. If the boost output current is limited by the
over-current protection of the IC, using a 10µH inductor may maximize the controller’s output current capability. A
22µH inductor can also be used for some applications, such as 6s2p and 7s2p, but may cause stability issue
when more than eight WLED diodes are connected per string. Therefore, customers need to verify the inductor in
their application if it is different from the values in RECOMMENDED OPERATING CONDITIONS.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the
inductor vendor defines saturation. When selecting an inductor, please make sure its rated current, especially the
saturation current, is larger than its peak current during the operation.
Follow Equation 4 to Equation 6 to calculate the inductor’s peak current. To calculate the current in the worst
case, use the minimum input voltage, maximum output voltage and maximum load current of the application. In
order to leave enough design margin, the minimum switching frequency (1MHz for TPS61162A/TPS61163A), the
inductor value with –30% tolerance, and a low power conversion efficiency, such as 80% or lower are
recommended for the calculation.
In a boost regulator, the inductor DC current can be calculated as Equation 4.
V
OUT ´IOUT
IDC
=
V ´ h
IN
(4)
(5)
(6)
Where:
VOUT = boost output voltage
IOUT = boost output current
VIN = boost input voltage
η = boost power conversion efficiency
The inductor current peak to peak ripple can be calculated as Equation 5.
1
IPP
=
æ
ç
è
ö
÷
ø
1
1
L ´
+
´F
S
VOUT - V
V
IN
IN
Where:
IPP = inductor peak-to-peak ripple
L = inductor value
FS = boost switching frequency
VOUT = boost output voltage
VIN = boost input voltage
Therefore, the peak current IP seen by the inductor is calculated with Equation 6.
IPP
IP = IDC
+
2
Select an inductor with saturation current over the calculated peak current. If the calculated peak current is larger
than the switch MOSFET current limit ILIM, use a larger inductor, such as 10µH, and make sure its peak current is
below ILIM
.
18
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
Boost converter efficiency is dependent on the resistance of its current path, the switching losses associated with
the switch MOSFET and power diode and the inductor’s core loss. The TPS61162A/TPS61163A has optimized
the internal switch resistance, however, the overall efficiency is affected a lot by the inductor’s DC Resistance
(DCR), Equivalent Series Resistance (ESR) at the switching frequency and the core loss. Core loss is related to
the core material and different inductors have different core loss. For a certain inductor, larger current ripple
generates higher DCR/ESR conduction losses as well as higher core loss. Normally a datasheet of an inductor
does not provide the ESR and core loss information. If needed, consult the inductor vendor for detailed
information. Generally, an inductor with lower DCR/ESR is recommended for TPS61162A/TPS61163A
application. However, there is a trade off among inductor’s inductance, DCR/ESR resistance, and its footprint;
furthermore, shielded inductors typically have higher DCR than unshielded ones. Table 3 lists some
recommended inductors for the TPS61162A/TPS61163A. Verify whether the recommended inductor can support
your target application by the calculations above as well as bench validation.
Table 3. Recommended Inductors
SATURATION CURRENT
PART NUMBER
L (µH)
DCR MAX (mΩ)
Size (L x W x H mm)
VENDOR
(A)
1.9
1.3
1.3
2.7
2.3
LPS4018-472ML
LPS4018-682ML
LPS4018-103ML
PIMB051B-4R7M
PIMB051B-6R8M
4.7
6.8
10
125
150
200
163
250
4 x 4 x 1.8
4 x 4 x 1.8
Coilcraft
Coilcraft
Coilcraft
Cyntec
4 x 4 x 1.8
4.7
6.8
5.4 x 5.2 x 1.2
5.4 x 5.2 x 1.2
Cyntec
SCHOTTKY DIODE SELECTION
The TPS61162A/TPS61163A demands a low forward voltage, high-speed and low capacitance Schottky diode
for optimum efficiency. Ensure that the diode average and peak current rating exceeds the average output
current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the open LED
protection voltage. ONSemi MBR0540 and NSR05F40, and Vishay MSS1P4 are recommended for the
TPS61162A/TPS61163A.
COMPENSATION CAPACITOR SELECTION
The compensation capacitor C4 (refer to ADDITIONAL APPLICATION CIRCUITS) connected from the COMP
pin to GND, is used to stabilize the feedback loop of the TPS61162A/TPS61163A. A 330nF ceramic capacitor for
C4 is suitable for most applications. A 470nF is also OK for some applications and customers are suggested to
verify it in their applications.
OUTPUT CAPACITOR SELECTION
The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. A 1µF to
2.2µF capacitor is recommended for the loop stability consideration. This ripple voltage is related to the
capacitor’s capacitance and its equivalent series resistance (ESR). Due to its low ESR, Vripple_ESR could be
neglected for ceramic capacitors. Assuming a capacitor with zero ESR, the output ripple can be calculated with
Equation 7.
(VOUT - V )´IOUT
=
IN
V
ripple
VOUT ´FS ´ COUT
(7)
Where: Vripple = peak-to-peak output ripple. The additional part of ripple caused by the ESR is calculated using
Vripple_ESR = IOUT x RESR and can be ignored for ceramic capacitors.
Note that capacitor degradation increases the ripple much. Select the capacitor with 50V rated voltage to reduce
the degradation at the output voltage. If the output ripple is too large, change a capacitor with less degradation
effect or with higher rated voltage could be helpful.
Copyright © 2013, Texas Instruments Incorporated
19
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
LAYOUT CONSIDERATION
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in
ADDITIONAL APPLICATION CIRCUITS, needs to be close to the inductor, as well as the VIN pin and GND pin
in order to reduce the input ripple seen by the IC. If possible, choose higher capacitance value for it. If the ripple
seen at VIN pin is so large that it affects the boost loop stability or internal circuits operation, R2 and C3 are
recommended to filter and decouple the noise. In this case, C3 should be placed as close as possible to the VIN
and GND pins. The SW pin carries high current with fast rising and falling edges. Therefore, the connection
between the SW pin to the inductor and Schottky diode should be kept as short and wide as possible. The trace
between Schottky diode and the output capacitor C2 should also be as short and wide as possible. It is also
beneficial to have the ground of the output capacitor C2 close to the GND pin since there is a large ground return
current flowing between them. When laying out signal grounds, it is recommended to use short traces separated
from power ground traces, and connect them together at a single point close to the GND pin.
ADDITIONAL APPLICATION CIRCUITS
L1
4.7µH
2.7V ~ 6.5V
D1
VBAT
R2
10ꢀ
C1
1µF
C2
1µF
SW
VIN
C3
1µF
Enable /
Disable
EN
TPS61162A/3A
PWM
Dimming
PWM
IFB1
IFB2
COMP
C4
330nF
ISET
R1
63.4kꢀ
GND
Figure 25. TPS61162A/TPS61163A Typical Application (PWM interface enabled,
EN pin can be used to enable or disable the IC)
20
Copyright © 2013, Texas Instruments Incorporated
TPS61162A
TPS61163A
www.ti.com.cn
ZHCSBU3 –NOVEMBER 2013
L1
4.7µH
2.7V ~ 6.5V
D1
VBAT
R2
10ꢀ
C1
1µF
C2
1µF
SW
VIN
C3
1µF
EN
TPS61162A/3A
PWM
Dimming
PWM
IFB1
IFB2
COMP
C4
330nF
ISET
R1
63.4kꢀ
GND
Figure 26. TPS61162A/TPS61163A Typical Application (PWM interface enabled, EN pin connected to VIN,
only PWM signal is used to enable or disable the IC)
L1
4.7µH
2.7V ~ 6.5V
D1
VBAT
R2
10ꢀ
C1
1µF
C2
1µF
SW
VIN
C3
1µF
EasyScale
Command
EN
TPS61162A/3A
Enable /
Disable
PWM
IFB1
IFB2
COMP
C4
330nF
ISET
R1
63.4kꢀ
GND
Figure 27. TPS61162A/TPS61163A Typical Application (1-wire digital interface enabled,
PWM pin can be used to enable or disable the IC)
Copyright © 2013, Texas Instruments Incorporated
21
TPS61162A
TPS61163A
ZHCSBU3 –NOVEMBER 2013
www.ti.com.cn
L1
4.7µH
2.7V ~ 6.5V
D1
VBAT
R2
10ꢀ
C1
1µF
C2
1µF
SW
VIN
C3
1µF
EasyScale
Command
EN
TPS61162A/3A
PWM
IFB1
IFB2
COMP
C4
330nF
ISET
R1
63.4kꢀ
GND
Figure 28. TPS61162A/TPS61163A Typical Application (1-wire digital interface enabled,
PWM pin connected to VIN, only EN signal is used to enable or disable the IC)
22
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61162AYFFR
TPS61163AYFFR
ACTIVE
DSBGA
DSBGA
YFF
9
9
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-40 to 85
TPS
61162A
ACTIVE
YFF
SNAGCU
TPS
61163A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
YFF0009
DSBGA - 0.625 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.8 TYP
C
B
SYMM
0.8
TYP
0.4 TYP
A
0.3
0.2
3
1
2
9X
SYMM
0.015
C A B
0.4 TYP
4219552/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
9X ( 0.23)
(0.4) TYP
1
2
A
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219552/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
9X ( 0.25)
1
3
2
A
(0.4) TYP
B
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219552/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明