TPS61178RNWT [TI]
具有负载断开控制功能的 20V、10A 全集成同步升压 | RNW | 13 | -40 to 85;
| 型号： | TPS61178RNWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有负载断开控制功能的 20V、10A 全集成同步升压 | RNW | 13 | -40 to 85 |
| 文件： | 总40页 (文件大小：1423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
具备负载断开控制功能的 TPS61178x 20V、10A 全集成同步升压器件
1 特性
3 说明
1
•
输入电压范围：2.7V 至 20V
输出电压范围：4.5V 至 20V
可编程开关峰值电流：高达 10A
集成了两个 16mΩ FET
TPS61178x 系列是内置了栅极驱动器（以实现负载断
开功能）的 20V 同步升压转换器。TPS61178x 集成了
两个低导通电阻的功率 FET：一个 16mΩ 开关 FET 和
一个 16mΩ 整流器 FET。
•
•
•
•
效率高达 96%：VIN = 7.2V，VOUT = 16V，IOUT
2A
=
TPS61178x 使用具有集成斜坡补偿功能的固定频率峰
值电流模式控制。在轻负载时，TPS61178 进入自动
PFM 模式，而 TPS611781 处于强制 PWM 模式。
•
•
可调节开关频率：高达 2.2MHz
外部时钟同步：
200kHz 至 2.2MHz
TPS61178x 可以在关断时将输出与输入侧隔离。输出
短接后，它将进入间断模式以减小热应力，并可在短接
结束后自动恢复。此外，TPS61178x 还具有 OVP 和
过热保护以避免故障运行。TPS61178x 采用 3.0mm x
3.5mm 13 引脚 VQFN 封装，具有增强的热耗散性
能。
•
•
•
•
•
•
•
可提供负载断开功能的栅极驱动器
自动切断短路保护功能
过压保护
自动 PFM 操作 - TPS61178
强制 PWM 模式 - TPS611781
3mm x 3.5mm 13 引脚 VQFN Hotrod 封装
使用 TPS61178 并借助 WEBENCH® 电源设计器
创建定制设计方案
器件信息(1)
器件号
TPS61178
TPS611781
封装
封装尺寸（标称值）
QFN (13)
3.00mm × 3.5mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
便携式扬声器
LCD 显示屏的电源驱动器
功率放大器的电源
电机驱动器的电源
USB Type-C 电力输送
典型应用
L
VIN
CIN
VIN
BST
VCC
CBST
CVCC
SW
VOUT2
P-FET (option)
ON
VOUT
EN
OFF
RGATE
CGATE
RUP
COUT2
COUT1
FREQ /
SYNC
RFreq
DISDRV
RDOWN
FB
ILIMIT
AGND
RLIMIT
COMP
PGND
Cc
RC
Cp
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDA7
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
9.3 System Examples .................................................. 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements ............................................... 6
7.7 Switching Characteristics.......................................... 6
7.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
9
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 器件和文档支持 ..................................................... 31
12.1 器件支持 ............................................................... 31
12.2 文档支持 ............................................................... 31
12.3 相关链接................................................................ 31
12.4 接收文档更新通知 ................................................. 31
12.5 社区资源................................................................ 32
12.6 商标....................................................................... 32
12.7 静电放电警告......................................................... 32
12.8 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 32
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (July 2019) to Revision E
Page
•
•
Restored hyperlink cross reference at the Thermal Information table footnote. .................................................................... 4
Deleted right-hand column (A/B/S) in the Electrical Characteristics table. ............................................................................ 5
Changes from Revision C (March 2018) to Revision D
Page
•
Corrected term 1–DR to 1–D in 公式 21............................................................................................................................... 23
Changes from Revision B (September 2017) to Revision C
Page
•
Changed 公式 21 ................................................................................................................................................................. 23
Changes from Revision A (April 2017) to Revision B
Page
•
已更改 graphs for 图 1 through 图 6 to include 3-A load ....................................................................................................... 7
Changes from Original (February 2017) to Revision A
Page
2
Copyright © 2017–2019, Texas Instruments Incorporated
TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
5 Device Comparison Table
Part Number
TPS61178
Operation Mode at Light Load
Auto PFM
TPS611781
Forced PWM
6 Pin Configuration and Functions
(RNW)
(13-Pin QFN)
Top View
8
7
6
DISDRV
VCC
9
5
4
FB
10
COMP
ILIMIT
11
12
13
3
2
1
EN
VIN
AGND
FREQ/SYNC
BST
Pin Functions
PIN
NUMBER
I/O
DESCRIPTION
NAME
FREQ / SYNC
1
I
The switching frequency is programmed by a resistor between this pin and the AGND. The
internal oscillator can be synchronized by an external clock connecting into this pin. This pin
can not be float in application.
AGND
2
-
Analog signal ground of the IC. Connect the AGND to PGND via a single point on the printed
circuit board.
ILIMIT
COMP
3
4
I
Programming the switching peak current limit by a resistor between this pin and AGND.
O
Output of the internal error amplifier. The loop compensation network should be connected
between this pin and AGND.
FB
5
6
7
I
Output voltage feedback, a resistor divider connecting to this pin sets the output voltage.
Power ground
PGND
SW
PWR
PWR
The switching node pin of the converter. It is connected to the drain of the internal low-side
power FET and the source of the internal high-side power FET.
VOUT
8
9
PWR
O
Boost converter output
DISDRV
A gate drive output for the external disconnect FET. Connect the DISDRV pin to the gate of
the external FET. Leave it floating if not using the load disconnect function.
VCC
10
O
Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required between
this pin and ground
EN
11
12
13
I
Enable logic input. Logic high level enables the device and low level shutdown the device.
IC power supply input.
VIN
BST
I
O
Power supply for high-side FET gate driver. A capacitor must be connected between this pin
and the SW pin
Copyright © 2017–2019, Texas Instruments Incorporated
3
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–40
MAX
SW + 7
23
UNIT
V
BST
(2)
Voltage range at terminals
VIN, SW, VOUT, DISCRG, EN
VCC, FB, COMP, FREQ / SYNC, ILIMIT
Operating junction temperature
Storage temperature
V
7
V
TJ
150
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
±2000
V(ESD)
Electrostatic discharge
V
(1)
Charged-device model (CDM), per JEDEC specification JESD22-
C101(3)
±750
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
20
UNIT
V
VIN
VOUT
L
Input voltage
Outputvoltage
4.5
20
V
Effective inductance range
Feedback resistance (low side)
Operating junction temperature
0.47
3.3
µH
kΩ
°C
RFB
TJ
200
125
–40
7.4 Thermal Information
TPS61178
THERMAL METRIC(1)
RNR (QFN Package)
UNIT
12 PINS
60.2
28.6
14.5
0.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.5
0.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report..
4
Copyright © 2017–2019, Texas Instruments Incorporated
TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
7.5 Electrical Characteristics
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.7
20
2.7
2.3
V
V
VIN rising
VIN falling
2.6
2.2
400
6
Input voltage under voltage lockout
(UVLO) threshold
VIN_UVLO
VIN_HYS
VCC
VIN UVLO hysteresis
VCC regulation voltage
VCC UVLO threshold
mV
V
ICC = 5mA, VIN = 8V
VCC falling
VCC_UVLO
2.1
V
IC enabled, no load, no ext. FET
VIN = 6 V, VOUT = 20 V, VFB = 1.3
V, TJ up to 85 ⁰C
Quiescent current into VIN pin
Quiescent current into VIN pin
Quiescent current into VOUT pin
Quiescent current into VOUT pin
1.5
270
250
5
3
320
300
12
µA
µA
µA
µA
IC enabled, no load, no ext. FET
VIN = 20 V, VOUT = 20 V, VFB = 1.3
V,TJ up to 85 ⁰C
IQ
(TPS61178)
IC enabled, no load, no ext. FET
VIN = 6 V, VFB = 1.3 V, VOUT = 20 V,
TJ up to 85 ⁰C
IC enabled, no load, no ext. FET
VIN = 20 V, VOUT = 20 V, VFB = 1.3
V, TJ up to 85 ⁰C
IC disabled, VIN = 6 V,
–40 °C ≤ TJ ≤ 85°C
1
3
3.5
6
µA
µA
ISD
Shutdown current into VIN pin
IC disabled, VIN = 20 V,
–40 °C ≤ TJ ≤ 85°C
IC disabled, VIN = VOUT = SW = 20
V
ILS_LKG
Reverse leakage current into SW
0.1
6.5
µA
–40 °C ≤ TJ ≤ 85°C
OUTPUT
VOLTAGE
VOUT
VOVP
Output voltage range
Freq = 500kHz
4.5
20
V
V
Output over-voltage protection
threshold
VIN = 8 V, VOUT rising
20.5
21
21.5
POWER
SWITCHES
RDS(on)
High-side MOSFET on resistance
Low-side MOSFET on resistance
VCC = 6 V
VCC = 6 V
16
16
25
25
mΩ
mΩ
Power stage trans-conductance
(peak current ratio with comp
voltage)
Gm
VCC = 6 V
12
A/V
CURRENT
LIMIT
ILIM_SW
ILIM_SW
TPS61178
RLIMIT = 80.6 kΩ
RLIMIT = 80.6 kΩ
6.4
5.7
8
7.4
20
9.4
8.7
A
A
A
TPS611781
ILIM_SHORT TPS61178 short current limit
VOLTAGE
REFERNCE
PWM mode
PFM mode
1.180
1.198
101%
10
1.210
60
V
VREF
Reference Voltage at FB pin
Leakage current into FB pin
VREF
nA
IFB_LKG
EN / SYNC LOGIC
VEN_H
VEN_L
EN Logic high threshold
EN Logic Low threshold
1.2
V
V
0.4
Copyright © 2017–2019, Texas Instruments Incorporated
5
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
UNIT
kΩ
V
REN
EN pulldown resistor
800
VSYNC_H
VSYNC_L
SYNC clock high threshold
SYNC clock low threshold
1.2
0.4
V
ERROR
AMPLIFIER
VCOMPH
VCOMPL
GmEA
COMP output high voltage
COMP output low voltage
Error amplifier trans conductance
Comp pin sink current
High threshold, VFB = VREF - 200 mV
1.9
1.25
195
20
V
Low threshold, VFB = VREF + 200
mV
V
VCOMP = 1.5 V
uS
uA
uA
VFB = VREF + 200 mV, VCOMP = 1.5
V
ISINK
ISOURCE
Comp pin source current
VFB = VREF –200 mV, VCOMP = 1.5 V
20
7.6 Timing Requirements
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
UNIT
CURRENT
LIMIT
tSHORT_ON Short active time
4
ms
ms
Time for Auto retry protection off
tSHORT_OFF
90
time
SOFT
START
tSTARTUP
Startup time
VIN = 8 V, VOUT = 16 V
Pre charge time
3.2
2.6
ms
ms
tPRE_CHARG Pre charge time
1.8
3.4
PROTECTION
tSD_R
tSD_F
Thermal shutdown rising threshold
Thermal shutdown falling threshold
TJ rising
TJ falling
150
130
°C
°C
7.7 Switching Characteristics
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
Unit
SWITCHING FREQUENCY / SYNC
RFREQ = 342 kΩ
RFREQ = 842 kΩ
RFREQ = 75 kΩ
400
160
500
200
600
240
kHz
kHz
kHz
ns
fSW
Switching frequency
1900
2200
105
2500
135
tON_min
Minimum on time
tOFF_min
fSYNC_MIN
Minimum off time
140
180
ns
Min Frequency using external clock
190
200
210
kHz
kHz
fSYNC_MAX Max Frequency using external clock
2090
2200
2310
GATE DRIVER
FOR LOAD DISCONNECT
IGH_SINK
External PFET drive current
55
uA
6
Copyright © 2017–2019, Texas Instruments Incorporated
TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
7.8 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
0.0001
0.001
0.01
Load (A)
0.1
1
3
0.0001
0.001
0.01
Load (A)
0.1
1
3
VOUT = 16 V
L = 3.3 µH
Auto PFM
VOUT = 16 V
L = 3.3 µH
Auto PFM
图 1. Efficiency vs. Output Current
图 2. Efficiency vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
VIN = 3 V
VIN = 3.6 V
VIN = 4.2 V
0.0001
0.001
0.01
Load (A)
0.1
1
3
0.001
VOUT = 14 V
图 3. Efficiency vs. Output Current
0.01
0.1
Load (A)
1
D046
VOUT = 16 V
L = 3.3 µH
Forced PWM
L = 1.8 µH
Auto PFM
图 4. Efficiency vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
16.5
16.4
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
15.5
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
0.0001
0.001
0.01
Load (A)
0.1
1
3
0.0001
0.001
0.01
Load (A)
0.1
1
3
VOUT = 16 V
L = 3.3 µH
Forced PWM
VOUT = 16 V
L = 3.3 µH
Auto PFM
图 5. Efficiency vs. Output Current
图 6. Output Voltage vs. Load
版权 © 2017–2019, Texas Instruments Incorporated
7
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
310
290
270
250
230
210
190
170
150
16.5
16.4
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
15.5
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
TJ = -40 èC
TJ = 25 èC
TJ = 85 èC
0.0001
0.001
0.01
Load (A)
0.1
1
3
8
10
12
14
Input Voltage (V)
16
18
20
D010
VOUT = 16 V
L = 3.3 µH
图 7. Output Voltage vs. Load
TJ = -40 èC
Auto PFM
图 8. Quiescent Current vs VIN
16
14
12
10
8
5
4.5
4
Auto PFM
TJ = 25 èC
TJ = 85 èC
3.5
3
2.5
2
6
1.5
1
4
2
0.5
0
0
40
60
80 100 120 140 160 180 200 220 240
Resistor (kW)
2
4
6
8
10 12
Input Voltage (V)
14
16
18
20
D040
VOUT = 16 V
VIN = 7.2 V
Auto PFM
D018
图 10. Switch Current Limit vs Setting Resistor
图 9. Shutdown Current vs VIN
26
24
22
20
18
16
14
12
10
24
22
20
18
16
14
12
10
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
-40
-20
VCC = 6 V
图 11. LS Rdson vs Temperature
0
20
40
60
80
100
120
D013
Temperature (èC)
VCC = 6 V
图 12. HS Rdson vs Temperature
D014
8
版权 © 2017–2019, Texas Instruments Incorporated
TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
Typical Characteristics (接下页)
3300
3000
2700
2400
2100
1800
1500
1200
900
1.205
1.203
1.201
1.199
1.197
1.195
600
300
0
-40
-20
0
20
40
60
80
100 120 140
0
100 200 300 400 500 600 700 800 900 1000
Resistor (kW)
Temperature (èC)
D015
VIN = 7.2 V
VOUT = 16 V
图 14. Reference Voltage vs Temperature
图 13. Frequency vs Setting Resistor
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
Rising
Falling
1.9
Rising
Falling
1.8
-40
-20
0
20
40
60
80
100
120130
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D023
D024
图 15. VIN UVLO Rising / Falling vs Temperature
图 16. EN Threshold Rising / Falling vs Temperature
版权 © 2017–2019, Texas Instruments Incorporated
9
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS61178x family is a synchronous boost converter designed for delivering the switch peak current up to 10
A and output voltage reaching to 20 V. The TPS61178x family operates at a fixed frequency pulse-width
modulation (PWM) at the moderate to heavy load currents. At the light load current, the TPS61178 operates in
the PFM mode while the TPS611781 operates in the Forced PWM mode. The PFM mode brings the high
efficiency crossing the entire load range while the Forced PWM mode can avoid the noise interference at the
light load.
With the peak current mode control scheme, the TPS61178x provides the excellent line and load transient
response with the minimal output capacitance. The external loop compensation brings the flexibility to use a
wider range of the inductor and output capacitor combinations.
The TPS61178x supports the adjustable switching frequency up to 2.2 MHz. The device implements a cycle-by-
cycle current limit to protect the device from overload during the boost operation phase. Additionally, if the output
current further increases and exceeds the short current threshold or the output voltage drops below the short
threshold. The TPS61178x triggers the hiccup short protection and recovers automatically once the short
condition releases.
Additionally, the TPS61178x provides the gate driver for the external FET to isolate the output from input end
during shutdown.
8.2 Functional Block Diagram
L
VIN
CBST
CIN
VIN
BST
SW
VOUT
VCC
VCC
VOUT2
COUT2
LS HS
DRV DRV
P-FET
CVCC
VIN VOUT
VCC
BST
SW
COUT1
RGATE
CGATE
LS
DRV
HS
DRV
CTL
CRT
REG
EN
ON
DISDRV
OFF
CR LIM
Comp
VCC
ISENSE
VOUT2
+
FREQ /
SYNC
ILimit
REF
RUP
Slope Comp
+
FB
RFREQ
OR
+
+
VREF
VCLK
Gm
RDOWN
PWM
Comp
VCC
ILIMIT
+
SS
ILimit REF
COMP
RLIMIT
Cc
RC
Cp
VOUT
OVP TH.
Temp
OTP TH.
AGND
PGND
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8.3 Feature Description
8.3.1 Under-voltage Lockout
An under-voltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the UVLO threshold of 2.3 V. A hysteresis of 400 mV is added so that the device cannot be enabled again until
the input voltage exceeds 2.7 V. This function is implemented in order to prevent malfunctioning of the device
when the input voltage is between 2.3 V and 2.7 V.
8.3.2 Enable and Disable
When the input voltage is above UVLO rising threshold of 2.7 V and the EN pin is pulled high above 1.2 V, the
TPS61178X is enabled. When the EN pin is pulled below 0.4 V, the TPS61178x goes into the shutdown mode
and stops switching.
8.3.3 Startup
When the input voltage to the device exceeds the UVLO threshold and EN pin pulled to high as well, the
TPS61178x starts to ramp up the output voltage. There is a switching pre-charge phase and the output voltage is
charged up to 10% higher than the input voltage (1.1 x VIN). The switching frequency is a fixed 500 kHz at the
pre-charge phase.
After the pre-charge phase ends (typical 2.6 ms), The TPS61178x regulates the FB pin to the internal soft start
voltage and results in a gradual rise of the output voltage starting from the input voltage level to the target output
voltage. The soft start time is typical 3.2 ms, which helps the regulator to gradually reach the steady state setting
point, thus reducing the startup stresses and surges. The switching frequency follows the oscillator setting by the
resistor connecting with the FREQ / SYNC pin.
If the device is synchronized by the external clock, the switching frequency is fixed 500 kHz at the soft start
phase and changes to the external clock when the soft start phase ends.
8.3.4 Load Disconnect Gate Driver
The TPS61178 device provides a DISDRV pin to drive the external FET at the output side, which completely
disconnects the output from the input end during shutdown or output short happens. During the device’s start-up
phase, the disconnect FET is controlled by the gate driver voltage of the external disconnect FET, there is an
internal 55 µA (typical) sink current. The load disconnect FET connection is shown as 图 17
The driver voltage and turn on / off timing can be set via the resistor and capacitor connecting between with the
DISDRV pin and the source of the external FET. See the Application and Implementation section for the details
of how to select the gate resistor and capacitor
P-MOS
VOUT2
VOUT
COUT2
COUT1
CGATE
VGS
RGATE
DISDRV
图 17. The Load Disconnect FET Connected
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Feature Description (接下页)
8.3.5 Adjustable Peak Current Limit
When the TPS61178x is in the normal boost switching phase, the device is prevented from the over current
condition via the cycle by cycle current limit by sensing the current through the internal low-side FET. When the
peak switch current triggers the current limit threshold, the low-side switch turns off to prevent the switching
current further increasing.
The peak switch current limit can be set by a resistor connecting with the ILIMIT pin. The relationship between the
current limit and the resistor is determined by 公式 1
745
RLIMIT
=
ILIMIT
(1)
Where RLIMIT is the resistor for setting the current limit, with the unit of kΩ, ILIMIT is switching peak current limit,
the unit is A. For instance, when the resistor value is 50 kΩ, the switch peak current limit is 15 A.
图 18 shows the current limit versus the setting resistor for both TPS61178 ( Auto PFM ) and TPS611781 (
Forced PWM ) with 7.2-V input to 16-V output.
16
Auto PFM
14
12
10
8
6
4
2
0
40
60
80 100 120 140 160 180 200 220 240
Resistor (kW)
D040
图 18. Switch Current Limit vs. Setting Resistor
The current limit value varies with the duty cycle, 图 30 shows the bench measurement current limit at different
duty cycles at RLIMIT = 80.6 kΩ.
9.9
Auto PFM
9.4
8.9
8.4
7.9
7.4
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
Duty Cycle
D041
图 19. Switch Current Limit vs. Duty Cycle
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Feature Description (接下页)
For the TPS611781, which works in the Forced PWM mode at the light load, the current limit is typically 0.8 A
lower than TPS61178 (Auto PFM) with the same setting resistor.
8.3.6 Output Short Protection (with load disconnected FET)
In addition to the cycle-by-cycle current limiting, the TPS61178x also has the output short protection. If the
inductor current reaches the short protection limit threshold (typical 20A ) or the output voltage drops below 30%
(typical) of the normal output voltage, the device enters into the hiccup protection mode. In the hiccup mode, the
device shuts down itself and restarts after 90ms (typical) waiting time which helps to reduce the total thermal
dissipation. After the short condition releases, the device can recover automatically and restart the start-up
phase. The hiccup protection scheme is illustrated in 图 20.
VOUT2
SW
P_MOS gate disabled
(Ilimit_short trigger or VOUT < 30%
x VOUT_Normal )
-VGS
Ishort_limit
(typical 20A )
P-MOS date gate turn off time:
2 = Rgate x Cgate
IL
Hiccup off time
Retry after hiccup off
time terminate
图 20. Output Short Protection
8.3.7 Adjustable Switching Frequency
The TPS61178x features of a wide adjustable switching frequency ranging up to 2.2 MHz. The switching
frequency is set by a resistor connecting with the FREQ / SYNC pin. This pin cannot be left floating in the
application. Use 公式 2 and 公式 3 to calculate the resistor value for a desired frequency.
1
T =
= k ´ CFREQ ´ RFREQ + TDELAY
Freq
(2)
1
- TDELAY
Freq
=
RFREQ
k ´ CFREQ
where
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Feature Description (接下页)
•
TDELAY = 50 nS, k = 3, CFREQ = 1.8 pF
(3)
For instance, if the RFREQ is 342 kΩ, the frequency is 500 kHz.
图 21 shows the switching frequency versus the setting resistor, which is measured with VOUT = 16 V from VIN
=
7.2 V .
3300
3000
2700
2400
2100
1800
1500
1200
900
600
300
0
0
100 200 300 400 500 600 700 800 900 1000
Resistor (kW)
图 21. Switching Frequency vs Setting Resistor
8.3.8 External Clock Synchronization (TPS611781)
The FREQ/ SYNC pin can be used to synchronize the internal oscillator by an external clock. A positive voltage
at the FREQ / SYNC pin must exceed the rising threshold (1.2 V) while must be lower than the falling threshold
(0.4 V) to trip the internal synchronization pulse detector. The recommended frequency for the external clock is
between 200 kHz and 2.2 MHz.
8.3.9 Error Amplifier
The TPS61178x has a trans-conductance amplifier and compares the feedback voltage with the internal voltage
reference (or the internal soft start voltage during startup phase). The trans-conductance of the error amplifier is
195 µA / V typically. The loop compensation components are required to be placed between the COMP terminal
and ground to balance the loop stability and the transient response time.
8.3.10 Slope Compensation
The TPS61178x adopts the peak current mode control and adds a compensating ramp to the switch current
signal. This slope compensation prevents the sub-harmonic oscillations when the duty cycle is larger than 50%.
The available peak inductor current varies a little bit with operating duty cycles shown in 图 19.
8.3.11 Start-up with the Output Pre-Biased
The TPS61178x has been designed to prevent the low-side FET from discharging a pre-biased output. During
the pre-biased startup, both high-side and low-side FETs are not allowed to be turned on until the internal soft
start voltage is higher than the sensed output voltage at FB pin.
8.3.12 Bootstrap Voltage (BST)
The TPS61178x has an integrated bootstrap regulator, and requires a small ceramic capacitor between the BST
pin and SW pin to provide the gate drive voltage for the high-side FET. The bootstrap capacitor is charged when
the BST-SW voltage is below regulation. The value of this ceramic capacitor should be above 0.1 µF. A ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of
the stable characteristics over temperature and DC biased voltage.
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Feature Description (接下页)
8.3.13 Over-voltage Protection
If the output voltage at the VOUT pin is detected above over-voltage protection threshold, typically 21 V, the
TPS61178x stops switching immediately until the voltage at the VOUT pin drops lower than the output over-
voltage protection threshold (with 500mV hysteresis). This function prevents the devices against the over-voltage
and secures the circuits connected to the output from excessive over voltage.
8.3.14 Thermal Shutdown
A thermal shutdown is implemented to prevent the damage due to the excessive heat and power dissipation.
Typically, the thermal shutdown occurs at the junction temperature exceeding 150°C. When the thermal
shutdown is triggered, the device stops switching and recover when the junction temperature falls below 130°C
(typical).
8.4 Device Functional Modes
8.4.1 Operation
TPS61178x operates at the peak current-mode pulse-width-modulation (PWM). At the beginning of each
switching cycle, the low-side FET switch turns on, and the inductor current ramps up to a peak current that is
determined by the output of the internal error amplifier. The PWM controller turns off the low-side FET when the
peak inductor current reaches a threshold level set by the error amplifier output. After the low-side FET turns off,
the high-side synchronous FET is turned on after a short dead time until the beginning of the next oscillator clock
cycle or until the inductor current reaches the reverse current sense threshold.
During the portion of the switching cycle when the low-side FET is on, the input voltage is applied across the
inductor and stores the energy as the inductor current ramps up. Meanwhile only the output capacitor supplies
the load current. When it turns off the low-side FET, the inductor transfers the stored energy via the high-side
synchronous FET to replenish the output capacitor and also supply the load current. This operation repeats every
switching cycle.
The device features the internal slope compensation to avoid sub-harmonic oscillation that is intrinsic to peak-
current mode control at duty cycle larger than 50%. The internal slope compensation may not be adequate to
maintain stability for a very low inductance in application.
At the light load condition, the TPS61178x implements two options: Auto PFM mode (TPS61178) and Forced
PWM mode (TPS611781) to meet different application requirements.
8.4.2 Auto PFM Mode (TPS61178)
The TPS61178 integrates a Power Save Mode with pulse frequency modulation ( PFM ) at the light load. When a
light load condition occurs, the COMP pin voltage naturally decreases and reduces the peak current. When the
COMP pin voltage further goes down with the load lowered and reaches the pre-set low threshold, the output of
the error amplifier is clamped at this threshold and does not go down any more. If the load is further lowered, the
output voltage of TPS61178 exceeds the nominal voltage and the device skips the switching cycles and regulate
the output voltage at a higher threshold (typical 101%*VOUT_NORMAL).
The Auto PFM mode reduces the switching losses and improves efficiency at the light load condition by reducing
the average switching frequency.
8.4.3 Forced PWM Mode (TPS611781)
In the Forced PWM mode, the TPS611781 keeps the switching frequency being constant for the whole load
range. When the load current decreases, the output of the internal error amplifier decreases as well to lower the
inductor peak current and delivers less power from input to output. The high-side FET is not turned off even if the
current through the FET goes negative to keep the switching frequency being the same as that of the heavy load.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS61178x family is the step up DC / DC converter. The following design procedure can be used to select
component values for the TPS61178x. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH® software uses an interactive design procedure and accesses a
comprehensive database of components when generating a design. This section presents a simplified discussion
of the design process.
9.2 Typical Application
The application described is for 6-V to 14-V input, 16-V output converter.
L
VIN
1.8 uH
CIN1
22 uF
VIN
BST
VCC
CBST
CVCC
0.1 uH
SW
4.7 uF
VOUT2
M1
VOUT
EN
RGATE CGATE
150 kΩ 22 nF
COUT1_2
10 uF
COUT1_1
10 uF
RUP
860 kΩ
COUT2_1 COUT2_2 COUT2_3
FREQ /
SYNC
22 uF
22 uF
22 uF
RFreq
DISDRV
348 kΩ
RDOWN
80.6 kΩ
FB
ILIMIT
AGND
RLIMIT
COMP
51.1 kΩ
PGND
Cc
6.8 nF
Cp
RC
10 pF
15.0 kΩ
Copyright © 2017, Texas Instruments Incorporated
图 22. TPS61178 16-V Output with Load Disconnect Schematic
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Typical Application (接下页)
9.2.1 Design Requirements
For this design example, use 表 1 as the design parameters.
表 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
6 V to 14 V
16 V
Output ripple voltage
Output current rating
Operating frequency
±3%
3 A
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61178 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
•
•
•
•
•
•
Input voltage range
Output voltage
Output ripple voltage
Output current rating
Operating frequency
Load disconnect needed or not
9.2.2.2 Setting the Switching Frequency
The switching frequency of the TPS61178 is set at 500 kHz. Use 公式 2 to calculate the required resistor value.
The calculated value is 342 kΩ. Use the next higher standard value of 348 kΩ.
9.2.3 Setting the Current Limit
The current limit of the TPS61178 could be programmed by an external resistor. For a target current limit of 13
A, the calculated resistor value is 57 kΩ. However, the minimum current limit is around 1.6 A lower than the
typical one. Here, selecting the 51.1 kΩ resistor to deliver 13-A peak current at the worst case.
9.2.4 Setting the Output Voltage
The output voltage of the TPS61178 is externally adjustable using a resistor divider network. The relationship
between the output voltage and the resistor divider is given by 公式 4.
RUP
VOUT = VFB ´ (1+
)
RDOWN
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where
•
•
•
VOUT is the output voltage
RUP the top divider resistor
RDOWN is the bottom divider resistor
(4)
Choose RDOWN to be approximately 80.6 kΩ. Slightly increasing or decreasing RDOWN can result in closer output
voltage matching when using standard value resistors. In this design, RDOWN = 80.6 kΩ and RUP = 1000 kΩ,
resulting in an output voltage of 16 V.
For the best accuracy, RDOWN is recommended to be smaller than 100 kΩ to ensure that the current following
through RDOWN is at least 100 times larger than FB pin leakage current. Changing RDOWN towards the lower value
increases the robustness against noise injection. Changing the RDOWN towards the higher values reduces the
quiescent current for achieving higher efficiency at the light load currents.
9.2.4.1 Selecting the Inductor
A boost converter normally requires two main passive components for storing the energy during the power
conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency ( including the
ripple and efficiency ) as well as the transient behavior and loop stability, which makes the inductor to be the
most critical component in application.
When selecting the inductor, as well as the inductance, the other parameters of importance are:
•
•
•
The maximum current rating (RMS and peak current should be considered),
The series resistance,
Operating temperature
Choosing the inductor ripple current with the low ripple percentage of the average inductor current results in a
larger inductance value, maximizes the converter’s potential output current and minimizes EMI. The larger ripple
results in a smaller inductance value, and a physically smaller inductor, improves transient response but results
in potentially higher EMI.
The rule of thumb to choose the inductor is that to make the inductor ripple current (ΔIL) is a certain percentage
(Ripple % = 20 – 30 %) of the average current. The inductance can be calculated by 公式 5, 公式 6, and 公式 7:
V
IN ´ D
DIL =
L ´ fSW
(5)
(6)
VOUT ´ IOUT
DIL _R = Ripple% ´
h ´ V
IN
h ´ V
IN
V ´ D
IN
1
L =
´
Ripple % VOUT ´ IOUT
´
ƒSW
where
•
•
•
•
•
•
•
•
•
ΔIL is the peak-peak inductor current ripple
VIN is the input voltage
D is the duty cycle
L is the inductor
ƒSW is the switching frequency
Ripple % is the ripple ration versus the DC current
VOUT is the output voltage
IOUT is the output current
η is the efficiency
(7)
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power-up, load faults, or transient load conditions, the inductor current can increase above the peak inductor
current calculated.
The TPS61178x has built-in slope compensation to avoid sub-harmonic oscillation associated with the current
mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 4 A, the
slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make
the peak-to-peak current ripple below 4 A when selecting the inductor.
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Inductor values can have ± 20% or even ± 30% tolerance with no current bias. When the inductor current
approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current
depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated
current, especially the saturation current, is larger than its peak current during the operation.
The inductor peak current varies as a function of the load, the switching frequency, the input and output voltages
and it can be calculated by 公式 8 and 公式 9.
1
IPEAK = I
+
´ DIL
IN
2
where
•
•
•
IPEAK is the peak current of the inductor
IIN is the input average current
ΔIL is the ripple current of the inductor
(8)
The input DC current is determined by the output voltage, the output current and efficiency can be calculated by :
VOUT ´ IOUT
I
=
IN
VIN ´ h
where
•
•
•
•
IIN is the input current of the inductor
VOUT is the output voltage
VIN is the input voltage
η is the efficiency
(9)
While the inductor ripple current depends on the inductance, the frequency, the input voltage and duty cycle
calculated by 公式 5, replace 公式 5, 公式 9 into 公式 8 and get the inductor peak current:
IOUT
VIN ´ D
1
IPEAK
=
+
´
(1- D) ´ h
2
L ´ fSW
where
•
•
•
•
•
•
•
IPEAK is the peak current of the inductor
IOUT is the output current
D is the duty cycle
η is the efficiency
VIN is the input voltage
L is the inductor
ƒSW is the switching frequency
(10)
The heat rating current (RMS) is as below:
1
(DIL )2
2
IL _RMS = I
+
IN
12
where
•
•
•
IL_RMS is the RMS current of the inductor
IIN is the input current of the inductor
ΔIL is the ripple current of the inductor
(11)
It is important that the peak current does not exceed the inductor saturation current and the RMS current is not
over the temperature related rating current of the inductors.
For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation
current. The total losses of the coil consists of the DC resistance ( DCR ) loss and the following frequency
dependent loss:
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
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For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the
frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,
it is usually a tradeoff between the loss and foot print.
The following inductor series in 表 2 from the different suppliers are recommended. 74437368033 from Würth is
used for this application case with balancing the size and power loss.
表 2. Recommended Inductors for TPS61178x(1)
SATURATION
DCR Typ (mΩ) Max CURRENT / Heat
SIZE (L × W × H
mm)
PART NUMBER
L (μH)
VENDOR(1)
Rating Current (A)
744325180
1.8
3.3
3.3
3.5
11.8
12
18
5 x 10 x 4
Würth
74437368033
23 / 8
10 / 10
10 x 10 x 3.8
10.9 x 10 x 4
Würth
DFEH10040D-
3R3M#
Murata / TOKO
PIMB104T-4R7MS
74437368068
4.7
6.8
10
20.0
17.5
27
15 / 8.5
14
10.9 x 10 x 3.8
11 x 10 x 3.8
11 x 10 x 3.8
Cyntec
Würth
Würth
74437368100
12.5
(1) See Third-party Products Disclaimer
9.2.4.2 Selecting the Output Capacitors
The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop
is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series
resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by 公式 12:
IOUT ´ (VOUT - V )
IN
COUT
=
fSW ´ DV ´ VOUT
where
•
•
•
•
•
•
COUT is the output capacitor
IOUT is the output current
VOUT is the output voltage
VIN is the input voltage
ΔV is the output voltage ripple required
ƒSW is the switching frequency
(12)
(13)
The additional output ripple component caused by ESR is calculated by 公式 13:
DVESR = IOUT ´ RESR
where
•
•
ΔVESR is the output voltage ripple caused by ESR
RESR is the resistor in series with the output capacitor
For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,
it must be considered if used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using
公式 14:
DISTEP
COUT
=
2p ´ fBW ´ DVTRAN
where
•
•
•
ΔISTEP is the transient load current step
ΔVTRAN is the allowed voltage dip for the load current step
ƒBW is the control loop bandwidth (i.e., the frequency where the control loop gain crosses zero)
(14)
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Care must be taken when evaluating a ceramic capacitor’s derating under the DC bias. Ceramic capacitors can
derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage
rating should be considered to ensure adequate capacitance at the required output voltage.
In applications of TPS61178x, it is recommended to run the converter with a reasonable amount of effective
output capacitance, for instance 3 x 22-μF X5R or X7R MLCC capacitors connected in parallel.
If the load disconnect FET is connected, the output capacitor should be split shown in 图 23. COUT2 should be no
larger than 10 x COUT1 to avoid the inrush current when turning on the disconnect FET.
P-FET
VOUT2
VOUT
VGS
CGATE
COUT1
RGATE
COUT2
DISDRV
图 23. Output Capacitor Configuration with the Load Disconnect FET
9.2.4.3 Selecting the Input Capacitors
Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they
have extremely low ESR and are available in small footprints. Input capacitors should be located as close as
possible to the device. While a 22-µF input capacitor is sufficient for the most applications, larger values may be
used to reduce input current ripple.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, should be placed
between CIN and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CIN.
9.2.4.4 Loop Stability and Compensation
9.2.4.4.1 Small Signal Model
The TPS61178x uses the fixed frequency peak current mode control; there is an internal adaptive slope
compensation to avoid the sub-harmonic oscillation. With the inductor current information sensed, the small-
signal model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole
system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. 图 24
shows the equivalent small signal elements of a boost converter.
版权 © 2017–2019, Texas Instruments Incorporated
21
TPS61178
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
L
VIN
VOUT
CIN
Q
RESR
COUT
ROUT
RSENSE
Slope
Comp
ISENSE
VOUT
RUP
Q
Q
S
FB
VREF
+
R
GEA
RDOWN
+
Cc
RC
Cp
REA
Copyright © 2017, Texas Instruments Incorporated
图 24. TPS61178x Control Equivalent Circuitry Model
The small signal of power stage including the slope compensation is:
S
S
(1+
)(1-
)
ROUT ´ (1- D)
2 ´ RSENSE
2p ´ fESR
2p ´ fRHP
GPS(S) =
´
´ He(S)
S
1+
2p ´ fP
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
RSENSE is the equivalent internal current sense resistor, which is typically 0.083 Ω of TPS61178x
(15)
(16)
The single pole of the power stage is:
2
fP =
2p ´ ROUT ´ COUT
where
•
COUT is the output capacitance, for a boost converter having multiple, identical output capacitors in parallel,
simply combine the capacitors with the equivalent capacitance
The zero created by the ESR of the output capacitor is:
1
fESR
=
2p ´ RESR ´ COUT
where
•
RESR is the equivalent resistance in series of the output capacitor.
(17)
The right-hand plane zero is:
ROUT ´ (1- D)2
fRHP
=
2p ´ L
22
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TPS61178
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ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
L is the inductance
(18)
Using He(s) to model the inductor current sampling effect as well as the slope compensation effect on the small
signal response, is shown in 公式 19
1
He(S) =
Se
Sn
é
ù
S ´ (1+
) ´ (1- D) - 0.5
S2
ê
ú
ë
û
1+
+
2
fSW
(p ´ fSW
)
(19)
(20)
V
IN
Sn =
´ RSENSE
L
where
•
Sn is the slew rate of the inductor current ramping up
fSW
Se = 0.06 ´
´ Rdson _ LS
1 - D
where
•
•
Se is the slope compensation slew rate
Rdson_LS is the on resistance of Low-side FET
(21)
The slope compensation adaptively changes with the switching frequency and duty cycle.
He(s) models the inductor current sampling effect as well as the slope compensation effect on the small signal
response. Note that if Sn > Se, e.g., when L is too small, the converter operates as a voltage mode converter
and the above model no longer holds.
The TPS61178x COMP pin is the output of the internal trans-conductance amplifier.
公式 22 shows the equation for feedback resistor network and the error amplifier.
S
1+
RDOWN
2´ p ´ fZ
HEA(S) = GEA ´REA
´
´
R
UP + RDOWN
S
S
(1+
)´(1+
)
2´ p ´ fP1
2´ p ´ fP2
where
•
kCOMP and REA are the ratio of peak current / comp voltage, for TPS61178x, the typical value is kCOMP = 12 A /
V and REA = 20 MΩ.
•
ƒP1, ƒP2 is the pole's frequency of the compensation, fZ is the zero’s frequency of the compensation network.
network
(22)
1
fP1
=
2p ´ REA ´ Cc
where
•
CC is the zero capacitor compensation
(23)
1
fP2
=
2p ´ RC ´ CP
where
•
•
CP is the pole capacitor compensation
RC is the resistor of the compensation network
(24)
(25)
23
1
fZ =
2p ´RC ´CC
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www.ti.com.cn
9.2.4.4.2 Loop Compensation Design Steps
With the small signal models coming out, the next step is to calculate the compensation network parameters with
the given inductor and output capacitance.
1. Set the Cross Over Frequency, ƒC
–
The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the
loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either
1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop
compensation network values of RC, CC, and CP by following below equations.
2. Set the Compensation Resistor, RC
–
By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~= RC and so RC × GEA sets the
compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s)
GPS(s) × HEA(s) × He(s) being zero at ƒC.
=
–
Therefore, to approximate a single-pole roll-off up to fP2, rearrange 公式 22 to solve for RC so that the
compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power stage
bode plot or more simply:
RDOWN
KEA(fC ) = 20 ´ log(GEA ´ RC ´
) = - KPS(fC)
RUP + RDOWN
where
•
•
•
KEA is gain of the error amplifier network
KPS is the gain of the power stage
GEA is the amplifier’s trans-conductance, the typical value of GEA = 195 µA / V
(26)
3. Set the compensation zero capacitor, CC
–
Place the compensation zero at the power stage ROUT ,COUT pole’s position, so to get:
1
fZ =
2p ´ RC ´ CC
(27)
(28)
–
Set ƒZ = ƒP, and get the
ROUT ´COUT
CC =
2RC
4. Set the compensation pole capacitor, CP
–
Place the compensation pole at the zero produced by the RESR and the COUT, it is useful for canceling
unhelpful effects of the ESR zero.
1
fP2
=
2p ´ RC ´ CP
(29)
(30)
1
fESR
=
2p ´ RESR ´ COUT
–
–
Set ƒP2 = ƒESR, and get the
RESR ´ COUT
CP =
RC
(31)
If the calculated value of CP is less than 10 pF, it can be neglected.
Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output
voltage ringing during the line and load transient. The RC = 15 kΩ , CC = 6.8 nF, Cp = 10 pF for this design
example.
9.2.4.4.3 Selecting the Disconnect FET
The TPS61178x provides a gate driver to control an external FET to disconnect the output from the input at
shutdown or output short conditions, shown in 图 25.
24
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TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
P-MOS
VOUT2
VOUT
COUT2
COUT1
CGATE
VGS
RGATE
DISDRV
图 25. Load Disconnect FET Connection
The VDS, IDS and safe operation area (SOA) should be taken into consideration when selecting the FET:
•
•
•
The drain-to-source voltage rating should be higher than the output max. voltage, VDS_DIS_MAX = VOUT
The drain-to-source RMS current rating is the maximum output current. I DS_DIS_RMS = IOUT
The SOA should be considered when the output short occurs, and there is heat caused by the short
,
,
protection response time and surge current, SOA > QSHORT
.
1
QSHORT
=
´ VOUT ´ ISHORT ´ TSHORT
2
where
•
•
•
•
•
VDS_DIS_Max is the maximum drain-source voltage
IDS_DIS is the drain-source RMS current
ISHORT is the short current
TSHORT is the response time before the short protection triggered
QSHORT is the heat produced for the output short
(32)
For instance: VOUT = 16 V, ISHORT = 20 A , TSHORT = 30 µs.
SOA ≥ 4.8 mJ, VDS_DIS_MAX ≥ 16 V.
The CSD25404Q3 –20 V P-Channel NexFET™ Power FET is used for this design example.
An additional capacitor between the gate and source of the external FET is required to slow the turn-on speed.
VTH_PFET ´ CGS_PFET
=
TON_PFET
IDIS_PFET
where
•
•
•
TON_PFET is the on time of external FET
VTH_PFET is the gate threshold of external FET
CGS_PFET is the total gate capacitance of connected between gate and source external FET. (including the self-
gate-source capacitance of the FET)
•
IDIS_PFET is the discharge current inside of TPS61178x, it is 55 µA typically
(33)
Given 1.5 V threshold, CGS_PFET is 10 nF, the TON_PFET is around 300 µs.Please be aware that the maximum turn-
on time should not exceed 3 ms, and the maximum capacitance CGS_PFET should be < 100 nF. Otherwise, the
TPS61178x could not startup normally if the disconnect FET could not be turn on within the 3 ms.
The gate resistor depends on the gate-source voltage of the external FET,
VGATE = RGATE ´ IDIS_PFET
(34)
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www.ti.com.cn
VGATE
=
RGATE
IDIS_PFET
(35)
Given the 5-V VGATE, the RGATE = 100 kΩ
9.2.4.4.4 Selecting the Bootstrap Capacitor
The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET
device gate during each cycle’s turn-on and also supplies charge for the bootstrap capacitor. The recommended
value of the bootstrap capacitor is 0.1 µF to 1 µF. CBST should be a good quality, low ESR, ceramic capacitor
located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance.
A value of 0.1 µF was selected for this design example.
9.2.4.4.5 VCC Capacitor
The primary purpose of the VCC capacitor is to supply the peak transient currents of the driver and bootstrap
capacitor as well as provide stability for the VCC regulator. The value of CVCC should be at least 10 times greater
than the value of CBST, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed close
to the pins of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value
of 4.7 µF was selected for this design example.
9.2.5 TPS61178 Application Waveform
Typical condition VIN = 6 V to 14 V, VOUT = 16 V, RLIMIT = 51.1 kΩ, RFREQ = 348 kΩ
Application waveforms are measured with the inductor 3.3 µH, Würth 74437368033, and the output capacitance:
3 x 22 µF, GRM32ER61E226KE15L plus 2 x 10 µF, GRM188R61E106MA73D.
VOUT2_AC
CH1: VOUT2_AC
50 mV / div
10 mV / div
CH3: SW
CH3: SW
7 V / Div
7 V / Div
CH4: IL
1 A / Div
CH4: IL
2 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
Auto PFM
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Load = 10 mA
COUT= 86 µF
Load = 1000 mA
图 27. Steady-state 10 mA
图 26. Steady State 1000 mA
26
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TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
CH3: EN
2 V / div
CH3: EN
2 V / div
CH1: VOUT2
CH1: VOUT2
5 V / div
5 V / div
CH4: IL
1 A / Div
CH4: IL
1 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
Auto PFM
VIN = 7.2 V
VOUT= 16 V
Auto PFM
COUT= 86 µF
Load = 32 Ω
L = 3.3 µH
COUT= 86 µF
Load = 32 Ω
图 29. Shutdown by EN
图 28. Startup by EN
CH1: VOUT2
8 V / div
CH2: VOUT
(before dis FET)
5 V / Div
CH1: VOUT2_AC
500 mV / div
CH4: Load
1 A / Div
M1: VGS
5 V / Div
CH4: IL
6 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
Load = 500 mA to 2 A,
0.1 A/µs slew rate
COUT= 86 µF
COUT= 86 µF
图 31. Output Short (with Disconnect FET)
图 30. Load Transient
CH1: VOUT2
8 V / div
CH2: VOUT
(before dis FET)
5 V / Div
M1: VGS
5 V / Div
CH4: IL
900 mA / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
图 32. Output Short Release (with Disconnect FET)
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ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
www.ti.com.cn
9.3 System Examples
9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
The 图 33 is the typical application schematic for 2.7-V to 4.4-V input (single cell Li+ battery) to output 14-V
output converter. The inductor can be lower to 1.8 µH for the 14-V output.
L
VIN
1.8 uH
CIN1
22 uF
VIN
BST
VCC
CBST
CVCC
0.1 uH
SW
4.7 uF
VOUT2
M1
VOUT
EN
RGATE CGATE
150 kΩ 22 nF
COUT1_2
10 uF
COUT1_1
10 uF
RUP
860 kΩ
COUT2_1 COUT2_2 COUT2_3
FREQ /
SYNC
22 uF
22 uF
22 uF
RFreq
DISDRV
348 kΩ
RDOWN
80.6 kΩ
FB
ILIMIT
AGND
RLIMIT
COMP
51.1 kΩ
PGND
Cc
6.8 nF
Cp
RC
10 pF
15.0 kΩ
Copyright © 2017, Texas Instruments Incorporated
图 33. 14-V Output Voltage from 2.7-V to 4.4-V Input Voltage
9.3.2 TPS61178 Without Load Disconnect Function
The 图 34 is the typical application schematic is for 6-V to 14-V input (2 / 3 cells Li+ battery or 12-V bus) to
output 14-V output converter without load disconnect. With removing the load disconnect FET, it simplifies the
design and minimizes the external components.
L
3.3 ꢀH
VIN
CIN1
22 ꢀF
VIN
BST
VCC
CBST
0.1 ꢀH
CVCC
4.7 ꢀF
SW
VOUT
VOUT
EN
COUT1_1
10 ꢀF
COUT2_1
COUT2_2
COUT2_3
22 ꢀF
RUP
1 MΩ
22 ꢀF
22 ꢀF
FREQ / SYNC
RFREQ
DISDRV
348 kΩ
RDOWN
80.6 kΩ
FB
ILIMIT
AGND
RLIMIT
51.1 kΩ
COMP
PGND
Cc
6.8 nF
Cp
10 pF
RC
15.0 kΩ
Copyright © 2017, Texas Instruments Incorporated
图 34. 16-V Output Voltage Without Load Disconnect Function
28
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TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
System Examples (接下页)
9.3.3 TPS611781 External Clock Synchronization
The 图 35 is the typical application schematic for synchronized by an external clock of 2.2 MHz. It is for the
Forced PWM mode operation to avoid the noise-sensitive frequency range, for instance the audible noise and
AM band.
L
1.8 uH
VIN
CIN1
22 uF
VIN
BST
VCC
CBST
0.1 uH
CVCC
SW
VOUT
VOUT
EN
COUT1_1
10 uF
RUP
COUT2_1
22 uF
COUT2_2
22 uF
FREQ /
SYNC
1 MΩ
2.2 MHz
DISDRV
RDOWN
80.6 kΩ
FB
ILIMIT
RLIMIT
51.1 kΩ
COMP
AGND
PGND
Cc
5.6 nF
RC
13 kΩ
Copyright © 2017, Texas Instruments Incorporated
图 35. 16-V Output Voltage Synchronized by 2.2 MHz External Clock
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply ranging from 2.7 V to 20 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS61178x, the bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 47 µF is a typical choice.
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TPS61178
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www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not
carefully done, the regulator could suffer from the instability or noise problems.
The checklist below is suggested that be followed to get good performance for a well-designed board:
1. Minimize the high current path including the switch FET, rectifier FET, and the output capacitor. This loop
contains high di/dt switching currents ( nano seconds per ampere ) and easy to transduce the high frequency
noise;
2. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under
the switching regulator to minimize inter plane coupling;
3. Use a combination of bulk capacitors and smaller ceramic capacitors with low series resistance for the input
and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for
decoupling the noise;
4. The ground area near the IC must provide adequate heat dissipating area. Connect the wide power bus
(e.g., VOUT, SW, GND ) to the large area of copper, or to the bottom or internal layer ground plane, using vias
for enhanced thermal dissipation;
5. Place the input capacitor being close to the VIN pin and the PGND pin in order to reduce the input supply
ripple;
6. Place the noise sensitive network like the feedback and compensation being far away from the SW trace;
7. Use a separate ground trace to connect the feedback, compensation, frequency set, and the current limit set
circuitry. Connect this ground trace to the main power ground at a single point to minimize circulating
currents.
11.2 Layout Example
REN
CVCC
CBST
VIN
RGATE CGATE
VCC DISDRV
BST VIN EN
VOUT2
VOUT
s
s
G
D
VOUT
SW
COUT2
COUT1
L
s
s
D
D
PGND
P-FET
GND
FREQ/
SYNC
ILIMIT
FB
AGND
COMP
RUP
RCOMP RDOWN
CCOMP
RFREQ
RLIMIT
图 36. Recommended Layout
30
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TPS61178
www.ti.com.cn
ZHCSG87E –FEBRUARY 2017–REVISED AUGUST 2019
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.1.2 开发支持
12.1.2.1 使用 WEBENCH® 工具创建定制设计
请单击此处，使用 TPS61178 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
《TPS61178EVM 评估板用户指南》，SLVUB05
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPS61178
TPS611781
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
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12.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 商标
NexFET, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS611781RNWR
TPS611781RNWT
TPS61178RNWR
TPS61178RNWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNW
RNW
RNW
RNW
13
13
13
13
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
1CDI
1CDI
15RI
15RI
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS611781RNWR
TPS611781RNWT
TPS61178RNWR
TPS61178RNWT
VQFN-
HR
RNW
RNW
RNW
RNW
13
13
13
13
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.8
3.8
3.8
3.8
1.2
1.2
1.2
1.2
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS611781RNWR
TPS611781RNWT
TPS61178RNWR
TPS61178RNWT
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNW
RNW
RNW
RNW
13
13
13
13
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNW0013A
VSON - 1 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.55
3.45
A
B
PIN 1 INDEX AREA
3.05
2.95
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
TYP
2X 0.55
0.3
0.2
3X
(0.2) TYP
8
6
5
9
2X
2
SYMM
1
13
8X 0.5
0.3
10X
0.2
0.1
0.05
SYMM
C A B
C
PIN 1 ID
0.55
0.45
0.55
0.45
9X
4222804/C 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RNW0013A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.55)
3X (0.25)
10X (0.7)
1
13
10X (0.25)
SYMM
3X
(3.4)
8X (0.5)
(R0.05) TYP
9
5
6
8
SYMM
(3.2)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
PADS 1-5 & 9-13
SOLDER MASK
DEFINED
PADS 6-8
SOLDER MASK DETAILS
4222804/C 11/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RNW0013A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
9X (0.25)
10X (0.7)
9X (1)
13
1
10X (0.25)
SYMM
8X (0.5)
(1.2) TYP
9
(R0.05) TYP
5
EXPOSED METAL
TYP
SOLDER MASK
EDGE
TYP
6
8
METAL UNDER
SOLDER MASK
TYP
(0.55) TYP
(3.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PADS 6-8
87% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222804/C 11/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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TPS61181
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TPS61181A
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TPS61181ARTE
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TPS61181ARTER
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TPS61181ARTET
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