TPS61252DSGT [TI]
电流精度为 ±20%、具备可调节输入电流限制的 3.5MHz、1.5A、效率为 92% 的升压转换器 | DSG | 8;
| 型号： | TPS61252DSGT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 电流精度为 ±20%、具备可调节输入电流限制的 3.5MHz、1.5A、效率为 92% 的升压转换器 | DSG | 8 升压转换器 PC 开关 光电二极管 |
| 文件： | 总28页 (文件大小：2082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61252
SLVSAG3A –SEPTEMBER 2010–REVISED DECEMBER 2014
TPS61252 Tiny 1.5-A Boost Converter With Adjustable Input Current Limit
1 Features
3 Description
The TPS61252 device provides a power supply
solution for products powered by either a three-cell
alkaline, NiCd or NiMH battery, or an one-cell Li-Ion
or Li-polymer battery. The wide input voltage range is
ideal to power portable applications like mobile
phones or computer peripherals. The device has a
resistor programmable (RILIM) input current limit and
is suitable for a wide variety of applications.
1
•
Resistor Programmable Input Current Limit
–
±20% Current Accuracy at 500 mA over Full
Temperature Range
–
Programmable from 100 mA up to 1500 mA
•
•
•
Up to 92% Efficiency
VIN Range from 2.3 V to 6.0 V
Power Good Indicates Appropriate Output Voltage
Level
During light loads, the device automatically enters
skip mode (PFM), which allows the converter to
maintain the required output voltage, while only
drawing 30 μA quiescent current from the battery.
This allows maximum efficiency at lowest quiescent
currents.
•
•
•
•
•
•
Adjustable Output Voltage up to 6.5 V
100% Duty-Cycle Mode When VIN > VOUT
Load Disconnect and Reverse Current Protection
Short Circuit Protection
TPS61252 allows the use of small inductors and
capacitors to achieve a small solution size. The
possibility to reduce the current limit by a external
resistor offers the potential use of physically even
smaller inductors with lower rated currents to further
reduce total solution sizes of the power supply.
During shutdown, the load is completely disconnected
from the battery. The TPS61252 is available in a 8-
pin WSON package measuring 2 mm × 2 mm (DSG).
Typical Operating Frequency 3.25 MHz
Available in a 2-mm × 2-mm WSON-8 Package
2 Applications
•
•
•
•
•
USB Host Supplies from a Single Li-Ion Battery
Current Limited Applications
Li-Ion Applications
Audio Applications
Device Information(1)
RF-PA Buffer
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS61252
WSON (8)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Schematic
TPS61252
L1
VOUT
SW
VOUT
FB
1 μH
5.0 V
R1
768 kΩ
CFF
100 pF
VIN
VIN
EN
COUT
22 µF
2.3 V to 6.0 V
C1
10 µF
R4
1 MΩ
R2
243 kΩ
ILIM
RILIM
20 kΩ
Power Good
Output
GND
PG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61252
SLVSAG3A –SEPTEMBER 2010–REVISED DECEMBER 2014
www.ti.com
Table of Contents
10.2 Functional Block Diagram ....................................... 8
10.3 Feature Description................................................. 9
10.4 Device Functional Modes...................................... 11
11 Application and Implementation........................ 12
11.1 Application Information.......................................... 12
11.2 Typical Application ............................................... 12
12 Power Supply Recommendations ..................... 17
13 Layout................................................................... 17
13.1 Layout Guidelines ................................................. 17
13.2 Layout Example .................................................... 17
13.3 Thermal Considerations........................................ 18
14 Device and Documentation Support ................. 19
14.1 Device Support...................................................... 19
14.2 Trademarks........................................................... 19
14.3 Electrostatic Discharge Caution............................ 19
14.4 Glossary................................................................ 19
1
2
3
4
5
6
7
8
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Typical Application Schematic............................. 1
Revision History..................................................... 2
Device Options....................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings.............................................................. 4
8.3 Recommended Operating Conditions....................... 4
8.4 Thermal Information.................................................. 4
8.5 Electrical Characteristics........................................... 5
8.6 Typical Characteristics.............................................. 5
Parameter Measurement Information .................. 7
9
10 Detailed Description ............................................. 8
15 Mechanical, Packaging, and Orderable
10.1 Overview ................................................................. 8
Information ........................................................... 19
5 Revision History
Changes from Original (September 2010) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
2
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SLVSAG3A –SEPTEMBER 2010–REVISED DECEMBER 2014
6 Device Options
TA
OUTPUT VOLTAGE(1)
PACKAGE MARKING
PACKAGE
PART NUMBER(2)
–40°C to 85°C
Adjustable
QTI
8-Pin SON
TPS61252DSG
(1) Contact TI for other fixed output voltage options
(2) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information.
7 Pin Configuration and Functions
DSG Package
8 Pins
Top View
GND
VOUT
FB
1
2
3
4
8
7
6
5
VIN
SW
EN
ILIM
PG
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
6
I
I
Enable input. (1 enabled, 0 disabled). This pin must not be left floating and must be terminated
FB
3
Voltage feedback pin
Ground
GND
ILIM
1
4
I
Adjustable input valley current limit. A resistor to ground programs the current limit. Can be
connected to VIN for maximum current.
PG
5
7
O
I
Output power good (1 good, 0 failure; open drain).If unused, connect to ground or leave floating
SW
Connection for Inductor
VIN
8
I
Supply voltage for control stage
Boost converter output
VOUT
Exposed
Thermal Pad
2
O
—
—
Must be soldered to achieve appropriate power dissipation and for mechanical reasons. Must be
connected to GND.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–40
–65
MAX
7
UNIT
Voltage(2)
VIN, VOUT, SW, EN, PG, FB, ILIM
Operating junction, TJ
Storage, Tstg
V
150
150
Temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
8.3 Recommended Operating Conditions
MIN
2.3
NOM
MAX
6.0
UNIT
V
Supply voltage at VIN
Output voltage at VOUT
3.0
6.5
V
Programmable valley switch current limit set by RILIM
Operating free air temperature range, TA
Operating junction temperature range, TJ
100
–40
–40
1500
85
mA
°C
125
°C
8.4 Thermal Information
TPS61252
THERMAL METRIC(1)
DSG
8 PINS
80.2
93.5
54.2
0.9
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
59.3
20
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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8.5 Electrical Characteristics
Over recommended free air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6 V, VOUT = 5.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-DC STAGE
VIN
Input voltage
Feedback voltage
2.3
6
V
V
VFB
1.182
1.2 1.218
0.5%
Lline regulation
Load regulation
0.5%
f
Oscillator frequency
3250
kHz
mΩ
mΩ
µA
High side switch on resistance
Low side switch on resistance
Reverse leakage current into VOUT
200
130
rDS(on)
EN = GND
3.5
+20%
3.5
ILIM pin set to VIN
1500
mA
ILIM
Programmable valley switch current limit
RILIM = 20 kΩ (500mA)
IOUT = 0 mA, device not switching
-20%
IQ
Quiescent current
Shutdown current
30
0.85
6.4
µA
μA
V
ISD
Falling
Rising
OVP
Input over voltage protection threshold
6.5
V
CONTROL STAGE
Falling
2.0
0.1
2.1
0.4
0.5
V
V
VUVLO Under voltage lockout threshold
Hysteresis
VIL
VIH
EN input low voltage
2.3 V ≤ VIN ≤ 6.0 V
2.3 V ≤ VIN ≤ 6.0 V
Clamped to GND or VIN
V
EN input high voltage
1.0
V
EN, PG input leakage current
µA
Rising (% VOUT
)
92.5%
87.5%
95% 97.5%
Power Good threshold voltage
Falling (% VOUT
)
90% 92.5%
Power good delay
10
140
20
µs
°C
°C
Overtemperature protection
Overtemperature hysteresis
Rising
8.6 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Efficiency
vs Output current (VOUT = 5.0 V, ILIM = 1.5 A)
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
vs Output current in 100% Duty-Cycle Mode (VOUT = 5.0 V, ILIM = 1.5 A)
vs Input voltage (VOUT = 5.0 V, ILoad = {10; 100; 1000 mA}) , ILIM = 1.5 A
vs Input voltage (VOUT = 5.0 V)
Maximum output current
Output voltage
vs Output current (VOUT = 5.0V, ILIM = 1.5 A)
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100
90
80
70
60
50
40
30
20
100
V = 4.2 V
V = 3.6 V
I
I
V = 5.5 V
I
90
80
70
60
50
40
30
20
10
V = 6 V
I
V = 2.3 V
I
V = 2.7 V
I
V = 3.3 V
I
V
I
= 5 V,
V
I
= 5 V,
O
O
10
0
= max
= max
lim
lim
0
0.0001
0.001
0.01
- Output Current - A
0.1
1
0.001
0.01
I
O
0.1
- Output Current - A
1
I
O
Figure 1. Efficiency vs Output Current
Figure 2. Efficiency vs Output Current
In 100% Duty Cycle Mode
100
90
1.7
1.6
1.5
I
= 1000 mA
O
I
(I_Lim = 1.5 A)
O
I
(I_Lim = 1 A)
O
1.4
1.3
1.2
1.1
1
80
I
= 10 mA
O
I
= 100 mA
O
70
60
50
40
30
20
0.9
0.8
0.7
0.6
0.5
0.4
0.3
I
(I_Lim = 0.5 A)
O
I
(I_Lim = 0.2 A)
O
I
(I_Lim = 0.1 A)
O
V
I
= 5 V,
O
0.2
0.1
0
10
0
= max
lim
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9
2.3
2.8
3.3
3.8
4.3
V - Input Voltage - V
4.8
5.3
5.8
V - Input Voltage - V
I
I
Figure 3. Efficiency vs Input Voltage
Figure 4. Maximum Output Current vs Input Voltage
5.1
5.075
5.05
5.025
5
V = 2.3 V
I
V = 2.7 V
I
4.975
4.95
4.925
V = 4.2 V
I
V = 3.6 V
I
V = 3.3 V
I
4.9
0.00001 0.0001
0.001
0.01
0.1
1
I
- Output Current - A
O
Figure 5. Output Voltage vs Output Current
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9 Parameter Measurement Information
U1
L1
VOUT
SW
VOUT
VIN
R1
R2
C2
VIN
EN
C3
FB
C1
R4
ILIM
R3
Power Good
Output
GND
PG
Figure 6. Parameter Measurement Schematic
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10 Detailed Description
10.1 Overview
The TPS61252 device provides a power supply solution for products powered by either a three-cell alkaline,
NiCd or NiMH battery, or an one-cell Li-Ion or Li-polymer battery. It has a resistor programmable (RILIM) input
current limit. During light loads the device will automatically enter skip mode (PFM). During shutdown, the load is
completely disconnected from the battery.
10.2 Functional Block Diagram
SW
VOUT
PMOS
NMOS
VIN
Current
Sense
PWM
Pulse
Modulator
FB
Softstart
VFB
Thermal
Shutdown
Control
Logic
EN
Undervoltage
Lockout
PG
VREF
Averaging
Circuit
IAVE
Error Amp.
Current
Sense
gm
VREF
1V
ILIM
GND
8
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10.3 Feature Description
10.3.1 Operation
The TPS61252 boost converter operates as a quasi-constant frequency adaptive on-time controller. In a typical
application, the frequency is 3.25 MHz and is defined by the input to output voltage ratio and does not vary from
moderate to heavy load currents. At light load currents, the converter automatically enters Power Save Mode and
operates in PFM (Pulse Frequency Modulation) mode. During pulse-width-modulation (PWM) operation, the
converter uses a unique fast response quasi-constant on-time valley current mode controller scheme which
offers very good line and load regulation allowing the use of small ceramic input and output capacitors.
Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching
cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined
by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on
and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by
setting the on-timer again and activating the low-side N-MOS switch.
The TPS61252 controls the input current through an intelligent adjustment of a valley current limit that corrects
the value in a way that it almost turns out as an average input current limit. The current can be adjusted with an
accuracy of ±20%.
This architecture with adaptive slope compensation provides excellent transient load response and requires
minimal output filtering. Internal softstart and loop compensation simplifies the design process, while minimizing
the number of external components.
10.3.2 Current Limit Operation
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time, through sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced when the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by
Equation 1.
1
IOUT(CL) = (1- D) g (ILIM
+
DIL )
2
(1)
The duty cycle (D) can be estimated by Equation 2:
g h
D = 1-
V
IN
VOUT
(2)
(3)
and the peak-to-peak current ripple (ΔIL) is calculated by Equation 3:
V g D
DIL =
IN
Lg f
The output current, IOUT(LIM), is the average of the rectifier current waveform. When the load current is increased
such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to
decrease to this threshold before the next on-time begins. When the current limit is reached, the output voltage
decreases if the load is further increased.
10.3.3 Softstart
The TPS61252 has an internal softstart circuit that controls the ramp-up of the current during start-up and
prevents the converter from inrush current that exceeds the set current limit. The current is ramped to the set
current limit in typical 100 µs . After reaching the current limit threshold, it stays there until VIN = VOUT then the
converter starts switching and boosting up the voltage to its nominal output voltage. During the complete start-up,
the input current does not exceed the current limit that is set by resistor RILIM
.
10.3.4 Enable
The device is enabled by setting the EN pin to a voltage above 1 V. At first, the internal reference is activated
and the internal analog circuits are settled. After typically 50 µs, the output voltage ramps up, controlled by the
softstart circuitry. The output voltage reaches its nominal value as fast as the current limit settings and the load
condition allows it.
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Feature Description (continued)
The EN input can be used to control power sequencing in a system with several DC-DC converters. The EN pin
can be connected to the output of another converter, to drive the EN pin high and get a sequencing of supply
rails. With EN = GND, the device enters shutdown mode. Do not leave the enable pin floating.
10.3.5 Under-Voltage Lockout (UVLO)
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation again once the rising VIN trips the
VUVLO threshold plus its hysteresis of typically 100 mV.
10.3.6 Power Good
The device has a built in power good function to indicate whether the output voltage operates within appropriate
levels. The PG pin is an open drain output, requiring a pull-up resistor. If the PG pin is not used, it may be left
floating or connected to GND. The power good output (PG) is set floating after the FB pin voltage reaches 95%
of its nominal value and stays there until the feedback voltage falls below 90 % of the nominal value. The power
good is operable as long as the converter is enabled and VIN is present. If the converter is disabled by pulling the
EN pin low the PG open drain output is high impedance. That means it follows the voltage it is connected to via
the pull-up resistor. If the converter is controlled by an external enable signal and the power good should indicate
that the output is turned off the application circuit below should be used. In the following circuit, the EN pin
voltage provides the high level for the PG pin pull-up resistor R4.
U1
L1
VOUT
SW
VOUT
1 μH
3.0 V to 6.5 V
VIN
R1
768 kΩ
CFF
100 pF
VIN
EN
COUT
22 µF
2.3 V to 6.0 V
C1
10 µF
FB
R2
243 kΩ
ILIM
RILIM
20 kΩ
Power Good
Output
GND
PG
Enable
Logic Input
R4 1 MΩ
Figure 7. Power Good Schematic
10.3.7 Input Over Voltage Protection
This converter has input over voltage protection that protects the device from damage due to a voltage higher
than the absolute maximum rating on the VIN pin. If 6.5 V (typical) at the input is exceeded, the converter
completely shuts down to protect its inner circuitry. If the input voltage drops below 6.4 V (typical), it turns on the
device again and enters normal start up.
10.3.8 Load Disconnect and Reverse Current Protection
Regular boost converters do not disconnect the load from the input supply and therefore a connected battery is
discharged during shutdown. The advantage of the TPS61252 is that this converter disconnects the output from
the input of the power supply when it is disabled. In case of a connected battery, it prevents it from being
discharged during shutdown of the converter. Furthermore, the output is not allowed to pass current to the input
(battery).
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Feature Description (continued)
10.3.9 Thermal Regulation
The TPS61252 contains a thermal regulation loop that monitors the die temperature. If the die temperature rises
to values above 110 °C, the device automatically reduces the current limit to prevent the die temperature from
further increasing. Once the die temperature drops about 10 °C below the threshold, the device automatically
increases the current to the set value. This function also reduces the current during a short-circuit-condition.
10.3.10 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typical), the device enters thermal shutdown. In this
mode, the High Side and Low Side MOSFETs are turned-off. When the junction temperature falls about 20 °C
below the thermal shutdown, the device resumes operation.
10.4 Device Functional Modes
10.4.1 Power Save Mode
The TPS61252 integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode again once the output voltage exceeds the set
threshold voltage. During the power save operation when the output voltage is above the set threshold, the
converter turns off some of the inner circuits to save energy.
Figure 8. Power Save Mode
The PFM mode is left and PWM mode entered, in case the output current can no longer be supported in PFM
mode.
10.4.2 100% Duty-Cycle Mode
If VIN > VOUT, the TPS61252 offers the lowest possible input-to-output voltage difference while still maintaining
current limit operation with the use of the 100% duty-cycle mode. In this mode, the high-side switch is constantly
turned on. During this operation, the output voltage follows the input voltage and will not fall below the
programmed value if the input voltage decreases below VOUT. The output voltage drop during 100% mode
depends on the load current and input voltage, and is calculated as:
VOUT = V - DCR + r
(
g I
OUT
)
IN
DS(on)
where
•
•
DCR is the DC resistance of the inductor
rDS(on) is the typical on-resistance of the high-side switch
(4)
If the load current exceeds the set current limit, the resistance of the high-side switch increases to limit the
current and the output voltage drops.
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The TPS61252 device provides a power supply solution for products powered by either a three-cell alkaline,
NiCd or NiMH battery, or an one-cell Li-Ion or Li-polymer battery. The wide input voltage range is ideal to power
portable applications like mobile phones or for computer peripherals. TPS61252 allows the use of small inductors
and input capacitors to achieve a small solution size. The possibility to reduce the current limit by a external
resistor offers the potential use of physically even smaller inductors with lower rated current to further reduce
total solution sizes of the power supply.
11.2 Typical Application
Typical application for 5-V output voltage with input current limit.
TPS61252
L1
VOUT
SW
VOUT
FB
1 μH
5.0 V
R1
768 kΩ
CFF
100 pF
VIN
VIN
EN
COUT
22 µF
2.3 V to 6.0 V
C1
10 µF
R4
1 MΩ
R2
243 kΩ
ILIM
RILIM
20 kΩ
Power Good
Output
GND
PG
Figure 9. Typical Application Circuit for 5-V Output Voltage
11.2.1 Design Requirements
In this example, use the TPS61252 to design a 5-V output power supply supporting customer required input
current limit, input voltage range and output driving capability. Below specific example will be used to define and
work with the different equations.
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Table 2. Design Parameters
PARAMETER
Input Voltage
VALUE
3.6
UNIT
V
VIN
VIN(min)
VOUT
ILIM
VFB
f
Minimum Input Voltage
Output Voltage
2.6
V
5.0
V
Input Current Limit set by RILIM
Feedback Voltage
1000
1.2
mA
V
Switching Frequency
Estimated Efficiency
Inductor Value of Choice
3.25
90
MHz
%
η
L1
1.0
µH
11.2.2 Detailed Design Procedure
Table 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
U1
L1
TPS61252
Texas Instruments
1.0 μH, 2.1 A, 27 mΩ, 2.8 mm x 2.8
DEM2815C, TOKO
mm x 1.5 mm
C1
C2
1 x 4.7 μF, 10 V, 0805, X7R ceramic GRM21BR71A475KA73, Murata
1 x 100 pF, 50 V, 0603, COG
ceramic
GRM1885C1H101JA01B, Murata
C3
R1
R2
R3
R4
2 × 22 μF, 10 V, 0805, X7R ceramic
GRM21BR61A226ME51, Murata
Depending on the output voltage of TPS61252, 1%, (all measurements with 5 V output voltage uses 768 kΩ)
Depending on the output voltage of TPS61252, 1%, (all measurements with 5 V output voltage uses 243 kΩ)
Depending on the input current limit of TPS61252, 1%
1 MΩ, 1%
any
11.2.2.1 Output Voltage Setting
The output voltage is calculated by Equation 5:
æ
ö
÷
ø
R1
R2
VOUT = VFB g 1+
ç
è
(5)
To minimize the current through the feedback divider network, R2 should be between 180 kΩ and 360 kΩ. The
sum of R1 and R2 should not exceed ~1 MΩ, to keep the network robust against noise. For the example, R1 is
768 kΩ and R2 is 243 kΩ.
An external feed forward capacitor C1 is required for optimum load transient response. The value of C1 should
be 100 pF. The connection from the FB pin to the resistor divider should be kept short and away from noise
sources, such as the inductor or the SW line.
11.2.2.2 Input Current Limit
The input current limit is set by selecting the correct external resistor value. Equation 6 is a guideline for selecting
the correct resistor value:
1.0V
RILIM
=
g 10,000
ILIM
(6)
For a current limit of 1 A, the resistor value is 10 kΩ.
To allow maximum current limit the ILIM pin can be directly connected to VIN.
11.2.2.3 Maximum Output Current
The maximum output current is set by RILIM and the input to output voltage ratio and can be calculated by
Equation 7:
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V
g
g h
IN
IOUT(max) » ILIM
VOUT
(7)
Following the example IOUT(max) is 648 mA at 3.6 V input voltage and decreases, with lower input voltage values.
11.2.2.4 Inductor Selection
As for all switching power supplies two main passive components are required for storing the energy during
operation: an inductor and an output capacitor. The inductor must be connected between the VIN pin and SW pin
to make sure that the TPS61252 device operates. To select the right inductor current rating, the programmed
input current limit as well as the current ripple through the inductor should be calculated. An estimation of the
maximum peak inductor current can be done using Equation 8.
V
IN(min) g D
V
g h
IN(min)
IL(max) = ILIM + DIL = ILIM
+
with D = 1-
Lg f
VOUT
(8)
Regarding the above example the current ripple (ΔIL) is 426 mA and therefore an inductor with a rated current of
about 1.5 A should be used.
The TPS61252 is designed to work with inductor values between 1.0 µH and 2.2 µH. For typical applications, a
1.5 µH inductor is recommended. In space constrained applications, it might be possible to consider smaller
inductor values depending on the targeted inductor ripple current. Therefore the inductor value can be reduced
down to 1.0 µH without degrading the stability.
In regular boost converter designs the current through the inductor is defined by the fixed switch current limit of
the converter's switches and therefore bigger inductors have to be chosen. The TPS61252 allows the design
engineer to reduce the current limit to the needs of the application regardless the maximum switch current limit of
the converter. Programming a lower current value allows the use of smaller inductors without the danger of
saturation.
11.2.2.5 Output Capacitor
For the output capacitor, it is recommended to use small X5R or X7R ceramic capacitors placed as close as
possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large
capacitors which cannot be placed close to the IC, a smaller ceramic capacitor in parallel to the large one is
required. This small capacitor should be placed as close as possible to the converter's VOUT and GND pins.
To maintain control loop stability of the boost converter, a minimum effective output capacitance of at least 8 µF
is recommended. That means due to DC Bias effect (see NOTE) a 22 µF capacitor with 0805 case size and a
voltage rating of 10 V is necessary. In height restricted application two 10 µF capacitors with 0603 case size and
6.3 V voltage rating can also be used.
In addition to the minimum COUT the application might need more capacitance. To get an estimate of the
minimum output capacitance necessary for the application, Equation 9 is used:
IOUT
g
V
- V
(
f g DV g VOUT
)
OUT IN
CMIN
=
(9)
Where ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 9.6 μF is needed regarding the
example. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple
can be calculated using Equation 10:
VESR = IOUT g RESR
(10)
11.2.2.6 Input Capacitor
Multilayer X5R or X7R ceramic capacitors are an excellent choice for input decoupling of the step-up converter
as they have extremely low ESR and are available in small form factors. The input capacitors should be located
as close as possible to the device. While a 10μF input capacitor is sufficient for most applications, larger values
may be used to reduce input current ripple. Also, low ESR tantalum capacitors may be used.
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NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which has a
strong influence on the final effective capacitance. Therefore the right capacitor value has
to be chosen very carefully. Package size and voltage rating in combination with dielectric
material are responsible for differences between the rated capacitor value and the
effective capacitance. A 10 V rated 0805 capacitor with 10 µF can have a effective
capacitance of less than 5 µF at an output voltage of 5 V.
11.2.2.7 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switch node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As the next step in the evaluation of the regulation loop, the load transient response is tested. During the time
between when the load transient takes place and the turn on of the high side switch, the output capacitor must
supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR,
where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT, generating a
feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily
interpreted when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 60° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET rDS(on)
)
that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load
current range, and temperature range.
11.2.3 Application Curves
FIGURE
Load transient response (VIN = 3.6 V, VOUT = 5.0V, ILIM = 500mA, Load change from 20 mA to 300 mA)
Figure 10
Load transient response (VIN = 3.6 V, VOUT = 5.0V, VIN > VOUT, ILIM = 1000mA, Load change from 50 mA to
550 mA)
Figure 11
Startup after enable (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 500mA)
Startup after enable (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 1000mA)
Startup after enable in 500 mA load (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 1000mA)
Figure 12
Figure 13
Figure 14
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spacing
VIN = 3.6 V, ILIM = 0.5 A
VIN = 3.6 V, ILIM = 1.0 A
VOUT
100mV/div; 4.77V offset
VOUT
100mV/div; 4.77V offset
Output Current
200mA/div
Output Current
500mA/div
Inductor Current
0.5A/div; 1.5A offset
Inductor Current
0.5A/div
Time = 500μs/div
Time = 500μs/div
Figure 10. Load Transient Response ILIM = 500 mA (20 to
300 mA)
Figure 11. Load Transient Response ILIM = 1000 mA (50 to
550 mA)
VIN = 3.6 V, ILIM = 0.5 A
VIN = 3.6 V, ILIM = 1.0 A
VOUT 2.0V/div; -2V offset
VOUT 2.0V/div; -2V offset
Inductor Current
0.5A/div; 0.5A offset
Inductor Current
0.5A/div; 0.5A offset
Voltage @ SW pin
2.0V/div; 8V offset
Voltage @ SW pin
2.0V/div; 8V offset
Time = 100μs/div
Time = 100μs/div
Figure 12. Startup After Enable ILIM = 500mA, No Load
Figure 13. Startup After Enable ILIM = 1000mA, NO Load
VIN = 3.6 V, ILIM = 1.0 A
VOUT 2.0V/div; -2V offset
Inductor Current
0.5A/div; 0.5A offset
Voltage @ SW pin
2.0V/div; 8V offset
Time = 100μs/div
Figure 14. Startup After Enable ILIM = 1000mA, 500 mA Load
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12 Power Supply Recommendations
The power supply can be a three-cell alkaline, NiCd or NiMH battery, or an one-cell Li-Ion or Li-polymer battery.
The input supply should be well regulated with the rating of TPS61252. If the input supply is located more than a
few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic or tantalum capacitor with a value of 47 µF is a typical choice.
13 Layout
13.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed close to the IC to keep the feedback connection short. To lay out the
ground, short and wide traces are recommended. This avoids ground shift problems, which can occur due to
superimposition of power ground current onto the feedback divider. Figure 15 shows the recommended board
layout.
13.2 Layout Example
10mm (0.39in)
GND
VOUT
VIN
CIN
L1
R1
R2
RILIM
CFF
GND
Figure 15. Suggested Layout
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13.3 Thermal Considerations
The implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
Improving the power dissipation capability of the PCB design
–
–
For example, increase of the GND plane on the top layer which is connected to the exposed thermal pad
Use thicker copper layer
•
•
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The maximum junction temperature (TJ) of the TPS61252 is 150°C.
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14 Device and Documentation Support
14.1 Device Support
14.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
14.2 Trademarks
All trademarks are the property of their respective owners.
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61252DSGR
TPS61252DSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
QTI
QTI
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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13-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61252DSGT
WSON
DSG
8
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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13-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DSG
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TPS61252DSGT
8
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
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PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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