TPS61379QWRTERQ1 [TI]

25µA 静态电流同步升压转换器 | RTE | 16 | -40 to 125;


型号：	TPS61379QWRTERQ1
厂家：	TEXAS INSTRUMENTS
描述：	25µA 静态电流同步升压转换器 \| RTE \| 16 \| -40 to 125 升压转换器
文件：	总34页 (文件大小：2439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS61379-Q1

ZHCSNP9B –MARCH 2021 –REVISED OCTOBER 2021

TPS61379-Q1 具有负载断开功能的25µA 静态电流同步升压转换器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准

TPS61379-Q1 是一款完全集成的同步升压转换器，集

成了负载断开功能。输入电压范围从 2.3V 到 14V，最

大输出电压高达 18.5V。开关电流限制典型值为 2A。

它会消耗V_IN25μA 的静态电流。

– 器件温度等级1：-40°C 至125°C 环境工作温度

范围

• 提供功能安全

– 可帮助进行功能安全系统设计的文档

• 灵活的输入和输出工作范围

– 输入电压范围：2.3V 至14V

– 可编程输出电压范围：4.0V 至18.5V

– 5V、5.25V、5.5V 固定输出选项

– 固定2A 峰值电流限制

TPS61379-Q1 采用峰值电流模式控制，可编程开关频

率在 200kHz 到 2.2MHz 之间。在中等到重负载条件

下，该器件在固定频率PWM 模式下运行。在轻负载条

件下，通过配置 MODE 引脚可实现两种可选模式：自

动 PFM 模式和强制 PWM 模式，以便在轻负载条件下

实现效率和抗噪性平衡。可与外部时钟同步开关频率。

TPS61379-Q1 使用内部时钟展频在 FPWM 模式下提

升 EMI 友好性。此外，还有内部软启动时间来限制浪

涌电流。

• 避免AM 频带干扰和串扰

– 动态可编程开关频率：200kHz 至2.2MHz

– 扩频调频

– 可选的时钟同步

TPS61379-Q1 有各种固定输出电压版本，可节省外部

反馈电阻器。它支持外部环路补偿，在更广泛的

V_OUT/V_IN范围内优化稳定性和瞬态响应。它还集成了

稳健的保护特性，包括输出短路保护、输出过压保护和

热关断保护。TPS61379-Q1 采用具有可湿性侧面的

3mm × 3mm 16 引脚QFN 封装。

• 尽量减小解决方案尺寸，用于空间受限型应用

– 集成式LS/HS/ISO FET：R_DS(ON)50mΩ/

50mΩ/100mΩ

– 支持高达2.2MHz，L-C 较小

• 尽量减少轻负载和空闲状态的电流消耗

– VIN 引脚静态电流为25µA

– VIN 引脚关断电流为0.5µA

– 可选择自动PFM 和强制PWM 模式

– 关断期间或出现故障时真正负载断开连接

• 集成型保护特性

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS61379-Q1

VQFN-16

3.0mm × 3.0mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 支持接近VOUT 运行电压的VIN

– 输入欠压锁定和输出过压保护

– 断续输出短路保护

VIN

– 电源正常状态指示器

VCC

– 165°C 的热关断保护限制

• 0.25A 负载条件下进行3.3V 至9V 转换时效率高于

90%

BST

VIN

OUT

TPS61379-Q1

VOUT

FREQ

2 应用

COMP

• 高级驾驶辅助系统(ADAS)

• 汽车信息娱乐系统与仪表组

• 车身电子装置和照明

• 紧急呼叫(eCall)

MODE/SYNC

GND

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSFJ0

TPS61379-Q1

ZHCSNP9B –MARCH 2021 –REVISED OCTOBER 2021

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Table of Contents

8.4 Device Functional Modes..........................................13

9 Application and Implementation..................................15

9.1 Application Information............................................. 15

9.2 Typical Application.................................................... 15

10 Power Supply Recommendations..............................24

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 25

12 Device and Documentation Support..........................26

12.1 Device Support....................................................... 26

12.2 接收文档更新通知................................................... 26

12.3 支持资源..................................................................26

12.4 Trademarks.............................................................26

12.5 术语表..................................................................... 26

12.6 静电放电警告.......................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................5

7.5 Electrical Characteristics ............................................6

7.6 Typical Characteristics................................................8

8 Detailed Description......................................................10

8.1 Overview...................................................................10

8.2 Functional Block Diagrams....................................... 11

8.3 Feature Description...................................................11

Information.................................................................... 26

4 Revision History

Changes from Revision A (June 2021) to Revision B (October 2021)

Page

• Replaced the operating ambient temperature with the operating junction temperature and added table note in

节7.3 ................................................................................................................................................................. 5

• Updated 节8.3.12 ............................................................................................................................................13

• Updated 图9-2 ................................................................................................................................................ 19

Changes from Revision * (March 2021) to Revision A (June 2021)

Page

• Updated resistor from FB to GND values........................................................................................................... 3

• Updated voltage reference specifications...........................................................................................................6

• Updated 节9.2.2.1 ...........................................................................................................................................15

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5 Device Comparison Table

PART NUMBER

OUTPUT VOLTAGE (V)

RESISTOR FROM FB TO GND (R_{FB_LOW}

0Ω≤R_{FB_LOW}≤2.4 kΩ

)

SPREAD SPECTRUM

5.25

3.6kΩ ≤R_{FB_LOW}≤4.8 kΩ

7.2kΩ ≤R_{FB_LOW}≤9.6kΩ

14.4kΩ≤R_{FB_LOW}≤100kΩ

TPS61379-Q1

Enable

5.5

Adjustable

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6 Pin Configuration and Functions

VIN

BST

Exposed

Thermal Pad

OUT

图6-1. 16-Pin WQFN RTE Package (Transparent Top View)

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

VIN

IC power supply input

Power supply for high-side N-MOSFET gate drivers. A capacitor must be connected

between this pin and SW pin.

BST

The switching node pin of the converter. It is connected to the drain of the internal low-side

FET and the source of the high-side FET.

3, 4

PWR

Mode selection pin. MODE = high, forced PWM mode. MODE = low or floating, auto PFM

mode. This pin can also be used to synchronize the external clock. Refer to 表8-1 for

details.

MODE/SYNC

VCC

Output of internal regulator. A ceramic capacitor with more than 1 μF must be connected

between this pin and GND.

GND

7, 8

PWR

Power ground of the IC. It is connected to the source of the low-side FET.

Output of the isolation FET. Connect load to this pin to achieve input/output isolation.

Output of the drain of the HS FET. Connect this pin as the output can disable the load

disconnect/short protection feature (or short this pin with VO pin).

OUT

PWR

Power good indicator, open-drain output

No connection pin

Feedback pin. Use a resistor divider to set the desired output voltage. Refer to 节9.2.2.1 for

details.

Output of the internal transconductance error amplifier. An external RC network is connected

to this pin to optimize the loop stability and response time.

COMP

Enable logic input

Frequency setting pin. Connect a resistor between this pin and GND pin to set the desired

frequency.

FREQ

Thermal Pad

The thermal pad must be connected to power ground plane for good power dissipation.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

MAX

UNIT

Voltage range at terminals ⁽²⁾

VIN

VO, SW, OUT

–0.3

-0.3

BST

SW + 6

MODE/SYNC, FB, FREQ, ILIM, VCC, COMP, EN

(3)

T_J

Operating junction temperature

Storage temperature

150

°C

–40

–65

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to network ground terminal.

(3) High junction temperatures degrade operating lifetime. Operating lifetime is de-rated for junction temperatures greater than 125°C

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽²⁾

Charged-device model (CDM), per AEC Q100-011⁽³⁾

All pins

Corner

pins (1,

4, 5, 8, 9,

12, 13,

and16)

(1)

V_(ESD)

Electrostatic discharge

±750

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary

precautions.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary

precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.3

NOM

MAX

UNIT

V_IN

V_OUT

T_J

Input voltage

Outputvoltage

18.5

150

Operating junction temperature⁽¹⁾

°C

–40

(1) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.4 Thermal Information

TPS61379-Q1

THERMAL METRIC⁽¹⁾

RTE

16 PINS

46.2

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

43.5

18.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.1

18.5

ψ_JB

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7.4 Thermal Information (continued)

TPS61379-Q1

RTE

THERMAL METRIC⁽¹⁾

UNIT

16 PINS

8.8

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

T_J= -40 to 125°C, L = 1 µH, V_IN= 3.3 V and V_OUT= 9 V (VO pin). Typical values are at T_J= 25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_IN

Input voltage range

2.3

2.2

V_INrising

V_INfalling

2.2

2.04

160

2.2

V_{IN_UVLO}

VIN under voltage lockout threshold

V_{IN_HYS}

V_{CC_UVLO}

V_{CC_HYS}

V_CC

VIN UVLO hysteresis

VCC UVLO threshold

VCC UVLO hysteresis

VCC regulation

V_CCrising

V_CChysteresis

150

4.8

I_VCC= 6 mA, V_OUT= 9V

IC enabled, no load,

V_IN= 3.3 V, V_OUT= 18.5 V, V_FB= V_REF

0.1 V

I_Q

Quiescent current into V_INpin

Quiescent current into OUT pin

µA

IC enabled, no load,

V_IN= 3.3 V, V_OUT= 18.5 V, V_FB= V_REF

0.1 V

I_Q

I_SD

Shutdown current into VIN pin

Leakage current into SW

IC disabled, V_IN= 14 V, EN = GND

IC disabled, V_IN= OUT = SW = 14 V

IC disabled, OUT= VO = 5 V, SW = 0

0.6

µA

I_{SW_LKG}

I_{VO_LKG}

Reverse leakage current into VO

OUTPUT VOLTAGE

V_OVP

Output over-voltage protection threshold

V_IN= 3.3 V, V_OUTrising

19.3

20.5

V_{OVP_HYS}

Output over-voltage protection hysteresis V_IN= 3.3 V, OVP threshold

0.5

VOLTAGE REFERENCE

V_REF

Reference Voltage at FB pin

0.788

4.85

5.10

5.35

0.800

5.00

5.25

5.50

0.812

5.15

5.35

5.65

T_J= -40 to 125°C, R_FB= 16.0 kΩ

T_J= -40 to 125°C, R_FB= 2.0 kΩ

T_J= -40 to 125°C, R_FB= 4.0 kΩ

T_J= -40 to 125°C, R_FB= 8.0 kΩ

V_{OUT_5V}

V_{OUT_5.25V}

V_{OUT_5.5V}

I_{FB_LKG}

Leakage current into FB pin

POWER SWITCH

R_DS(on)

Low-side MOSFET on resistance

V_CC= 4.85 V

mΩ

High-side MOSFET on resistance

Isolation MOSFET on resistance

100

CURRENT LIMIT

I_{LIM_SW}Peak switching current limit Auto PFM

I_{LIM_SW}Peak switching current limit FPWM

SWITCHING FREQUENCY

Duty cycle = 65%

1.58

2.25

Fsw

Switching frequency

2050

180

2200

200

2400

230

kHz

R_FREQ= 18 kΩ

R_FREQ= 218 kΩ

R_FREQ= 18 kΩ

Fsw

Switching frequency

Maximum Duty Cycle

Minimal on time

D_max

t_{ON_min}

F_DITHER

F_pattern

10%

0.4%

Fsw

ERROR AMPLIFIER

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7.5 Electrical Characteristics (continued)

T_J= -40 to 125°C, L = 1 µH, V_IN= 3.3 V and V_OUT= 9 V (VO pin). Typical values are at T_J= 25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_SINK

COMP pin sink current

V_FB= V_REF+ 0.2V

I_SOURCE

V_CCLPH

V_CCLPL

G_mEA

COMP pin source current

COMP pin high clamp voltage

COMP pin low clamp voltage

Error amplifier trans conductance

V_FB= V_REF- 0.2V

V_FB= V_REF- 0.2 V, ILIM = 2 A

V_FB= V_REF+ 0.2 V,

V_COMP= 1.0 V

0.6

POWER GOOD

V_{PG_TH}

PG threhold for rising FB voltage

Reference to V_REF

V_PG= 0.4 V

90%

V_{PG_HYS}

PG hysteresis

I_{PG_SINK}

PG pin sink current capability

PG delay time

t_{PG_DELAY}

DOWN MODE

2.5

3.4

4.3

Delay time between EN high and device

working

t_{EN_DELAY}

0.4

t_SS

Softstart time

Hiccup on time

Hiccup off time

2.5

1.8

t_{HCP_ON}

t_{HCP_OFF}

SYNC TIMING

f_{SYNC_MIN}

f_{SYNC_MAX}

200

kHz

2200

EN/SYNC LOGIC

EN, MODE/SYNC pins Logic high

threshold

VI_H

1.2

EN, MODE/SYNC pins Logic Low

threshold

VI_L

0.4

EN, MODE/SYNC pins internal pull down

resistor

R_DOWN

800

kΩ

THERMAL SHUTDOWN

t_{SD_R}Thermal shutdown rising threshold

t_{SD_F}Thermal shutdown falling threshold

TJ rising

TJ falling

165

145

°C

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7.6 Typical Characteristics

V_IN= 3.3 V, V_OUT= 9 V (VO pin), T_A= 25°C, Fsw = 2.2 MHz, unless otherwise noted.

100

Vin = 2.7 V

Vin = 3.3 V

Vin = 5 V

Vin = 2.7 V

Vin = 3.3 V

Vin = 5 V

1E-5 2E-5

0.0001

0.001

0.005

0.02 0.05 0.1 0.2

0.5

1E-5 2E-5

0.0001

0.001

0.005

0.02 0.05 0.1 0.2

0.5

Output Current (A)

VOUT = 9 V

Auto PFM

Fsw = 2.2 MHz

VOUT = 9 V

FPWM

Fsw = 2.2 MHz

图7-1. 9 V_OUTEfficiency vs Output Current

图7-2. 9 V_OUTEfficiency vs Output Current

8.97

8.96

8.95

8.94

8.93

8.92

8.91

8.9

Vin = 2.7 V

Vin = 3.3 V

Vin = 5 V

T_J= -40 °C

T_J= 25 °C

T_J= 125 °C

0.0001

0.0005

0.002 0.005 0.01 0.02

0.05 0.1

0.2 0.3 0.5

2.3

2.6

2.9

3.2

3.5

3.8

4.1

4.4

4.7

Output Current (A)

Input Voltage (V)

D001

VOUT = 9 V

Auto PFM

Fsw = 2.2 MHz

图7-3. 9 V_OUTRegulation vs Output Current

图7-4. Quiescent Current into V_INvs Input Voltage

0.5

0.4

0.3

0.2

0.1

5.7

5.6

5.5

5.4

5.3

5.2

5.1

T_J= -40 °C

T_J= 25 °C

T_J= 125 °C

5V Output (V)

5.238V Output (V)

5.5V Output (V)

4.9

-40

2.3

2.6

2.9

3.2

3.5

3.8

4.1

4.4

4.7

-20

100

120

140

Input Voltage (V)

D002

Temperature (°C)

D014

图7-5. Shutdown Current vs Input Voltage

图7-6. Fixed Output Voltage vs Temperature

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7.6 Typical Characteristics (continued)

0.805

0.804

0.803

0.802

0.801

0.8

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.799

0.798

0.797

0.796

0.795

-40

-20

100

120

140

100

125

150

175

200

225

Temperature (°C)

Resistor (kW)

D003

D005

图7-7. Reference Voltage vs Temperature

图7-8. Switching Frequency vs Setting Resistance

2.3

2.2

2.1

1.2

Rising

Falling

Rising

Falling

1.1

0.9

0.8

0.7

0.6

0.5

0.4

-40

-20

100

120

140

-40

-20

100

120

140

Temperature (°C)

D010

D011

图7-9. V_INUVLO Threshold Voltage vs Temperature

图7-10. EN Threshold Voltage vs Temperature

3.5

150

140

130

120

110

100

Low Side FET (mW)

High Side FET (mW)

Isolation FET (mW)

3.475

3.45

3.425

3.4

-40

-20

100

120

140

-40

-20

100

120

140

Temperature (°C)

D012

D013

图7-11. PG Delay Time vs Temperature

图7-12. R_DSONvs Temperature

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8 Detailed Description

8.1 Overview

The TPS61379-Q1 is a fully integrated synchronous boost converter with load disconnect function. It supports

output voltage up to 18.5 V with a maximum 2-A fixed switching peak current limit. The input voltage ranges from

2.3 V to 14 V while consuming 25-µA quiescent current.

The device utilizes the fixed frequency peak current control scheme, which has an internal oscillator and

supports adjustable switching frequency from 200 kHz to 2.2 MHz.

The device operates with fixed frequency pulse width modulation (PWM) from medium to heavy load. At the

beginning of each switching cycle, the low-side N-MOSFET switch is turned on, and the inductor current ramps

up to a peak current that is determined by the output of the internal error amplifier (EA). Once the switching peak

current triggers the output of the EA, the low-side N-MOSFET is turned off and the high-side N-MOSFET is

turned on after a short dead time. The high-side N-MOSFET switch is not turned off until the next cycle as

determined by the internal oscillator. The low-side switch turns on again after a short dead time and the

switching cycle is repeated.

The TPS61379-Q1 provides either Auto PFM or Forced PWM option for light load operation by configuring the

MODE/SYNC pin. In Forced PWM mode, the switching frequency remains constant across the entire load range,

which helps avoid the frequency variation with load. The internal oscillator can be synchronized to an external

clock applied on the MODE / SYNC pin. Spread spectrum modulation of the frequency in Forced PWM mode

helps optimize the EMI performance for automotive applications. In Auto PFM mode, the switching frequency

can decrease, resulting in higher efficiency.

The device implements a cycle-by-cycle current limit to protect the device from overload during the boost

operation phase. If the output current further increases and triggers the output voltage to fall below the input

voltage, the TPS61379-Q1 enters into hiccup mode short protection.

There is a built-in soft-start time that prevents the inrush current during the start-up. The TPS61379-Q1 also

provides a power good (PG) indicator to enable the power sequence control for start-up.

The TPS61379-Q1 also has a number of protection features including output short protection, output overvoltage

protection (OVP), and thermal shutdown protection (OTP).

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8.2 Functional Block Diagrams

VIN

OUT

BST

VIN

OUT

VCC

VOUT

1/K

Logic

BST

ULVO

LDO

& BIAS

COMP

VUVLO

Fixed

Output

OVP

SCP

ISO

VCC

OTP

Soft

Start

VCC

MODE

COMP

CLIM

Slope Compensation

COMP

Vref

VO Voltage

SELECT

PGOOD

VOVP

COMP

OVP

OTP

1/N

VOUT

Dithering

OSC

SYNC

MODE

FREQ

VOTP

Temp

GND

COMP

MODE/

SYNC

8.3 Feature Description

8.3.1 VCC Power Supply

The internal LDO in the TPS61379-Q1 outputs a regulated voltage of 4.8 V with 10-mA output current capability.

A ceramic capacitor is connected between the VCC pin and GND pin to stabilize the VCC voltage and also

decouple the noise on the VCC pin. The value of this ceramic capacitor must be above 1 µF. A ceramic capacitor

with an X7R or X5R grade dielectric with a voltage rating higher than 10 V is recommended.

8.3.2 Input Undervoltage Lockout (UVLO)

An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below

the UVLO threshold of 2.04 V (typical). A hysteresis of 160 mV (typical) is added so that the device cannot be

enabled again until the input voltage exceeds 2.2 V (typical). This function is implemented to prevent

malfunctioning of the device when the input voltage is between 2.04 V and 2.2 V.

8.3.3 Enable and Soft Start

When the input voltage is above the UVLO threshold and the EN pin is pulled above 1.2 V, the TPS61379-Q1 is

enabled. The TPS61379-Q1 starts to monitor the FB pin. With a typical 400-µs delay time after EN is pulled high,

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the TPS61379-Q1 starts switching. There is an internal built-in start-up time, which is typically 2.5 ms, to limit the

inrush current during start-up.

8.3.4 Shut Down

When the input voltage is below the UVLO threshold or the EN pin is pulled low, the TPS61379-Q1 is in

shutdown mode and all the functions are disabled. The input voltage is isolated from the output to minimize the

leakage currents.

8.3.5 Switching Frequency Setting

The TPS61379-Q1 uses a fixed frequency control scheme. The switching frequency can be programmed

between 200 kHz and 2.2 MHz using a resistor from the FREQ pin to GND. The resistor must be connected

when the oscillator is synchronized by an external clock. The resistance is defined by 方程式1.

41.9

(₅₉(/*V) =

;

4_(4'3GÀ + 1.05

(1)

where

• R_FREQis the resistance between the FREQ pin and the GND pin

For instance, the switching frequency is 2.2 MHz if the resistance between the FREQ pin and GND is 18 kΩ.

This pin cannot be left floating or tied to VCC.

8.3.6 Spread Spectrum Frequency Modulation

The TPS61379-Q1 uses a triangle waveform to spread the switching frequency with ±10% of normal frequency.

The frequency of the triangle waveform is typically 0.4% of the switching frequency. For example, if the normal

switching frequency of TPS61379-Q1 is programmed to 2.2 MHz, the spread spectrum function modulates the

switching frequency in the range of 1.98 MHz to 2.42 MHz in a triangle behavior with 8.8 kHz rate.

The spread spectrum is only available while the clock of the TPS61379-Q1 is free running at its natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

• An external clock is applied to the MODE/SYNC pin.

• The device works in the PFM operation at light load.

8.3.7 Bootstrap

The TPS61379-Q1 has an integrated bootstrap regulator circuit. A small ceramic capacitor is needed between

the BST pin and SW pin to provide the gate drive supply voltage for the high-side switches. The bootstrap

capacitor is charged during the time when the low-side switch is in the ON state. The value of this ceramic

capacitor must be above 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating

higher than 6.3 V is recommended.

8.3.8 Load Disconnect

The TPS61379-Q1 integrates a load disconnect function when the input source is DC, which completely cuts off

the path between the input side and the output side during shutdown.

The output disconnect function also allows the output short protection and minimize the inrush current at start-

up.

8.3.9 MODE/SYNC Configuration

表8-1 summarizes the MODE/SYNC function and the entry condition.

表8-1. MODE/SYNC Configuration

MODE/SYNC PIN CONFIGURATION

Logic Low or Floating

MODE

Auto PFM Mode

Forced PWM Mode

Logic High

External Synchronization

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The TPS61379-Q1 can be synchronized to an external clock applied to the MODE / SYNC pin.

8.3.10 Overvoltage Protection (OVP)

If the output voltage exceeds the OVP threshold (typical 20 V), the TPS61379-Q1 stops switching immediately

until the output voltage drops below the recovery threshold (typical 19.5 V). This function protects the device

against excessive voltage.

8.3.11 Output Short Protection/Hiccup

In addition to the cycle-by-cycle current limit function, the TPS61379-Q1 also has output short protection. If the

output current causes low-side FET to reach current limit and pull the output voltage below the input voltage, the

device enters into short circuit protection mode which triggers the hiccup timer. When the hiccup timer is

triggered, the device limits the current to a relative lower level for 1.8 ms, and then shuts down. After 67 ms, it

restarts. If the short condition disappears, the device automatically restarts.

When FB voltage is below ≤ 0.1 V during fault condition, the current limit threshold is reduced to 1/5 of the

programmed current limit, and frequency is clamped to 1.1 MHz if the FREQ pin setting is greater than 1.1 MHz

and VIN and V_Ovoltage delta is greater than 6 V.

8.3.12 Power-Good Indicator

The TPS61379-Q1 integrates a power-good function. The power-good output consists of an open-drain NMOS,

requiring an external pullup resistor connect to a suitable voltage supply like VCC. The PG pin goes high with a

typical 3.4-ms delay time after VOUT reaches 90% of the target output voltage. When the output voltage drops

below 85% of the target output voltage, the PG pin immediately goes low without delay.

8.3.13 Thermal Shutdown

A thermal shutdown is implemented to prevent damage due to the excessive heat and power dissipation.

Typically, the thermal shutdown occurs at the junction temperature exceeding 165°C. When the thermal

shutdown is triggered, the device stops switching and recovers when the junction temperature falls below 145°C

(typical).

8.4 Device Functional Modes

8.4.1 Forced PWM Mode

The TPS61379-Q1 enters forced PWM mode by pulling the MODE/SYNC pin to logic high for more than five

switching cycles. In forced PWM mode, the TPS61379-Q1 keeps the switching frequency constant at light load

condition. When the load current decreases, the output of the internal error amplifier also decreases to keep the

inductor peak current down. When the output current decreases further, the high-side switch is not turned off

even if the current of the high-side switch goes negative to keep the frequency constant.

8.4.2 Auto PFM Mode

The TPS61379-Q1 enters auto PFM mode by pulling the MODE/SYNC pin to logic low for more than five

switching cycles or leave the pin floating. The TPS61379-Q1 improves the efficiency at light load when operating

in PFM mode. When the output current decreases to a certain level, the output voltage of the error amplifier is

clamped by the internal circuit. If the output current reduces further, the inductor current through the high-side

switch is clamped but not further lowered. Pulses are skipped to improve the efficiency at light load.

8.4.3 External Clock Synchronization

The TPS61379-Q1 supports external clock synchronization with a range of 200 kHz to 2.2 MHz. The TPS61379-

Q1 remains in the forced PWM mode and operates in CCM across the entire load range if the oscillator is

synchronized by an external clock. Spread spectrum feature is disabled when external synchronization is used.

8.4.4 Down Mode

The TPS61379-Q1 features Down mode operation when input voltage is close to or higher than output voltage.

In Down mode, output voltage is regulated at target value even when V_IN> VO. The high-side and low-side FETs

of the TPS61379-Q1 are switching devices that always work in boost operation, where the isolation FET always

works as a linear device.

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For boost circuits, on time or duty cycle is reduced as input voltage approaches output voltage. The TPS61379-

Q1 enters Down mode when V_INreaches 85% (typical) of VO voltage at 2.2 MHz; while exiting Down mode

requires V_INto be reduced below 85% (typical) of VO voltage at 2.2 MHz.

In normal operation, isolation FET is fully on.

When Down mode is triggered and V_INis less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above

VO pin voltage. Isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage drop.

When Down mode is triggered and V_INis 100 mV (typical) higher than VO pin voltage, the OUT pin has an

approximated 3 V (typical) above V_INpin voltage, as V_INkeeps rising, the OUT pin continues to raise with 3 V on

top of V_IN, isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of OUT pin and

VO pin.

Refer to 图8-1.

Vin > Vo

Vin < Vo

Down Mode

Entering

Threshold

Down Mode

Exiting

Threshold

Voltage

OUT

VIN

图8-1. Down Mode

Care should be taken during short-to-ground condition when operation V_INis above 6 V. During hiccup on, the

device operates in Down mode and isolation FET voltage drop is V_IN+ 3 V (OUT pin to VO pin).

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9 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPS61379-Q1 is a 25-µA quiescent current boost converter that supports 2.3-V to 14-V input voltage range.

It also supports load disconnect to minimize the leakage current. The following design procedure can be used to

select component values for the TPS61379-Q1.

9.2 Typical Application

VIN

VCC

OUT

BST

VIN

TPS61379-Q1

VOUT

FREQ

COMP

MODE/SYNC

GND

图9-1. Typical Application

9.2.1 Design Requirements

A typical application example is dual cameras powered through a coax cable, which normally requires 9.0-V

output as its bias voltage and consumes less than 200-mA current per camera. 250-mA load current is designed

to provide margin. The following design procedure can be used to select external component values for the

TPS61379-Q1.

表9-1. Design Requirements

PARAMETERS

Input voltage

VALUES

3.3 V to 6.4 V

9.0 V

Output voltage

Switching frequency

Output current

2.2 MHz

250 mA

Output voltage ripple

± 25 mV

9.2.2 Detailed Design Procedure

9.2.2.1 Programming the Output Voltage

There are two ways to set the output voltage of the TPS61379-Q1: adjustable or fixed. If the resistance between

FB and GND is higher than 14.4kΩ and less than 100kΩ during start-up, the TPS61379-Q1 works as an

adjustable output version. The FB pin is connected to the negative input of the internal error amplifier directly.

The output voltage can be programmed by adjusting the external resistor divider R_Upperand R_Loweraccording to

方程式2. When the output voltage is in well regulation, the typical voltage at the FB pin is V_REFof 0.8 V.

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(4_7LLAN+ 4_.KSAN

)

8₁₇₆= 8_4'(

4_.KSAN

(2)

For some applications where the resistor needs to be as low as possible, the low-side divider can be 20 kΩ. The

reference voltage is 0.8 V, the high-side divider is 205 kΩfor 9-V output voltage.

For other applications without specific requirements on divider resistance, the user can choose R_Lowerto be

approximately 80.6 kΩ. Slightly increasing or decreasing R_Lowercan result in closer output voltage matching

when using standard values resistors.

For the best accuracy, R_Loweris recommended to be smaller than 100 kΩ to ensure that the current following

through R_Loweris at least 100 times larger than FB pin leakage current. Changing R_Lowertowards the lower value

increases the robustness against noise injection. Changing the R_Lowerto higher values reduces the quiescent

current for achieving higher efficiency at light load.

If the resistance between FB and GND is less than 9.6kΩ during start-up, the TPS61379-Q1 works as a fixed

output voltage version. The TPS61379-Q1 uses the internal resistor divider.

For 5-V fixed output voltage, R_Loweris between 0Ωand 2.4kΩand R_Uppershould be removed.

For 5.25-V fixed output voltage, R_Loweris between 3.6kΩand 4.8 kΩand R_Uppershould be removed.

For 5.5-V fixed output voltage, R_Loweris between 7.2kΩand 9.6kΩand R_Uppershould be removed.

9.2.2.2 Setting the Switching Frequency

The switching frequency of the TPS61379-Q1 is set at 2.2 MHz. Use 方程式 1 to calculate the required resistor

value. The calculated value is 18 kΩto get the frequency of 2.2 MHz.

9.2.2.3 Selecting the Inductor

A boost converter normally requires two main passive components for storing the energy during the power

conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency (including the

ripple and efficiency) as well as the transient behavior and loop stability, which makes the inductor the most

critical component in application.

When selecting the inductor, as well as the inductance, the other important parameters are:

• The maximum current rating (RMS and peak current must be considered)

• The series resistance

• Operating temperature

The TPS61379-Q1 has built-in slope compensation to avoid subharmonic oscillation associated with the current

mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 2 A, the

slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make

the peak-to-peak current ripple between 800 mA to 2 A when selecting the inductor.

The inductance can be calculated by 方程式3, 方程式4, and 方程式5:

_IN´ D

DI_L=

L ´ f_SW

(3)

(4)

(5)

V_OUT´ I_OUT

DI_{L _R}= Ripple% ´

h ´ V

Ripple % V_OUT´ I_OUT

V ´ D

L =

ƒ_SW

where

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• Δ_ILis the peak-peak inductor current ripple

• V_INis the input voltage

• D is the duty cycle

• L is the inductor

• ƒ_SWis the switching frequency

• Ripple % is the ripple ration versus the DC current

• V_OUTis the output voltage

• I_OUTis the output current

• ηis the efficiency

The current flowing through the inductor is the inductor ripple current plus the average input current. During

power up, load faults, or transient load conditions, the inductor current can increase above the peak inductor

current calculated.

Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current

approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current

depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated

current, especially the saturation current, is larger than its peak current during the operation.

The inductor peak current varies as a function of the load, the switching frequency, the input and output voltages

and it can be calculated by 方程式6 and 方程式7.

I_PEAK= I

´ DI_L

(6)

where

• I_PEAKis the peak current of the inductor

• I_INis the input average current

• Δ_ILis the ripple current of the inductor

The input DC current is determined by the output voltage, the output current can be calculated by:

V_OUT´ I_OUT

V_IN´ h

(7)

where

• I_INis the input current of the inductor

• V_OUTis the output voltage

• V_INis the input voltage

• ηis the efficiency

While the inductor ripple current depends on the inductance, the frequency, the input voltage, and duty cycle are

calculated by 方程式3. Replace 方程式3 and 方程式7 into 方程式6 and get the inductor peak current:

I_OUT

V_IN´ D

I_PEAK

(1- D) ´ h

L ´ f_SW

(8)

where

• I_PEAKis the peak current of the inductor

• I_OUTis the output current

• D is the duty cycle

• ηis the efficiency

• V_INis the input voltage

• L is the inductor

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• ƒ_SWis the switching frequency

The heat rating current (RMS) is as below:

(DI_L)²

I_{L _RMS}= I

(9)

where

• I_{L_RMS}is the RMS current of the inductor

• I_INis the input current of the inductor

• Δ_ILis the ripple current of the inductor

It is important that the peak current does not exceed the inductor saturation current and the RMS current is not

over the temperature related rating current of the inductors.

For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation

current. The total losses of the coil consists of the DC resistance (DCR) loss and the following frequency

dependent loss:

• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

• Additional losses in the conductor from the skin effect (current displacement at high frequencies)

• Magnetic field losses of the neighboring windings (proximity effect)

For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the

frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,

it is usually a tradeoff between the loss and foot print. 表9-2 lists some recommended inductors.

表9-2. Recommended Inductors

DCR TYP

(mΩ) MAX

SATURATION

CURRENT (A)

PART NUMBER

SIZE (L × W × H mm)

VENDOR⁽¹⁾

L (μH)

XGL3515-451ME

XGL3515-102ME

0.45

8.2

18.5

3.2

2.2

4.9

4.7

3.5 × 3.2 × 1.5

3.2 × 2.5 × 1.2

Coilcraft

TDK

TFM252012ALMAR47MTAA

TFM252012ALMA1R0MTAA

0.47

TDK

(1) See Third-party Products Disclaimer

9.2.2.4 Selecting the Output Capacitors

The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop

is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series

resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum

capacitance needed for a given ripple can be calculated by 方程式10:

I_OUT´ (V_OUT- V )

C_OUT

f_SW´ DV ´ V_OUT

(10)

where

• C_OUTis the output capacitor

• I_OUTis the output current

• V_OUTis the output voltage

• V_INis the input voltage

• Δ_Vis the output voltage ripple required

• ƒ_SWis the switching frequency

The additional output ripple component caused by ESR is calculated by 方程式11:

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DV_ESR= I_OUT´ R_ESR

(11)

where

• ΔV_ESRis the output voltage ripple caused by ESR

• R_ESRis the resistor in series with the output capacitor

For the ceramic capacitor, the ESR ripple can be neglected. However, for tantalum or electrolytic capacitors, it

must be considered if used.

The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using

方程式12:

DI_STEP

C_OUT

2p ´ f_BW´ DV_TRAN

(12)

where

• ΔI_STEPis the transient load current step

• ΔV_TRANis the allowed voltage dip for the load current step

• ƒ_BWis the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)

For the output capacitor on the OUT pin, the effective capacitance is recommended between 0.22 μF to 1 μF.

Care must be taken when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors

can derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage

rating must be considered to ensure adequate capacitance at the required output voltage.

9.2.2.5 Selecting the Input Capacitors

Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they

have extremely low ESR and are available in small footprints. Input capacitors must be located as close as

possible to the device. While a 22-µF input capacitor or equivalent is sufficient for the most applications, larger

values can be used to reduce input current ripple.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the V_INpin. This ringing can couple to the output and be mistaken as loop instability or could even

damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, must be placed

between C_INand the power source lead to reduce ringing that can occur between the inductance of the power

source leads and C_IN.

9.2.2.6 Loop Stability and Compensation

9.2.2.6.1 Small Signal Model

The TPS61379-Q1 uses the fixed frequency peak current mode control. There is an internal adaptive slope

compensation to avoid the subharmonic oscillation. With the inductor current information sensed, the small-

signal model of the power stage reduces from a two-pole system, created by L and C_OUT, to a single-pole

system, created by R_OUTand C_OUT. The single-pole system is easily used with the loop compensation. 图 9-2

shows the equivalent small signal elements of a boost converter.

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VIN

VOUT

C_IN

R_ESR

C_OUT

R_OUT

R_SENSE

Slope

Comp

I_SENSE

VOUT

R_UP

G_EA

R_DOWN

V_REF

R_C

R_EA

图9-2. TPS61379-Q1 Control Equivalent Circuitry Model

The small signal of power stage is:

2è × B

(1 +

)(1 F

)

4₁₇₆× (1 F &)

2 × 4_5'05'

'54

4*2

-₂₅(5) =

2è × B

(1 +

)

(13)

where

• D is the duty cycle

• R_OUTis the output load resistor

• R_SENSEis the equivalent internal current sense resistor, which is typically 118 mΩ

The single pole of the power stage is:

f_P=

2p ´ R_OUT´ C_OUT

(14)

where

• C_OUTis the output capacitance. For a boost converter having multiple, identical output capacitors in parallel,

simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor is:

f_ESR

2p ´ R_ESR´ C_OUT

(15)

where

• R_ESRis the equivalent resistance in series of the output capacitor

The right-hand plane zero is:

R_OUT´ (1- D)²

2p ´ L

f_RHP

(16)

where

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• D is the duty cycle

• R_OUTis the output load resistor

• L is the inductance

方程式17 shows the equation for feedback resistor network and the error amplifier.

R_DOWN

2´ p ´ f_Z

H_EA(S) = G_EA´R_EA

_UP+ R_DOWN

(1+

)´(1+

)

2´ p ´ f_P1

2´ p ´ f_P2

(17)

where

• R_EAis the output impedance of the error amplifier and typical R_EA= 500 MΩ.

• ƒ_P1, ƒ_P2is the pole's frequency of the compensation, f_Zis the zero’s frequency of the compensation network

f_P1

2p ´ R_EA´ C_c

(18)

where

• C_Cis the zero capacitor compensation

f_P2

2p ´ R_C´ C_P

(19)

where

• C_Pis the pole capacitor compensation

• R_Cis the resistor of the compensation network

f_Z=

2p ´R_C´C_C

(20)

9.2.2.6.2 Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with

the given inductor and output capacitance.

1. Set the Cross Over Frequency, ƒ_C.

The first step is to set the loop crossover frequency, ƒ_C. The higher crossover frequency, the faster the loop

response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of

the switching frequency, ƒ_SW, or 1/5 of the RHPZ frequency, ƒ_RHPZ. Then calculate the loop compensation

network values of R_C, C_C, and C_Pby the following equations.

2. Set the Compensation Resistor, R_C.

By placing ƒ_Zbelow ƒ_C, for frequencies above ƒ_C, R_C| | R_EA~ = R_Cand so R_C× G_EAsets the compensation

gain. Setting the compensation gain, K_COMP-dB, at ƒ_Z, results in the total loop gain, T_(s)= K_PS(s)× H_EA(s)being

zero at ƒ_C.

Therefore, to approximate a single-pole roll-off up to f_P2, rearrange 方程式17 to solve for RC so that the

compensation gain, K_EA, at f_Cis the negative of the gain, K_PS, read at frequency f_Cfor the power stage bode

plot or more simply:

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R_DOWN

R_UP+ R_DOWN

K_EA(f_C) = 20 ´ log(G_EA´ R_C´

) = - K_PS(f_C)

(21)

where

• K_EAis gain of the error amplifier network

• K_PSis the gain of the power stage

• G_EAis the transconductance of the amplifier, the typical value of G_EA= 70 µA / V

3. Set the Compensation Zero capacitor, C_C.

Place the compensation zero at the power stage R_OUT,C_OUTpole’s position to get:

f_Z=

2p ´ R_C´ C_C

(22)

(23)

Set ƒ_Z= ƒ_P, and get

_OUT´C_OUT

C_C

2R_C

4. Set the Compensation Pole Capacitor, C_P.

Place the compensation pole at the zero produced by the R_ESRand the C_OUT. It is useful for canceling

unhelpful effects of the ESR zero.

f_P2

2p ´ R_C´ C_P

(24)

(25)

f_ESR

2p ´ R_ESR´ C_OUT

Set ƒ_P2= ƒ_ESR, and get

R_ESR´ C_OUT

C_P=

R_C

(26)

9.2.2.6.3 Selecting the Bootstrap Capacitor

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET

device gate during turn-on of each cycle and also supplies charge for the bootstrap capacitor. The

recommended value of the bootstrap capacitor is 0.1 µF to 1 µF. C_BSTmust be a good quality, low-ESR, ceramic

capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace

inductance. A value of 0.1 µF was selected for this design example.

9.2.2.6.4 V_CCCapacitor

The primary purpose of the V_CCcapacitor is to supply the peak transient currents of the driver and bootstrap

capacitor as well as provide stability for the V_CCregulator. The value of C_VCCmust be at least 10 times greater

than the value of C_BST, and must be a good quality, low-ESR, ceramic capacitor. C_VCCmust be placed close to

the pins of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value of

2.2 µF was selected for this design example.

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9.2.3 Application Curves

5 V/div

200 ns/div

200 µs/div

Inductor

Current

500 mA/div

Inductor

Current

500 mA/div

Vout (AC)

10 mV/div

Vout (AC)

10 mV/div

图9-3. Switching Waveform V_IN= 5 V, V_OUT= 9 V,

图9-4. Switching Waveform V_IN= 5 V, V_OUT= 9 V,

I_OUT= 250 mA, FPWM

I_OUT= 0 mA, Auto PFM

2 V/div

Vout (AC)

100 mV/div

5 V/div

Vout

5 V/div

500 µs/div

Output

Current

100 mA/div

50 µs/div

Inductor

Current

500 mA/div

图9-5. Load Transient V_IN= 5 V, V_OUT= 9 V, I_OUT= 图9-6. Start-up from EN Waveform V_IN= 5 V, V_OUT

50 mA to 250 mA, FPWM 9 V, I_OUT= 250 mA, FPWM

Vout

5 V/div

2 V/div

5 V/div

200 µs/div

Vout

5 V/div

20 µ s/div

Inductor

Current

1 A/div

Inductor

Current

500 mA/div

图9-7. Shutdown from EN Waveforms V_IN= 5 V,

图9-8. Short Circuit Protection V_IN= 5 V, V_OUT= 9

V_OUT= 9 V, I_OUT= 250 mA, FPWM

V, FPWM

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Vout

5 V/div

Vout

2 V/div

5 V/div

500 µ s/div

10 ms/div

Inductor

Current

500 mA/div

Inductor

Current

500 mA/div

图9-9. Short Circuit Recovery V_IN= 5 V, V_OUT= 9 V, 图9-10. Hiccup Short Circuit Protection V_IN= 5 V,

I_OUT= 0 mA, FPWM

V_OUT= 9 V, FPWM

10 Power Supply Recommendations

The TPS61379-Q1 is designed to operate from an input voltage supply range between 2.3 V to 14 V. This input

supply must be well regulated. If the input supply is located more than a few inches from the device, the bulk

capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value

of 47 µF is a typical choice.

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11 Layout

11.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator can show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

paths. The input and output capacitor, as well as the inductor must be placed as close as possible to the IC.

11.2 Layout Example

The bottom layer is a large GND plane connected by vias.

GND

VIN

BST

GND

OUT

VIN

GND

图11-1. Recommended Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

26-Jul-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS61379QWRTERQ1

ACTIVE

WQFN

RTE

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

2H1H

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS61379QWRTERQ1

WQFN

RTE

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WQFN RTE 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPS61379QWRTERQ1

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTE 16

3 x 3, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225944/A

www.ti.com

PACKAGE OUTLINE

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08

0.05

0.00

1.66 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

12X 0.5

(0.16)

TYP

SYMM

1.5

0.30

0.18

16X

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4224938/C 03/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.66)

SYMM

16X (0.6)

16X (0.24)

SYMM

(2.8)

(0.58)

TYP

12X (0.5)

(

0.2) TYP

VIA

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224938/C 03/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.51)

16X (0.6)

16X (0.24)

SYMM

(2.8)

12X (0.5)

METAL

ALL AROUND

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4224938/C 03/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS61379QWRTERQ1 [TI]

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