TPS62000-Q1_16 [TI]
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER;
| 型号： | TPS62000-Q1_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER 功效 DC-DC转换器 |
| 文件： | 总26页 (文件大小：1215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER
1
FEATURES
•
High-Efficiency Synchronous Step-Down
Converter With Greater Than 95% Efficiency
•
Low-Noise Operation Antiringing Switch and
PFM/PWM Operation Mode
•
•
2 V to 5.5 V Operating Input Voltage Range
•
•
•
Internal Softstart
Adjustable Output Voltage Range From 0.8 V
to VI
50-µA Quiescent Current (TYP)
Available in the 10-Pin Microsmall Outline
Package (MSOP)
•
•
Fixed Output Voltage Options Available in
0.9 V, 1 V, 1.2 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, and
3.3 V
•
Evaluation Module Available
Synchronizable to External Clock Signal up to
1 MHz
APPLICATIONS
•
•
•
•
•
•
Low-Power CPUs and DSPs
Cellular Phones
•
•
•
Up to 600 mA Output Current
Organizers, PDAs, and Handheld PCs
MP-3 Portable Audio Players
Digital Cameras
USB-Based DSL Modems and Other Network
Interface Cards
Pin-Programmable Current Limit
High Efficiency Over a Wide Load Current
Range in Power Save Mode
•
100% Maximum Duty Cycle for Lowest
Dropout
DESCRIPTION
The TPS6200x devices are a family of low-noise synchronous step-down dc-dc converters that are ideally suited
for systems powered from a 1-cell Li-ion battery or from a 2- to 3-cell NiCd, NiMH, or alkaline battery. The
TPS6200x operates typically down to an input voltage of 1.8 V, with a specified minimum input voltage of 2 V.
EFFICIENCY
vs
LOAD CURRENT
10 mH
100
90
80
70
60
50
40
30
20
10
0
V = 2 V
I
1
8
V = 0.8 V
O
9
5
V
L
FB
IN
to 5.5 V
to V
I
10 mF
EN
TPS6200x
†
10 mF
10
4
SYNC = Low
6
7
ILIM
PGND
SYNC = High
SYNC
GND
PG
PG
FC
3
2
0.1 mF
†
WithVO ≥1.8 V; C = 10 mF, V <1.8 V; C = 47 mF
o
o
O
V = 3.6 V,
I
V
O
= 2.5 V
0.1
1
10
100
1000
I
O
− Load Current − mA
Figure 1.
Figure 2. Typical Application Circuit for Fixed Output
Voltage Option
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2008, Texas Instruments Incorporated
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
DESCRIPTION (CONTINUED)
The TPS6200x is a synchronous current-mode PWM converter with integrated – and P-channel power MOSFET
switches. Synchronous rectification is used to increase efficiency and to reduce external component count. To
achieve the highest efficiency over a wide load current range, the converter enters a power-saving
pulse-frequency modulation (PFM) mode at light load currents. Operating frequency is typically 750 kHz, allowing
the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the
range of 500 kHz to 1 MHz. For low-noise operation, the converter can be operated in the PWM mode and the
internal antiringing switch reduces noise and EMI. In the shutdown mode, the current consumption is reduced to
less than 1 µA. The TPS62000 is available in the 10-pin (DGS) microsmall outline package (MSOP). The device
operates over a free-air temperature range of –40°C to 85°C.
MSOP (DGS) PACKAGE
(TOP VIEW)
PGND
V
1
2
3
4
5
10
9
IN
L
FC
GND
PG
EN
8
SYNC
ILIM
7
6
FB
AVAILABLE OPTIONS
PACKAGE(1)
MARKING
DGS
AIH
TA
VOLTAGE OPTIONS
MSOP
Adjustable
0.9 V
1 V
TPS62000DGS
TPS62001DGS
TPS62002DGS
TPS62003DGS
TPS62004DGS
TPS62005DGS
TPS62008DGS
TPS62006DGS
TPS62007DGS
AII
AIJ
1.2 V
1.5 V
1.8 V
1.9 V
2.5 V
3.3 V
AIK
–40°C to 85°C
AIL
AIM
AJI
AIN
AIO
(1) For shipment quantities and additional package information see the Package Option Addendum at the
end of the data sheet.
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Product Folder Link(s): TPS62000, TPS62001, TPS62003 TPS62004, TPS62005, TPS62006 TPS62007, TPS62008
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
FUNCTIONAL BLOCK DIAGRAM
PG
FC (See Note B)
V
IN
Undervoltage
Lockout
10 Ω
Bias Supply
EN
Current
Sense
P-Channel
Power MOSFET
Slope Compensation
PFM/PWM
Power Good
+
_
Mode Select
PFM/PWM
Comparator
_
Error Amplifier
_
R1
PFM/PWM
Control Logic
Current Limit
Logic
Driver
Shoot-Through
Logic
FB
(See
L
+
+
Note A)
Soft
Compensation
Start
R2
R1 + R2 ≈ 1 MΩ
N-Channel
Power MOSFET
EN
Current Sense
Sync
+
+
_
Load Comparator
V
ref
= 0.45 V
+
Offset
Oscillator
+
_
PGND
Antiringing
FB
GND
SYNC
ILIM
A. The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly
connected to the error amplifier.
B. Do not connect the FC pin to an external power source
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME
NO.
Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply
current to less than 1 µA.
EN
FB
8
I
I
Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is
connected to FB. The internal voltage divider is disabled for the adjustable version.
5
Supply bypass pin. A 0.1 µF coupling capacitor should be connected as close as possible to this pin for good
high frequency input voltage supply filtering.
FC
2
3
GND
ILIM
L
Ground
Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin
to VIN to set the current limit to typically 1200 mA.
6
I
9
I/O Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.
Power good comparator output. This is an open-drain output. A pullup resistor should be connected between
PG and VO. The output goes active high when the output voltage is greater than 92% of the nominal value.
PG
4
O
PGND
10
Power ground. Connect all power grounds to PGND.
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an
external clock signal with CMOS level:
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC
VIN
7
1
I
SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled.
I
Supply voltage input
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
DETAILED DESCRIPTION
Operation
The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching
frequency of 750 kHz.
At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the
converter enters a power save mode (pulse frequency modulation) to keep the efficiency high.
In the PWM mode operation, the part operates at a fixed frequency of 750 kHz. At the beginning of each clock
cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an
internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator to
trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM).
After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and
the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next
clock cycle starts.
In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle.
In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current
becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and low
side MOSFET to ground that would cause additional losses.
As the load current decreases and the peak inductor current does not reach the power save mode threshold of
typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM) mode.
In the PFM mode, the converter operates with:
•
•
•
Variable frequency
Constant peak current that reduces switching losses
Quiescent current at a minimum
Thus maintaining the highest efficiency at light load currents. In this mode, the output voltage is monitored with
the error amplifier. As soon as the output voltage falls below the nominal value, the high side switch is turned on
and the inductor current ramps up. When the inductor current reaches the peak current of typical: 150 mA +
50 mA/V × (VI – VO), the high side switch turns off and the low side switch turns on. As the inductor current
ramps down, the low side switch is turned off before the inductor current becomes negative which completes the
cycle. When the output voltage falls below the nominal voltage again, the next cycle is started.
The converter enters the PWM mode again as soon as the output voltage can not be maintained with the typical
peak inductor current in the PFM mode.
The control loop is internally compensated reducing the amount of external components.
The switch current is internally sensed and the maximum current limit can be set to typical 600 mA by connecting
ILIM to ground; or, to typically 1.2 A by connecting ILIM to VIN.
100% Duty Cycle Operation
As the input voltage approaches the output voltage and the duty cycle exceeds typical 95%, the converter turns
the P-channel high side switch continuously on. In this mode, the output voltage is equal to the input voltage
minus the voltage drop across the P-channel MOSFET.
Synchronization, Power Save Mode and Forced PWM Mode
If no clock signal is applied, the converter operates with a typical switching frequency of 750 kHz. It is possible to
synchronize the converter to an external clock within a frequency range from 500 kHz to 1000 kHz. The device
automatically detects the rising edge of the first clock and is synchronizes immediately to the external clock. If
the clock signal is stopped, the converter automatically switches back to the internal clock and continues
operation without interruption. The switch over is initiated if no rising edge on the SYNC pin is detected for a
duration of four clock cycles. Therefore, the maximum delay time can be 8 µs in case the internal clock has a
minimum frequency of 500 kHz.
In case the device is synchronized to an external clock, the power save mode is disabled and the device stays in
forced PWM mode.
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Product Folder Link(s): TPS62000, TPS62001, TPS62003 TPS62004, TPS62005, TPS62006 TPS62007, TPS62008
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM
mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide
load current range.
Connecting the SYNC pin to the VIN pin forces the converter to operate permanently in the PWM mode even at
light or no load currents. The advantage is the converter operates with a fixed switching frequency that allows
simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower
compared to the power save mode during light loads (see Figure 1).
It is possible to switch from forced PWM mode to the power save mode during operation.
The flexible configuration of the SYNC pin during operation of the device allows efficient power management by
adjusting the operation of the TPS6200x to the specific system requirements.
Low Noise Antiringing Switch
An antiringing switch is implemented in order to reduce the EMI radiated from the converter during discontinuous
conduction mode (DCM). In DCM, the inductor current ramps to zero before the end of each switching period.
The internal load comparator turns off the low side switch at that instant thus preventing the current flowing
backward through the inductance which increases the efficiency. An antiringing switch across the inductor
prevents parasitic oscillation caused by the residual energy stored in the inductance (see Figure 12).
NOTE:
The antiringing switch is only activated in the fixed output voltage versions. It is not
enabled for the adjustable output voltage version TPS62000.
Soft Start
As the enable pin (EN) goes high, the soft-start function generates an internal voltage ramp. This causes the
start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start
duration is typical 1 ms (see Figure 13). When the soft-start function is completed, the error amplifier is
connected directly to the internal voltage reference.
Enable
Logic low on EN forces the TPS6200x into shutdown. In shutdown, the power switch, drivers, voltage reference,
oscillator, and all other functions are turned off. The supply current is reduced to less than 1 µA in the shutdown
mode.
Undervoltage Lockout
An undervoltage lockout circuit provides the save operation of the device. It prevents the converter from turning
on when the voltage on VIN is less than typically 1.6 V.
Power Good Comparator
The power good (PG) comparator has an open drain output capable of sinking typically 10 µA. The PG is only
active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is high
impedance.
The PG output is only valid after a 100 µs delay after the device is enabled and the supply voltage is greater
than 1.2 V. This is only important in cases where the pullup resistor of the PG pin is connected to an external
voltage source which might cause an initial spike (false high signal) within the first 100 µs after the input voltage
exceeds 1.2 V. This initial spike can be filtered with a small R-C filter to avoid false power good signals during
start-up.
If the PG pin is connected to the output of the TPS62000 with a pullup resistor, no initial spike (false high signal)
occurs and no precautions have to be taken during start-up.
The PG pin becomes active high when the output voltage exceeds typically 94.5% of its nominal value. Leave
the PG pin unconnected when not used.
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Product Folder Link(s): TPS62000, TPS62001, TPS62003 TPS62004, TPS62005, TPS62006 TPS62007, TPS62008
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
No Load Operation
In case the converter operates in the forced PWM mode and there is no load connected to the output, the
converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 6
UNIT
Supply voltages on pin VIN and FC(2)
Voltages on pins EN, ILIM, SYNC, PG, FB, L(2)
Peak switch current
V
V
A
–0.3 to VIN + 0.3
1.6
Continuous power dissipation
See Dissipation Rating Table
–40 to 150
TJ
Operating junction temperature range
Storage temperature range
°C
°C
°C
Tstg
–65 to 150
Lead temperature (soldering, 10 sec)
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR
TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE(1)
POWER RATING
10 pin MSOP
555 mW
5.56 mW/°C
305 mW
221 mW
(1) The thermal resistance junction to ambient of the 10-pin MSOP is 180°C/W. The device will not run into thermal limitations provided it is
operated within the specified range.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2
TYP
MAX
5.5
UNIT
V
VI
Supply voltage
VO
IO
Output voltage range for adjustable output voltage version
Output current for 3-cell operation (VI ≥ 2.5 V; L = 10 µH, f = 750 kHz)
Output current for 2-cell operation (VI ≥ 2 V; L = 10 µH, f = 750 kHz)
Inductor(1) (see Note 2)
Input capacitor(1)
Output capacitor(1) (VO ≥ 1.8 V)
0.8
VI
V
600
200
mA
mA
µH
µF
µF
µF
°C
IO
L
10
CI
Co
Co
TA
TJ
10
10
Output capacitor(1) VO < 1.8 V)
47
Operating ambient temperature
–40
–40
85
Operating junction temperature
125
°C
(1) Refer to application section for further information.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VI = 3.6 V, VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA =
–40°C to 85°C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
IO = 0 mA to 600 mA
2.5
2
5.5
V
VI
Input voltage range
IO = 0 mA to 200 mA
5.5
I(Q)
Operating quiescent current
IO = 0 mA, SYNC = GND (PFM-mode
enabled)
50
75
1
µA
µA
I(SD)
Shutdown current
EN = GND
0.1
ENABLE
VIH
EN high-level input voltage
EN low level input voltage
EN input leakage current
Undervoltage lockout threshold
1.3
V
V
VIL
0.4
0.1
Ilkg
EN = GND or VIN
0.01
1.6
µA
V
V(UVLO)
1.2
1.95
POWER SWITCH AND CURRENT LIMIT
VI = VGS = 3.6 V, I = 200 mA
VI = VGS = 2 V, I = 200 mA
VDS = 5.5 V
200
280
480
410
P-channel MOSFET on-resistance
mΩ
µA
P-channel leakage current
rDS(on)
1
VI = VGS = 3.6 V, IO = 200 mA
VI = VGS = 2 V, IO = 200 mA
VDS = 5.5 V
200
280
500
410
N-channel MOSFET on-resistance
mΩ
µA
N-channel leakage current
1
1600
900
2.5 V ≤ VI ≤ 5.5 V, ILIM = VIN
2 V ≤ VI ≤ 5.5 V, ILIM = GND
800
390
1.3
1200
600
I(LIM)
P-channel current limit
mA
VIH
VIL
Ilkg
ILIM high-level input voltage
ILIM low-level input voltage
V
V
0.4
0.1
ILIM input leakage current
ILIM = GND or VIN
0.01
µA
(1)
POWER GOOD OUTPUT (see
)
V(PG)
Power good threshold
Power good hysteresis
PG output low voltage
Feedback voltage falling
88% VO 92% VO 94% VO
V
V
2.5% VO
0.3
VOL
Ilkg
V(FB) = 0.8 × VO nominal, I(sink) = 10 µA
V
PG output leakage current
V(FB) = VO nominal
0.01
1
µA
V
Minimum supply voltage for valid
power good signal
1.2
OSCILLATOR
fs
Oscillator frequency
500
500
1.3
750
1000
1000
kHz
kHz
V
f(SYNC)
VIH
VIL
Synchronization range
CMOS-logic clock signal on SYNC pin
SYNC = GND or VIN
SYNC high level input voltage
SYNC low level input voltage
SYNC input leakage current
Duty cycle of external clock signal
0.4
0.1
V
Ilkg
0.01
µA
20%
60%
(1) Power good is not valid for the first 100 µs after EN goes high. Refer to the application section for more information.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VI = 3.6 V, VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA =
–40°C to 85°C (unless otherwise noted)
PARAMETER
Adjustable output voltage range
Reference voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VO
TPS62000
TPS6200x
0.8
5.5
Vref
0.45
V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
–3%
4%
3%
4%
3%
4%
3%
4%
3%
4%
3%
4%
3%
4%
3%
4%
3%
4%
3%
TPS62000
adjustable
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62001
0.9 V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62002
1 V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62003
1.2 V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62004
1.5 V
(1)
VO
Fixed output voltage
V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62005
1.8 V
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62008
1.9 V
VI = 2.7 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62006
2.5 V
VI = 3.6 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA
10 mA < IO ≤ 600 mA
TPS62007
3.3 V
Line regulation
Load regulation
VI = VO + 0.5 V (min. 2 V) to 5.5 V, IO = 10 mA
VI = 5.5 V; IO = 10 mA to 600 mA
VI = 5 V; VO = 3.3 V; IO = 300 mA
VI = 3.6 V; VO = 2.5 V; IO = 200 mA
IO = 0 mA, time from active EN to VO
0.05
%/V
ms
0.6%
η
Efficiency
95%
Start-up time
0.4
2
(1) The output voltage accuracy includes line and load regulation over the full temperature range, TA = –40°C to 85°C.
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Product Folder Link(s): TPS62000, TPS62001, TPS62003 TPS62004, TPS62005, TPS62006 TPS62007, TPS62008
TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
η
Efficiency
vs Load current
3, 4, 5
6
V(drop)
IQ
Dropout voltage
vs Load current
Operating quiescent current
vs Input voltage (power save mode)
vs Input voltage (forced PWM)
vs Free-air temperature
7
8
fOSC
Oscillator frequency
Load transient response
Line transient response
Power save mode operation
Start-up
9
10
11
12
13
14
vs Time
VO
Output voltage
vs Load current
EFFICIENCY
EFFICIENCY
vs
LOAD CURRENT
vs
LOAD CURRENT
100
V
O
= 2.5 V
90
80
70
V = 3.6 V
I
V = 5 V
I
60
50
40
0.1
1
10
100
1000
I
− Load Current − mA
O
Figure 3.
Figure 4.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
EFFICIENCY
vs
LOAD CURRENT
DROPOUT VOLTAGE
vs
LOAD CURRENT
Figure 5.
Figure 6.
OPERATING QUIESCENT CURRENT
vs
INPUT VOLTAGE (POWER SAVE MODE)
OPERATING QUIESCENT CURRENT
vs
INPUT VOLTAGE (FORCED PWM)
Figure 7.
Figure 8.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
OSCILLATOR FREQUENCY
vs
FREE-AIR TEMPERATURE
LOAD TRANSIENT RESPONSE
200 ms/div
Figure 9.
Figure 10.
LINE TRANSIENT RESPONSE
POWER SAVE MODE OPERATION
400 ms/div
10 ms/div
Figure 11.
Figure 12.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
START-UP
vs
TIME
EN
2 V/div
V
O
1 V/div
Power Good
1 V/div
I
I
200 mA/div
250 ms/div
Figure 13.
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
0
100
200
300
400
500
600
I
− Load Current − mA
O
Figure 14.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
APPLICATION INFORMATION
ADJUSTABLE OUTPUT VOLTAGE VERSION
When the adjustable output voltage version (TPS62000DGS) is used, the output voltage is set by the external
resistor divider (see Figure 15).
The output voltage is calculated as:
R1
æ
ö
VO = 0.45 V ´ 1 +
ç
÷
R2
è
ø
(1)
With R1 + R2 ≤ 1 MΩ
R1 + R2 should not be greater than 1 MW because of stability reasons.
For stability reasons, a small bypass capacitor (Cff) is required in parallel to the upper feedback resistor, refer to
Figure 15. The bypass capacitor value can be calculated as:
1
C(ff)
=
for Co < 47mF
2p ´30000´R1
1
(2)
C(ff)
=
for Co ³ 47mF
2p ´5000´R1
(3)
R1 is the upper resistor of the voltage divider. For C(ff), choose a value which comes closest to the computed
result.
L1 = 10 mH
V
= 2.5 V/600 mA
O
V = 2.7 V to 5.5 V
I
1
8
6
7
9
5
4
V
L
FB
PG
IN
R3 = 320 kΩ
+
EN
C = 10 mF
i
C
(ff)
=
6.8 pF
R1 = 820 kΩ
TPS62000
+
ILIM
PG
C
o
= 10 mF
10
R2 = 180 kΩ
SYNC
GND
3
PGND
FC
2
C3 = 0.1 mF
Figure 15. Typical Application Circuit for Adjustable Output Voltage Option
INDUCTOR SELECTION
A 10 µH minimum output inductor is used with the TPS6200x. Values larger than 22 µH or smaller than 10 µH
may cause stability problems because of the internal compensation of the regulator.
For output voltages greater than 1.8 V, a 22 µH inductance might be used in order to improve the efficiency of
the converter.
After choosing the inductor value of typically 10 µH, two additional inductor parameters should be considered:
first the current rating of the inductor and second the dc resistance.
The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with
lowest dc resistance should be selected for highest efficiency.
In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current
plus the inductor ripple current which is calculated as:
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TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
VO
1 -
V
DIL
I
DIL = VO
´
IL(max) = IO(max) +
L ´ f
2
(4)
Where:
ƒ = Switching frequency (750 kHz typical)
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
IL(max) = Maximum inductor current
The highest inductor current occurs at maximum VI.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS6200x which is 1.6 A with ILIM = VIN and 900 mA with ILIM = GND. See Table 1 for recommended inductors.
Table 1. Tested Inductors
OUTPUT CURRENT
INDUCTOR VALUE
COMPONENT SUPPLIER
COMMENTS
0 mA to 600 mA
10 µH
Coilcraft DO3316P-103
Coilcraft DT3316P-103
Sumida CDR63B-100
Sumida CDRH5D28-100
High efficiency
Coilcraft DO1608C-103
Sumida CDRH4D28-100
Smallest solution
0 mA to 300 mA
10 µH
Coilcraft DO1608C-103
Murata LQH4C100K04
High efficiency
Smallest solution
OUTPUT CAPACITOR SELECTION
For best performance, a low ESR output capacitor is needed. At output voltages greater than 1.8 V, ceramic
output capacitors can be used to show the best performance. Output voltages below 1.8 V require a larger output
capacitor and ESR value to improve the performance and stability of the converter.
Table 2. Capacitor Selection
OUTPUT VOLTAGE RANGE
1.8 V ≤ VI ≤ 5.5 V
OUTPUT CAPACITOR
OUTPUT CAPACITOR ESR
ESR ≤ 120 mΩ
Co ≥ 10 µF
o ≥ 47 µF
0.8 V ≤ VI < 1.8 V
C
ESR > 50 mΩ
See Table 3 for recommended capacitors.
If an output capacitor is selected with an ESR value ≤ 120 mΩ, its RMS ripple current rating always meets the
application requirements. Just for completeness, the RMS ripple current is calculated as:
VO
1 -
V
1
I
IRMS(C = VO
´
´
)
O
L ´ f
2´ 3
(5)
The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the
voltage ripple caused by charge and discharging the output capacitor:
VO
1 -
æ
ç
è
ö
÷
ø
V
1
I
DVO = VO ´
´
+ESR
L ´ f
8´CO ´ f
(6)
Where the highest output voltage ripple occurs at the highest input voltage VI.
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
Table 3. Tested Capacitors
CAPACITOR VALUE
ESR/mΩ
50
COMPONENT SUPPLIER
Taiyo Yuden JMK316BJ106KL
Sanyo 6TPA47M
COMMENTS
Ceramic
10 µF
47 µF
68 µF
100
POSCAP
Tantalum
100
Spraque 594D686X0010C2T
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes.
The input capacitor should have a minimum value of 10 µF and can be increased without any limit for better input
voltage filtering.
The input capacitor should be rated for the maximum input ripple current calculated as:
æ
ö
÷
ø
VO
VO
IRMS = IO(max)
´
´ 1-
ç
V
V
I
I
è
(7)
IO
2
IRMS
=
The worst case RMS ripple current occurs at D = 0.5 and is calculated as:
Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against
voltage transients compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin of the IC for best performance.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design especially at high peak currents
and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well
as EMI problems.
Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input
capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Place
the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground,
PGND, need to be separated. Use a common ground node as shown in Figure 16 to minimize the effects of
ground noise.
L1
1
8
6
7
9
V
I
V
O
V
L
FB
PG
IN
+
R3
5
4
EN
C
i
C
(ff)
R1
TPS62000
+
ILIM
PG
C
o
R2
10
SYNC
GND
PGND
FC
C3
3
2
Figure 16. Layout Diagram
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TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
TYPICAL APPLICATION
L1
22 mH
1
8
6
7
9
V
L
FB
V
O
= 3.3 V/600 mA
V = 5 V
I
IN
C1
10 mF
5
EN
C2
10 mF
TPS62007DGS
680 kΩ
10
ILIM
PGND
4
SYNC
GND
Power
Good
PG
FC
3
2
L1: Sumdia CDRH5D28-220
C1, C2: 10 mF Ceramic Taiyo Yuden
C3
0.1 mF
JMK316BJ106KL
0.1 mF Ceramic
C3:
Figure 17. Standard 5 V to 3.3 V/600 mA Conversion; High Efficiency
L1
10 mH
1
8
6
7
9
V
L
FB
V = 2.5 V/600 mA
O
V = 2.7 V to 4.2 V
I
IN
C1
10 mF
5
EN
C2
10 mF
TPS62006DGS
470 kΩ
10
ILIM
PGND
4
SYNC
GND
3
Power Good
L1:
PG
FC
Sumdia CDRH5D28-100
C1,C2: 10 mF Ceramic Taiyo Yuden
2
C3
0.1 mF
JMK316BJ106KL
0.1 mF Ceramic
C3:
Figure 18. Single Li-ion to 2.5 V/600 mA Using Ceramic Capacitors Only
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
www.ti.com ........................................................................................................................................... SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008
L1
10 mH
1
8
6
7
9
V
L
FB
V
= 1.8 V/300 mA
V = 2.5 V to 4.2 V
I
IN
O
C1
10 mF
5
EN
C2
10 mF
TPS62005DGS
10
ILIM
PGND
4
SYNC
GND
PG
FC
L1: Murata LQH4C100K04
C1,C2: 10 mF Ceramic Taiyo Yuden
3
2
C3
0.1 mF
JMK316BJ106KL
0.1 mF Ceramic
C3:
NOTE: For low noise operation connect SYNC to VIN
Figure 19. Single Li-ion to 1.8 V/300 mA; Smallest Solution Size
L1
10 mH
1
8
6
7
9
V
L
FB
V = 1.2 V/200 mA
O
V = 2 V to 3.8 V
I
IN
C1
10 mF
5
EN
+
C2
47 mF
TPS62003
10
ILIM
PGND
4
SYNC
GND
PG
FC
L1:
C1:
Murata LQH4C100K04
3
2
C3
0.1 mF
10 mF Ceramic Taiyo Yuden
JMK316BJ106KL
Sanyo 6TPA47M
C2:
C3:
0.1 mF Ceramic
Figure 20. Dual Cell NiMH or NiCd to 1.2 V/200 mA; Smallest Solution Size
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TPS62000, TPS62001, TPS62003
TPS62004, TPS62005, TPS62006
TPS62007, TPS62008
SLVS294E–SEPTEMBER 2000–REVISED AUGUST 2008 ........................................................................................................................................... www.ti.com
10 mH
820 kW
(2)
470 kW
10 mF
47 mF
326 kW
524 kW
0.1 mF
Sumida CDRH5D28-100
10 mF Ceramic Taiyo Yuden
JMK316BJ106KL
Sanyo 6TPA47M
0.1 mF Ceramic
(1) Use a small R-C filter to filter wrong reset signals during output voltage transitions.
(2) A large value is used for C(ff) to compensate for the parasitic capacitance introduced into the regulation loop by Q1.
Figure 21. Dynamic Output Voltage Programming As Used in Low Power DSP Applications
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2013
PACKAGING INFORMATION
Orderable Device
TPS62000DGS
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
DGS
10
10
10
10
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
AIH
AIH
AIH
AIH
TPS62000DGSG4
TPS62000DGSR
TPS62000DGSRG4
ACTIVE
ACTIVE
ACTIVE
DGS
DGS
DGS
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
-40 to 85
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS62000YZGR
TPS62000YZGT
TPS62002DGS
OBSOLETE
OBSOLETE
ACTIVE
DSBGA
DSBGA
VSSOP
YZG
YZG
DGS
12
12
10
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
TPS62000
80
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
AIJ
AIJ
AIJ
AIJ
AIK
AIK
AIK
AIK
AIL
AIL
AIL
AIL
TPS62002DGSG4
TPS62002DGSR
TPS62002DGSRG4
TPS62003DGS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
10
10
10
10
10
10
10
10
10
10
10
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2500
2500
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
TPS62003DGSG4
TPS62003DGSR
TPS62003DGSRG4
TPS62004DGS
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
2500
2500
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
TPS62004DGSG4
TPS62004DGSR
TPS62004DGSRG4
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
2500
2500
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS62005DGS
TPS62005DGSG4
TPS62005DGSR
TPS62005DGSRG4
TPS62006DGS
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGS
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
AIM
AIM
AIM
AIM
AIN
AIN
AIN
AIN
AIO
AIO
AIO
AIO
AJI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
80
2500
2500
80
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
TPS62006DGSG4
TPS62006DGSR
TPS62006DGSRG4
TPS62007DGS
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
2500
2500
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TPS62007DGSG4
TPS62007DGSR
TPS62007DGSRG4
TPS62008DGS
80
Green (RoHS
& no Sb/Br)
2500
2500
80
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
TPS62008DGSG4
TPS62008DGSR
TPS62008DGSRG4
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
AJI
2500
2500
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
AJI
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
AJI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2013
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62000, TPS62004, TPS62005, TPS62006, TPS62007 :
Automotive: TPS62000-Q1, TPS62004-Q1, TPS62005-Q1, TPS62006-Q1, TPS62007-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62000DGSR
TPS62002DGSR
TPS62003DGSR
TPS62004DGSR
TPS62005DGSR
TPS62006DGSR
TPS62007DGSR
TPS62008DGSR
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
10
10
10
10
10
10
10
10
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62000DGSR
TPS62002DGSR
TPS62003DGSR
TPS62004DGSR
TPS62005DGSR
TPS62006DGSR
TPS62007DGSR
TPS62008DGSR
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
10
10
10
10
10
10
10
10
2500
2500
2500
2500
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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