TPS62040_技术文档

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

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D

USB Powered Modems

CPUs and DSPs

FEATURES

D

Up to 95% Conversion Efficiency

Typical Quiescent Current: 18 µA

Load Current: 1.2 A

PC Cards and Notebooks

xDSL Applications

Standard 5-V to 3.3-V Conversion

Operating Input Voltage Range: 2.5 V to 6.0 V

Switching Frequency: 1.25 MHz

DESCRIPTION

Adjustable and Fixed Output Voltage

The TPS6204x family of devices are high efficiency

synchronous step-down dc-dc converters optimized for

battery powered portable applications. The devices are

ideal for portable applications powered by a single Li-Ion

battery cell or by 3-cell NiMH/NiCd batteries. With an

output voltage range from 6.0 V down to 0.7 V, the devices

support low voltage DSPs and processors in PDAs,

pocket PCs, as well as notebooks and subnotebook

computers. The TPS6204x operates at a fixed switching

frequency of 1.25 MHz and enters the power save mode

operation at light load currents to maintain high efficiency

over the entire load current range. For low noise

applications, the devices can be forced into fixed

frequency PWM mode by pulling the MODE pin high. The

TPS6204x supports up to 1.2-A load current.

Power Save Mode Operation at Light load

Currents

D

100% Duty Cycle for Lowest Dropout

Internal Softstart

Dynamic Output Voltage Positioning

Thermal Shutdown

Short-Circuit Protection

10 Pin MSOP PowerPad Package

10 Pin QFN 3 X 3 mm Package

APPLICATIONS

D

PDA, Pocket PC and Smart Phones

EFFICIENCY

vs

LOAD CURRENT

100

V

= 1.8 V

O

Typical Application Circuit 1.2-A Output Current

95

90

85

80

75

70

65

60

55

50

45

40

V

= 2.7 V

= 3.6 V

I

V

I

V

TPS6204x

SW

V

O

I

L1

6.2 µH

0.7 V to V /1.2 A

2.5 V to 6 V

V = 5 V

I

8

7

2

3

1

6

4

VIN

SW

FB

VIN

C1

22 µF

C2

22 µF

5

EN

10

PGND

MODE

GND

MODE = Low

9

PGND

V

= 3.6 V

I

MODE = High

0

0.01

0.1

1

10

100 1 k

10 k

I

− Load Current − mA

L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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Copyright  2003, Texas Instruments Incorporated

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE

PACKAGE MARKING

MSOP

T

A

VOLTAGE OPTIONS

(1)

MSOP

(2)

QFN

BBO

BBS

BBT

BBU

BBW

Adjustable

1.5 V

TPS62040DGQ

TPS62042DGQ

TPS62043DGQ

TPS62044DGQ

TPS62046DGQ

TPS62040DRC

TPS62042DRC

TPS62043DRC

TPS62044DRC

TPS62046DRC

BBI

BBL

BBM

BBN

BBQ

1.6 V

−40°C to 85°C

1.8 V

3.3 V

(1)

(2)

The DGQ package is available in tape and reel. Add R suffix (DGQR) to order quantities of 2500 parts per reel.

The DRC package is available in tape and reel. Add R suffix (DRCR) to order quantities of 3000 parts per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNITS

(2)

Supply voltage VIN

−0.3 V to 7 V

(2)

Voltages on EN, MODE, FB, SW

Continuous power dissipation

−0.3 V to V +0.3 V

CC

See Dissipation Rating Table

−40°C to 150°C

−65°C to 150°C

260°C

Operating junction temperature range

Storage temperature range

Lead temperature (soldering, 10 sec)

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

PACKAGE DISSIPATION RATINGS

T

≤ 25°C

T

= 70°C

T = 85°C

A

POWER RATING

A

(1)

R

QJA

PACKAGE

POWER RATING

MSOP

QFN

60°C/W

1.67 W

917 mW

667 mW

48.7°C/W

2.05 W

1.13 W

821 mW

(1)

The thermal resistance, R

is based on a soldered PowerPAD using thermal vias.

ΘJA

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

V

Supply voltage

2.5

0.7

6.0

V

I

Output voltage range for adjustable output voltage version

Output current

V

I

O

I

O

1.2

A

(1)

L

Inductor

6.2

22

µH

µF

°C

(1)

C

Input capacitor

I

(1)

Output capacitor

O

T

A

Operating ambient temperature

Operating junction temperature

−40

85

T

125

J

(1)

Refer to application section for further information

2

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

ELECTRICAL CHARACTERISTICS

(1)

V = 3.6 V, V = 1.8 V, I = 600 mA, EN = VIN, T = −40°C to 85°C typical values are at T = 25°C (unless otherwise noted)

I

O

A

,

A

SUPPLY CURRENT

PARAMETER

TEST CONDITIONS

MIN

2.5

TYP

MAX

6.0

35

UNIT

V

Input voltage range

I

Operating quiescent current

Shutdown supply current

Under−voltage lockout threshold

I

O

= 0 mA, device is not switching

18

µA

V

(Q)

SD

EN = GND

0.1

1

V

1.5

1.4

2.3

UVLO

ENABLE AND MODE

V

EN high level input voltage

EN low level input voltage

EN input bias current

V

EN

0.4

1.0

EN

I

EN = GND or VIN

0.01

µA

V

EN

V

MODE high level input voltage

MODE low level input voltage

MODE input bias current

1.4

(MODE)

0.4

1.0

V

I

MODE = GND or VIN

µA

POWER SWITCH

P-channel MOSFET on−resistance

V = V

= 3.6 V

= 2.5 V

115

145

210

270

1

mΩ

µA

mΩ

µA

A

I

GS

r

DS(ON)

P-channel MOSFET on−resistance

P-channel leakage current

N-channel MOSFET on−resistance

N-channel leakage current

P-channel current limit

V = V

I

GS

I

V

= 6.0 V

lkg(P)

DS

V = V

= 3.6 V

= 2.5 V

85

200

280

1

I

GS

r

DS(ON)

V = V

I

115

I

V

= 6.0 V

Ikg(N)

DS

2.5 V < V < 6.0 V

1.5 1.85

150

2.2

L

I

Thermal shutdown

°C

OSCILLATOR

V

= 0.5 V

= 0 V

1

1.25

625

1.5

MHz

kHz

FB

f

S

Oscillator frequency

FB

OUTPUT

V

Adjustable output voltage range

Reference voltage

TPS62040

0.7

V

IN

V

O

V

ref

0.5

0%

3%

TPS62040 V = 2.5 V to 6.0 V; I = 0 mA

I

O

V

FB

Feedback voltage

Adjustable V = 2.5 V to 6.0 V; 0 mA ≤ I ≤ 1.2 A

−3%

I

O

0%

3%

TPS62042 V = 2.5 V to 6.0 V; I = 0 mA

I

O

1.5V

V = 2.5 V to 6.0 V; 0 mA ≤ I ≤ 1.2 A

I O

−3%

0%

3%

TPS62043 V = 2.5 V to 6.0 V; I = 0 mA

I

O

1.6V

V = 2.5 V to 6.0 V; 0 mA ≤ I ≤ 1.2 A

I O

−3%

V

O

Fixed output voltage

0%

3%

TPS62044 V = 2.5 V to 6.0 V; I = 0 mA

I

O

1.8V

V = 2.5 V to 6.0 V; 0 mA ≤ I ≤ 1.2 A

I O

−3%

0%

3%

TPS62046 V = 3.6 V to 6.0 V; I = 0 mA

I

O

3.3V

V = 3.6 V to 6.0 V; 0 mA ≤ I ≤ 1.2 A

I O

−3%

V = V + 0.5 V (min. 2.5 V) to 6.0 V,

I

O

(1)

Line regulation

0

%/V

I

O

= 10 mA

(1)

Load regulation

I

= 10 mA to 1200 mA

0

0.1

625

%/mA

µA

O

Leakage current into SW pin

V >V , 0 V ≤ Vsw ≤ V

I

1

I

O

I

f

Ikg(SW)

Reverse leakage current into pin SW

Short circuit switching frequency

V = open; EN = GND; V

SW

= 6.0 V

µA

I

V

= 0 V

kHz

FB

(1)

The line and load regulations are digitally controlled to assure an output voltage accuracy of 3%.

3

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

PIN ASSIGNMENTS

DGQ PACKAGE

(TOP VIEW)

DRC PACKAGE

(TOP VIEW)

PGND

SW

EN

VIN

GND

FB

1

2

3

4

5

10

9

1

2

3

4

5

10

9

EN

VIN

GND

FB

PGND

SW

8

SW

MODE

7

SW

6

MODE

:

NOTE The PowerPAD must be connected to GND.

Terminal Functions

TERMINAL

NAME NO.

EN

I/O

DESCRIPTION

1

I

Enable. Pulling EN to ground forces the device into shutdown mode. Pulling EN to V enables the device. EN should

I

not be left floating and must be terminated.

VIN

GND

FB

2,3

4

I

Supply voltage input

Analog ground

5

I

Feedback pin. Connect FB directly to the output if the fixed output voltage version is used. For the adjustable version

an external resistor divider is connected to this pin. The internal voltage divider is disabled for the adjustable version.

MODE

6

Pulling the MODE pin high allows the device to be forced into fixed frequency operation. Pulling the MODE pin to low

enables the power save mode where the device operates in fixed frequency PWM mode at high load currents and

in PFM mode (pulse frequency modulation) at light load currents.

SW

7,8

I/O This is the switch pin of the converter and is connected to the drain of the internal power MOSFETs

Power ground

PGND

9,10

4

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

FUNCTIONAL BLOCK DIAGRAM

VIN

Current limit Comparator

Ref

VIN

Undervoltage

Lockout

Bias supply

+

−

Soft

Start

EN

+

SkipComparator

Ref

−

V

MODE

Vcomp

1.25 MHz

Oscillator

I

Comparator

S

R

SW

Driver

Shoot−thru

Logic

+

−

Control Logic

Saw Tooth

Generator

Comp High

Comp Low

Comp Low 2

Comp High

LoadComparator

−

+

R1

R2

Gm

Compensation

+

−

Comp Low

+

−

Comp Low 2

Vref = 0.5 V

FB

PGND

MODE

GND

For the Adjustable Version the FB Pin Is

Directly Connected to the Gm Amplifier

5

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

η

Efficiency

vs Load current

vs Input voltage

1, 2, 3

4

Efficiency

I

Quiescent current

Switching frequency

5, 6

7

Q

s

f

r

P-Channel r

DS(on)

8

DS(on)

r

N-Channel rectifier r

)

9

DS(on

Load transient response

PWM operation

Power save mode

Start-up

10

11

12

13

EFFICIENCY

vs

EFFICIENCY

vs

LOAD CURRENT

100

95

90

85

80

75

70

65

60

55

50

45

40

V

= 3.3 V

V

= 1.8 V

O

95

90

85

80

75

70

65

V = 2.7 V

I

V = 3.6 V

I

MODE = Low

V = 3.6 V

I

V = 5 V

I

V = 5 V

I

MODE = Low

V = 3.6 V

I

MODE = High

MODE = Low

V = 3.6 V

I

60

55

50

V = 5 V

I

MODE = High

45

40

0

0.01 0.1

1

10

100

1 k 10 k

0

0.01

0.1

1

10

100

1 k

10 k

I

L

− Load Current − mA

I

L

− Load Current − mA

Figure 1

Figure 2

6

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

EFFICIENCY

vs

EFFICIENCY

vs

LOAD CURRENT

INPUT VOLTAGE

100

95

90

85

80

V

= 1.5 V

V

= 1.8 V

O

95

90

85

MODE = Low

V = 2.7 V

I

L

= 500 mA

V = 3.6 V

I

80

75

70

65

60

55

50

45

40

V = 5 V

I

L

= 1000 mA

I

L

= 1 mA

75

70

0

0.01

0.1

1

10

100

1 k

10 k

2.5

3

3.5

4

4.5

5

5.5

6

I

L

− Load Current − mA

V − Input Voltage − V

I

Figure 3

Figure 4

QUIESCENT CURRENT

vs

QUIESCENT CURRENT

vs

INPUT VOLTAGE

23

21

19

17

15

13

11

9

7.5

7

MODE = Low

MODE = High

T

= 85°C

= 25°C

= −40°C

A

6.5

6

T

A

= 25°C

A

T

A

5.5

5

4.5

4

7

5

3.5

3

2.5

3

3.5

4

4.5

5

5.5

6

2.4 2.8 3.2 3.6

4

4.4 4.8 5.2 5.6

6

V − Input Voltage − V

I

V − Input Voltage − V

I

Figure 5

Figure 6

7

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

SWITCHING FREQUENCY

vs

P-CHANNEL r

vs

DS(on)

INPUT VOLTAGE

0.180

0.170

0.160

0.150

0.140

0.130

1.23

1.22

1.21

1.20

1.19

T

= 85°C

A

T

A

= 25°C

T

= 85°C

A

T

A

= 25°C

T

A

= −40°C

0.120

0.110

0.100

T

= −40°C

A

0.090

0.080

1.18

2.5 2.9 3.3 3.7 4.1 4.5

4.9 5.3 5.7

6

2.5 2.9 3.3 3.7 4.1 4.5

4.9 5.3 5.7

6

V − Input Voltage − V

I

V − Input Voltage − V

I

Figure 7

Figure 8

N-CHANNEL RECTIFIER r

vs

DS(on)

INPUT VOLTAGE

0.150

0.140

0.130

0.120

T

A

= 85°C

T

A

= 25°C

0.110

0.100

0.090

0.080

0.070

T

A

= −40°C

0.060

0.050

2.5 2.9 3.3 3.7 4.1 4.5

4.9 5.3 5.7

6

V − Input Voltage − V

I

Figure 9

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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003

PWM OPERATION

LOAD TRANSIENT RESPONSE

V = 3.6 V

I

O

V

= 1.8 V

PWM/PFM Operation

500 ns/div

50 µs/div

Figure 10

Figure 11

POWER SAVE MODE

START-UP

V = 3.6 V

I

O

V

I

= 1.8 V

= 1.1 A

200 µs/div

2.5 µs/div

Figure 12

Figure 13

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DETAILED DESCRIPTION

OPERATION

The TPS6204x is a synchronous step-down converter operating with typically 1.25 MHz fixed frequency. At moderate

to heavy load currents, the device operates in pulse width modulation (PWM), and at light load currents, the device

enters power save mode operation using pulse frequency modulation (PFM). When operating in PWM mode, the

typical switching frequency is 1.25 MHz with a minimum switching frequency of 1 MHz. This makes the device

suitable for xDSL applications minimizing RF (radio frequency) interference.

During PWM operation the converter uses a unique fast response voltage mode controller scheme with input voltage

feed−forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors.

At the beginning of each clock cycle initiated by the clock signal (S) the P-channel MOSFET switch turns on and the

inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit

comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time

preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down.

The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel

switch.

The Gm amplifier as well as the input voltage determines the rise time of the saw tooth generator, and therefore, any

change in input voltage or output voltage directly controls the duty cycle of the converter, giving a very good line and

load transient regulation.

POWER SAVE MODE OPERATION

As the load current decreases, the converter enters power save mode operation. During power save mode the

converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current

maintaining high efficiency.

The converter monitors the average inductor current and the device enters power save mode when the average

inductor current is below the threshold. The transition point between PWM and power save mode is given by the

transition current with the following equation:

V

I

18.66 W

I

+

transition

(1)

During power save mode the output voltage is monitored with the comparator by the threshold’s comp low and comp

high. As the output voltage falls below the comp low threshold set to typically 0.8% above the nominal output voltage,

the P-channel switch turns on. The P-channel switch remains on until the transition current (1) is reached. Then the

N-channel switch turns on completing the first cycle. The converter continues to switch with its normal duty cycle

determined by the input and output voltage but with half the nominal switching frequency of 625-kHz typ. Thus the

output voltage rises and as soon as the output voltage reaches the comp high threshold of 1.6%, the converter stops

switching. Depending on the load current, the converter switches for a longer or shorter period of time in order to

deliver the energy to the output. If the load current increases and the output voltage can not be maintained with the

transition current , equation (1), the converter enters PWM again. See Figure 11 and Figure 12 under the typical

graphs section and Figure 14 for power save mode operation. Among other techniques this advanced power save

mode method allows high efficiency over the entire load current range and a small output ripple of typically 1% of

the nominal output voltage.

Setting the power save mode thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load

current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient

changes. This allows the converter to operate with small output capacitors like 22 µF and still having a low absolute

voltage drop during heavy load transient. Refer to Figure 14 as well for detailed operation of the power save mode.

10

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PFM Mode at Light Load

Comp High

Comp Low

1.6%

0.8%

V

O

Comp Low 2

PWM Mode at Medium to Full Load

Figure 14. Power Save Mode Thresholds and Dynamic Voltage Positioning

The converter enters the fixed frequency PWM mode as soon as the output voltage falls below the comp low 2

threshold.

DYNAMIC VOLTAGE POSITIONING

As described in the power save mode operation sections before and as detailed in Figure 14 the output voltage is

typically 0.8% (i.e., 1% on average) above the nominal output voltage at light load currents, as the device is in power

save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load.

In the other direction during a load transient from full load to light load the voltage overshoot is also minimized by

turning on the N-Channel rectifier switch to pull the output voltage actively down.

MODE (AUTOMATIC PWM/PFM OPERATION AND FORCED PWM OPERATION)

Connecting the MODE pin to GND enables the automatic PWM and power save mode operation. The converter

operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,

maintaining high efficiency over a wide load current range.

Pulling the MODE pin high forces the converter to operate constantly in the PWM mode even at light load currents.

The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching

frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode

during light loads (see Figure 1 to Figure 3). For additional flexibility it is possible to switch from power save mode

to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the

TPS6204x to the specific system requirements.

100% DUTY CYCLE LOW DROPOUT OPERATION

The TPS6204x offers a low input to output voltage difference while still maintaining regulation with the use of the 100%

duty cycle mode. In this mode, the P−Channel switch is constantly turned on. This is particularly useful in battery

powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range.

i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be

calculated as:

_maxǒ_{rDS(on) max ) R}Ǔ

V min + V max ) I

I

O

L

(2)

with:

I

= maximum output current plus inductor ripple current

O(max)

r

max= maximum P-channel switch t

.

DS(on)

R = DC resistance of the inductor

L

V max = nominal output voltage plus maximum output voltage tolerance

O

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SOFTSTART

The TPS6204x series has an internal softstart circuit that limits the inrush current during start up. This prevents

possible voltage drops of the input voltage in case a battery or a high impedance power source is connected to the

input of the TPS6204x.

The softstart is implemented with a digital circuit increasing the switch current in steps of typically I /8, I /4, I /2

LIM

and then the typical switch current limit 1.85 A as specified in the electrical parameter table. The start-up time mainly

depends on the output capacitor and load current, see Figure 13.

SHORT-CIRCUIT PROTECTION

As soon as the output voltage falls below 50% of the nominal output voltage, the converter switching frequency as

well as the current limit is reduced to 50% of the nominal value. Since the short-circuit protection is enabled during

start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds 50%

of the nominal output voltage. This needs to be considered in case a load acting as a current sink is connected to

the output of the converter.

THERMAL SHUTDOWN

As soon as the junction temperature of typically 150_C is exceeded the device goes into thermal shutdown. In this

mode, the P-Channel switch and N-Channel rectifier are turned off. The device continues its operation when the

junction temperature falls below typically 150°C again.

ENABLE

Pulling the EN low forces the part into shutdown mode, with a shutdown current of typically 0.1 µA. In this mode, the

P-Channel switch and N-Channel rectifier are turned off and the whole device is in shut down. If an output voltage

is present during shut down, which could be an external voltage source or super cap, the reverse leakage current

is specified under electrical parameter table. For proper operation the enable (EN) pin must be terminated and should

not be left floating.

Pulling EN high starts up the TPS6204x with the softstart as described under the section Softstart.

UNDERVOLTAGE LOCKOUT

The undervoltage lockout circuit prevents device misoperation at low input voltages. It prevents the converter from

turning on the switch or rectifier MOSFET with undefined conditions.

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APPLICATION INFORMATION

ADJUSTABLE OUTPUT VOLTAGE VERSION

When the adjustable output voltage version TPS62040 is used, the output voltage is set by the external resistor

divider. See Figure 15.

The output voltage is calculated as:

R1

R2

_{+ 0.5 V}ǒ_{1 )}Ǔ

V

O

(3)

with R1 + R2 ≤ 1 MΩ and internal reference voltage V typical = 0.5 V

ref

R1 + R2 should not be greater than 1 MΩ because of stability reasons. To keep the operating quiescent current to

a minimum, the feedback resistor divider should have high impedance with R1+R2≤1 MΩ. Due to this and the low

reference voltage of V = 0.5 V, the noise on the feedback pin (FB) needs to be minimized. Using a capacitive divider

ref

C1 and C2 across the feedback resistors minimizes the noise at the feedback, without degrading the line or load

transient performance.

C1 and C2 should be selected as:

1

C1 +

2 p 10 kHz R1

(4)

with:

R1 = upper resistor of voltage divider

C1 = upper capacitor of voltage divider

For C1 a value should be chosen that comes closest to the calculated result.

R1

C2 +

C1

(5)

R2

with:

R2 = lower resistor of voltage divider

C2 = lower capacitor of voltage divider

For C2, the selected capacitor value should always be selected larger than the calculated result. For example, in

Figure 15 for C2 100 pF are selected for a calculated result of C2 = 88.42 pF.

If quiescent current is not a key design parameter C1 and C2 can be omitted, and a low impedance feedback divider

has to be used with R1 + R2 < 100 kΩ. This reduces the noise available on the feedback pin (FB) as well but increases

the overall quiescent current during operation. The higher the programmed output voltage the lower the feedback

impedance has to be for best operation when not using C1 and C2.

V

O

L1

I

TPS62040

1.8 V / 1.2 A

10 µH

2.5 V to 6 V

8

7

2

3

1

6

4

SW

VIN

SW

FB

VIN

C3

10 µF

C4

10 µF

5

EN

R1

470 kΩ

C1

33 pF

10

9

PGND

MODE

GND

PGND

R2

180 kΩ

C2

100 pF

Figure 15. Adjustable Output Voltage Version

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Inductor Selection

The TPS6204x typically uses a 6.2-µH output inductor. Larger or smaller inductor values can be used to optimize

the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc

resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of the

converter. Therefore an inductor with the lowest dc resistance should be selected for highest efficiency.

Formula (7) calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with formula (7). This is needed

because during heavy load transient the inductor current rises above the value calculated under (7).

V

O

1–

V

I

DI + V

L

O

L ƒ

(6)

(7)

DI

L

I max + I max )

L

O

2

with

ƒ = Switching frequency (1.25 MHz typical)

L = Inductor value

∆I = Peak-to-peak inductor ripple current

L

I max = Maximum inductor current

L

The highest inductor current occurs at maximum V .

I

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus

a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the

maximum switch current of 2.2 A for the TPS6204x. Keep in mind that the core material from inductor to inductor

differs and has an impact on the efficiency, especially at high switching frequencies. Refer to Table 1 and the typical

applications and inductors selection.

Table 1. Inductor Selection

INDUCTOR VALUE

4.7 µH

DIMENSIONS

COMPONENT SUPPLIER

Sumida CDRH4D28C-4.7

Coiltronics SD25-4R7

5,0 mm × 5,0 mm × 3,0 mm

5,2 mm × 5,2 mm × 2,5 mm

5,7 mm × 5,7 mm × 3,0 mm

7,0 mm × 7,0 mm × 3,0 mm

4.7 µH

5.3 µH

Sumida CDRH5D28-5R3

Sumida CDRH5D28-6R2

Sumida CDRH6D28-6R0

6.2 µH

6.0 µH

14

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Output Capacitor Selection

The advanced fast response voltage mode control scheme of the TPS6204x allows the use of small ceramic

capacitors with a typical value of 22 µF without having large output voltage under and overshoots during heavy load

transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended.

If required, tantalum capacitors may also be used. Refer to Table 2 for component selection.

If ceramic output capacitor are used, the capacitor RMS ripple current rating always meets the application

requirements. Just for completeness the RMS ripple current is calculated as:

V

O

1–

V

I

1

I

+ V

RMSCout

O

Ǹ

L ƒ

2 3

(8)

At nominal load current the device operates in PWM mode and the overall output voltage ripple is the sum of the

voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the

output capacitor:

V

O

1–

V

I

1

DV + V

) ESR

ǒ

Ǔ

O

L ƒ

8 C ƒ

O

(9)

Where the highest output voltage ripple occurs at the highest input voltage, V .

I

At light load currents, the device operates in power save mode and the output voltage ripple is independent of the

output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical output

voltage ripple is 1% of the nominal output voltage.

Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required

for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes.

The input capacitor should have a minimum value of 22 µF. The input capacitor can be increased without any limit

for better input voltage filtering.

Table 2. Input and Output Capacitor Selection

CAPACITOR

CASE SIZE

COMPONENT SUPPLIER

COMMENTS

VALUE

22 µF

1206

1210

Taiyo Yuden JMK316BJ226ML

Taiyo Yuden JMK325BJ226MM

Ceramic

22 µF

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Layout Considerations

For all switching power supplies, the layout is an important step in the design especially at high peak currents and

switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI

problems. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 16. These

traces should be routed first. The input capacitor should be placed as close as possible to the IC pins as well as the

inductor and output capacitor. The feedback resistor network should be routed away from the inductor and switch

node to minimize noise and magnetic interference. To further minimize noise from coupling into the feedback network

and feedback pin, the ground plane or ground traces should be used for shielding. A common ground plane or a star

ground as shown below should be used. This becomes very important especially at high switching frequencies of

1.25 MHz.

The Switch Node Must Be

Kept as Small as Possible

L1

10 µH

TPS6204x

V

O

I

8

7

2

3

1

6

4

SW

VIN

SW

FB

VIN

EN

C3

22 µF

C2

22 µF

5

10

PGND

MODE

GND

9

PGND

Figure 16. Layout Diagram

THERMAL INFORMATION

One of the most influential components on the thermal performance of a package is board design. In order to take

full advantage of the heat dissipating abilities of the PowerPADt packages, a board should be used that acts similar

to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. For further information

please refer to Texas Instruments application note (SLMA002) PowerPAD Thermally Enhanced Package.

The PowerPADt of the 10-pin MSOP package has an area of 1,52 mm × 1,79 mm ( 0,05 mm) and must be soldered

to the PCB to lower the thermal resistance. Thermal vias to the next layer further reduce the thermal resistance.

16

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TYPICAL APPLICATIONS

V

TPS62046

SW

O

I

L1

6.2 µH

3.3 V / 1.2 A

Li-lon

8

7

2

3

1

6

4

VIN

SW

FB

VIN

C1

22 µF

C2

5

EN

22 µF

10

PGND

MODE

GND

9

PGND

Components:

C1: Taiyo Yuden JMK316BJ226ML

C2: Taiyo Yuden JMK316BJ226ML

L1: Sumida CDRH5D28−6R2

Figure 17. Li-Ion to 3.3 V/1.2 A Conversion

V

O

L1

I

TPS62040

1.8 V / 1.2 A

4.7 µH

2.5 V to 6 V

8

2

3

1

6

4

SW

VIN

EN

7

5

SW

FB

C3

22 µF

C4

R1

22 µF

C1

33 µF

10

9

PGND

470 kΩ

MODE

GND

PGND

Components:

C1: Taiyo Yuden JMK316BJ226ML

C2: Taiyo Yuden JMK316BJ226ML

L1: Sumida CDRH4D28C−4R7

R2

180 kΩ

C2

100 µF

Figure 18. Li-Ion to 1.8 V/1.2 A Conversion Using the Adjustable Output Voltage Version

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THERMAL PAD MECHANICAL DATA

PowerPADt PLASTIC SMALL-OUTLINE

DGQ (S−PDSO−G10)

18

IMPORTANT NOTICE

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Post Office Box 655303 Dallas, Texas 75265


型号：	TPS62040
厂家：	TEXAS INSTRUMENTS
描述：	1.2 A/1.25 MHZ, HIGH EFFICIENCY STEP DOWN CONVERTER 1.2 A / 1.25MHz的，高效率的降压转换器转换器功效
文件：	总21页 (文件大小：370K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS62040 [TI]

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