TPS62067DSGT [TI]
3-MHz 2A Step Down Converter in 2x2 SON Package; 3 MHz的2A降压转换器采用2x2 SON封装
| 型号： | TPS62067DSGT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-MHz 2A Step Down Converter in 2x2 SON Package |
| 文件： | 总26页 (文件大小：1159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62065, TPS62067
www.ti.com
SLVS833A –MARCH 2010–REVISED MAY 2010
3-MHz 2A Step Down Converter in 2x2 SON Package
Check for Samples: TPS62065, TPS62067
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
•
•
•
•
•
•
3 MHz Switching Frequency
VIN Range from 2.9V to 6V
The TPS6206x is
synchronous step down DC-DC converters. They
provide up to 2.0A output current.
a family of highly efficient
Up to 97% Efficiency
Power Save Mode / 3MHz Fixed PWM Mode
Power Good Output
With an input voltage range of 2.9V to 6V the device
is a perfect fit for power conversion from a 5V or 3.3V
system supply rail. The TPS6206x operates at 3MHz
fixed frequency and enters Power Save Mode
operation at light load currents to maintain high
efficiency over the entire load current range. The
Power Save Mode is optimized for low output voltage
ripple. For low noise applications, TPS62065 can be
forced into fixed frequency PWM mode by pulling the
MODE pin high. TPS62067 provides an open drain
power good output.
Output Voltage Accuracy in PWM Mode ±1.5%
Output Capacitor Discharge Function
Typical 18 µA Quiescent Current
100% Duty Cycle for Lowest Dropout
Voltage Positioning
Clock Dithering
Supports Maximum 1mm Height Solutions
Available in a 2x2x0.75mm SON
In the shutdown mode, the current consumption is
reduced to less than 1µA and an internal circuit
discharges the output capacitor.
APPLICATIONS
•
•
•
•
POL
TPS6206x family is optimized for operation with a tiny
1.0µH inductor and a small 10µF output capacitor to
achieve smallest solution size and high regulation
performance.
Notebooks, Pocket PCs
Portable Media Players
DSP Supply
The TPS6206X is available in a small 2x2x0.75mm
8-pin SON package.
100
TYPICAL APPLICATION CIRCUIT
VIN = 3.7 V
95
90
VIN = 5 V
VIN = 4.2 V
TPS62067
L
1.0 mH
VOUT
85
80
VIN = 2.9 V to 6 V
1.8 V 2 A
PVIN
SW
AVIN
R1
75
70
RPG
100 kW
360 kW
CIN
Cff
COUT
EN
FB
22 pF
10 mF
10 mF
R2
AGND
65
60
180 kW
PGND
PG
L = 1.2 mH (NRG4026T 1R2),
COUT = 22 mF (0603 size),
VOUT = 3.3 V,
55
50
Mode: Auto PFM/PWM
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
IL - Load Current - A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS62065, TPS62067
SLVS833A –MARCH 2010–REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
FUNCTION
MAXIMUM
OUTPUT
CURRENT
PART
NUMBER
OUTPUT
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TA
ORDERING(3)
VOLTAGE(2)
MODE
Power Good
(PG)
TPS62065
TPS62067
Adjustable
Adjustable
Selectable
No
2.0 A
2.0 A
DSG
DSG
TPS62065DSG
TPS62067DSG
OFA
ODH
–40°C to
85°C
Auto
PWM/PFM
Yes
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Contact TI for other fixed output voltage options
(3) The DSG (SON-8) packages is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
MIN
–0.3
MAX
(2)
Voltage Range
AVIN, PVIN
EN, MODE, PG, FB
SW
7
–0.3 to
–0.3
VIN +0.3 < 7
V
7
1
Current (sink)
into PG
mA
A
Current (source)
Peak output
Internally limited
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)(3)
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)
Electrostatic Discharge (Machine model)
2
kV
1
200
125
150
V
TJ
–40
–65
°C
°C
Temperature
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS(1)(2)
POWER RATING
TA = ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
PACKAGE
RqJA
DSG
75°C/W
1300 mW
13 mW/°C
(1) Maximum power dissipation is a function of TJ(max), qJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/ qJA
(2) This thermal data measured with high-K board (4 layers according to JESD51-7 JEDEC Standard).
.
2
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Product Folder Link(s) :TPS62065 TPS62067
TPS62065, TPS62067
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SLVS833A –MARCH 2010–REVISED MAY 2010
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
AVIN
PVIN
,
Supply voltage
2.9
6
V
Output current capability
2000
VIN
1.6
22
mA
V
Output voltage range for adjustable voltage
Effective Inductance Range
0.8
0.7
L
1.0
10
µH
µF
°C
°C
COUT
TA
Effective Output Capacitance Range
Operating ambient temperature(1)
Operating junction temperature
4.5
–40
–40
85
TJ
125
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the
part/package in the application (qJA), as given by the following equation: TA(max)= TJ(max)–(qJA X PD(max)
)
ELECTRICAL CHARACTERISTICS
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6V. External components CIN = 10mF 0603, COUT = 10mF 0603, L = 1.0mH, see the parameter
measurement information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
2.9
6
V
IOUT = 0 mA, device operating in PFM mode
and not device not switching
IQ
Operating quiescent current
Shutdown current
18
mA
mA
ISD
EN = GND, current into AVIN and PVIN combined
0.1
1.78
1.95
1
1.83
1.99
Falling
Rising
1.73
1.9
VUVLO
Undervoltage lockout threshold
V
ENABLE, MODE
VIH
VIL
IIN
High level input voltage
2.9 V ≤ VIN ≤ 6 V
1.0
0
6
0.4
1
V
V
Low level input voltage
Input bias current
2.9 V ≤ VIN ≤ 6 V
EN, Mode tied to GND or AVIN
0.01
mA
POWER GOOD OPEN DRAIN OUTPUT
Rising feedback voltage
93%
87%
95%
90%
98%
92%
0.3
VTHPG
Power good threshold voltage
Falling feedback voltage
IOUT = –1mA; must be limited by external pullup
VOL
VH
Output low voltage
Output high voltage
V
V
(1)
resistor
Voltage applied to PG pin via external pullup
resistor
VIN
ILKG
Leakage current into PG pin
Internal power good delay time
V(PG) = 3.6V
100
nA
µs
tPGDL
5
POWER SWITCH
(1)
VIN = 3.6 V
120
95
180
150
130
100
RDS(on)
High-side MOSFET on-resistance
mΩ
VIN = 5.0 V(1)
VIN = 3.6 V(1)
VIN = 5.0 V(1)
90
RDS(on)
ILIMF
Low-side MOSFET on-resistance
mΩ
mA
°C
75
Forward current limit MOSFET
high-side and low-side
2.9V ≤ VIN ≤ 6 V
2300
2750
3300
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
TSD
Thermal shutdown hysteresis
10
(1) Maximum value applies for TJ = 85°C
Copyright © 2010, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted,
specifications apply for condition VIN = EN = 3.6V. External components CIN = 10mF 0603, COUT = 10mF 0603, L
= 1.0mH, see the parameter measurement information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
mV
OSCILLATOR
fSW
Oscillator frequency
2.9 V ≤ VIN ≤ 6 V
2.6
3
3.4
OUTPUT
Vref
Reference voltage
600
0
PWM operation, MODE = VIN
,
VFB(PWM)
VFB(PFM)
Feedback voltage PWM Mode
–1.5
1.5
2.9 V ≤ VIN ≤ 6 V, 0 mA load
device in PFM mode, voltage positioning active(2)
%
Feedback voltage PFM mode,
Voltage Positioning
1
Load regulation
Line regulation
-0.5
0
%/A
%/V
VFB
Activated with EN = GND, 2.9V ≤ VIN≤ 6V, 0.8 ≤
75
200
1450
R(Discharge)
tSTART
Internal discharge resistor
Start-up time
Ω
VOUT≤ 3.6V
Time from active EN to reach 95% of VOUT
500
ms
(2) In PFM mode, the internal reference voltage is set to typ. 1.01×Vref. See the parameter measurement information.
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
SON 2x2-8
NAME
PGND
1
2
3
4
PWR GND supply pin for the output stage.
This is the switch pin and is connected to the internal MOSFET switches. Connect the
external inductor between this terminal and the output capacitor.
SW
OUT
IN
AGND
FB
Analog GND supply pin for the control circuit.
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin.
In case of fixed output voltage option, connect this pin directly to the output capacitor
IN
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown
mode. Pulling this pin to high enables the device. This pin must be terminated
EN
5
IN
IN
MODE: MODE pin = high forces the device to operate in fixed frequency PWM mode. MODE
pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed
frequency PWM mode. This pin must be terminated.
MODE
PG
6
Open PG: Power Good Open Drain output. Connect an external pull up resistor to a rail which is
Drain below or equal AVIN
.
Analog VIN power supply for the control circuit. Need to be connected to PVIN and input
capacitor.
AVIN
7
8
IN
PVIN
PWR VIN power supply pin for the output stage.
For good thermal performance, this PAD must be soldered to the land pattern on the pcb.
This PAD should be used as device GND.
Power PAD
4
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Product Folder Link(s) :TPS62065 TPS62067
TPS62065, TPS62067
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SLVS833A –MARCH 2010–REVISED MAY 2010
FUNCTIONAL BLOCK DIAGRAM
AVIN
PVIN
Current
Limit Comparator
Undervoltage
Lockout 1.8V
Thermal
Shutdown
Limit
High Side
PFM Comparator
Reference
0.6V VREF
FB
VREF
Softstart
VOUT RAMP
CONTROL
Gate Driver
Anti
Shoot-Through
Control
Stage
Error Amp.
VREF
SW
Integrator
FB
PWM
Comp.
Zero-Pole
AMP.
Internal
FB
Network*
Limit
Low Side
MODE *
PG
Sawtooth
Generator
3MHz
Clock
Current
Limit Comparator
MODE/
PG
FB
VREF
RDischarge
PG Comparator*
EN
PGND
AGND
* Function depends on device option
Vertical spacer
Vertical spacer
PARAMETER MEASUREMENT INFORMATION
L
VOUT
TPS6206X
VIN = 2.9 V to 6 V
1.0 µH/1.2 µH
up to 2.0 A
PVIN
SW
AVIN
R1
COUT
Cff
EN
FB
CIN
10 µF
MODE/PG
R2
10 µF
AGND
PGND
L: LQH44PN1R0NP0, L = 1.0 mH,Murata,
NRG4026T1R2, L = 1.2 mH, Taiyo Yuden
CIN/COUT: GRM188R60J106U, Murata 0603 size
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE
Load Current, VOUT = 1.2 V, Auto PF//PWM Mode, Linear Scale
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode, Linear Scale
Load Current, VOUT = 3.3 V, PFM/PWM Mode, Linear Scale
Figure 1
Figure 2
Figure 3
h
Efficiency
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode vs. Forced PWM
Mode, Logarithmic Scale
Figure 4
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode
Load Current, VOUT = 1.8 V, Forced PWM Mode
Input Voltage and Ambient Temperature
Input Voltage
Figure 5
Figure 6
Output Voltage Accuracy
Shutdown Current
Quiescent Current
Oscillator Frequency
Figure 7
Figure 8
Input Voltage
Figure 9
Input Voltage, Low-Side Switch
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Static Drain-Source On-State
Resistance
Input Voltage, High-Side Switch
RDISCHARGE
Input Voltage vs. VOUT
PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 mH, COUT = 10mF
PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 mH, COUT = 10mF
PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A
PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA
VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA
PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2-Ω
Typical Operation
Load Transient
Line Transient
Startup into Load
Startup TPS62067
Output Discharge
Shutdown TPS62067
Into 2.2-Ω Load with Power Good
VIN = 3.6 V, VOUT = 1.8 V, No Load
VIN = 4.2 V, VOUT = 3.3 V, No Load, PG Pullup Resistor 10 kΩ
6
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SLVS833A –MARCH 2010–REVISED MAY 2010
EFFICIENCY
vs
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
95
100
95
V
= 4.2 V
90
85
80
75
70
65
60
55
90
85
80
75
70
65
60
IN
V
= 5 V
IN
V
= 5 V
IN
V
= 4.2 V
IN
V
= 3 V
IN
V
= 3 V
V
= 3.3 V
IN
IN
V
= 3.6 V
IN
V
= 3.3 V
IN
V
= 3.6 V
IN
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
V
= 1.8 V,
V
= 1.2 V,
OUT
Mode: Auto PFM/PWM
OUT
Mode: Auto PFM/PWM
55
50
50
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
I
- Load Current - A
I
- Load Current - A
L
L
Figure 1. VOUT = 1.2V, Auto PFM/PWM Mode,
Linear Scale
Figure 2. VOUT = 1.8V, Auto PFM/PWM Mode,
Linear Scale
EFFICIENCY
vs
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
95
100
90
V
= 3.7 V
Auto PFM/PWM Mode
IN
90
85
80
75
70
65
60
80
70
60
50
40
30
20
10
0
V
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
V
= 5 V
IN
IN
V
= 4.2 V
IN
V
V
IN
IN
V
Forced PWM Mode
IN
V
V
V
V
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
IN
IN
IN
IN
L = 1.2 mH (NRG4026T 1R2),
COUT = 22 mF (0603 size),
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
V
= 3.3 V,
OUT
Mode: Auto PFM/PWM
55
50
V
= 1.8 V
OUT
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
0.001
0.01
0.1
- Load Current - A
1
10
I
- Load Current - A
I
L
L
Figure 3. VOUT = 3.3V, Auto PFM/PWM Mode,
Linear Scale
Figure 4. Auto PFM/PWM Mode vs. Forced PWM Mode,
Logarithmic Scale
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OUTPUT VOLTAGE ACCURACY
OUTPUT VOLTAGE ACCURACY
vs
vs
LOAD CURRENT
LOAD CURRENT
1.890
1.872
1.890
1.872
L = 1 mH,
COUT = 10 mF,
= 1.8 V,
V
OUT
Voltage Positioning PFM Mode
1.854
1.836
1.818
1.800
1.782
1.764
1.746
1.854
1.836
1.818
1.800
1.782
1.764
1.746
Mode: Forced PWM
PWM Mode
V
= 3.3 V
IN
V
= 3.6 V
IN
V
= 3.3 V
IN
V
= 4.2 V
IN
V
= 3.6 V
IN
V
= 5 V
IN
V
= 4.2 V
IN
L = 1 mH,
COUT = 10 mF,
= 1.8 V,
V
= 5 V
IN
V
OUT
1.728
1.710
1.728
1.710
Mode: Auto PFM/PWM
0.001
0.01
0.1
- Load Current - A
1
10
0.001
0.01
0.1
- Load Current - A
1
10
I
L
I
L
Figure 5. Auto PFM/PWM Mode
Figure 6. Forced PWM Mode
SHUTDOWN CURRENT
vs
QUIESCENT CURRENT
vs
INPUT VOLTAGE AND AMBIENT TEMPERATURE
INPUT VOLTAGE
1
0.75
0.50
25
20
15
10
T
= 85°C
A
T
= 85°C
A
T
= 25°C
A
T
= -40°C
A
T
= 25°C
0.25
A
5
0
T
= -40°C
A
0
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
I
I
Figure 7.
Figure 8.
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SLVS833A –MARCH 2010–REVISED MAY 2010
OSCILLATOR FREQUENCY
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.1
3.05
3
0.12
0.1
T
= 85°C
A
T
= 85°C
T
J
T
= 25°C
= 25°C
A
J
0.08
0.06
0.04
T
= -40°C
J
2.95
2.9
T
= -40°C
A
2.85
2.8
0.02
0
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
I
I
Figure 9.
Figure 10. Low-Side Switch
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
RDISCHARGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
0.2
0.18
0.16
0.14
0.12
0.1
600
500
400
300
200
V
= 3.3 V
O
T
= 85°C
T
J
= 25°C
J
V
= 1.8 V
T
= -40°C
O
J
0.08
0.06
0.04
V
= 1.2 V
O
100
0
0.02
0
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
2.5
3
3.5
4
4.5
V - Input Voltage - V
5
5.5
6
I
I
Figure 11. High-Side Switch
Figure 12.
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MODE = GND
L = 1.2 mH
= 10 mF
V
V
I
= 3.6 V
V
50mV/Div
IN
OUT
= 20 mA
OUT
= 1.8 V
V
50mV/Div
C
OUT
OUT
OUT
SW 2V/Div
SW 2V/Div
I
500mA/Div
COIL
MODE = GND
L = 1.2 mH
V
V
I
= 3.6 V
IN
OUT
= 500 mA
= 1.8 V
C
= 10 mF
OUT
I
200mA/Div
COIL
OUT
Time Base - 4ms/Div
Figure 14. Typical Operation (PFM Mode)
Time Base - 100ns/Div
Figure 13. Typical Operation (PWM Mode)
V
V
I
= 3.6 V,
IN
OUT
= 20 mA to 250 mA
= 1.2 V,
V
100 mV/Div
OUT
V
100 mV/Div
OUT
OUT
SW 2V/Div
SW 2V/Div
I
1A/Div
COIL
I
1A/Div
COIL
V
V
I
= 3.6 V,
IN
OUT
= 0.2 A to 1 A
= 1.2 V,
OUT
MODE = V
IN
I
500 mA/Div
LOAD
I
500 mA/Div
LOAD
Time Base - 10 µs/Div
Time Base - 10 µs/Div
Figure 15. Load Transient Response
PWM Mode 0.2A To 1A
Figure 16. Load Transient
PFM Mode 20 mA to 250mA
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VIN = 3.6 V to 4.2 V,
VOUT = 1.8 V,
IOUT = 500 mA
L = 1.2 mH,
200 mV/Div
500 mV/Div
2A/Div
V
V
= 3.6 V,
50 mV/Div
IN
= 1.8 V,
OUT
L = 1.2 mH
C
I
= 10 mF
OUT
200 mA to 1500 mA
1A/Div
OUT
Time Base - 100 ms/Div
Time Base - 100ms/Div
Figure 17. Load Transient Response
200 mA To 1500 mA
Figure 18. Line Transient Response PWM Mode
2 V/Div
500 mV/Div
1 V/Div
2 A/Div
500 mA/Div
500 mA/Div
V
V
I
= 3.6 V to 4.2 V,
= 1.8 V,
IN
50 mV/Div
OUT
V
V
= 3.6 V,
L = 1.2 mH,
= 10 mF
IN
= 50 mA,
OUT
C
= 1.8 V,
OUT
OUT
L = 1.2 mH,
C
Load = 2R2
= 10 mF
OUT
Time Base - 100 ms/Div
Time Base - 100 ms/Div
Figure 19. Line Transient PFM Mode
Figure 20. Startup Into Load – VOUT 1.8V
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EN
1 V/Div
V
V
= 3.6 V,
IN
= 1.8 V,
= 10 mF,
OUT
C
OUT
No Load
2 V/Div
2 V/Div
SW
2 V/Div
V
OUT
1 A/Div
1 V/Div
V
= 4.2 V,
IN
V
= 3.3 V,
OUT
Load = 2R2
PG Pullup resistor 10 kW
2 V/Div
Time Base - 2ms/Div
Time Base - 100 ms/Div
Figure 21. Startup TPS62067 into 2.2-Ω Load with Power
Figure 22. Output Discharge
Good
V
V
= 4.2 V,
IN
= 3.3 V,
OUT
Load = no load
PG Pullup resistor 10 kW
2 V/Div
2 V/Div
5 V/Div
Time Base - 1 ms/Div
Figure 23. Shutdown TPS62067
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DETAILED DESCRIPTION
OPERATION
The TPS6206x step down converter operates with typically 3MHz fixed frequency pulse width modulation (PWM)
at moderate to heavy load currents. At light load currents the converter can automatically enter Power Save
Mode and operates then in PFM (Pulse Frequency Mode) mode.
During PWM operation the converter use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is
turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor
to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the
control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current
limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low
Side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the
inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET
rectifier..
The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on
the High Side MOSFET switch.
POWER SAVE MODE
At TPS62065 pulling the Mode pin low enables Power Save Mode. In TPS62067 Power Save Mode is enabled
per default. If the load current decreases, the converter enters Power Save Mode operation automatically. During
Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a
minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically +1%
above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden
load step.
The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUTnominal +1%, the device starts a PFM current pulse. For this the High
Side MOSFET switch will turn on and the inductor current ramps up. After the On-time expires the switch will be
turned off and the Low Side MOSFET switch will be turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with typ. 18µA current consumption.
In case the output voltage is still below the PFM comparator threshold, further PFM current pulses will be
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold due to the load current.
The PFM mode is exited and PWM mode entered in case the output current can no longer be supported in PFM
mode.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
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Output voltage
Vout +1%
PFM Comparator
threshold
Voltage Positioning
Light load
PFM Mode
Vout (PWM)
moderate to heavy load
PWM Mode
Figure 24. Power Save Mode Operation with automatic Mode transition
100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage.
In order to maintain the output voltage, the High-Side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN the High-Side MOSFET switch is turned on completely. In this case the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (RDS(on)max + RL)
With:
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on)
RL = DC resistance of the inductor
.
VOmax = nominal output voltage plus maximum output voltage tolerance
Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
under-voltage lockout threshold VUVLO. The under-voltage lockout threshold VUVLO for falling VIN is typically
1.78V. The device starts operation once the rising VIN trips under-voltage lockout threshold VUVLO again at
typically 1.95V.
Output Capacitor Discharge
With EN = GND, the device enters shutdown mode and all internal circuits are disabled. The SW pin is
connected to PGND via an internal resistor to discharge the output capacitor. This feature ensures a startup in a
discharged output capacitor once the converter is enabled again and prevents "floating" charge on the output
capacitor. The output voltage ramps up monotonic starting from 0V.
MODE SELECTION (TPS62065)
The MODE pin allows mode selection between forced PWM mode and Power Save Mode.
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Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light
load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode,
the efficiency is lower compared to the power save mode during light loads.
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
In device options where the MODE Pin is replaced with Power Good output, the Power Save Mode is enabled
per default.
POWER GOOD OUTPUT (TPS62067)
This function is available in the TPS62067. The Power Good Output is an open-drain output and requires an
external pull-up resistor. The circuit is active once the device is enabled and AVIN is above the undervoltage
lockout threshold VUVLO. It is driven by an internal comparator connected to the FB voltage. The PG output
provides a high level once the feedback voltage exceeds typically 95% of its nominal value. The PG output is
driven to low level once the feedback voltage falls below typically 90% of its nominal value. The PG output is
activated with an internal delay of 5µs.
The PG open-drain output transistor is turned on immediately with EN = low level and pulls the output low. The
external pull up resistor can be connected to any voltage rail lower or equal the voltage applied to AVIN of the
device. The value of the pull-up resistor must be carefully selected in order to limit the current into the PG pin to
maximum 1.0mA. The external pull up resistor can be connected to VOUT or another voltage rail which does not
exceed the VIN level. The current flowing through the pull up resistor impacts the current consumption of the
application circuit in shutdown mode.
The shut down current of the device does not include the current through the external pull-up and internal
open-drain stage. The PG signal can be used for sequencing various converters or to reset a microcontroller.
EN
Overload
Startup
95%
90%
VOUT
PG
Output
discharge
t
Ramp
t
Start
WithEN = low
PG --> low
Figure 25. Power Good Output PG
ENABLE
The device is enabled by setting EN pin to high. At first, the internal reference is activated and the internal
analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output
voltages reaches 95% of its nominal value within tSTARTof typically 500 µs after the device has been enabled. The
EN input can be used to control power sequencing in a system with various DC/DC converters. The EN pin can
be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply
rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin is
connected to PGND via an internal resistor to discharge the output.
SOFT START
The TPS6206x has an internal soft start circuit that controls the ramp up of the output voltage. Once the
converter is enabled and the input voltage is above the undervoltage lockout threshold VUVLOthe output voltage
ramps up from 5% to 95% of its nominal value within tRamp of typ. 250µs.
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This limits the inrush current in the converter during start up and prevents possible input voltage drops when a
battery or high impedance power source is used.
During soft start, the switch current limit is reduced to 1/3 of its nominal value ILIMF until the output voltage
reaches 1/3 of its nominal value. Once the output voltage trips this threshold, the device operates with its
nominal current limit ILIMF
.
INTERNAL CURRENT LIMIT / FOLD-BACK CURRENT LIMIT FOR SHORT-CIRCUIT PROTECTION
During normal operation the High-Side and Low-Side MOSFET switches are protected by its current limits ILIMF
.
Once the High-Side MOSFET switch reaches its current limit, it is turned off and the Low-Side MOSFET switch is
turned on. The High-Side MOSFET switch can only turn on again, once the current in the Low -Side MOSFET
switch decreases below its current limit ILIMF. The device is capable to provide peak inductor currents up to its
internal current limit ILIMF.
.
As soon as the switch current limits are hit and the output voltage falls below 1/3 of the nominal output voltage
due to overload or short circuit condition, the foldback current limit is enabled. In this case the switch current limit
is reduced to 1/3 of the nominal value ILIMF
.
Due to the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of its
nominal current limit ILIMF until the output voltage exceeds 1/3 of the nominal output voltage. This needs to be
considered when a load is connected to the output of the converter, which acts as a current sink.
CLOCK DITHERING
In order to reduce the noise level of switch frequency harmonics in the higher RF bands, the TPS6206x family
has a built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a sub clock causing a
clock dither of typ. 6ns.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the High-Side and Low-Side MOSFETs are turned off. The device continues its operation with a softstart
once the junction temperature falls below the thermal shutdown hysteresis.
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APPLICATION INFORMATION
L
VOUT = 1.8 V
up to 2 A
TPS62065
1.0 mH
VIN = 2.9 V to 6 V
PVIN
SW
R1
COUT
AVIN
Cff
360 kΩ
22 pF
10 µF
EN
FB
CIN
MODE
R2
10 µF
AGND
PGND
180 kΩ
Figure 26. TPS62065 1.8V Adjustable Output Voltage Configuration
L
1.0 mH
VOUT
TPS62067
PVIN
VIN = 2.9 V to 6 V
1.8 V 2 A
SW
R1
AVIN
EN
RPG
360 kW
Cff
COUT
CIN
100 kW
FB
22 pF
10 mF
10 mF
R2
AGND
PGND
180 kW
PG
Figure 27. TPS62067 Adjustable 1.8-V Output
OUTPUT VOLTAGE SETTING
The output voltage can be calculated to:
æ
ç
è
ö
÷
ø
æ
ç
è
ö
÷
ø
R1
R2
VOUT
VREF
VOUT = VREF ´ 1+
R1 =
-1 ´ R2
with an internal reference voltage VREF typically 0.6V.
To minimize the current through the feedback divider network, R2 should be within the range of 120 kΩ to 360
kΩ. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. An external
feed-forward capacitor Cff is required for optimum regulation performance. Lower resistor values can be used. R1
and Cff places a zero in the loop. The right value for Cff can be calculated as:
1
fz
=
= 25 kHz
2 ´ p ´ R1 ´ Cff
1
Cff
=
2 ´ p ´ R1 ´ 25 kHz
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OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The internal compensation network of TPS6206x is optimized for a LC output filter with a corner frequency of:
1
fc =
= 50kHz
2´p ´ (1μH ´10μF)
The part operates with nominal inductors of 1.0µH to 1.2 µH and with 10µF to 22µF small X5R and X7R ceramic
capacitors. Please refer to the lists of inductors and capacitors. The part is optimized for a 1.0µH inductor and
10µF output capacitor.
Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
Equation 1 calculates the maximum inductor current in PWM mode under static load conditions. The saturation
current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 2.
This is recommended because during heavy load transient the inductor current rises above the calculated value.
Vout
Vin
1 *
DI + Vout
L
L ƒ
(1)
DI
L
I
+ I
)
outmax
Lmax
2
(2)
With:
f = Switching Frequency (3MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
A more conservative approach is to select the inductor current rating just for the switch current limit ILIMFof the
converter.
The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both
the losses in the dc resistance R(DC) and the following frequency-dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
Table 2. List of Inductors
DIMENSIONS [mm3]
3.2 x 2.5 x 1.0 max
3.7 x 4 x 1.8 max
INDUCTANCE mH
INDUCTOR TYPE
LQM32PN (MLCC)
SUPPLIER
Murata
1.0
1.0
1.2
1.2
LQH44 (wire wound)
NRG4026T (wire wound)
DE3518 (wire wound)
Murata
4.0 x 4.0 x 2.6 max
3.5 x 3.7 x 1.8 max
Taiyo Yuden
TOKO
Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS6206x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance over temperature, become resistive at high frequencies and may
not be used. For most applications a nominal 10µF or 22µF capacitor is suitable. At small ceramic capacitors, the
DC-bias effect decreases the effective capacitance. Therefore a 22µF capacitor can be used for output voltages
higher than 2V, see list of capacitors.
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In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter,
the output capacitor COUT need to be decreased in order not to exceed the recommended effective capacitance
range. In this case a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
Vout
Vin
1 *
1
I
+ Vout
RMSCout
Ǹ
L ƒ
2 3
(3)
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a 10µF ceramic capacitor is recommended. The input capacitor can be
increased without any limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 3. List of Capacitors
CAPACITANCE
10mF
TYPE
SIZE [ mm3]
SUPPLIER
Murata
GRM188R60J106M
GRM188R60G226M
CL10A226MQ8NRNC
CL10A106MQ8NRNC
0603: 1.6 x 0.8 x 0.8
0603: 1.6 x 0.8 x 0.8
0603: 1.6 x 0.8 x 0.8
0603: 1.6 x 0.8 x 0.8
22mF
Murata
22µF
Samsung
Samsung
10µF
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter
combinations. As a next step in the evaluation of the regulation loop, the load transient response is tested. The
time between the application of the load transient and the turn on of the P-channel MOSFET, the output
capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to
ΔI(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO
generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are
most easily interpreted when the device operates in PWM mode at medium to high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
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LAYOUT CONSIDERATIONS
VIN
GND
VOUT
CIN
COUT
L
R2
R1
CFF
Figure 28. PCB Layout
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI and thermal problems. It is critical to provide a low inductance, impedance ground path. Therefore, use
wide and short traces for the main current paths. The input capacitor should be placed as close as possible to
the IC pins as well as the inductor and output capacitor.
Connect the AGND and PGND Pins of the device to the PowerPAD™ land of the PCB and use this pad as a star
point. Use a common Power PGND node and a different node for the Signal AGND to minimize the effects of
ground noise. The FB divider network should be connected right to the output capacitor and the FB line must be
routed away from noisy components and traces (e.g., SW line).
Due to the small package of this converter and the overall small solution size the thermal performance of the
PCB layout is important. To get a good thermal performance a four or more Layer PCB design is recommended.
The PowerPAD of the IC must be soldered on the power pad area on the PCB to get a proper thermal
connection. For good thermal performance the PowerPAD on the PCB needs to be connected to an inner GND
plane with sufficient via connections. Please refer to the documentation of the evaluation kit.
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REVISION HISTORY
NOTE: Page numbers of previous versions may differ from current version.
Changes from Original (March 2010) to Revision A
Page
•
•
•
•
Changed VIN Range from "3V to 6V" to "2.9V to 6V", throughout ........................................................................................ 1
Added equation to "Output Voltage Setting" section. ......................................................................................................... 17
Changed equation for calculating fz. ................................................................................................................................... 17
Changed equation for calculating Cff. .................................................................................................................................. 17
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PACKAGE OPTION ADDENDUM
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27-Apr-2010
PACKAGING INFORMATION
Orderable Device
TPS62065DSGR
TPS62065DSGT
TPS62067DSGR
TPS62067DSGT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
WSON
DSG
8
8
8
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
WSON
WSON
WSON
DSG
DSG
DSG
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 1
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