TPS62097-Q1 [TI]
采用具有可湿性侧面的 3x3 QFN 封装的 2A 汽车类降压转换器;
| 型号： | TPS62097-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用具有可湿性侧面的 3x3 QFN 封装的 2A 汽车类降压转换器 转换器 |
| 文件： | 总24页 (文件大小：1681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
采用可湿侧面 QFN 封装的 TPS62097-Q1 2A 高效降压转换器
1 特性
3 说明
1
•
符合 AEC-Q100 标准，其中包括以下内容：
TPS62097-Q1 器件是一款同步降压转换器，经优化可
用于高效率和噪声关键 应用。此器件主要用于宽输出
电流范围内的高效转换。在中等负载至重负载状态下，
此转换器在 PWM 模式下运行，且会在轻负载下自动
进入节能运行模式。可使用外部电阻器在 1.5MHz 至
2.5MHz 范围内选择开关频率。iDCS-Control 可在强制
PWM 模式下以恒定开关频率实现低噪声运行。
–
–
器件温度 1 级：–40°C 至 125°C 工作结温范围
器件人体放电模型 (HBM) 静电放电 (ESD) 分类
等级 2
–
器件 CDM ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
具有可选开关频率的 iDCS-Control 拓扑
强制 PWM 或省电模式
效率高达 97%
为了解决系统电源轨的需求，内部补偿电路支持使用电
容值高于 150µF 的各种外部输出电容器。为在启动过
程中控制浪涌电流，此器件通过连接至 SS/TR 引脚的
外部电容器提供了可编程软启动功能。SS/TR 引脚还
可用于电压跟踪配置中。此器件还集成了短路保护、电
源正常和热关断 功能。
2.5V 至 6.0V 输入电压
0.8V 至 VIN 可调输出电压
3.3V 固定输出电压，TPS6209733-Q1
输出电压精度为 ±1%
间断短路保护功能
可编程软启动
器件信息(1)
输出电压跟踪
器件型号
封装
封装尺寸（标称值）
3.0mm x 3.0mm
3.0mm x 3.0mm
可实现 100% 占空比，以确保最低压降
输出放电
TPS62097-Q1
TPS6209733-Q1
QFN (16)
QFN (16)
电源正常输出
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
热关断保护
采用可湿侧面 3mm x 3mm QFN 封装
输出电压选项
2 应用
器件型号
输出电压
可调
标记符号
9700Q
•
•
•
•
网关
TPS62097-Q1
TPS6209733-Q1
3.3V
9733Q
音响主机
仪表组
远程信息处理
1.8V 输出，典型应用
1.8V 输出，效率，模式 = 开环
VIN
5.0 V
100
90
80
70
60
TPS62097-Q1
L1
1.0 µH
VOUT
1.8 V
PVIN
AVIN
SW
VOS
C1
10 µF
C2
22 µF
R1
EN
24.9 kꢀ
SS/TR
MODE
FB
VPG
PG
C3
R2
20 kꢀ
R4*
AGND PGND
10 nF
R3
100 kꢀ
R4: optional
VIN
Copyright Ú 2016, Texas Instruments Incorporated
VIN = 3.3 V
VIN = 5.0 V
0
0.5
1
1.5
2
Load (A)
D026
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDZ7
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
目录
7.4 Device Function Modes ............................................ 8
Application Information....................................... 12
8.1 Application Information............................................ 12
8.2 1.8-V Output Application........................................ 12
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommend Operating Conditions........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
8
9
10 PCB Layout.......................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Information.............................................. 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持 ............................................................... 19
11.2 社区资源................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
Changes from Original (August 2017) to Revision A
Page
•
产品数据发布。....................................................................................................................................................................... 1
2
Copyright © 2017, Texas Instruments Incorporated
TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
5 Terminal Configuration and Functions
RGT Package with Wettable Flanks
16-Pin VQFN
(Top View)
Anchor Pin
Anchor Pin
SW
16
SW
SW
SW
13
15
14
VOS
FB
1
2
3
4
12
11
10
9
EN
PG
Exposed
Thermal Pad
MODE
AGND
SS/TR
AVIN
5
6
7
8
PGND PGND PVIN
PVIN
Anchor Pin
Anchor Pin
Copyright Ú 2016, Texas Instruments Incorporated
Pin Functions
PIN
I/O
DESCRIPTION
NAME
PGND
SW
NO.
5,6
Power ground pin.
13,14,15,16 PWR Switch pin. It is connected to the internal MOSFET switches. Connect the external inductor between this
terminal and the output capacitor.
VOS
FB
1
2
I
I
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Feedback pin. For the adjustable output voltage version, a resistor divider sets the output voltage. For the
fixed output voltage versions, this pin is recommended to be connected to AGND for improved thermal
performance. The pin also can be left floating as an internal 400kΩ resistor is connected between this pin
and AGND for fixed output voltage versions.
PG
EN
11
12
O
I
Power good open drain output pin. The pull-up resistor should not be connected to any voltage higher than
6 V. If it's not used, leave the pin floating.
Enable pin. To enable the device this pin needs to be pulled high. Pulling this pin low disables the device.
This pin has an internal pull-down resistor of typically 375kΩ when the device is disabled.
PVIN
AVIN
SS/TR
7,8
9
PWR Power input supply pin.
I
I
Analog input supply pin. Connect it to the PVIN pin together.
10
Soft startup and voltage tracking pin. A capacitor is connected to this pin to set the soft startup time. Leaving
this pin floating sets the minimum startup time.
MODE
3
I
Mode selection pin. Connect this pin to AGND to enable Power Save Mode with automatic transition
between PWM and Power Save Mode. Connect this pin to an external resistor or leave floating to enable
forced PWM mode only. See 表 1.
AGND
4
Analog ground pin.
Exposed Thermal Pad
Anchor Pins
The exposed thermal pad is connected to AGND. It must be soldered for mechanical reliability.
These pins do not require an electrical connection but can be connected to AGND. They must be soldered
for mechanical reliability. Refer to EXAMPLE BOARD LAYOUT at the end of this data sheet.
Copyright © 2017, Texas Instruments Incorporated
3
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
-3
MAX
6.0
UNIT
AVIN, PVIN, EN, VOS, PG
MODE, SS/TR, SW (DC)
VIN+0.3V
3.0
Voltage at Pins(2)
FB
V
SW (AC, less than 100ns)(3)
11
Sink current
Temperature
PG
0
1.0
mA
°C
Operating Junction, TJ
Storage, Tstg
-40
–65
150
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011(1)
Electrostatic
discharge
VESD
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommend Operating Conditions
MIN
2.5
0
MAX
6.0
UNIT
VIN
Input voltage range
V
V
VPG
VOUT
IOUT
TJ
Pull-up resistor voltage
Output voltage range
Output current range
6.0
0.8
0
VIN
V
2.0
A
Operating junction temperature
-40
125
°C
6.4 Thermal Information
THERMAL METRIC(1)
TPS62097-Q1WRGT
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.2
51.7
19.3
1.1
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
19.3
3.6
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
4
Copyright © 2017, Texas Instruments Incorporated
TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
6.5 Electrical Characteristics
TJ = -40°C to 125°C, and VIN = 2.5V to 6.0V. Typical values are at TJ = 25°C and VIN = 3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
EN = High, Device not switching, TJ = –40°C to 85°C
40
40
57
µA
65
IQ
Quiescent current into AVIN, PVIN
EN = High, Device not switching
EN = Low, TJ = –40°C to 85°C
EN = Low
0.7
0.7
2.3
2.4
160
20
3
µA
10
ISD
Shutdown current into AVIN, PVIN
Under voltage lock out threshold
VIN falling
2.2
2.3
2.4
V
VUVLO
VIN rising
2.5
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
TQ JSD
TJ falling
LOGIC INTERFACE (EN, MODE)
VH_EN
VL_EN
High-level input voltage, EN pin
Low-level input voltage, EN pin
1.6
1.3
2.0
0.9
V
V
1.0
IEN,LKG Input leakage current into EN pin
EN = High
EN = Low
0.01
375
µA
kΩ
V
RPD
Pull-down resistance at EN pin
High-level input voltage, MODE pin
Low-level input voltage, MODE pin
VH_MO
VL_MO
1.2
0.4
5.5
V
IMO,LKG Input leakage current into MODE pin
MODE = High
0.01
0.16
9.5
µA
SOFT STARTUP, POWER GOOD (SS/TR, PG)
ISS
Soft startup current
7.5
1
µA
Voltage tracking gain factor
VFB / VSS/TR
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1mA
92
87
95
90
98
92
VPG
Power good threshold
%
VPG,OL Low-level output voltage, PG pin
IPG,LKG Input leakage current into PG pin
OUTPUT
0.4
1.6
V
VPG = 5.0V
0.01
µA
PWM mode, No load
PSM mode(1)
–1.0
–1.0
792
792
1.0
2.1
Output voltage accuracy
TPS6209733Q
VOUT
%
PWM mode
PSM mode(1)
800
800
0.01
165
0.02
0.2
808
817
0.1
VFB
Feedback reference voltage
mV
IFB,LKG Input leakage current into FB pin
VFB = 0.8V
µA
Ω
RDIS
Output discharge resistor
Line regulation
EN = Low, VOUT = 1.8V
IOUT = 0.5A, VOUT = 1.8V(1)
%/V
%/A
(1)
Load regulation
PWM mode, VOUT = 1.8V
POWER SWITCH
ISW = 500mA, VIN = 5.0V
ISW = 500mA, VIN = 3.6V
ISW = 500mA, VIN = 5.0V
ISW = 500mA, VIN = 3.6V
42
53
High-side FET on-resistance
mΩ
mΩ
RDS(on)
40
Low-side FET on-resistance
50
3.1
3.3
3.6
3.6
–1.1
4.2
3.9
ILIMF
ILIMN
High-side FET forward current limit
Low-side FET negative current limit
A
A
VIN = 5.0V
Forced PWM mode
–1.25
-0.7
(1) Conditions: L = 1μH, COUT = 22μF, Switching Frequency = 2.0MHz
版权 © 2017, Texas Instruments Incorporated
5
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
120
120
100
80
60
40
20
0
TJ = -40°C
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
100
80
60
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
Input Voltage (V)
D014
D015
图 1. High-Side FET On-Resistance
图 2. Low-Side FET On-Resistance
6
版权 © 2017, Texas Instruments Incorporated
TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
7 Detailed Description
7.1 Overview
The TPS62097-Q1 synchronous step-down converter is based on the iDCS-Control (Industrial Direct Control with
Seamless transition into Power Save Mode) topology. The control topology not only keeps the advantages of
DCS-Control, but also provides other features:
•
•
•
•
Forced PWM mode over the whole load range
Selectable PWM switching frequency
1% output voltage accuracy
Output voltage sequencing and tracking
The iDCS-Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode (PSM) at light load conditions. Or the forced PWM mode removes power
save mode operation and operates the device always at its nominal switching frequency.
In PWM mode, the device operates with a predictive On-time switching pulse. A constant switching frequency
over the input and output voltage range is achieved by using an input and output voltage feed forward to set the
on-time, as shown in 表 1. In PSM mode, the switching frequency is reduced to achieve high efficiency over the
entire load current range. Since iDCS-Control supports both operation modes within a single building block, the
transition from PWM mode to Power Save Mode is seamless and without effects on the output voltage.
7.2 Functional Block Diagram
AVIN
Hiccup
Counter
PG
PVIN
VFB
High-side
Current Sense
VREF
Low-side
Current Sense
EN
Bandgap
Undervoltage Lockout
Thermal Shutdown
375kΩ(2)
AGND
SW
MOSFET Driver
Control Logic
VIN
Voltage
Clamp
VREF
PGND
VOS
SS/TR
MODE
Ramp
VIN
Direct Control
and
Compensation
Comparator
R1(1)
R2(1)
On time
Selection
tON
Timer
FB
VREF
Error Amplifier
165Ω
iDCS - Control
EN Output Discharge
Logic
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 375 kΩ resistor is disconnected.
版权 © 2017, Texas Instruments Incorporated
7
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 100% Duty Cycle Mode
The device offers a low input to output voltage dropout by entering 100% duty cycle mode, when the input
voltage reaches the level of the output voltage. In this mode the high-side MOSFET switch is constantly turned
on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation,
depending on the load current and output voltage, is calculated as:
VIN(min) = VOUT(min) + IOUT x (RDS(on) + RL)
where
•
•
•
•
VIN(min) = Minimum input voltage to maintain a minimum output voltage
IOUT = Output current
RDS(on) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
(1)
When the device operates close to 100% duty cycle mode, the TPS62097-Q1 can't enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
7.3.2 Switch Current Limit and Hiccup Short Circuit Protection
The switch current limit prevents the devices from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted/saturated inductor or a heavy
load/shorted output circuit condition. If the inductor current reaches the threshold ILIMF, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current. Once this switch current
limit is triggered 32 times, the devices stop switching and enable the output discharge. The devices then
automatically start a new startup after a typical delay time of 100µs has passed. This is HICCUP short circuit
protection and is implemented to reduce the current drawn during a short circuit condition. The devices repeat
this mode until the high load condition disappears.
When the device is in forced PWM mode, the negative current limit of the low-side MOSFET is active. The
negative current limit prevents excessive current from flowing back through the inductor to the input.
7.3.3 Under Voltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 100mV.
7.3.4 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Function Modes
7.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. Accordingly, shutdown mode is forced if the EN pin
is pulled Low with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 165 Ω discharges the output via the VOS pin smoothly. The output discharge function also works
when thermal shutdown, undervoltage lockout or HICCUP short circuit protection are triggered.
An internal pull-down resistor of 375 kΩ is connected to the EN pin when the EN pin is Low. The pull-down
resistor is disconnected when the EN pin is High.
7.4.2 Power Save Mode and Forced PWM Mode (MODE)
The MODE pin is a multi-functional pin that allows the device operation in forced PWM mode or PWM/PSM
mode, and to select the PWM switching frequency.
8
版权 © 2017, Texas Instruments Incorporated
TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
Device Function Modes (接下页)
Once the EN pin is pulled high, the IC enables internal circuit blocks and prepares to ramp the output up. The
period between the rising edge of the EN pin and the beginning of the power stage switching is called the MODE
detection time, typically 50µs. During the MODE detection time period, shown in 图 3, the PWM switching
frequency and operating mode are set by the MODE pin status, as shown in 表 1.
The PWM switching frequency can't be changed after the detection time period. Only when the device is set in
PWM/PSM mode during the MODE detection time period (MODE = AGND), it is possible to switch between
PWM/PSM and forced PWM operation modes by toggling the MODE pin with a GPIO pin of a micro-controller,
for example. The other four MODE pin selections force the device in PWM mode only.
EN
Disable
Enable
VOUT
Soft Startup
PG
MODE
Detection
图 3. Power Up Sequence
表 1. Switching Frequency and Mode Selection
Typical PWM
Switching
Frequency (MHz)
Resistance at MODE pin
Toggle MODE pin after
MODE detection
ON-Time Equation
Operating Mode
(E24 EIA Value)
1.50
1.75
8.2kΩ ±5%
18kΩ ±5%
No
No
tON = 667ns x VOUT / VIN
tON = 571ns x VOUT / VIN
Forced PWM
Forced PWM
PWM/PSM and
Forced PWM
2.00
AGND
Yes
tON = 500ns x VOUT / VIN
2.25
2.50
39kΩ ±5%
No
No
tON = 444ns x VOUT / VIN
tON = 400ns x VOUT / VIN
Forced PWM
Forced PWM
75kΩ ±5% or Open
Connecting the MODE pin to AGND with a resistor or leaving the MODE pin open forces the device into PWM
mode for the whole load range. The device operates with a constant switching frequency that allows simple
filtering of the switching frequency for noise sensitive applications. In forced PWM mode, the efficiency is lower
than that of PSM at light load.
Connecting the MODE pin to the AGND pin enables Power Save Mode with an automatic transition between
PWM and Power Save Mode. As the load current decreases and the inductor current becomes discontinuous,
the device enters Power Save Mode operation automatically. In Power Save Mode, the switching frequency is
reduced and estimated by 公式 2. In Power Save Mode, the output voltage rises slightly above the nominal
output voltage, as shown in 图 13. This effect is minimized by increasing the output capacitor.
2´IOUT
fPSM
=
V
VIN - VOUT
2
IN
´
tON
´
VOUT
L
(2)
When the device operates close to 100% duty cycle mode, the TPS62097-Q1 can't enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
版权 © 2017, Texas Instruments Incorporated
9
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7.4.3 Soft Startup (SS/TR)
The TPS62097-Q1 programs its output voltage ramp rate with the SS/TR pin. Connecting an external capacitor
to SS/TR enables output soft startup to reduce inrush current from the input supply. The device charges the
capacitor voltage to the input supply voltage with a constant current of typically 7.5μA. The FB pin voltage follows
the SS/TR pin voltage until the internal reference voltage of 0.8V is reached. The soft startup time is calculated
using 公式 3. Keep the SS/TR pin floating to set the minimum startup time.
0.8V
tSS = CSS / TR
´
7.5mA
(3)
An active pull-down circuit is connected to the SS/TR pin. It discharges the external soft startup capacitor in case
of disable, UVLO, thermal shutdown and HICCUP short circuit protection.
7.4.4 Voltage Tracking (SS/TR)
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in 图 4. From 0 V to 0.8 V, the internal reference voltage to the internal error amplifier follows the
SS/TR pin voltage. When the SS/TR pin voltage is above 0.8 V, the voltage tracking is disabled and the FB pin
voltage is regulated at 0.8 V. The device achieves ratiometric or coincidental (simultaneous) output tracking, as
shown in 图 5.
VOUT1
VOUT2
TPS62097
R1
R3
SS/TR
FB
R2
R4
图 4. Output Voltage Tracking
Voltage
Voltage
VOUT1
VOUT1
VOUT2
VOUT2
R3 R1
<
R3 R1
=
R4 R2
R4 R2
t
t
a) Ratiometric Tracking
b) Coincidental Tracking
图 5. Voltage Tracking Options
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 µA soft startup current
into account. 1 kΩ or smaller is a sufficient value for R2.
For decreasing SS/TR pin voltage, the device doesn't sink current from the output when the device is in PSM. So
the resulting decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When
driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is
VIN+0.3V.
10
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TPS62097-Q1
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ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
7.4.5 Power Good (PG)
The TPS62097-Q1 has a power good output. The PG pin goes high impedance once the output voltage is above
95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal
voltage. The PG pin is an open drain output and is specified to sink up to 1mA. The power good output requires
a pull-up resistor connected to any voltage rail less than 6V. The PG signal can be used for sequencing of
multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when not used. 表 2
shows the PG pin logic.
表 2. PG Pin Logic
Logic Status
Device Conditions
High Z
Low
EN = High, VFB ≥ VPG
EN = Low, VFB ≤ VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
0.7 V < VIN < VUVLO
VIN ≤ 0.7 V
Power Supply Removal
√
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8 Application Information
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design of
the TPS62097-Q1.
8.2 1.8-V Output Application
VIN
5.0 V
TPS62097-Q1
L1
1.0 µH
VOUT
1.8 V
PVIN
SW
AVIN
EN
VOS
C1
10 µF
C2
22 µF
R1
24.9 kꢀ
SS/TR
MODE
FB
VPG
PG
C3
10 nF
R2
20 kꢀ
R4*
AGND PGND
R3
100 kꢀ
R4: optional
VIN
Copyright Ú 2016, Texas Instruments Incorporated
图 6. 1.8-V Output Application Schematic
8.2.1 Design Requirements
For this design example, use the following as the input parameters.
表 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Output voltage
2.5 V to 6 V
1.8 V
Output current
2.0 A
表 4 lists the components used for the example.
表 4. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER(1)
C1
C2
C3
L1
10 μF, Ceramic Capacitor, 6.3V, X7R, size 0805, C2012X7R0J106M125AB
22 μF, Ceramic Capacitor, 6.3V, X7S, size 0805, C2012X7S1A226M125AC
10 nF, Ceramic Capacitor, 6.3V, X7R, size 0603, GRM188R70J103KA01
1 µH, Shielded, 5.4A, XFL4020-102MEB
TDK
TDK
Murata
Coilcraft
Std
R1
R2
R3
Depending on the output voltage, 1% accuracy
20 kΩ, 1% accuracy
Std
100 kΩ, 1% accuracy
Std
(1) See Third-party Products Disclaimer
12
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TPS62097-Q1
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ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equation:
R1
R1
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(4)
R2 should not be higher than 20 kΩ to reduce noise coupling into the FB pin and improve the output voltage
regulation. Choose additional resistor values for other outputs. A feed forward capacitor is not required.
The fixed output voltage version, TPS6209733-Q1, does not need an external resistor divider. TI recommends to
connect the FB pin to AGND for improved thermal performance.
8.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, 表 5
outlines possible inductor and capacitor value combinations for most applications.
表 5. Output Capacitor / Inductor Combinations
NOMINAL COUT [µF](2)
NOMINAL L [µH](1)
10
22
47
100
150
0.47
1
(3)
+
+
+
+
2.2
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
-30%. The required effective inductance is 500nH minimum.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
20% and -50%.
(3) Typical application configuration. Other '+' mark indicates recommended filter combinations. Other
values may be acceptable in applications but should be fully tested by the user. Refer to the
application note SLVA710.
8.2.2.3 Inductor Selection
The main parameters for the inductor selection are the inductor value and the saturation current. To calculate the
maximum inductor current under static load conditions, 公式 5 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
Where:
´
L ´ fSW
(5)
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
TI recommends to choose the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of 公式 5.
A higher inductor value is also useful to lower ripple current but increases the transient response time as well.
8.2.2.4 Capacitor Selection
The input capacitor is the low impedance energy source for the converters which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is required for best filtering and should be placed between
PVIN and PGND as close as possible to those pins. For most applications a 10-μF capacitor is sufficient, though
a larger value reduces input current ripple.
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TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
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The architecture of the TPS62097-Q1 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends to
use X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF and can vary over a wide
range as outlined in 表 5.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Ensure
that the input effective capacitance is at least 5 μF and the output effective capacitance is at least 10 μF.
8.2.3 Application Performance Curves
TA = 25°C, BOM = 表 4 unless otherwise noted.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VIN = 3.3V PSM
VIN = 5.0V PSM
VIN = 3.3V FPWM
VIN = 5.0V FPWM
VIN = 3.3V PSM
VIN = 5.0V PSM
VIN = 3.3V FPWM
VIN = 5.0V FPWM
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D001
D002
VOUT = 1.0 V
FSW = 2.0 MHz
图 7. Efficiency
VOUT = 1.2 V
FSW = 2.0 MHz
图 8. Efficiency
100
90
80
70
60
50
40
100
90
80
70
60
50
40
VIN = 3.3V PSM
VIN = 5.0V PSM
VIN = 3.3V FPWM
VIN = 5.0V FPWM
VIN = 3.3V PSM
VIN = 5.0V PSM
VIN = 3.3V FPWM
VIN = 5.0V FPWM
30
30
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D003
D004
VOUT = 1.8 V
FSW = 2.0 MHz
图 9. Efficiency
VOUT = 2.5 V
FSW = 2.0 MHz
图 10. Efficiency
14
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TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
100
90
80
70
60
50
40
95
85
75
FSW = 1.5 MHz
FSW = 2.0 MHz
FSW = 2.5 MHz
VIN = 5.0V PSM
VIN = 5.0V FPWM
30
1m
10m
100m
1
5
0
0.5
1
1.5
2
Load (A)
Load (A)
D005
D016
VOUT = 3.3 V
FSW = 2.0 MHz
VOUT = 1.8 V
VIN = 5.0 V
图 11. Efficiency
图 12. Efficiency with Different Switching Frequency
1.809
1.8
1.809
1.8
1.791
1.782
1.773
1.791
1.782
VIN = 3.3V PSM
IOUT = 1mA PSM
IOUT = 1A PSM
IOUT = 1mA FPWM
IOUT = 1A FPWM
VIN = 5.0V PSM
VIN = 3.3V FPWM
VIN = 5.0V FPWM
1.773
1m
10m
100m
1
5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Load (A)
Input Voltage (V)
D006
D007
图 13. Load Regulation
图 14. Line Regulation
1.8x106
1.6x106
1.4x106
1.2x106
1x106
2x106
1.8x106
1.6x106
1.4x106
1.2x106
1x106
IOUT = 1mA FPWM
IOUT = 1mA FPWM
IOUT = 10mA FPWM
IOUT = 0.1A FPWM
IOUT = 1A FPWM
IOUT = 2A FPWM
IOUT = 10mA FPWM
IOUT = 0.1A FPWM
IOUT = 1A FPWM
IOUT = 2A FPWM
8x105
6x105
2.5
8x105
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
Input Voltage (V)
D008
D009
VOUT = 1.0 V
RMode = 8.2 kΩ
VOUT = 1.0 V
MODE = AGND, Forced PWM
图 15. Switching Frequency, Forced PWM Mode (1.5 MHz)
图 16. Switching Frequency, Forced PWM Mode (2.0MHz)
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TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
2.2x106
2x106
VSW
2V/DIV
1.8x106
1.6x106
1.4x106
VOUT
10mV/DIV
AC
IOUT = 1mA FPWM
IOUT = 10mA FPWM
IOUT = 0.1A FPWM
IOUT = 1A FPWM
IOUT = 2A FPWM
ICOIL
200mA/DIV
2A OFFSET
1.2x106
1x106
Time - 200ns/DIV
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
D016
Input Voltage (V)
D010
VOUT = 1.2 V
IOUT = 2 A
VOUT = 1.0 V
MODE = Open
图 18. Output Ripple, PWM Operation (2.0MHz)
图 17. Switching Frequency, Forced PWM Mode (2.5MHz)
IOUT
2A/DIV
VSW
2V/DIV
VOUT
100mV/DIV
AC
VOUT
20mV/DIV
AC
ICOIL
2A/DIV
ICOIL
300mA/DIV
Time - 2ꢀs/DIV
Time - 5ꢀs/DIV
D017
D018
VOUT = 1.2 V
IOUT = 30 mA
VOUT = 1.2 V
IOUT = 0 A to 2 A, 1A / µs
图 19. Output Ripple, PSM Operation
图 20. Load Transient, PWM/PSM Mode (2.0MHz)
VEN
IOUT
2V/DIV
2A/DIV
VOUT
500mV/DIV
VOUT
100mV/DIV
AC
ICOIL
ICOIL
2A/DIV
300mA/DIV
Time - 5ꢀs/DIV
Time - 250ꢀs/DIV
D019
D020
VOUT = 1.2 V
IOUT = 0 A to 2 A, 1A / µs
VOUT = 1.2 V
ROUT = No Load
图 21. Load Transient, Forced PWM Mode (2.0MHz)
图 22. Startup and Shutdown without Load
16
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TPS62097-Q1
www.ti.com.cn
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
Short
Recovery
VEN
2V/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
ICOIL
ICOIL
1A/DIV
2A/DIV
Time - 250ꢀs/DIV
Time - 300ꢀs/DIV
D021
D022
VOUT = 1.2 V
ROUT = 0.6 Ω (2 A)
VOUT = 1.2 V
ROUT = 0.8 Ω (1.5 A) with 1-ms short
图 23. Startup and Shutdown with Load
图 24. Short Circuit Protection, HICCUP
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5V and 6V. The average
input current of the TPS62097-Q1 is calculated as:
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(6)
Ensure that the power supply has a sufficient current rating for the application.
版权 © 2017, Texas Instruments Incorporated
17
TPS62097-Q1
ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
10 PCB Layout
10.1 Layout Guidelines
•
TI recommends to place all components as close as possible to the IC. Specially, the input capacitor
placement must be closest to the PVIN and PGND pins of the device.
•
The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground
potential shift.
•
•
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being
induced. Keep the trace away from SW nodes.
•
Refer to 图 25 for an example of component placement, routing and thermal design.
10.2 Layout Example
R4
R2
GND
R1
GND
C2
VOUT
PGND
SW
SW
SW
SW
PAC102
C1
PGNDP ANT102
PVIN
PVIN
VIN
L1
C3
图 25. TPS62097-Q1 PCB Layout
10.3 Thermal Information
Implementation of integrated circuits in low-profile and fine pitch surface mount packages typically requires
special attention to power dissipation. Many system dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component. For more details on how to use the thermal parameters, see the
application notes: Thermal Characteristics Application Notes SZZA017 and SPRA953.
18
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ZHCSH71A –SEPTEMBER 2017–REVISED DECEMBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
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19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6209733QWRGTRQ1
TPS62097QWRGTRQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
16
16
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
9733Q
9700Q
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6209733QWRGTRQ1 VQFN
TPS62097QWRGTRQ1 VQFN
RGT
RGT
16
16
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.0
1.0
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS6209733QWRGTRQ1
TPS62097QWRGTRQ1
VQFN
VQFN
RGT
RGT
16
16
3000
3000
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
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TPS6209718RWKR
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS6209718RWKT
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS6209733QWRGTRQ1
采用具有可湿性侧面的 3x3 QFN 封装的 2A 汽车类降压转换器 | RGT | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS6209733RWKR
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS6209733RWKT
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS62097QWRGTRQ1
采用具有可湿性侧面的 3x3 QFN 封装的 2A 汽车类降压转换器 | RGT | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS62097RWKR
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS62097RWKT
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS621
TOSHIBA PHOTO TRNSISTOR SILICON NPN EPITAXIAL PLANARWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS621(A)
Photo Transistor, PHOTO TRANSISTOR DETECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS621(A,F)
暂无描述Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TOSHIBA
TPS621(B)
Photo Transistor, PHOTO TRANSISTOR DETECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TOSHIBA
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