TPS621351RGXT [TI]
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125;
| 型号： | TPS621351RGXT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125 开关 输出元件 转换器 |
| 文件： | 总47页 (文件大小：2698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
TPS62135, TPS621351 High Accuracy 3-V to 17-V 4-A Step-Down Converters
with DCS-Control™
1 Features
3 Description
The TPS62135 and TPS621351 are high efficiency
and easy to use synchronous step-down DC-DC
converters, based on the DCS-Control™ Topology.
The devices wide input voltage range of 3-V to 17-V
makes it suitable for multi-cell Li-Ion as well as 12-V
intermediate supply rails. The devices provide 4-A
1
•
Output Voltage Accuracy ± 1% (PWM mode)
Input Voltage Range: 3 V to 17 V
Quiescent Current 18 µA Typ
•
•
•
•
•
•
Output Voltage from 0.8 V to 12 V
Adjustable Soft-Start
continuous
output
current.
The
TPS62135
Forced PWM or PWM/PFM operation
automatically enters Power Save Mode at light loads
to maintain high efficiency across the whole load
range. With that, the device is well suited for
applications that require connected standby
performance, like ultra low power computers. With the
MODE pin set to low, the switching frequency of the
device is adapted automatically based on the input
and output voltage. This technique is called
Automatic Efficiency Enhancement (AEE™) and
maintains high conversion efficiency over the whole
operation range. It provides a 1% output voltage
accuracy in PWM mode and therefore enables the
design of a power supply with high output voltage
accuracy.
Typical switching frequency of 2.5MHz in forced
PWM
•
Precise ENABLE input allows
–
–
User-Defined Undervoltage Lockout
Exact Sequencing
•
•
•
•
•
•
•
100% Duty Cycle Mode
Automatic Efficiency Enhancement AEE™
DCS-Control™ Topology
Available with Active Output Discharge
Optional HICCUP Overcurrent Protection
Power Good Output
The device has a typical quiescent current of 18 µA.
In shutdown mode the current is typically 1 µA and
the output is actively discharged for TPS62135 while
the output voltage discharge feature is disabled in
TPS621351.
Available in 3-mm x 2-mm VQFN Package
2 Applications
•
•
•
•
•
Standard 12-V Rail Supplies
POL for Connected Standby Requirements
POL Supply from Single or Multiple Li-Ion Battery
Gaming Consoles, SSD Drives
The TPS62135 is available as an adjustable version,
packaged in a 3-mm x 2-mm VQFN package.
Device Information(1)
Mobile and Embedded Computers
PART NUMBER
TPS62135
PACKAGE
VQFN
VQFN
BODY SIZE (NOM)
3.00 mm x 2.00 mm
3.00 mm x 2.00 mm
TPS621351
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
Simplified Schematic
TPS62135
1 uH
Efficiency vs Output Current for Vo = 3.3 V
100
90
80
70
60
50
VBAT = 3.0V to 17V
10uF
VOUT = 0.8V to 12V
VIN
EN
SW
VOS
R
1
FB
22uF
R
2
PG
FB2
VSEL
MODE
SS/TR
VIN = 4 V
VIN = 5 V
40
30
20
10
0
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
GND
Copyright © 2016, Texas Instruments Incorporated
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT (A)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Table of Contents
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Applications ............................................. 16
10.3 System Examples ................................................. 32
11 Power Supply Recommendations ..................... 36
12 Layout................................................................... 36
12.1 Layout Guidelines ................................................. 36
12.2 Layout Example .................................................... 36
12.3 Thermal Considerations........................................ 37
13 Device and Documentation Support ................. 38
13.1 Device Support .................................................... 38
13.2 Receiving Notification of Documentation Updates 38
13.3 Related Links ........................................................ 38
13.4 Community Resources.......................................... 38
13.5 Trademarks........................................................... 38
13.6 Electrostatic Discharge Caution............................ 38
13.7 Glossary................................................................ 38
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 7
8.1 Schematic ................................................................. 7
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
9.3 Feature Description................................................... 9
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Revision A (September 2016) to Revision B
Page
•
•
•
•
•
•
•
•
•
Deleted table note from Device Comparison Table ............................................................................................................... 3
Changed Figure 6 to Figure 30 ........................................................................................................................................... 17
Added Figure 72 .................................................................................................................................................................. 28
Added Figure 74 .................................................................................................................................................................. 28
Added Figure 76 .................................................................................................................................................................. 28
Added Figure 78 .................................................................................................................................................................. 29
Added Figure 80 .................................................................................................................................................................. 29
Added Figure 81 .................................................................................................................................................................. 29
Added Figure 82 .................................................................................................................................................................. 30
Changes from Original (June 2016) to Revision A
Page
•
Changed from Product Preview to Production Data .............................................................................................................. 1
2
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
5 Device Comparison Table
DEVICE NUMBER
FEATURES
OUTPUT VOLTAGE
MARKING
TPS62135RGX
nominal switching frequency = 2.5 MHz
output voltage discharge
adjustable
62135
voltage selection input / output VSEL/FB2
HICCUP current limit
TPS621351RGX
TPS62136RGX
voltage selection input / output VSEL/FB2
nominal switching frequency = 2.5 MHz
adjustable
adjustable
621351
nominal switching frequency = 1 MHz
output voltage discharge
see the TPS62136
data sheet
voltage selection input / output VSEL/FB2
HICCUP current limit
TPS621361RGX
nominal switching frequency = 1 MHz
voltage selection input / output VSEL/FB2
adjustable
see the TPS621361
data sheet
6 Pin Configuration and Functions
RGX Package
11-Pin VQFN
bottom view
top view
7
7
8
8
9
EN
PG
PG
VOS
FB
EN
9
6
6
5
4
SS/TR
VOS
SS/TR
5
4
SW
VIN
10
GND
GND
SW
10
VIN
MODE
FB
MODE
11
11
VSEL
FB 2
FB 2
VSEL
3
2
1
2
3
1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
FB
8
5
I
I
Voltage feedback input, connect resistive output voltage divider to this pin.
Open drain of an internal switch to GND. Allows to turn on a resistor in parallel to the
feedback resistor R2 and increase the output voltage with VSEL = high.
FB2
4
O
GND
MODE
PG
3
Ground pin.
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected.
10
7
I
O
Open drain power good output.
Soft-Start / Tracking pin. An external capacitor connected from this pin to GND defines the
rise time for the internal reference voltage. The pin can also be used as an input for tracking
and sequencing - see Detailed Description section in this document.
SS/TR
9
I
SW
2
1
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
VIN
VOS
VSEL
6
I
I
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
Voltage scaling control input. Turns on an internal switch from FB2 to GND when this pin is
set high.
11
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
MIN
-0.3
-0.3
-2
MAX
20
UNIT
V
Pin voltage range(2)
VIN
SW, VOS
SW (transient for t<10ns)(3)
VIN+0.3
25.5
V
V
EN, MODE, VSEL, PG, FB, FB2, SS/TR
-0.3
-40
-65
VIN+0.3
150
V
Operating junction temperature, TJ
Storage temperature range, Tstg
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground pin.
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human Body Model - (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charge Device Model - (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
3
NOM
MAX
17
UNIT
V
VIN
VOUT
L
Supply voltage range
Output voltage range
0.8
0.6
6
12
V
Effective inductance
1
22
10
2.9
200(2)
µH
µF
µF
°C
CO
CI
Effective output capacitance(1)
Effective input capacitance(1)(3)
Operating junction temperature
3
TJ
-40
+125
(1) Due to the dc bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This
is why the capacitance is specified to allow the selection of the smallest capacitor required with the dc bias effect for this type of
capacitor in mind. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required.
(2) This is for capacitors directly at the output of the TPS62135x. More capacitance is allowed if there is a series resistance associated to
the capacitors. See also the systems examples Powering Multiple Loads for applications where many distributed capacitors are
connected to the output.
(3) Larger values may be required if the source impedance can not support the transient requirements of the load.
4
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
7.4 Thermal Information
TPS62135,
TPS621351
THERMAL METRIC(1)
UNIT
RGX (VQFN)
11 PIN
RθJA
Junction-to-ambient thermal resistance
38.4
2.0
7.6
0.1
7.6
3.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. Thermal data is taken according JEDEC 51-5 on a 4-layer pcb with 6 thermal vias.
7.5 Electrical Characteristics
over operating junction temperature (TJ= -40 °C to +125 °C) and VIN= 3 V to 17 V. Typical values at VIN = 12 V and TA= 25
°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Operating Quiescent
Current
EN = high, IOUT= 0 mA, Device not switching, TJ= 85
°C
IQ
35
46
8
µA
µA
µA
Operating Quiescent
Current
EN = high, IOUT= 0 mA, Device not switching
IQ
18
1
ISD
EN = 0 V, Nominal value at TJ= 25 °C, Max value at
TJ= 85 °C
Shutdown Current
VUVLO
Rising Input Voltage
2.8
2.5
2.9
2.6
3.0
2.7
V
V
Undervoltage Lockout
Threshold
Falling Input Voltage
TSD
Thermal Shutdown
Temperature
Rising Junction Temperature
160
20
°C
Thermal Shutdown
Hysteresis
CONTROL (EN, SS/TR, PG, MODE, VSEL)
High Level Input Voltage
for VSEL, MODE pin
VIH
0.9
V
V
VIL
VIH
VIL
Low Level Input Voltage
for VSEL, MODE pin
0.3
0.83
0.73
100
Input Threshold Voltage
for EN pin; rising edge
0.77
0.67
0.8
0.7
V
Input Threshold Voltage
for EN pin; falling edge
V
Input Leakage Current for
EN, VSEL, MODE
ILKG_EN
VTH_PG
VOL_PG
VIH = VIN or VIL= GND
nA
Power Good Threshold
Voltage; dc level
Rising (%VOUT
)
93%
3%
96%
0.07
98%
4.5%
0.3
Hysteresis
Falling (%VOUT
)
Power Good Output Low
Voltage
IPG = 2 mA
V
Input Leakage Current
(PG)
ILKG_PG
ISS/TR
VPG = 5 V
100
nA
SS/TR pin source current
ISS/TR tolerance
2.5
±0.2
1
µA
µA
TJ= -40 °C to +125 °C
VFB / VSS/TR
Tracking gain
Tracking offset
feedback voltage with VSS/TR = 0 V
11
mV
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Electrical Characteristics (continued)
over operating junction temperature (TJ= -40 °C to +125 °C) and VIN= 3 V to 17 V. Typical values at VIN = 12 V and TA= 25
°C. (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RDS(ON)
High-Side MOSFET ON-
Resistance
V
IN ≥ 4 V
IN ≥ 4 V
100
39
180
67
mΩ
mΩ
A
Low-Side MOSFET ON-
Resistance
V
High-Side MOSFET
Current Limit
dc value(1)
dc value(1)
dc value
ILIMH
4.8
4.8
5.6
5.6
6.5
6.5
Low-Side MOSFET
Current Limit
ILIML
A
A
ILIMNEG
fSW
Negative current limit
1.5
2.5
PWM Switching
Frequency
MODE = high; VIN = 12V, VOUT = 3.3V; IOUT = 1A
MHz
OUTPUT
VFB
Feedback Voltage
0.7
1
V
Input Leakage Current
(FB)
ILKG_FB
VFB
VFB= 0.7 V
70
1%
2%
nA
Feedback Voltage
Accuracy(2)
VIN ≥ VOUT +1 V
PWM mode
-1%
-1%
VIN ≥ VOUT +1 V; VOUT
1.5 V
≥
PFM mode; Co,eff ≥ 47
µF, L = 1 µH
1 V ≤ VOUT < 1.5 V
PFM mode; Co,eff ≥ 47
µF, L = 1 µH
-1%
-1%
2.5%
2.5%
VOUT < 1 V
PFM mode; Co,eff ≥ 75
µF, L = 1 µH
VFB
Feedback Voltage
Accuracy with Voltage
Tracking
VIN ≥ VOUT +1 V; VSS/TR
0.35 V
=
PWM mode
-2%
7.5%
RDS(ON)
ILKG_FB2
FB2 resistance to GND
when VSEL= high
10
30
70
Ω
Input Leakage Current in
FB2 when VSEL = low
1
0.05
0.02
nA
Load Regulation
Line Regulation
PWM mode operation
%/A
%/V
PWM mode operation, IOUT= 1 A, VIN ≥ Vout + 1 V
or VIN ≥ 3.5 V whichever is larger
Output Discharge
Resistance
TPS62135 only
100
200
150
Ω
tdelay
tramp
Start-up Delay time
IO= 0 mA, Time from EN=high to start switching; VIN
applied already
300
µs
µs
Ramp time; SS/TR pin
open
IO= 0 mA, Time from first switching pulse until 95%
of nominal output voltage; device not in current limit
(1) See also HICCUP Current Limit And Short Circuit Protection (TPS62135 only) and Current Limit And Short Circuit Protection
(TPS621351 only).
(2) The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage
ripple (see Pulse Width Modulation (PWM) Operation).
6
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
7.6 Typical Characteristics
2.5
35
30
25
20
15
10
5
2
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
1.5
1
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
0.5
0
0
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
D001
D001
EN = low
Figure 1. Shutdown Current vs Input Voltage
EN = high
device not switching
Figure 2. Quiescent Supply Current vs Input Voltage
8 Parameter Measurement Information
8.1 Schematic
TPS62135
VBAT = 3.0V to 17V
CIN
L
VOUT = 0.8V to 12V
VIN
EN
SW
VOS
R
3
R
1
COUT
FB
R
2
VSEL
MODE
SS/TR
PG
FB2
GND
CSS
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Measurement Setup
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
TPS62135; Texas Instruments
XFL4020-102; Coilcraft
IC
L
17 V, 4 A Step-Down Converter
1 µH inductor
CIN
10 µF, 25 V, Ceramic, 0805
TMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
-
COUT
COUT
COUT
CSS
R1
2 x 10 µF, 16 V, Ceramic, 0805; all VOUT except 9 V and 1.2 V
3 x 10 µF, 16 V, Ceramic, 0805 for VOUT = 1.2 V
4 x 10 µF, 16 V, Ceramic, 0805 for VOUT = 9 V
3.3 nF, 10 V, Ceramic, X7R
Depending on Vout; see Table 5
Standard 1% metal film
R2
Depending on Vout; see Table 5
Standard 1% metal film
R3
470 kΩ, Chip, 0603, 1/16 W, 1%
Standard 1% metal film
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
9 Detailed Description
9.1 Overview
The TPS62135 synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control. This control loop takes information about output voltage
changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for
steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate
DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves
fast and stable operation with small external components and low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5 MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-Control™ supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage. An internal current limit
supports nominal output currents of up to 4 A. The TPS62135x family offers both excellent DC voltage and
superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF
circuits.
9.2 Functional Block Diagram
PG
VIN
Thermal
Shutdown
Soft
start
UVLO
PG control
HS lim
comp
EN
SS/TR
MODE
power
control
gate
drive
control logic
SW
VSEL
FB2
comp
LS lim
VOS
FB
direct control &
compensation
ramp
_
timer tON, tOFF
comparator
error
amplifier
+
DCS - ControlTM
EN
GND
The discharge switch on the VOS pin is only available in the TPS62135.
8
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable pin of the TPS62135x is compared to a fixed threshold of 0.8 V for a rising
voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network
to achieve a power-up delay.
The Precise Enable input allows the use as a user programmable undervoltage lockout by adding a resistor
divider to the input of the Enable pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62135x starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be
terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown
current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off and the entire
internal control circuitry is switched off.
9.3.2 Power Good (PG)
The TPS62135x has a built in power good (PG) function to indicate whether the output voltage has reached its
target. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output
that requires a pull-up resistor to any voltage up to a voltage level of the input voltage at VIN. It can sink 2 mA of
current and maintain its specified logic low level. PG is low when the device is turned off due to EN, UVLO or
thermal shutdown, so it can be used to actively discharge Vout. VIN must remain present for the PG pin to stay
low.
In case VSEL is used to change the output voltage during operation, PG is not blanked for a change from low
output voltage to high output voltage. It therefore will indicate "power bad" if the voltage step is large enough to
trigger the power good comparator.
If the power good output is not used, it is recommended to tie to GND or leave open.
9.3.3 Pin-Selectable Output Voltage (VSEL and FB2)
The output voltage of the TPS62135x is set by the resistor divider from VOUT to FB to GND. The topology
requires a voltage divider on FB, so the minimum output voltage is 0.8 V while the feedback voltage on the FB
pin is 0.7 V.
VSEL and FB2 can optionally be used to enable a second resistor from FB2 to GND which increases the divider
ratio, hence increasing the output voltage. See Typical Application using VSEL and FB2 .
9.3.4 MODE
When MODE is set low, the device operates in PWM or PFM mode depending on the output current. Automatic
Efficiency Enhancement (AEE) is enabled for highest efficiency over a wide input voltage, output voltage and
output current range. The MODE pin allows to force PWM mode when set high. In forced PWM mode, AEE is
disabled. See also Power Save Mode Operation (PWM/PFM).
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
9.3.6 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 20°C, the converter resumes normal
operation, beginning with Soft-Start. During a PFM skip pause, the thermal shutdown is not active. See also
Power Save Mode Operation (PWM/PFM).
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
TPS62135x has two operating modes: Forced PWM mode discussed in this section and PWM/PFM as discussed
in Power Save Mode Operation (PWM/PFM).
With the MODE pin set to high, the TPS62135x operates with pulse width modulation in continuous conduction
mode (CCM) with a nominal switching frequency of 2.5 MHz. The frequency variation in PWM is controlled and
depends on VIN, VOUT and the inductance. The on-time in forced PWM mode is given by:
VOUT
TON =
´400[ns]
VIN
(1)
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE pin is low, Power Save Mode is allowed. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current. For improved transient response, PWM mode is
forced for 8 switching cycles if the output voltage is above target due to a load release. The Power Save Mode is
entered seamlessly, if the load current decreases and the MODE pin is set low. This ensures a high efficiency in
light load operation. The device remains in Power Save Mode as long as the inductor current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode is seamless in both directions.
The AEE function in TPS62135 and TPS621351 adjust the on-time (TON) in power save mode depending on the
input voltage and the output voltage to maintain highest efficiency. The on-time, in steady-state operation, can be
estimated as:
VIN
TON =100´
[ns]
VIN -VOUT
(2)
For very small output voltages, an absolute minimum on-time of about 50 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the
typical peak inductor current in Power Save Mode is approximated by:
(V IN - VO U T )´ TO N
IL P SM ( peak )
=
L
(3)
There is a minimum off-time which limits the duty cycle of the TPS62135x. When VIN decreases to typically 15%
above VOUT, the TPS62135x does not enter Power Save Mode, regardless of the load current. The device
maintains output regulation in PWM mode.
The output voltage ripple in power save mode is given by Equation 4:
2 æ
ö
÷
ø
L´VIN
1
1
DV =
+
ç
200´C VIN -VOUT VOUT
è
(4)
9.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter operated in PWM mode is given as D = VOUT/VIN. The duty cycle
increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the
minimum off-time of typically 80ns is reached, TPS62135 scales down its switching frequency while it
approaches 100% mode. In 100% mode it keeps the high-side switch on continuously. The high-side switch
stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small
input to output voltage differences, for example for longest operation time of battery-powered applications. In
100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
10
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
Device Functional Modes (continued)
VIN(min) =VOUT + IOUT(RDS(on) + R
L
)
(5)
where:
IOUT is the output current,
RDS(on) is the on-state resistance of the high-side FET and
RL is the DC resistance of the inductor used.
9.4.4 HICCUP Current Limit And Short Circuit Protection (TPS62135 only)
The TPS62135 is protected against overload and short circuit events. If the inductor current exceeds the current
limit I(LIMH), the high side switch is turned off and the low side switch is turned on to ramp down the inductor
current. The high side FET turns on again only if the current in the low side FET has decreased below the low
side current limit threshold. Once the high side switch current limit is triggered for 512 subsequent switching
cycles, the device stops switching. After a typical delay of 800 µs, the device begins a new Soft-Start cycle. This
is called HICCUP short circuit protection. TPS62135 repeats this mode until the short circuit condition
disappears.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
´tPD
(6)
where:
ILIMH is the static current limit as specified in the electrical characteristics
L is the effective inductance at the peak current
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
V IN - VO U T
I
peak ( typ ) = IL IM H
+
´ 50 ns
L
(7)
9.4.5 Current Limit And Short Circuit Protection (TPS621351 only)
The TPS621351 is protected by a current limit the same as the TPS62135 but does not turn off after a certain
time. This allows it to provide the maximum current, for example, charging a large output capacitance without the
need to increase the Soft-Start time. Equation 6 and Equation 7 also apply.
9.4.6 Soft-Start / Tracking (SS/TR)
The internal Soft-Start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving SS/TR pin un-connected provides fastest startup behavior with 150 µs typically.
If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls
the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup sequence as
set by the SS/TR connection.
A voltage supplied to SS/TR can be used to track a master voltage. The output voltage follows this voltage in
both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the
load current. The SS/TR pin of several devices must not be connected with each other.
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Device Functional Modes (continued)
9.4.7 Output Discharge Function (TPS62135 only)
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active once TPS62135 has been enabled at least once since the supply voltage was applied. The
internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon as the device
is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for the
discharge function to remain active typically is 2 V. Output discharge is not activated during a HICCUP current
limit event.
9.4.8 Starting into a Pre-Biased Load (TPS621351 only)
The TPS621351 is capable of starting into a pre-biased output. The device only starts switching when the
internal Soft-Start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPS621351 does not start switching unless the voltage at the
feedback pin drops to the target.
This functionality actually also applies to TPS62135 but the discharge function in TPS62135 keeps the voltage
close to 0 V, so starting into a pre-biased output does not apply.
12
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62135x is adjustable. It can be programmed for output voltages from 0.8 V to 12 V,
using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 700 mV. The value of the
output voltage is set by the selection of the resistor divider from Equation 8. It is recommended to choose resistor
values which allow a current of at least 2 uA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor
values are recommended for highest accuracy and most robust design.
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(8)
10.1.2 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the device´s
control loop. The TPS62135x is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter and Loop Stability). Table 2 can be used to simplify the output filter
component selection.
Table 2. Recommended LC Output Filter Combinations(1)
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
≥400 µF
0.68 µH
1 µH
√
√
√
√
√
√
√
√
√
(2)
(3)
√
√
√
√
√
√
√
√
(3)
1.5 µH
2.2 µH
3.3 µH
√
√
√
(3)
√
(1) The values in the table are nominal values.
(2) This LC combination is the standard value and recommended for most applications.
(3) Output capacitance needs to have a ESR of ≥ 10 mΩ for stable operation, see also Powering Multiple Loads.
10.1.3 Inductor Selection
The TPS62135x is designed for a nominal 1-µH inductor. Larger values can be used to achieve a lower inductor
current ripple but they may have a negative impact on efficiency and transient response. Smaller values than
1µH will cause a larger inductor current ripple which causes larger negative inductor current in forced PWM
mode at low or no output current. Therefore they are not recommended at large voltages across the inductor as it
is the case for high input voltages and low output voltages. With low output current in forced PWM mode this
causes a larger negative inductor current peak which may exceed the negative current limit. At low or no output
current and small inductor values the output voltage can therefore not be regulated any more. More detailed
information on further LC combinations can be found in SLVA463.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 9 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(9)
13
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
VIN(max)
DIL(max)
=
´100ns
L
(min)
(10)
where:
IL(max) is the maximum inductor current
ΔIL is the Peak to Peak Inductor Ripple Current
L(min) is the minimum effective inductor value.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62135x and are recommended for use:
Table 3. List of Inductors
TYPE
XFL4020-102ME
INDUCTANCE [µH]
1.0 µH, ±20%
1.0 µH, ±20%
1.5 µH, ±20%
1.0 µH, ±20%
1.0 µH, ±20%
CURRENT [A](1)
DIMENSIONS [LxBxH] mm MANUFACTURER
5.4
8.7
4 x 4 x 2.1
4 x 4 x 2.1
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Murata
XAL4020-102ME
XAL4020-152ME
7.1
4 x 4 x 2.1
XFL4030-102ME
4.1
3.1(2)
4 x 4 x 3.1
1277AS-H-1R0M (DFE322512C)
3.2 x 2.5 x 1.2
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.
(2) For smallest size solutions that in average do not require the full output current TPS62135x can provide.
The inductor value also determines the load current at which Power Save Mode is entered:
1
Iload(PSM )
=
DIL
2
(11)
10.1.4 Capacitor Selection
10.1.4.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS62135x allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value
has advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
In Power Save Mode, the output voltage ripple depends on the output capacitance, its ESR, ESL and the peak
inductor current. Using ceramic capacitors provides small ESR, ESL and low ripple. The output capacitor needs
to be as close as possible to the device.
For large output voltages the dc bias effect of ceramic capacitors is large and the effective capacitance has to be
observed.
10.1.4.2 Input Capacitor
For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
should be placed between VIN and GND as close as possible to those pins.
Table 4. List of Capacitors(1)
TYPE
NOMINAL CAPACITANCE [µF]
VOLTAGE RATING [V]
SIZE
0805
0805
MANUFACTURER
Taiyo Yuden
TMK212BBJ106MG-T
EMK212BBJ226MG-T
10
22
25
16
Taiyo Yuden
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.
14 Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
10.1.4.3 Soft-Start Capacitor
A capacitor connected between SS/TR pin and GND allows a user programmable start-up slope of the output
voltage. A constant current source provides typically 2.5 µA to charge the external capacitance. The capacitor
required for a given Soft-Start ramp time is given by:
(12)
where:
CSS is the capacitance required at the SS/TR pin and
tSS is the desired Soft-Start ramp time
The fastest achievable typical ramp time is 150 µs even if the external Css capacitance is lower than 680 pF or
the pin is open.
10.1.5 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
electrical characteristics.
When the SS/TR pin voltage is above 0.7 V, the internal voltage is clamped and the device goes to normal
regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage
is inside the recommended operating conditions. For decreasing SS/TR pin voltage in PFM mode, the device
does not sink current from the output. The resulting decrease of the output voltage may therefore be slower than
the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the
voltage rating of the SS/TR pin which is VIN + 0.3 V. The SS/TR pin is internally connected with a resistor to GND
when EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage will go to zero, independent of the
tracking voltage. Figure 4 shows how to connect devices to get ratiometric and simultaneous sequencing by
using the tracking function. See also Voltage Tracking in the systems examples. SS/TR is internally clamped to
approximately 3 V.
DEVICE 1
TPS62135
VIN = 12V
10uF
1 uH
VOUT = 3.3V
22uF
VIN
EN
SW
VOS
560k
150k
FB
VSEL
MODE
SS/TR
PG
FB2
GND
3.3nF
DEVICE 2
TPS62135
VIN = 12V
10uF
1 uH
VOUT = 1.8V
VIN
EN
SW
VOS
470k
300k
22uF
FB
VSEL
PG
FB2
MODE
SS/TR
R5 = 56k
GND
R6 = 15k
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Schematic for Ratiometric and Simultaneous Startup
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
The resistive divider of R5 and R6 can be used to change the ramp rate of VOUT2 to be faster, slower or the
same as VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT of DEVICE 1 to the EN pin of DEVICE2. PG
requires a pull-up resistor. Ratiometric start up sequence happens if both supplies are sharing the same Soft-
Start capacitor. Equation 12 gives the Soft-Start time, though the SS/TR current has to be doubled. Details about
these and other tracking and sequencing circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.7 V, the output voltage accuracy may have a
wider tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the tracking
function, especially for high resistive external voltage dividers on the SS/TR pin.
10.1.6 Output Filter and Loop Stability
The devices of the TPS6213x family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 13:
1
fLC
=
2p L × C
(13)
Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which is affected. More information
including a detailed LC stability matrix can be found in SLVA463.
The TPS62135x devices include an internal 15 pF feedforward capacitor, connected between the VOS and FB
pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors
of the feedback divider, per equation Equation 14 and Equation 15:
1
f
zero
=
2p ´ R
1
´15pF
(14)
1
1
1
æ
ö
÷
ø
f
pole
=
+
ç
2p ´15pF R
1
R
2
è
(15)
Though the TPS62135x devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability versus transient response can be found in SLVA289 and SLVA466.
10.2 Typical Applications
10.2.1 Typical Application with Adjustable Output Voltage
TPS62135
VBAT = 3.0V to 17V
1 uH
VOUT = 0.8V to 12V
VIN
EN
SW
10uF
VOS
R
3
R
1
100kΩ
FB
22uF
R
2
VSEL
MODE
SS/TR
PG
FB2
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Typical Application
16
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
Typical Applications (continued)
10.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. See Table 1 for the Bill of Materials used to generate the application curves.
10.2.1.2 Detailed Design Procedure
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(16)
With VFB = 0.7 V:
Table 5. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
R1
R2
EXACT OUTPUT VOLTAGE
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5 V
51 kΩ
360 kΩ
180 kΩ
130 kΩ
300 kΩ
240 kΩ
150 kΩ
82 kΩ
0.799 V
1.206 V
1.508 V
1.797 V
2.508 V
3.313 V
5.054 V
9.002 V
11.99 V
130 kΩ
150 kΩ
470 kΩ
620 kΩ
560 kΩ
510 kΩ
510 kΩ
1000 kΩ
9 V
43 kΩ
12 V
62 kΩ
10.2.1.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
0.01
0.1
1
4
IOUT (A)
IOUT [A]
D001
D001
Vout = 1.2 V
PFM
TA = 25°C
Vout = 1.2 V
PWM
TA = 25°C
Figure 6. Efficiency vs Output Current
Figure 7. Efficiency vs Output Current
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
90
85
80
75
70
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
65
60
0
0.5
1
1.5
2
2.5
3
3.5
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 1.2 V
PWM
TA= 25 °C
Vout = 1.8 V
PFM
TA = 25°C
Figure 8. Efficiency vs Output Current
Figure 9. Efficiency vs Output Current
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0.01
0.1
1
4
0
0.5
1
1.5
2
2.5
3
3.5
4
IOUT [A]
IOUT (A)
D001
D001
Vout = 1.8 V
PWM
TA = 25°C
Vout = 1.8 V
PWM
TA= 25 °C
Figure 10. Efficiency vs Output Current
Figure 11. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 4 V
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 3.3 V
PFM
TA = 25°C
Vout = 3.3 V
PWM
TA = 25°C
Figure 12. Efficiency vs Output Current
Figure 13. Efficiency vs Output Current
18
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0
0.5
1
1.5
2
2.5
3
3.5
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 3.3 V
PWM
TA = 25°C
Vout = 5 V
PFM
TA = 25°C
Figure 14. Efficiency vs Output Current
Figure 15. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
VIN = 6 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0.01
0.1
1
4
0
0.5
1
1.5
2
2.5
3
3.5
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 5 V
PWM
TA = 25°C
Vout = 5 V
PWM
TA = 25°C
Figure 16. Efficiency vs Output Current
Figure 17. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 9 V
PFM
TA = 25°C
Vout = 9 V
PWM
TA = 25°C
Figure 18. Efficiency vs Output Current
Figure 19. Efficiency vs Output Current
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
100
95
90
85
80
75
70
65
60
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0
0.5
1
1.5
2
2.5
3
3.5
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 9 V
PWM
TA = 25°C
Vout = 1.2 V
PFM
TA = 25°C
Figure 20. Efficiency vs Output Current
Figure 21. Output Voltage vs Output Current
1.210
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.208
1.206
1.204
1.202
1.200
1.198
1.196
1.194
1.192
1.190
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 1.2 V
PWM
TA = 25°C
Vout = 1.8 V
PFM
TA = 25°C
Figure 22. Output Voltage vs Output Current
Figure 23. Output Voltage vs Output Current
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 1.8 V
PWM
TA = 25°C
Vout = 3.3 V
PFM
TA = 25°C
Figure 24. Output Voltage vs Output Current
Figure 25. Output Voltage vs Output Current
20
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 3.3 V
PWM
TA = 25°C
Vout = 5 V
PFM
TA = 25°C
Figure 26. Output Voltage vs Output Current
Figure 27. Output Voltage vs Output Current
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
9.10
9.08
9.06
9.04
9.02
9.00
8.98
8.96
8.94
8.92
8.90
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1E-5
0.0001
0.001
0.01
0.1
1
4
1E-5
0.0001
0.001
0.01
0.1
1
4
IOUT [A]
IOUT [A]
D001
D001
Vout = 5 V
PWM
TA = 25°C
Vout = 9 V
PFM
TA = 25°C
Figure 28. Output Voltage vs Output Current
Figure 29. Output Voltage vs Output Current
9.10
9.08
9.06
9.04
9.02
9.00
8.98
8.96
8.94
8.92
8.90
4.5
4
3.5
3
2.5
2
1.5
1
VIN = 10 V
VIN = 12 V
VIN = 15 V
TA = 25oC
TA = 85oC
TA = 125oC
0.5
0
1E-5
0.0001
0.001
0.01
IOUT [A]
0.1
1
4
3
5
7
9
11
VIN (V)
13
15
17
D001
D001
Vout = 9 V
PWM
TA = 25°C
Vout = 1.2 V
PWM
measurement taken up to 4 A
Curves for TA= 25 °C and TA= 85 °C overlap
Figure 30. Output Voltage vs Output Current
Figure 31. Maximum Output Current vs Input Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
TA = 25oC
TA = 85oC
TA = 125oC
TA = 25oC
TA = 85oC
0.5
0
0.5
0
TA = 125oC
3
5
7
9
11
VIN (V)
13
15
17
3
5
7
9
11
VIN (V)
13
15
17
D001
D001
Vout = 1.8 V
PWM
measurement taken up to 4 A
Vout = 3.3 V
PWM
measurement taken up to 4 A
Figure 32. Maximum Output Current vs Input Voltage
Figure 33. Maximum Output Current vs Input Voltage
4.5
4.5
4
3.5
3
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
TA = 25oC
TA = 85oC
TA = 125oC
TA = 25oC
TA = 85oC
TA = 125oC
0.5
0
0.5
0
5
7
9
11
13
15
17
9
10
11
12
13
14
15
16
17
VIN (V)
VIN (V)
D001
D001
Vout = 5 V
PWM
measurement taken up to 4 A
Vout = 9 V
PWM
measurement taken up to 4 A
Figure 34. Maximum Output Current vs Input Voltage
Figure 35. Maximum Output Current vs Input Voltage
Vin = 12 V;
PFM
Io = 350 mA to 3.1 A;
TA= 25 °C
Vin = 12 V;
PWM
Io = 350 mA to 3.1 A
TA= 25 °C
Vout = 1.2 V;
Vout = 1.2 V
Figure 36. Load Transient Response
Figure 37. Load Transient Response
22
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
Vin = 6 V to 8.4 V;
Vout = 1.2 V
PFM
Io = 1 A
Vin = 6 V to 8.4 V;
Vout = 1.2 V
PWM
Io = 1 A
TA= 25 °C
TA= 25 °C
Figure 38. Line Transient Response
Figure 39. Line Transient Response
Vin = 5 V;
PWM
Rload = 1 kΩ
Vin = 5 V;
Vout = 1.2 V
PFM
Io = 0.1 A
TA= 25 °C
Vout = 1.2 V
TA= 25 °C
Figure 40. Start-Up Timing
Figure 41. Output Voltage Ripple
Vin = 5 V;
PWM
Io = 1 A
Vout = 1.8 V
PFM
Io = 350 mA to 3.1 A
TA= 25 °C
Vout = 1.2 V
TA= 25 °C
Figure 42. Output Voltage Ripple
Figure 43. Load Transient Response
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PFM
Io = 1 A
TA= 25 °C
Vout = 1.8 V
PWM
Io = 350 mA to 3.1 A
TA= 25°C
Figure 44. Load Transient Response
Figure 45. Line Transient Response
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PWM
Io = 1 A
TA= 25 °C
Vout = 1.8 V
PWM
Rload = 1 kΩ
TA= 25 °C
Figure 47. Start-Up Timing
Figure 46. Line Transient Response
Vout = 1.8 V
PFM
Io = 0.1 A
TA= 25 °C
Vout = 1.8 V
PWM
Io = 1 A
TA= 25 °C
Figure 48. Output Voltage Ripple
Figure 49. Output Voltage Ripple
24
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
Vout = 3.3 V
PFM
Io = 350 mA to 3.1 A
TA= 25 °C
Vout = 3.3 V
PWM
Io = 350 mA to 3.1 A
TA= 25 °C
Figure 50. Load Transient Response
Figure 51. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 3.3 V
PFM
Io = 1 A
Vin = 6 V to 8.4 V;
Vout = 3.3 V
PWM
Io = 1 A
TA= 25 °C
TA= 25 °C
Figure 52. Line Transient Response
Figure 53. Line Transient Response
Vout = 3.3 V
PWM
Rload = 1 kΩ
Vout = 3.3 V
PFM
Io = 0.1 A
TA= 25 °C
TA= 25 °C
Figure 54. Start-Up Timing
Figure 55. Output Voltage Ripple
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Vout = 3.3 V
PWM
Io = 1 A
Vout = 5 V
PFM
Io = 350 mA to 3.1 A
TA= 25 °C
TA= 25 °C
Figure 56. Output Voltage Ripple
Figure 57. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 5 V
PFM
Io = 1 A
TA= 25 °C
Vout = 5 V
PWM
Io = 350 mA to 3.1 A
TA= 25 °C
Figure 59. Line Transient Response
Figure 58. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 5 V
PWM
Io = 1 A
TA= 25 °C
Vout = 5 V
PWM
Rload = 1 kΩ
TA= 25 °C
Figure 60. Line Transient Response
Figure 61. Start-Up Timing
26
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
Vout = 5 V
PFM
Io = 0.1 A
TA= 25 °C
Vout = 5 V
PWM
Io = 1 A
TA= 25 °C
Figure 62. Output Voltage Ripple
Figure 63. Output Voltage Ripple
Vout = 9 V
PFM
Io = 300 mA to 2.7 A
TA= 25 °C
Vout = 9 V
PWM
Io = 300 mA to 2.7 A
TA= 25 °C
Figure 64. Load Transient Response
Figure 65. Load Transient Response
Vin = 12 V to 15 V;
Vout = 9 V
PFM
Io = 1 A
Vin = 12 V to 15 V;
Vout = 9 V
PWM
Io = 1 A
TA= 25 °C
TA= 25 °C
Figure 66. Line Transient Response
Figure 67. Line Transient Response
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
Vout = 9 V
PWM
Rload = 1 kΩ
Vout = 9 V
PFM
Io = 0.1 A
TA= 25 °C
TA= 25 °C
Figure 68. Start-Up Timing
Figure 69. Output Voltage Ripple
2.5
2.0
1.5
1.0
0.5
0.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
2
4
6
8
10
12
14
16
18
Input Voltage (V)
D001
Vout = 1.2 V
PWM
TA= 25 °C
Vout = 9 V
PWM
Io = 1 A
TA= 25 °C
Figure 70. Output Voltage Ripple
Figure 71. Switching Frequency vs Input Voltage
3000
2500
2000
1500
1000
500
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN = 3.3 V
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
VIN = 5 V
VIN = 9 V
VIN = 12 V
0
-40
-20
0
20
40
60
80
100
120
2
4
6
8
10
12
14
16
18
Temperature (oC)
Input Voltage (V)
D001
D001
Vout = 1.2 V
PWM
Iout = 1 A
Vout = 1.8 V
PWM
TA= 25 °C
Figure 72. Switching Frequency vs Junction Temperature
Figure 73. Switching Frequency vs Input Voltage
28
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
2700
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2650
2600
2550
2500
2450
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
VIN = 5 V
VIN = 9 V
VIN = 12 V
2400
2350
-40
-20
0
20
40
60
80
100
120
2
4
6
8
10
12
14
16
18
Temperature (oC)
Input Voltage (V)
D001
D001
Vout = 1.8 V
PWM
Iout = 1 A
Vout = 3.3 V
PWM
TA= 25 °C
Figure 74. Switching Frequency vs Junction Temperature
Figure 75. Switching Frequency vs Input Voltage
2650
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2600
2550
2500
2450
2400
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
VIN = 5 V
VIN = 9 V
VIN = 12 V
2350
2300
-40
-20
0
20
40
60
80
100 120
4
6
8
10
12
14
16
18
Temperature (oC)
Input Voltage (V)
D001
D001
Vout = 3.3 V
PWM
Iout = 1 A
Vout = 5 V
PWM
TA= 25 °C
Figure 76. Switching Frequency vs Junction Temperature
Figure 77. Switching Frequency vs Input Voltage
2700
2650
2600
2550
2500
2450
2400
3.0
2.5
2.0
1.5
1.0
0.5
0.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3 A
2350
VIN = 9 V
VIN = 12 V
VIN = 15 V
2300
2250
-40
-20
0
20
40
60
80
100 120 140
9
10
11
12
13
14
15
16
17
Temperature (oC)
Input Voltage (V)
D001
D001
Vout = 5.0 V
PWM
Iout = 1 A
Vout = 9 V
PWM
TA= 25 °C
Figure 78. Switching Frequency vs Junction Temperature
Figure 79. Switching Frequency vs Input Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
2600
2580
2560
2540
2520
2500
2480
2460
2440
20
15
10
5
MIN
TYP
MAX
0
VIN = 12 V
VIN = 15 V
-5
-40
-20
0
20
40
60
80
100 120 140
-10
Temperature (oC)
50 100 150 200 250 300 350 400 450 500 550 600 650
VSS/TR (mV)
D001
D001
Vout = 9.0 V
PWM
Iout = 1 A
Figure 81. Feedback Voltage Accuracy with Voltage
Tracking vs Voltage at SS/TR Pin
Figure 80. Switching Frequency vs Junction Temperature
60
50
40
30
20
10
0
180
150
120
90
60
30
0
-10
-20
-30
-30
-60
-90
-120
-150
-180
-40
Gain
Phase
-50
-60
100
1000
10000
100000
1000000
Frequency (Hz)
D001
Vout = 3.3 V
Io = 3.5 A
Vin = 12 V
TA= 25 °C
Figure 82. Bode Plot
30
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
10.2.2 Typical Application using VSEL and FB2
TPS62135
VBAT = 3.0V to 17V
10uF
1 uH
VOUT = Vo1 / Vo2
VIN
EN
SW
VOS
R 1
R 2
R
CFF
4
22uF
100kΩ
FB
R
3
FB2
VSEL
PG
MODE
SS/TR
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 83. Typical Application using VSEL
10.2.2.1 Design Requirements
VSEL allows to switch between two output voltages by changing the output voltage divider ratio. This is done by
an internal MOSFET connecting resistor R3 to GND. Pulling VSEL high turns on the MOSFET that connects R3
in parallel to R2. The divider ratio is changed such that the output voltage increases from Vo1 to Vo2.
When the output voltage is ramped down and the device is in forced PWM mode, the device will sink current.
10.2.2.2 Detailed Design Procedure
TPS62135x typically does not require a feed forward capacitor in parallel to R1. For a large voltage change such
as 3.3 V to 5 V, a small feed forward capacitor CFFhelps to improve the settling behavior. In order to switch from
an output voltage of for example 3.3 V to an output voltage of 5 V, set the resistor divider for R1 and R2 to 3.3V
and calculate R3 with Equation 17. With R1 = 560 kΩ and R2 = 150 kΩ this gives R3 = 232 kΩ. A feedforward
capacitor of 12 pF was used to get a voltage transition as shown below.
(17)
10.2.2.3 Application Curves
Figure 84. Output Voltage Change from 3.3 V to 5 V in PFM
Figure 85. Output Voltage Change from 3.3 V to 5 V in
with 20 Ω load resistance
PWM with 20 Ω load resistance
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
10.3 System Examples
10.3.1 LED Power Supply
The TPS62135x can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 18. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62135x.
Figure 86 shows an application circuit, tested with analog dimming:
TPS62135
VBAT = 3.0V to 17V
10uF
1 uH
VIN
EN
SW
VOS
22uF
FB
R4
VSEL
MODE
SS/TR
PG
FB2
analog dimming
GND
R5
470pF
Copyright © 2016, Texas Instruments Incorporated
Figure 86. Single Power LED Supply
spacing
The resistor at SS/TR defines the FB voltage. It is set to 350 mV by R5 = 140 kΩ using Equation 18. This cuts
the losses on R4 to half from the nominal 0.7 V of feedback voltage while it still provides good accuracy.
spacing
VFB = 2.5mA´ RSS /TR +11mV
(18)
spacing
The device now supplies a constant current set by resistor R4 from FB to GND. The minimum input voltage has
to be rated according the forward voltage needed by the LED used. More information is available in the
Application Note SLVA451.
spacing
10.3.2 Powering Multiple Loads
In applications where TPS62135x is used to power multiple load circuits, it may be the case that the total
capacitance on the output is very large. In order to properly regulate the output voltage, there needs to be an
appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output
voltage ripple sufficiently high on the VOS pin. With low ESR ceramic capacitors, the output voltage ripple may
get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are
several load circuits with their associated input capacitor on a pcb, these loads are typically distributed across the
board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper
regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n x Cin in the use
case below was 32 x 47 uF of ceramic X7R capacitors.
32
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
System Examples (continued)
Rtrace
Cin
load
Rtrace
TPS62135
VIN = 12V
Cin
1 uH
VOUT = 1.8V
load
VIN
EN
SW
Rtrace
10uF
VOS
R
3
Cin
R
1
100kΩ
load
FB
22uF
Rtrace
R
2
Cin
load
MODE
VSEL
PG
Rtrace
FB2
Cin
load
GND
SS/TR
Rtrace
Cin
load
Copyright © 2016, Texas Instruments Incorporated
Figure 87. Multiple Loads
10.3.3 Voltage Tracking
DEVICE 2 follows the voltage applied to the SS/TR pin. A ramp on SS/TR to 0.7 V ramps the output voltage
according to the 0.7 V reference.
Tracking the 3.3 V of DEVICE 1 requires a resistor divider on SS/TR of DEVICE 2 equal to the output voltage
divider of DEVICE 1. The output current of 2.5µA from the SS/TR pin cases an offset voltage on the resistor
divider formed by R5 and R6. The equivalent resistance of R6 // R5 should therefore be kept below 15kΩ.
DEVICE 1
TPS62135
VIN = 12V
10uF
1 uH
VOUT = 3.3V
22uF
VIN
EN
SW
VOS
560k
150k
FB
VSEL
MODE
SS/TR
PG
FB2
GND
3.3nF
DEVICE 2
TPS62135
VIN = 12V
10uF
1 uH
VOUT = 1.8V
VIN
EN
SW
VOS
470k
300k
22uF
FB
VSEL
PG
FB2
MODE
SS/TR
R5 = 56k
GND
R6 = 15k
Copyright © 2016, Texas Instruments Incorporated
Figure 88. Tracking Example
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
System Examples (continued)
Figure 89. Tracking
10.3.4 Precise Soft-Start Timing
The SS/TR pin of the TPS62135x can be used for tracking as well as for setting the Soft-Start time. The
TPS62135x has one GND terminal which is used for the power ground as well as for the analog ground
connection. While starting the device with a load current above approximately 1 A, the noise on the GND
connection can lead to a Soft-Start time shorter than calculated. There are two external work arounds as given
below.
Adding a 10 kΩ resistor filters the noise on the GND connection and keeps the Soft-Start time at the value
calculated.
Figure 91 does not require an external component. It provides a connection to the internal analog ground by
using the FB2 pin and its internal NMOS to that node. The internal NMOS needs to be turned ON by setting
VSEL = high.
TPS62135
VBAT = 3.0V to 17V
L
VOUT = 0.8V to 12V
VIN
EN
SW
CIN
1 uH
VOS
10uF
R
3
R
1
100kΩ
COUT
FB
2 x 10uF
R
2
VSEL
MODE
SS/TR
PG
FB2
GND
CSS
RSS
Copyright © 2016, Texas Instruments Incorporated
10kΩ
Figure 90. Adding a Series Resistor to CSS
34
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
System Examples (continued)
TPS62135
VBAT = 3.0V to 17V
L
VOUT = 0.8V to 12V
VIN
EN
SW
CIN
1 uH
VOS
10uF
R
3
R
R
1
100kΩ
COUT
FB
2 x 10uF
2
VSEL
MODE
SS/TR
PG
FB2
GND
CSS
Copyright © 2016, Texas Instruments Incorporated
Figure 91. Connecting CSS to the Internal Analog Ground by using FB2
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
11 Power Supply Recommendations
The power supply to the TPS62135x needs to have a current rating according to the supply voltage, output
voltage, and output current of the TPS62135x.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS62135x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 92 for the recommended layout of the TPS62135x, which is designed for common external ground
connections. The input capacitor should be placed as close as possible between the VIN and GND pin of
TPS62135x. Also connect the VOS pin in the shortest way to VOUT at the output capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (for
example SW). As they carry information about the output voltage, they should be connected as close as possible
to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors,
R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The
same applies to R3 if FB2 is used to scale the output voltage.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND and SW pins help to spread the
heat through the pcb.
In case any of the digital inputs EN, VSEL or MODE need to be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in its User's Guide, SLVUAI7.
12.2 Layout Example
GND
GND
C1
C2
EN
PG
VOS
FB
SS/TR
MODE
VSEL
FB2
VIN
VOUT
L1
Figure 92. Layout
36
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
12.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
Improving the power dissipation capability of the PCB design, for example, increasing copper thickness,
thermal vias, number of layers
•
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS62135x is designed for a maximum operating junction temperature (TJ) of 125 °C. Therefore the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the
size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
www.ti.com
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TPS62135
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
TPS621351
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
DCS-Control, AEE, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TPS62135 TPS621351
TPS62135, TPS621351
www.ti.com
SLVSBH3B –JUNE 2016–REVISED APRIL 2017
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Links: TPS62135 TPS621351
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS621351RGXR
TPS621351RGXT
TPS62135RGXR
TPS62135RGXT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RGX
RGX
RGX
RGX
11
11
11
11
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
621351
Samples
Samples
Samples
Samples
NIPDAU
Call TI | NIPDAU
NIPDAU
621351
62135
62135
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS621351RGXR
TPS621351RGXT
TPS62135RGXR
TPS62135RGXT
VQFN-
HR
RGX
RGX
RGX
RGX
11
11
11
11
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.25
2.25
2.25
2.25
3.25
3.25
3.25
3.25
1.05
1.05
1.05
1.05
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS621351RGXR
TPS621351RGXT
TPS62135RGXR
TPS62135RGXT
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RGX
RGX
RGX
RGX
11
11
11
11
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RGX0011A
VQFN - 1 mm max height
SCALE 4.250
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
(0.2) TYP
6X 0.5
7
4
0.3
0.2
3X
2X 0.5
3
1
SYMM
1
0.45
8X
0.35
PIN 1 ID
11
8
0.3
SYMM
8X
0.2
0.1
0.05
C B
C
A
ALL PADS
4221908/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RGX0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (0.5)
8X (0.25)
11
8
8X (0.6)
1
2X (0.5)
SYMM
(2.8)
(R0.05) TYP
3
3X (0.25)
3X (2.4)
4
7
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
ALL AROUND
0.05 MIN
SOLDER MASK
OPENING
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
PADS 4-7 & 8-11
PADS 1-3
SOLDER MASK DETAILS
4221908/A 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
RGX0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (0.5)
8X (0.25)
11
8
8X (0.6)
6X
EXPOSED METAL
9X (0.66)
9X (0.25)
1
SYMM
(2.8)
(0.5) TYP
3
SOLDER MASK
EDGE, TYP
METAL UNDER
SOLDER MASK
TYP
(0.86) TYP
4
7
(R0.05) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PADS 1-3
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221908/A 10/2015
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
TPS62135RGXR
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62135RGXT
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62136
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS621361RGXR
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS621361RGXT
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62136RGXR
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62136RGXT
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 4.0A 降压转换器 | RGX | 11 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62140
3-V to 17-V 2-A Step-Down Converter in 3-mm à 3-mm QFN PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62140A
3-V to 17-V 2-A Step-Down Converter in 3x3 QFN PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62140ARGTR
3-V to 17-V 2-A Step-Down Converter in 3x3 QFN PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62140ARGTT
3-V to 17-V 2-A Step-Down Converter in 3x3 QFN PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS62140RGT
3-V to 17-V 2-A Step-Down Converter in 3-mm à 3-mm QFN PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明