TPS62147RGXT [TI]
采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 2.0A 降压转换器 | RGX | 11 | -40 to 125;
| 型号： | TPS62147RGXT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x3QFN 封装并具有 1% 精度和 PFM/强制 PWM 特性的 3-17V 2.0A 降压转换器 | RGX | 11 | -40 to 125 开关 输出元件 转换器 |
| 文件： | 总46页 (文件大小：2794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62147, TPS62148
ZHCSHZ8B –APRIL 2018 –REVISED FEBRUARY 2023
具有DCS-Control 的TPS62147、TPS62148 高精度3V 至17V 2A 降压转换器
1 特性
3 说明
• 额定TJ 范围内的输出电压精度为±1%（PWM 模
式）
• 输入电压范围：3V 至17V
• 静态电流18µA（典型值）
• 输出电压范围为0.8V 至12V
• 可调软启动
• 强制PWM 或PWM/PFM 操作
• 强制PWM 模式中具有1.25 MHz 或2.5MHz 的开
关频率
TPS62147 和 TPS62148 是基于 DCS-Control 拓扑的
高效且易于使用的同步直流/直流降压转换器。3V 至
17V 的宽输入电压范围使这些器件适用于多节锂离子
电池以及 12V 中间电源轨。该器件提供 2A 连续输出
电流。这些器件可在轻负载时自动进入节能模式，从而
可在整个负载范围内保持高效率。因此，这些器件非常
适合需要联网待机性能的应用，如工业 PC 和视频监
控。MODE 引脚设置为低之后，器件会根据输出电流
以及输入和输出电压自动调整开关频率。该技术称为自
动效率增强 (AEE)，可在整个工作范围内保持高转换效
率。TPS62147、TPS62148 可在 PWM 模式中提供
1% 的输出电压精度，因此可支持高输出电压精度的电
源设计。FSEL 引脚允许在强制 PWM 模式中分别设置
1.25MHz 或2.5MHz 的开关频率。
• 精密使能输入可实现
– 用户定义的欠压锁定
– 准确排序
• 100% 占空比模式
• 自动效率增强(AEE)
• DCS-Control 拓扑
• 有源输出放电(TPS62148)
• HICCUP 过流保护(TPS62147)
• 电源正常状态输出
典型静态电流为 18µA。在关断模式中，典型电流为
1µA。
此器件提供了可调节版本，采用 3mm x 2mm VQFN
封装。
• 采用2mm × 3mm VQFN 封装
2 应用
器件信息
封装(1)
器件型号(2)
TPS62147
TPS62148
封装尺寸（标称值）
3.00mm x 2.00mm
3.00mm x 2.00mm
• 标准12V 电源轨
• 移动和嵌入式计算机
• 多节电池组成的POL 电源
• 工厂自动化、PLC、工业PC
• 楼宇自动化、视频监控
RGX（VQFN，11）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 请参阅Device Comparison Table。
100
90
80
70
60
50
TPS62147
VBAT = 3.0 V to 17 V
10 uF
1 uH / 2.2 uH
VOUT = 0.8 V to 12 V
VIN
EN
SW
VOS
R
R
22 uF / 2x22 uF
1
FB
FSEL
2
FSEL = low: fsw = 1.25 MHz
FSEL = high: fsw = 2.5 MHz
VIN = 4 V
VIN = 5 V
40
PG
30
20
10
0
VIN = 8 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
AGND
GND
MODE
SS/TR
10m
100m
1m 10m
Output Current (A)
100m
1
D041
简化原理图
效率与输出电流间的关系，Vo = 3.3V；fsw =
1.25MHz；PFM
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDR8
TPS62147, TPS62148
ZHCSHZ8B –APRIL 2018 –REVISED FEBRUARY 2023
www.ti.com.cn
Table of Contents
9.3 Feature Description...................................................11
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................15
10.1 Application Information........................................... 15
10.2 Typical Applications................................................ 19
10.3 System Examples................................................... 33
10.4 Power Supply Recommendations...........................35
10.5 Layout..................................................................... 35
11 Device and Documentation Support..........................38
11.1 Device Support........................................................38
11.2 接收文档更新通知................................................... 38
11.3 支持资源..................................................................38
11.4 Trademarks............................................................. 38
11.5 静电放电警告...........................................................38
11.6 术语表..................................................................... 38
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Parameter Measurement Information............................7
8.1 Schematic................................................................... 7
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram.........................................10
Information.................................................................... 38
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2023) to Revision B (February 2023)
Page
• Revision B expanded the listings shown in revision A......................................................................................20
• Updated 图10-7 to the correct graph............................................................................................................... 20
Changes from Revision * (April 2018) to Revision A (January 2023)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 删除了 DCS-Control 和 AEE 商标...................................................................................................................... 1
• Updated Absolute Maximum Ratings table note.................................................................................................4
• Updated 图10-4 Efficiency vs Output current graph on page 20..................................................................... 20
• Updated 图10-8 Efficiency vs Output current graph on page 21..................................................................... 20
• Updated 图10-66 Switching Frequency vs Input Voltage graph on page 30................................................... 20
• Updated 图10-68 Switching Frequency vs Input Voltage graph on page 31................................................... 20
• Removed the graph “Switching Frequency vs Junction Temperature (Vout = 1.2 V, 1.8 V, PWM, FSEL=
high)" on page 30..............................................................................................................................................20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDR8
2
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5 Device Comparison Table
DEVICE NUMBER
FEATURES
OUTPUT VOLTAGE
MARKING
frequency selection on FSEL
HICCUP current limit
TPS62147
adjustable
62147
frequency selection on FSEL
output voltage discharge
TPS62148
adjustable
62148
6 Pin Configuration and Functions
bottom view
top view
7
6
8
7
8
9
EN
PG
VOS
FB
PG
EN
9
6
5
4
SS/TR
VOS
SS/TR
5
4
SW
VIN
10
GND
GND
SW
10
VIN
MODE
FB
MODE
11
11
FSEL
AGND
AGND
FSEL
3
2
1
2
3
1
图6-1. RGX Package 11-Pin VQFN
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
1
VIN
SW
I
2
3
4
5
6
7
Switch pin of the converter connected to the internal Power MOSFETs.
Ground pin.
GND
AGND
FB
I
I
Connect to GND.
I
Voltage feedback input. Connect resistive output voltage divider to this pin.
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
Open drain power good output. Leave open or tie to GND if not used.
VOS
PG
I
O
Enable pin of the device. Connect to logic low to disable the device. Pull high to enable the
device. Do not leave this pin unconnected.
8
9
EN
I
I
Soft-start / Tracking pin. An external capacitor connected from this pin to GND defines the
rise time for the internal reference voltage. The pin can also be used as an input for tracking
and sequencing - see Detailed Description section in this document.
SS/TR
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected.
10
11
MODE
FSEL
I
I
Switching frequency setting pin. Pull to logic low for a switching frequency of 1.25 MHz. Pull
to logic high for a switching frequency of 2.5 MHz. Do not leave FSEL unconnected.
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English Data Sheet: SLVSDR8
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–2
MAX
20
UNIT
V
Pin voltage range(2)
VIN
SW, VOS
VIN+0.3
25.5
V
SW (transient for t<10ns)(2)
EN, MODE, FSEL, PG, FB, , SS/TR
V
VIN+0.3
150
V
–0.3
–40
–65
Operating junction temperature, TJ
Storage temperature range, Tstg
°C
°C
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) While switching
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Electrostatic discharge
Human Body Model - (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Charge Device Model - (CDM), per JEDEC specification JESD22-C101(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
3
NOM
MAX
17
UNIT
V
VIN
VOUT
L
Supply voltage
Output voltage
0.7
0.6
12
V
Effective inductance for fsw = 2.5 MHz
Effective inductance for fsw = 1.25 MHz
Effective output capacitance for fsw = 2.5 MHz(1)
Effective output capacitance for fsw = 1.25 MHz(1)
Effective input capacitance(1) (2)
Operating junction temperature
1
2.9
µH
µH
µF
µF
µF
°C
L
0.7 1.5 or 2.2
2.9
CO
CO
CI
6
12
22
47
10
200(3)
200(3)
3
125
TJ
–40
(1) The values given for all the capacitors are effective capacitance, which includes the dc bias effect. Please check the manufacturer´s dc
bias curves for the effective capacitance vs dc bias voltage applied.
(2) Larger values can be required if the source impedance can not support the transient requirements of the load.
(3) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitors. See also the systems examples 节10.3.2 for applications with many distributed capacitors on the output.
7.4 Thermal Information
TPS62147, TPS62148
THERMAL METRIC(1)
RGX (VQFN)
UNIT
11 PINS
38.4
2.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
7.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
7.6
ψJB
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English Data Sheet: SLVSDR8
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TPS62147, TPS62148
THERMAL METRIC(1)
RGX (VQFN)
11 PINS
3.2
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40 °C to +125 °C and VIN = 3 V to 17 V. Typical values at VIN = 12 V and TA = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
Operating Quiescent
Current
EN = high, IOUT= 0 mA, Device not switching, TJ= 85
°C
IQ
35
46
8
µA
µA
µA
Operating Quiescent
Current
EN = high, IOUT= 0 mA, Device not switching
IQ
18
1
ISD
EN = 0 V, Nominal value at TJ= 25 °C, Max value at
TJ= 85 °C
Shutdown Current
VUVLO
Rising Input Voltage
2.8
2.5
2.9
2.6
3.0
2.7
V
V
Undervoltage Lockout
Threshold
Falling Input Voltage
TSD
Thermal Shutdown
Temperature
Rising Junction Temperature
160
20
°C
Thermal Shutdown
Hysteresis
CONTROL (EN, SS/TR, PG, MODE, FSEL)
High Level Input Voltage
for FSEL, MODE pin
VIH
0.9
V
V
VIL
VIH
VIL
Low Level Input Voltage
for FSEL, MODE pin
0.3
0.83
0.73
100
Input Threshold Voltage
for EN pin; rising edge
0.77
0.67
0.8
0.7
V
Input Threshold Voltage
for EN pin; falling edge
V
Input Leakage Current for
EN, FSEL, MODE
ILKG_EN
VTH_PG
VOL_PG
VIH = VIN or VIL= GND
nA
Power Good Threshold
Voltage; dc level
Rising (%VOUT
)
93%
3%
96%
0.07
98%
4.5%
0.3
Hysteresis
Falling (%VOUT
IPG = -2 mA
)
Power Good Output Low
Voltage
V
Input Leakage Current
(PG)
ILKG_PG
ISS/TR
VPG = 5 V
100
nA
SS/TR pin source current
ISS/TR tolerance
2.5
±0.2
1
µA
µA
TJ= –40 °C to +125 °C
VFB / VSS/TR
Tracking gain
Tracking offset
feedback voltage with VSS/TR = 0 V
11
mV
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English Data Sheet: SLVSDR8
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www.ti.com.cn
7.5 Electrical Characteristics (continued)
TJ = –40 °C to +125 °C and VIN = 3 V to 17 V. Typical values at VIN = 12 V and TA = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SWITCH
RDS(ON)
High-Side MOSFET ON-
Resistance
100
39
180
67
VIN ≥4 V
mΩ
mΩ
Low-Side MOSFET ON-
Resistance
VIN ≥4 V
High-Side MOSFET
Current Limit
dc value(2)
ILIMH
2.8
2.8
3.5
3.5
4.2
4.2
A
A
Low-Side MOSFET
Current Limit
dc value(2)
dc value
ILIML
Negative current limit;
average value
1.5
A
ILIMNEG
OUTPUT
VFB
Feedback Voltage
0.7
1
V
Input Leakage Current
(FB)
ILKG_FB
VFB
VFB= 0.7 V
70
nA
Feedback Voltage
Accuracy(1)
PWM mode
-1%
-1%
1%
2%
VIN ≥VOUT +1 V
VIN ≥VOUT +1 V; VOUT
1.5 V
≥
PFM mode; Co,eff ≥47
µF, L = 1 µH for FSEL =
high, L = 1.5 µH for FSEL
= low
-1%
-1%
-2%
2.5%
2.5%
7.5%
1 V ≤VOUT < 1.5 V
PFM mode; Co,eff ≥47
µF, L = 1 µH for FSEL =
high, Co,eff ≥60 µF, L =
1.5 µH for FSEL = low
VOUT < 1 V
PFM mode; Co,eff ≥75
µF, L = 1 µH for FSEL =
high, L = 1.5 µH for FSEL
= low
VFB
Feedback Voltage
Accuracy with Voltage
Tracking
PWM mode
=
VIN ≥VOUT +1 V; VSS/TR
0.35 V
Load Regulation
Line Regulation
PWM mode operation
0.05
0.02
%/A
%/V
PWM mode operation, IOUT= 1 A, VIN ≥Vout + 1 V or
VIN ≥3.5 V whichever is larger
Output Discharge
Resistance
100
200
Ω
tdelay
tramp
Start-up Delay time
IO= 0 mA, Time from EN=high to start switching; VIN
applied already
300
µs
Ramp time; SS/TR pin
open
IO= 0 mA, Time from first switching pulse until 95% of
nominal output voltage; device not in current limit
150
µs
(1) The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output
voltage ripple (see Pulse Width Modulation (PWM) Operation).
(2) See also 节9.4.5.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDR8
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7.6 Typical Characteristics
2.5
35
30
25
20
15
10
5
2
1.5
1
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
0.5
0
0
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
D001
D001
EN = low
EN = high
device not switching
图7-1. Shutdown Current vs Input Voltage
图7-2. Quiescent Supply Current vs Input Voltage
8 Parameter Measurement Information
8.1 Schematic
TPS62147
VBAT = 3.0 V to 17 V
1 uH
VOUT = 0.8 V to 12 V
VIN
EN
SW
10uF
VOS
R
3
R
R
1
100 kΩ
22 uF
FB
2
FSEL
MODE
SS/TR
PG
AGND
GND
3.3 nF
图8-1. Measurement Setup with FSEL = high
表8-1. List of Components for FSEL = high (fsw = 2.5 MHz)
REFERENCE
DESCRIPTION
MANUFACTURER
IC
L
17 V, 2 A Step-Down Converter
TPS62147; Texas Instruments
XFL4020-102; Coilcraft
1 µH inductor
CIN
10 µF, 25 V, Ceramic, 0805
TMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
EMK212BBJ106MG-T; Taiyo Yuden
-
COUT
COUT
COUT
CSS
R1
2 × 10 µF, 16 V, Ceramic, 0805; all VOUT except 9 V and 1.2 V
3 × 10 µF, 16 V, Ceramic, 0805 for VOUT = 1.2 V
4 × 10 µF, 16 V, Ceramic, 0805 for VOUT = 9 V
3.3 nF, 10 V, Ceramic, X7R
Standard 1% metal film
Depending on Vout; see 表10-4
R2
Standard 1% metal film
Depending on Vout; see 表10-4
R3
Standard 1% metal film
470 kΩ, Chip, 0603, 1/16 W, 1%
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English Data Sheet: SLVSDR8
TPS62147, TPS62148
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www.ti.com.cn
TPS62147
VBAT = 3.0 V to 17 V
10uF
2.2 uH
VOUT = 0.8 V to 12 V
VIN
EN
SW
VOS
R
3
R
1
100 kΩ
2 x 22 uF
FB
R
2
FSEL
MODE
SS/TR
PG
AGND
GND
3.3 nF
图8-2. Measurement Setup with FSEL = low
表8-2. List of Components for FSEL = low (fsw = 1.25 MHz)
REFERENCE
DESCRIPTION
MANUFACTURER(1)
IC
L
17 V, 2 A Step-Down Converter
TPS62147; Texas Instruments
2.2 µH inductor
XFL4020-222; Coilcraft
TMK212BBJ226MG-T; Taiyo Yuden
EMK212BBJ226MG-T; Taiyo Yuden
EMK212BBJ226MG-T; Taiyo Yuden
-
CIN
10 µF, 25 V, Ceramic, 0805
COUT
COUT
CSS
R1
2 × 22 µF, 16 V, Ceramic, 0805; all VOUT except 9 V and 1.2 V
3 × 22 µF, 16 V, Ceramic, 0805 for VOUT = 1.2 V and VOUT = 9 V
3.3 nF, 10 V, Ceramic, X7R
Standard 1% metal film
Depending on Vout; see 表10-4
R2
Standard 1% metal film
Depending on Vout; see 表10-4
R3
Standard 1% metal film
470 kΩ, Chip, 0603, 1/16 W, 1%
(1) See Third-party Products Disclaimer
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDR8
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9 Detailed Description
9.1 Overview
The TPS62147, TPS62148 synchronous switched mode power converters are based on DCS-Control (Direct
Control with Seamless Transition into Power Save Mode), an advanced regulation topology that combines the
advantages of hysteretic, voltage mode and current mode control. This control loop takes information about
output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is
constant for steady state operating conditions, and provides immediate response to dynamic load changes. To
get accurate dc load regulation, a voltage feedback loop is used. The internally compensated regulation network
achieves fast and stable operation with small external components and low ESR capacitors.
The DCS-Control topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 1.25 MHz or 2.5 MHz, depending on the setting of
the FSEL pin, with a controlled frequency variation depending on the input voltage. If the load current decreases,
the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode
the switching frequency decreases linearly with the load current. Because DCS-Control supports both operation
modes within one single building block, the transition from PWM to Power Save Mode is seamless. An internal
current limit supports nominal output currents of up to 2 A. The TPS62147, TPS62148 offer both excellent dc
voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing
interference with RF circuits.
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9.2 Functional Block Diagram
VIN
PG
Thermal
Shutdown
PG
Control
Soft Start
UVLO
HS Limit
Comp
EN
SS/TR
MODE
FSEL
SW
Gate
Driver
Control Logic
Power Control
AGND
Comp
LS Limit
VOS
Output
Discharge
Direct Control
and
Compensation
Comp
Timer tON, tOFF
VFB
–
+
FB
DCS-Control
VREF
GND
The discharge switch on the VOS pin is not available in the TPS62147.
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9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable pin of the TPS62147, TPS62148 is compared to a fixed threshold of 0.8 V for
a rising voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
The Precise Enable input allows the use as a user programmable undervoltage lockout by adding a resistor
divider to the input of the Enable pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62147, TPS62148 start operation when the rising threshold is exceeded. For proper operation, the EN pin
must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a
shutdown current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off
and the entire internal control circuitry is switched off.
9.3.2 Power Good (PG)
The built-in power good (PG) function indicates whether the output voltage has reached its target. The PG signal
can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up
resistor to any voltage up to a voltage level of the input voltage at VIN. It can sink 2 mA of current and maintain
its specified logic low level. PG is low when the device is turned off due to EN, UVLO or thermal shutdown, so it
can be used to actively discharge Vout. VIN must remain present for the PG pin to stay low.
The power good threshold in transient operation can be slightly different from the dc values given in the electrical
specification in case a feed forward capacitor is used on the output voltage divider. Due to the capacitive
coupling, power good can go high for a short time after a release of a short circuit on the output.
If the power good output is not used, it is recommended to tie to GND or leave open.
9.3.3 MODE
When MODE is set low, the device operates in PWM or PFM mode depending on the output current. Automatic
Efficiency Enhancement (AEE), which scales the switching frequency based on the input voltage and the output
voltage, is enabled for highest efficiency over a wide input voltage, output voltage and output current range. The
MODE pin allows to force PWM mode when set high. In forced PWM mode, AEE is disabled. See also Power
Save Mode Operation (PWM/PFM).
9.3.4 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
9.3.5 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 20°C, the converter resumes normal
operation, beginning with soft-start. During a PFM skip pause, the thermal shutdown is not active. See also
Power Save Mode Operation (PWM/PFM).
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9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
TPS62147, TPS62148 have two operating modes: Forced PWM mode discussed in this section and PWM/PFM
as discussed in Power Save Mode Operation (PWM/PFM).
With the MODE pin set to high, the TPS62147, TPS62148 operate with pulse width modulation in continuous
conduction mode (CCM) with a nominal switching frequency of 2.5 MHz for FSEL = high and 1.25 MHz for FSEL
= low. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The on-
time (TON) in forced PWM mode depends on the setting of FSEL.
For FSEL = high (2.5 MHz):
VOUT
TON =
´400[ns]
VIN
(1)
For FSEL = low (1.25 MHz):
VOUT
TON =
´800[ns]
VIN
(2)
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE pin is low, Power Save Mode is allowed. The device operates in PWM mode as long the output
current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters
Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current
becomes smaller than half the inductor ripple current. For improved transient response, PWM mode is forced for
8 switching cycles if the output voltage is above target due to a load release. The Power Save Mode is entered
seamlessly, if the load current decreases and the MODE pin is set low. This ensures a high efficiency in light
load operation. The device remains in Power Save Mode as long as the inductor current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode is seamless in both directions.
The AEE function in TPS62147, TPS62148 adjusts the on-time (TON) in power save mode depending on the
input voltage and the output voltage to maintain highest efficiency. The on-time, in steady-state operation, can be
estimated as follows.
For FSEL = high (2.5MHz):
VIN
TON =100´
[ns]
VIN -VOUT
(3)
For FSEL = low (1.25MHz):
VIN
TON = 200´
[ns]
VIN -VOUT
(4)
For very small output voltages, an absolute minimum on-time of about 50 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the
typical peak inductor current in Power Save Mode is approximated by:
(V IN - VO U T )´ TO N
=
IL P SM ( peak )
L
(5)
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There is a minimum off-time which limits the duty cycle of the TPS62147, TPS62148. When VIN decreases to
typically 15% above VOUT, the TPS62147, TPS62148 does not enter Power Save Mode, regardless of the load
current. The device maintains output regulation in PWM mode.
The output voltage ripple in power save mode is given by 方程式6:
2 æ
ç
ö
÷
ø
L´VIN
1
1
DV =
+
200´C VIN -VOUT VOUT
è
(6)
9.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = VOUT / VIN and increases as the input voltage comes close
to the output voltage. The minimum off-time is about 80 ns. When the minimum off-time is reached, TPS62147,
TPS62148 scale down the switching frequency while they approach 100% mode. In 100% mode the high-side
switch is on continuously. The high-side switch stays turned on as long as the output voltage is below the
internal set point. This allows the conversion of small input to output voltage differences, for example for longest
operation time of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
VIN(min) =VOUT + IOUT(RDS(on) + R
)
L
(7)
where
• IOUT is the output current,
• RDS(on) is the on-state resistance of the high-side FET and
• RL is the dc resistance of the inductor used.
9.4.4 Current Limit And Short Circuit Protection (for TPS62148)
The TPS62148 is protected against overload and short circuit events. If the inductor current exceeds the current
limit I(LIMF), the high side switch is turned off and the low side switch is turned on to ramp down the inductor
current. This allows it to provide the maximum current, for example, charging a large output capacitance without
the must increase the soft-start time.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
´tPD
L
(8)
where
• ILIMF is the static current limit as specified in the electrical characteristics
• L is the effective inductance at the peak current
• VL is the voltage across the inductor (VIN - VOUT) and
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
V IN - VO U T
I
peak ( typ ) = IL IM H
+
´ 50 ns
(9)
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9.4.5 HICCUP Current Limit And Short Circuit Protection (for TPS62147)
The TPS62147 is protected against overload and short circuit events. If the inductor current exceeds the current
limit I(LIMF), the high side switch is turned off and the low side switch is turned on to ramp down the inductor
current. After the switch current limit is triggered for 512 switching cycles, the device stops switching. After a
typical delay of 800 µs, the device begins a new soft-start cycle. This is called HICCUP short circuit protection.
TPS62147 repeats this mode until the short circuit condition disappears.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
equations given under Current Limit And Short Circuit Protection (for TPS62148) also apply.
9.4.6 Soft Start / Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving SS/TR pin unconnected provides fastest startup ramp with 150 µs typically.
If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls
the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup sequence
as set by the SS/TR connection.
A voltage supplied to SS/TR can be used to track a master voltage. The output voltage follows this voltage in
both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the
load current. The SS/TR pin of several devices must not be connected with each other.
9.4.7 Output Discharge Function (TPS62148 only)
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active once TPS62148 has been enabled at least once since the supply voltage was applied. The
internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon as the device
is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for the
discharge function to remain active typically is 2 V.
9.4.8 Starting into a Pre-Biased Load
The TPS62147 is capable of starting into a pre-biased output. The device only starts switching when the internal
soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased to a
higher voltage than the nominal value, the TPS62147 does not start switching unless the voltage at the feedback
pin drops to the target.
This functionality actually also applies to TPS62148 but the discharge function in TPS62148 keeps the voltage
close to 0 V, so starting into a pre-biased output does not apply.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage is adjustable. It can be programmed for output voltages from 0.8 V to 12 V, using a resistor
divider from VOUT to GND. The voltage at the FB pin is regulated to 0.7 V. The value of the output voltage is set
by the selection of the resistor divider from 方程式10. It is recommended to choose resistor values which allow a
current of at least 2 uA, meaning the value of R2 must not exceed 400 kΩ. Lower resistor values are
recommended for highest accuracy and most robust design.
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(10)
10.1.2 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the device´s
control loop. The TPS62147, TPS62148 are optimized to work within a range of external components. The LC
output filters inductance and capacitance have to be considered together, creating a double pole, responsible for
the corner frequency of the converter (see Output Filter and Loop Stability). 表 10-1 can be used to simplify the
output filter component selection.
表10-1. Recommended LC Output Filter Combinations(1)
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
≥400 µF
0.68 µH
1 µH
√
√
√
(2)
(4)
(4)
(4)
√
√
√
√
√
√
√
√
√
√
1.5 µH
2.2 µH
3.3 µH
√
√
√
√
√
√
(3)
√
√
(1) The values in the table are nominal values.
(2) This LC combination is the standard value and recommended for most applications with FSEL = high.
(3) This LC combination is the standard value and recommended for most applications with FSEL = low.
(4) Output capacitance must have a ESR of ≥10 mΩfor stable operation, see also Powering Multiple Loads.
10.1.3 Inductor Selection
The TPS62147, TPS62148 are designed for a nominal 1-µH inductor if FSEL = high and a 1.5-uH or 2.2-uH
inductor if FSEL = low. Larger values can be used to achieve a lower inductor current ripple but they can have a
negative impact on efficiency and transient response. Smaller values than 1 µH cause a larger inductor current
ripple which causes larger negative inductor current in forced PWM mode at low or no output current. Therefore
they are not recommended at large voltages across the inductor as it is the case for high input voltages and low
output voltages. With low output current in forced PWM mode this causes a larger negative inductor current peak
which can exceed the negative current limit.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and dc resistance (DCR). 方程式11 calculates the maximum inductor current.
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DIL(max)
IL(max) = IOUT(max)
+
2
(11)
(12)
VIN(max)
DIL(max)
=
´100ns
L
(min)
where
• IL(max) is the maximum inductor current
• ΔIL is the Peak to Peak Inductor Ripple Current
• L(min) is the minimum effective inductor value.
Above equation is valid for FSEL = high. With FSEL = low, the ON-time is doubled from 100 ns to 200 ns so the
peak inductor current doubles given the same input voltage and inductor.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62147, TPS62148 and are recommended for use:
表10-2. List of Inductors(1)
TYPE
INDUCTANCE [µH]
1.0 µH, ±20%
1.2µH, ±20%
1.0 µH, ±20%
1.5 µH, ±20%
2.2 µH, ±20%
2.2 µH, ±20%
1.5 µH, ±20%
1.0 µH, ±20%
CURRENT [A](2)
DIMENSIONS [LxBxH] mm MANUFACTURER(1)
XFL3012-102ME
XFL4015-122ME
XFL4020-102ME
XFL4020-152ME
XFL4020-222ME
DFE322512F-2R2M
DFE322512F-1R5M
DFE322512F-1R0M
2.3
4.5
5.4
4.6
3.7
2.6
3.0
3.8
3 x 3 x 1.3
4 x 4 x 1.6
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Murata
4 × 4 x 2.1
4 x 4 x 2.1
4 x 4 x 2.1
3.2 x 2.5 x 1.2
3.2 x 2.5 x 1.2
3.2 x 2.5 x 1.2
Murata
Murata
(1) See Third-Party Products Disclaimer
(2) Lower of IRMS at 40°C rise or ISAT at 30% drop.
The inductor value also determines the load current at which Power Save Mode is entered:
1
Iload(PSM )
=
DIL
2
(13)
10.1.4 Capacitor Selection
10.1.4.1 Output Capacitor
The recommended value for the output capacitor is 22 µF with FSEL = high (fsw = 2.5 MHz) and 2 x 22 µF with
FSEL = low (fsw = 1.25 MHz). The architecture of the TPS62147, TPS62148 allows the use of tiny ceramic
output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple
and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance
variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value has
advantages like smaller voltage ripple and a tighter dc output accuracy in Power Save Mode.
In Power Save Mode, the output voltage ripple depends on the output capacitance, its ESR, ESL and the peak
inductor current. Using ceramic capacitors provides small ESR, ESL and low ripple. The output capacitor must
be as close as possible to the device.
For large output voltages the dc bias effect of ceramic capacitors is large and the effective capacitance has to be
observed.
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10.1.4.2 Input Capacitor
For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
must be placed between VIN and GND as close as possible to those pins.
表10-3. List of Capacitors(1)
NOMINAL CAPACITANCE [µF] VOLTAGE RATING [V]
TYPE
TMK212BBJ106MG-T
SIZE
MANUFACTURER(1)
Taiyo Yuden
10
22
25
16
0805
0805
EMK212BBJ226MG-T
Taiyo Yuden
(1) See Third-Party Products Disclaimer
10.1.4.3 Soft-Start Capacitor
A capacitor connected between SS/TR pin and GND sets user programmable start-up slope of the output
voltage. A constant current source provides typically 2.5 µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time is given by:
(14)
where
• CSS is the capacitance required at the SS/TR pin and
• tSS is the desired soft-start ramp time
The fastest achievable typical ramp time is 150 µs even if the external Css capacitance is lower than 680 pF or
the pin is open.
10.1.5 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
electrical characteristics.
VFB » VSS /TR
(15)
When the SS/TR pin voltage is above 0.7 V, the internal voltage is clamped and the device goes to normal
regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage
is inside the recommended operating conditions. For decreasing SS/TR pin voltage in PFM mode, the device
does not sink current from the output. The resulting decrease of the output voltage can therefore be slower than
the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the
voltage rating of the SS/TR pin which is VIN + 0.3 V. The SS/TR pin is internally connected with a resistor to
GND when EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage goes to zero, independent of the
tracking voltage. 图10-1 shows how to connect devices to get ratiometric and simultaneous sequencing by using
the tracking function. See also 节 10.3.3 in the systems examples. SS/TR is internally clamped to approximately
3 V.
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DEVICE 1
TPS62147
VIN = 12
10 uF
1 uH
VOUT = 3.3 V
VIN
EN
SW
VOS
560 k
150 k
22 uF
FB
FSEL
MODE
SS/TR
PG
AGND
GND
3.3 nF
DEVICE 2
TPS62147
VIN = 12 V
10 uF
1 uH
VOUT = 1.8 V
VIN
EN
SW
VOS
470k
22 uF
FB
300 k
FSEL
PG
AGND
MODE
SS/TR
R5 = 56 k
R6 = 15 k
GND
图10-1. Schematic for Ratiometric and Simultaneous Startup
The resistive divider of R5 and R6 can be used to change the ramp rate of VOUT2 to be faster, slower or the
same as VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT of DEVICE 1 to the EN pin of DEVICE2. PG
requires a pull-up resistor. Ratiometric start up sequence happens if both supplies are sharing the same soft-
start capacitor. 方程式14 gives the soft-start time, though the SS/TR current has to be doubled.
Note: If the voltage at the FB pin is below its typical value of 0.7 V, the output voltage accuracy can have a wider
tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the tracking
function, especially for high resistive external voltage dividers on the SS/TR pin.
10.1.6 Output Filter and Loop Stability
The TPS62147, TPS62148 are internally compensated to be stable with L-C filter combinations corresponding to
a corner frequency to be calculated with 方程式16:
1
fLC
=
2p L × C
(16)
Proven nominal values for inductance and ceramic capacitance are given in 表 10-1 and are recommended for
use. Different values can work, but care has to be taken for the loop stability which is affected.
The TPS62147, TPS62148 include an internal 15 pF feedforward capacitor, connected between the VOS and
FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the
resistors of the feedback divider, per equation 方程式17 and 方程式18:
1
f
zero
=
2p ´ R
1
´15pF
(17)
1
1
1
æ
ö
÷
ø
f
pole
=
+
ç
2p ´15pF R
1
R
2
è
(18)
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Though the TPS62147, TPS62148 are stable without the pole and zero being in a particular location, adjusting
their location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability versus transient response can be found in SLVA289 and SLVA466.
10.2 Typical Applications
10.2.1 Typical Application with Adjustable Output Voltage
TPS62147
VBAT = 3.0 V to 17 V
10uF
1 uH
VOUT = 0.8 V to 12 V
VIN
EN
SW
VOS
R
3
R
1
100 kΩ
22 uF
FB
R
2
FSEL
MODE
SS/TR
PG
AGND
GND
3.3 nF
10.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. See 表8-1 for the Bill of Materials used to generate the application curves.
10.2.1.2 Detailed Design Procedure
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(19)
With VFB = 0.7 V:
表10-4. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
R1
R2
EXACT OUTPUT VOLTAGE
0.799 V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5 V
51 kΩ
130 kΩ
150 kΩ
470 kΩ
620 kΩ
560 kΩ
510 kΩ
510 kΩ
1000 kΩ
360 kΩ
180 kΩ
130 kΩ
300 kΩ
240 kΩ
150 kΩ
82 kΩ
1.206 V
1.508 V
1.797 V
2.508 V
3.313 V
5.054 V
9.002 V
9 V
43 kΩ
11.99 V
12 V
62 kΩ
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10.2.1.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m 10m
Output Current (A)
100m
1
D025
D037
Vout = 1.2 V PFM FSEL = high
TA = 25°C
Vout = 1.2 V
PFM FSEL = low
TA = 25°C
图10-2. Efficiency vs Output Current
图10-3. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
IOUT (A)
1
2
10m
100m
Output Current (A)
1
Vout = 1.2 V PWM FSEL = high
TA = 25°C
D038
Vout = 1.2 V
PWM FSEL = low
TA = 25°C
图10-4. Efficiency vs Output Current
图10-5. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m 10m
Output Current (A)
100m
1
D023
D039
Vout = 1.8 V PFM FSEL = high
TA = 25°C
Vout = 1.8 V
PFM FSEL = low
TA = 25°C
图10-6. Efficiency vs Output Current
图10-7. Efficiency vs Output Current
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100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0
10m
100m
IOUT (A)
1
2
10m
100m
Output Current (A)
1
Vout = 1.8 V PWM FSEL = high
TA = 25°C
D040
Vout = 1.8 V
PWM FSEL = low
TA = 25°C
图10-8. Efficiency vs Output Current
图10-9. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 4 V
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 5 V
VIN = 8 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m 10m
Output Current (A)
100m
1
D021
D041
Vout = 3.3 V PFM FSEL = high
TA = 25°C
Vout = 3.3 V
PFM FSEL = low
TA = 25°C
图10-10. Efficiency vs Output Current
图10-11. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 12 V
VIN = 15 V
10m
100m
IOUT (A)
1
2
10m
100m
Output Current (A)
1
D020
D042
Vout = 3.3 V PWM FSEL = high
TA = 25°C
Vout = 3.3 V
PWM FSEL = low
TA = 25°C
图10-12. Efficiency vs Output Current
图10-13. Efficiency vs Output Current
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100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m 10m
Output Current (A)
100m
1
D019
D043
Vout = 5 V PFM FSEL = high
TA = 25°C
Vout = 5 V
PFM FSEL = low
TA = 25°C
图10-14. Efficiency vs Output Current
图10-15. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
IOUT (A)
1
2
10m
100m
Output Current (A)
1
D018
D044
Vout = 5 V PWM FSEL = high
TA = 25°C
Vout = 5 V
PWM FSEL = low
TA = 25°C
图10-16. Efficiency vs Output Current
图10-17. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m 10m
Output Current (A)
100m
1
D017
D045
Vout = 9 V PFM FSEL = high
TA = 25°C
Vout = 9 V
PFM FSEL = low
TA = 25°C
图10-18. Efficiency vs Output Current
图10-19. Efficiency vs Output Current
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100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0
10m
100m
IOUT (A)
1
2
0.01
0.1
Output Current (A)
1
2
D046
D016
Vout = 9 V PWM FSEL = high
TA = 25°C
Vout = 9 V
PWM FSEL = low
TA = 25°C
图10-20. Efficiency vs Output Current
图10-21. Efficiency vs Output Current
1.23
1.225
1.22
1.21
1.208
1.206
1.204
1.202
1.2
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.215
1.21
1.198
1.196
1.194
1.192
1.19
1.205
1.2
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.195
1.19
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m
10m
IOUT (A)
100m
1
2
D015
D014
Vout = 1.2 V
PFM
TA = 25°C
Vout = 1.2 V
PWM
TA = 25°C
图10-22. Output Voltage vs Output Current
图10-23. Output Voltage vs Output Current
1.82
1.815
1.81
1.82
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.815
1.81
1.805
1.8
1.805
1.8
1.795
1.79
1.795
1.79
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.785
1.78
1.785
1.78
10m
100m
1m
10m
IOUT (A)
100m
1
2
10m
100m
1m
10m
IOUT (A)
100m
1
2
D013
D012
Vout = 1.8 V
PFM
TA = 25°C
Vout = 1.8 V
PWM
TA = 25°C
图10-24. Output Voltage vs Output Current
图10-25. Output Voltage vs Output Current
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3.34
3.33
3.32
3.31
3.3
3.34
3.33
3.32
3.31
3.3
3.29
3.29
3.28
3.27
3.26
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
3.28
3.27
3.26
10m
100m
1m
10m
IOUT (A)
100m
1
2
1000m 100m
1m
10m
IOUT [A]
100m
1
2
D011
D008
Vout = 3.3 V
PFM
TA = 25°C
Vout = 3.3 V
PWM
TA = 25°C
图10-26. Output Voltage vs Output Current
图10-27. Output Voltage vs Output Current
5.05
5.05
VIN = 6 V
VIN = 8 V
VIN = 6 V
VIN = 8 V
5.04
5.04
VIN = 10 V
VIN = 12 V
VIN = 15 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
5.03
5.03
5.02
5.01
5
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
4.99
4.98
4.97
4.96
4.95
10m
100m
1m
10m
IOUT [A]
100m
1
2
10m
100m
1m
10m
IOUT (A)
100m
1
2
D010
D009
Vout = 5 V
PFM
TA = 25°C
Vout = 5 V
PWM
TA = 25°C
图10-28. Output Voltage vs Output Current
图10-29. Output Voltage vs Output Current
9.1
VIN = 10 V
VIN = 12 V
VIN = 15 V
9.08
9.06
9.04
9.02
9
8.98
8.96
8.94
8.92
8.9
10m
100m
1m
10m
IOUT (A)
100m
1
2
Vin = 12 V;
PFM
Io = 200 mA to 1.8 A;
TA= 25 °C
D007
Vout = 1.2 V; FSEL = high
Vout = 9 V
PFM
TA = 25°C
图10-31. Load Transient Response
图10-30. Output Voltage vs Output Current
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Vin = 6 V to 8.4 V;
Vout = 1.2 V
PFM
Io = 1 A
Vin = 12 V;
PWM Io = 200 mA to 1.8 A
FSEL = high
TA= 25 °C
Vout = 1.2 V
FSEL = high
TA= 25 °C
图10-33. Line Transient Response
图10-32. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 1.2 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
图10-34. Line Transient Response
Vin = 5 V;
PFM
Rload = 1 kΩ
Vout = 1.2 V
FSEL = high
TA= 25 °C
图10-35. Start-Up Timing
Vin = 5 V;
PFM
Io = 0.1 A
TA= 25 °C
Vin = 5 V;
PWM
Io = 1 A
Vout = 1.2 V
FSEL = high
Vout = 1.2 V
FSEL = high
TA= 25 °C
图10-36. Output Voltage Ripple
图10-37. Output Voltage Ripple
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Vin = 12 V
PFM Io = 200 mA to 1.8 A
Vin = 12 V
PWM Io = 200 mA to 1.8 A
Vout = 1.8 V
FSEL = high
TA= 25 °C
Vout = 1.8 V
FSEL = high
TA= 25°C
图10-38. Load Transient Response
图10-39. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PFM
Io = 1 A
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
FSEL = high
TA= 25 °C
图10-40. Line Transient Response
图10-41. Line Transient Response
Vin = 5 V
PWM
Vin = 5 V
PFM
Io = 0.1 A
TA= 25 °C
Rload = 1 kΩ
Vout = 1.8 V
FSEL = high
Vout = 1.8 V
FSEL = high
TA= 25 °C
图10-43. Output Voltage Ripple
图10-42. Start-Up Timing
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Vin = 12 V
PFM Io = 200 mA to 1.8 A
Vout = 3.3 V
FSEL = high
TA= 25 °C
Vin = 5 V
Vout = 1.8 V
PWM
Io = 1 A
图10-45. Load Transient Response
FSEL = high
TA= 25 °C
图10-44. Output Voltage Ripple
Vin = 6 V to 8.4 V;
Vout = 3.3 V
PFM
Io = 1 A
Vin = 12 V
PWM Io = 200 mA to 1.8 A
FSEL = high
TA= 25 °C
Vout = 3.3 V
FSEL = high
TA= 25 °C
图10-47. Line Transient Response
图10-46. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 3.3 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
图10-48. Line Transient Response
Vin = 5V
PWM
Rload = 1 kΩ
Vout = 3.3 V
FSEL = high
TA= 25 °C
图10-49. Start-Up Timing
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Vin = 12 V
PFM
Io = 0.1 A
TA= 25 °C
Vin = 12 V
PWM
Io = 1 A
Vout = 3.3 V
FSEL = high
Vout = 3.3 V
FSEL = high
TA= 25 °C
图10-50. Output Voltage Ripple
图10-51. Output Voltage Ripple
Vin = 12 V
Vout = 5 V
PFM Io = 200 mA to 1.8 A
Vin = 12 V
Vout = 5 V
PWM
Io = 200 mA to 1.8 A
TA= 25 °C
FSEL = high
TA= 25 °C
FSEL = high
图10-52. Load Transient Response
图10-53. Load Transient Response
Vin = 6 V to 8.4 V;
Vout = 5 V
PFM
Io = 1 A
Vin = 6 V to 8.4 V;
Vout = 5 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
FSEL = high
TA= 25 °C
图10-54. Line Transient Response
图10-55. Line Transient Response
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Vin = 12 V
Vout = 5 V
PWM
Vin = 12 V
Vout = 5 V
PFM
Io = 0.1 A
TA= 25 °C
Rload = 1 kΩ
FSEL = high
FSEL = high
TA= 25 °C
图10-57. Output Voltage Ripple
图10-56. Start-Up Timing
Vin = 12 V
Vout = 9 V
PFM Io = 200 mA to 1.8 A
Vin = 12 V
Vout = 5 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
FSEL = high
TA= 25 °C
图10-59. Load Transient Response
图10-58. Output Voltage Ripple
Vin = 12 V to 15 V;
Vout = 9 V
PFM
Io = 1 A
FSEL = high
TA= 25 °C
Vin = 12 V
Vout = 9 V
PWM Io = 200 mA to 1.8 A
FSEL = high TA= 25 °C
图10-61. Line Transient Response
图10-60. Load Transient Response
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Vin = 12 V to 15 V;
Vout = 9 V
PWM
Io = 1 A
FSEL = high
TA= 25 °C
图10-62. Line Transient Response
Vin = 12 V
Vout = 9 V
PWM
Rload = 1 kΩ
FSEL = high
TA= 25 °C
图10-63. Start-Up Timing
Vin = 12 V
Vout = 9 V
PFM
Io = 0.1 A
TA= 25 °C
Vin = 12 V
Vout = 9 V
PWM
Io = 1 A
FSEL = high
FSEL = high
TA= 25 °C
图10-64. Output Voltage Ripple
图10-65. Output Voltage Ripple
2
1.75
1.5
1.25
1
1.6
1.4
1.2
1
.8
0.75
0.5
0.25
0
.6
Io = 0 A
Io = 1 A
Io = 2 A
.4
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
.2
3
5
7
9
11
13
15
17
0
Input Voltage (V)
PWM FSEL =
high
3
5
7
9
11
Input Voltage (V)
13
15
17
Vout = 1.2 V
TA= 25 °C
D047
Vout = 1.2 V
PWM FSEL =
low
TA= 25 °C
图10-66. Switching Frequency vs Input Voltage
图10-67. Switching Frequency vs Input Voltage
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2.5
2.25
2
1.6
1.4
1.2
1
1.75
1.5
1.25
1
.8
.6
0.75
0.5
Io = 0 A
Io = 1 A
Io = 2 A
.4
0.25
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
.2
0
3
5
7
9
11
13
15
17
0
Input Voltage (V)
3
5
7
9
11
Input Voltage (V)
13
15
17
Vout = 1.8 V
PWM FSEL = high
TA= 25 °C
D048
Vout = 1.8 V
PWM FSEL = low
TA= 25 °C
图10-68. Switching Frequency vs Input Voltage
图10-69. Switching Frequency vs Input Voltage
3
2.5
2
1.6
1.4
1.2
1
.8
1.5
.6
.4
1
IO = 0 A
IO = 1 A
IO = 2 A
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
.2
0
0.5
3
5
7
9 11
Input Voltage (V)
13
15 17
3
5
7
9 11
Input Voltage (V)
13
15
17
D003
D049
Vout = 3.3 V
PWM FSEL = high
TA= 25 °C
Vout = 3.3 V
PWM FSEL = low
TA= 25 °C
图10-70. Switching Frequency vs Input Voltage
图10-71. Switching Frequency vs Input Voltage
2650
3
2600
2550
2500
2450
2.5
2
1.5
1
2400
VIN = 5 V
VIN = 9 V
VIN = 12 V
IO = 0 A
IO = 1 A
IO = 2 A
2350
0.5
2300
-40
0
-20
0
20
40
60
80
100 120
5
7
9
11
Input Voltage (V)
13
15 17
Temperature (oC)
D001
D004
Vout = 3.3 V
PWM FSEL = high
Iout = 1 A
Vout = 5 V
PWM FSEL = high
TA= 25 °C
图10-72. Switching Frequency vs Junction
图10-73. Switching Frequency vs Input Voltage
Temperature
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TPS62147, TPS62148
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1.6
1.4
1.2
1
2700
2650
2600
2550
2500
2450
2400
2350
2300
2250
.8
.6
.4
VIN = 9 V
VIN = 12 V
VIN = 15 V
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
.2
0
-40
-20
0
20
40
60
80
100 120 140
D001
5
7
9
11
Input Voltage (V)
13
15
17
Temperature (oC)
D050
Vout = 5 V
PWM FSEL = high
Iout = 1 A
Vout = 5 V
PWM FSEL = low
TA= 25 °C
图10-75. Switching Frequency vs Junction
图10-74. Switching Frequency vs Input Voltage
Temperature
3
2.5
2
1.6
1.4
1.2
1
1.5
1
.8
.6
.4
IO = 0 A
IO = 1 A
IO= 2 A
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
0.5
0
.2
0
9
10
11
12
Input Voltage (V)
13
14
15
16
17
9
10
11
12
Input Voltage (V)
13
14
15
16
17
D005
D051
Vout = 9 V
PWM FSEL = high
TA= 25 °C
Vout = 9 V
PWM FSEL = low
TA= 25 °C
图10-76. Switching Frequency vs Input Voltage
图10-77. Switching Frequency vs Input Voltage
2600
2580
2560
2540
2520
2500
2480
20
MIN
TYP
MAX
15
10
5
0
2460
2440
VIN = 12 V
VIN = 15 V
-5
-40
-20
0
20
40
60
80
100 120 140
-10
Temperature (oC)
D001
50 100 150 200 250 300 350 400 450 500 550 600 650
VSS/TR (mV)
Vout = 9.0 V PWM FSEL = high
Iout = 1 A
D001
图10-79. Feedback Voltage Accuracy with Voltage
图10-78. Switching Frequency vs Junction
Tracking vs Voltage at VSS/TR
Temperature
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10.3 System Examples
10.3.1 LED Power Supply
The TPS62147, TPS62148 can be used as a power supply for power LEDs. The FB pin can be easily set down
to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to
avoid excessive power loss. Because this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an
external resistor per 方程式 20. This drop, proportional to the LED current, is used to regulate the output voltage
(anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the
TPS62147, TPS62148.
图10-80 shows an application circuit, tested with analog dimming:
TPS62147
VBAT = 3.0 V to 17
10 uF
1 uH
VIN
EN
SW
VOS
22 uF
FB
R4
FSEL
MODE
SS/TR
PG
AGND
GND
Analog Dimming
R5
470 pF
图10-80. Single Power LED Supply
spacing
The resistor at SS/TR defines the FB voltage. It is set to 350 mV by R5 = 140 kΩusing 方程式 20. This cuts the
losses on R4 to half from the nominal 0.7 V of feedback voltage while it still provides good accuracy.
spacing
VFB = 2.5mA´ RSS /TR +11mV
(20)
spacing
The device supplies a constant current set by resistor R4 from FB to GND. The minimum input voltage has to be
rated according the forward voltage needed by the LED used. More information is available in the Application
Note SLVA451.
spacing
10.3.2 Powering Multiple Loads
In applications where TPS62147, TPS62148 are used to power multiple load circuits, it can be the case that the
total capacitance on the output is very large. To properly regulate the output voltage, there must be an
appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output
voltage ripple sufficiently high on the VOS pin. With low ESR ceramic capacitors, the output voltage ripple can
get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are
several load circuits with their associated input capacitor on a pcb, these loads are typically distributed across
the board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for
proper regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × Cin in the use
case below was 32 × 47 uF of ceramic X7R capacitors.
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Rtrace
Rtrace
Cin
Cin
Cin
Cin
Cin
Cin
Load
Load
Load
Load
Load
Load
TPS62147
VIN = 12 V
1 uH
VOUT = 1.8 V
VIN
SW
Rtrace
Rtrace
10 uF
VOS
R
EN
3
R
1
100 kΩ
22 uF
FB
R
2
MODE
FSEL
PG
Rtrace
Rtrace
AGND
GND
SS/TR
图10-81. Multiple Loads
10.3.3 Voltage Tracking
DEVICE 2 follows the voltage applied to the SS/TR pin. A ramp on SS/TR to 0.7 V ramps the output voltage
according to the 0.7 V reference.
Tracking the 3.3 V of DEVICE 1 requires a resistor divider on SS/TR of DEVICE 2 equal to the output voltage
divider of DEVICE 1.
DEVICE 1
TPS62147
VIN = 12
10 uF
1 uH
VOUT = 3.3 V
VIN
EN
SW
VOS
560 k
150 k
22 uF
FB
FSEL
MODE
SS/TR
PG
AGND
GND
3.3 nF
DEVICE 2
TPS62147
VIN = 12 V
10 uF
1 uH
VOUT = 1.8 V
VIN
EN
SW
VOS
470k
22 uF
FB
300 k
FSEL
PG
AGND
MODE
SS/TR
R5 = 56 k
GND
R6 = 15 k
图10-82. Tracking Example
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图10-83. Tracking
10.3.4 Precise Soft-Start Timing
The SS/TR pin of the TPS62147, TPS62148 can be used for tracking as well as for setting the soft-start time.
The TPS62147, TPS62148 has one GND terminal which is used for the power ground as well as for the analog
ground connection. While starting the device with a load current above approximately 1 A, the noise on the GND
connection can lead to a soft-start time shorter than calculated. There is an external work around as given below.
Adding a 10 kΩ resistor filters the noise on the GND connection and keeps the soft-start time at the value
calculated.
TPS62147
VBAT = 3.0 V to 17 V
L
VOUT = 0.8 V to 12 V
VIN
EN
SW
CIN
1 uH
VOS
10 uF
R
3
R
1
100 kΩ
COUT
FB
2 x 10 uF
R
2
FSEL
MODE
SS/TR
PG
AGND
GND
CSS
RSS
10 kΩ
图10-84. Adding a Series Resistor to CSS
10.4 Power Supply Recommendations
The power supply to the TPS62147, TPS62148 must have a current rating according to the supply voltage,
output voltage, and output current of the TPS62147, TPS62148.
10.5 Layout
10.5.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS62147, TPS62148 demands careful attention to ensure
operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line
and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity.
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See 节10.5.2 for the recommended layout of the TPS62147, TPS62148, which is designed for common external
ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin of
TPS62147, TPS62148. Also connect the VOS pin in the shortest way to VOUT at the output capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops which conduct an
alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS must be connected with short wires and not nearby high dv/dt signals (for
example SW). As they carry information about the output voltage, they must be connected as close as possible
to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors,
R1 and R2, must be kept close to the IC and connect directly to those pins and the system ground plane. The
same applies to R3 if FB2 is used to scale the output voltage.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND and SW pins help to spread the
heat through the pcb.
In case any of the digital inputs EN, FSEL or MODE must be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics. Please also see the EVM
User´s Guide SLVUBE9.
10.5.2 Layout Example
GND
GND
C1
C2
EN
PG
VOS
FB
SS/TR
MODE
FSEL
AGND
VIN
VOUT
L1
图10-85. Layout
10.5.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design, for example, increasing copper thickness,
thermal vias, number of layers
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs), and
(Semiconductor and IC Package Thermal Metrics application report).
The TPS62147, TPS62148 are designed for a maximum operating junction temperature (TJ) of 125 °C.
Therefore the maximum output power is limited by the power losses that can be dissipated over the actual
thermal resistance, given by the package and the surrounding PCB structures. If the thermal resistance of the
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package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce
the thermal resistance. To get an improved thermal behavior, TI recommends to use top layer metal to connect
the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for
improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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English Data Sheet: SLVSDR8
TPS62147, TPS62148
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SLVSDR8
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PACKAGE OPTION ADDENDUM
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2-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62147RGXR
TPS62147RGXT
TPS62148RGXR
TPS62148RGXT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RGX
RGX
RGX
RGX
11
11
11
11
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
62147
62147
62148
62148
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62147RGXR
TPS62147RGXT
TPS62148RGXR
TPS62148RGXT
VQFN-
HR
RGX
RGX
RGX
RGX
11
11
11
11
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.25
2.25
2.25
2.25
3.25
3.25
3.25
3.25
1.05
1.05
1.05
1.05
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62147RGXR
TPS62147RGXT
TPS62148RGXR
TPS62148RGXT
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RGX
RGX
RGX
RGX
11
11
11
11
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RGX0011A
VQFN - 1 mm max height
SCALE 4.250
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
(0.2) TYP
6X 0.5
7
4
0.3
0.2
3X
2X 0.5
3
1
SYMM
1
0.45
8X
0.35
PIN 1 ID
11
8
0.3
SYMM
8X
0.2
0.1
0.05
C B
C
A
ALL PADS
4221908/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RGX0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (0.5)
8X (0.25)
11
8
8X (0.6)
1
2X (0.5)
SYMM
(2.8)
(R0.05) TYP
3
3X (0.25)
3X (2.4)
4
7
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
ALL AROUND
0.05 MIN
SOLDER MASK
OPENING
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
PADS 4-7 & 8-11
PADS 1-3
SOLDER MASK DETAILS
4221908/A 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
RGX0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (0.5)
8X (0.25)
11
8
8X (0.6)
6X
EXPOSED METAL
9X (0.66)
9X (0.25)
1
SYMM
(2.8)
(0.5) TYP
3
SOLDER MASK
EDGE, TYP
METAL UNDER
SOLDER MASK
TYP
(0.86) TYP
4
7
(R0.05) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PADS 1-3
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221908/A 10/2015
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
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相关型号：
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3-17V 1A 3MHz Step-Down Converter with DCS-Control in 3x3 QFN Package 16-VQFN -40 to 125
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