TPS62152A-Q1 [TI]
具有 DCS-Control™ 的 3V 到 17V 1A 降压转换器;
| 型号： | TPS62152A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 DCS-Control™ 的 3V 到 17V 1A 降压转换器 DCS 分布式控制系统 转换器 |
| 文件： | 总40页 (文件大小：1864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
采用 DCS-ControlTM 技术的 TPS6215xA-Q1 3V 至 17V 1A 降压转换器
1 特性
3 说明
1
•
DCS-Control™拓扑
TPS62150A-Q1 器件是一款易于使用的同步降压直流/
直流转换器，针对 应用 进行了优化。通常为 2.5MHz
的高开关频率允许使用小型电感器，并且通过使用
DCS-Control™ 拓扑技术提供快速瞬态响应以及高输出
电压精度。
•
•
符合汽车类 应用要求
具有符合 AEC-Q100 标准的下列特性：
–
器件温度等级：-40°C 至 125°C 的工作结温范
围
–
–
器件 HBM ESD 分类等级 2
借助 3 至 17V 的宽运行输入电压范围，此器件非常适
合于由中间总线电源轨供电的系统。其输出电压为
0.9V 至 6V，支持高达 1A 的持续输出电流（使用
100% 占空比模式）。
器件 CDM ESD 分类等级 C4B
•
•
•
•
•
•
•
•
•
•
•
•
•
•
输入电压范围：3V 至 17V
可调节输出电压范围为 0.9V 至 6V
引脚可选输出电压（标称值，+5%）
可编程软启动和跟踪
输出电压启动斜率由软启动引脚控制，从而实现作为独
立电源或者在跟踪配置下的运行。通过配置使能和开漏
电源正常引脚也有可能实现电源排序。
节能模式无缝转换
17µA 的静态电流（典型值）
可选工作频率
在省电模式下，此器件显示来自 VIN 的静态电流大约为
17μA。如果负载较小，则自动且无缝进入省电模式，
并在整个负载范围内保持高效率。在关断模式下，此器
件被关闭且关断流耗少于 2μA。该器件采用 3mm ×
3mm (RGT) 16 引脚超薄型四方扁平无引线 (VQFN)
封装。。
电源正常状态输出
100% 占空比模式
短路保护
过热保护
与 TPS62130A-Q1 引脚对引脚兼容
采用 3mm × 3mm VQFN-16 封装
借助 WEBENCH® 电源设计器并使用 TPS62150A-
Q1 创建定制设计方案
器件信息(1)
器件型号
TPS62150A-Q1
TPS62152A-Q1
TPS62153A-Q1
封装
封装尺寸（标称值）
VQFN (16)
3.00 x 3.00mm
2 应用
•
•
•
•
汽车负载点 (POL) 电源
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
信息娱乐系统、CAN、USB 电源
嵌入式系统
space
space
LDO 替代产品
典型应用电路原理图
效率与输出电流
空白
空白
空白
空白
100
90
12V
2.2µH
3.3V / 1A
PVIN
AVIN
EN
SW
VOS
PG
80
VIN=5V
VIN=12V
VIN=17V
100k
10uF
1.21M
383k
22uF
70
60
50
40
TPS62150A-Q1
SS/TR
FSW
DEF
FB
3.3nF
VOUT
AGND
PGND
VOUT=3.3V
fsw=1.25MHz
Copyright © 2017, Texas Instruments Incorporated
0.0
0.2
0.4
0.6
0.8
1.0
Output Current (A)
G001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCC3
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
www.ti.com.cn
目录
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 29
13 器件和文档支持 ..................................................... 30
13.1 器件支持 ............................................................... 30
13.2 相关链接................................................................ 30
13.3 接收文档更新通知 ................................................. 30
13.4 社区资源................................................................ 30
13.5 商标....................................................................... 30
13.6 静电放电警告......................................................... 30
13.7 Glossary................................................................ 30
14 机械、封装和可订购信息....................................... 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings ...................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (July 2017) to Revision C
Page
•
已添加 添加了 TPS62152A-Q1 的初始发行版........................................................................................................................ 1
Changes from Revision A (November 201 6) to Revision B
Page
•
•
已添加 通篇添加了 WEBENCH® 链接.................................................................................................................................... 1
Changed "LOG" pin to "FSW" pin on the Pin Configuration and Functions and added FSW description throughout
the document.......................................................................................................................................................................... 3
•
•
Added SW (AC) spec to the Absolute Maximum Ratings table ............................................................................................ 4
Added Power Good Pin Logic Table and Frequency Selection (FSW) section regarding pin control. ................................ 12
Changes from Original (May 2014) to Revision A
Page
•
•
•
•
•
•
•
•
•
已添加 引脚对引脚兼容与特性列表 ........................................................................................................................................ 1
Moved Tstg spec from Handling Ratings table to Absolute Maximum Ratings table .............................................................. 4
Changed Thermal Information ............................................................................................................................................... 4
Added body diodes to Functional Block Diagrams ................................................................................................................ 8
Changed text in Input Capacitor section for clarity .............................................................................................................. 16
Added more Switching Frequency graphs to Application Curves section ........................................................................... 21
Changed resistor value at the LED from 0.1 Ω to 0.3 Ω in Figure 40 ................................................................................. 25
Deleted decoupling capacitor from figures in the Various Output Voltages section ........................................................... 26
已添加 接收文档更新通知 和 社区资源 部分......................................................................................................................... 30
2
Copyright © 2014–2019, Texas Instruments Incorporated
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
www.ti.com.cn
ZHCSCG9C –MAY 2014–REVISED JULY 2019
5 Device Comparison Table
PART NUMBER
TPS62150A-Q1
TPS62152A-Q1
TPS62153A-Q1
OUTPUT VOLTAGE
PACKAGE MARKING
PA8IQ
adjustable
3.3V
152Q1
5V
PA8JQ
6 Pin Configuration and Functions
RGT Package
16-Pin VQFN
Top View
16
15
14
13
1
2
3
4
12
11
10
9
SW
SW
SW
PG
PVIN
PVIN
AVIN
SS/TR
Exposed
Thermal Pad
5
6
7
8
Pin Functions
PIN(1)
NAME
I/O
DESCRIPTION
NO.
SW
PG
FB
1,2,3
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
4
5
O
I
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor)
Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
AGND
FSW
DEF
6
7
8
Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Switching Frequency Select (Low=2.5MHz, High=1.25MHz for typical operation)(2)
Output Voltage Scaling (Low = nominal, High = nominal + 5%)(2)
I
I
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
time. It can be used for tracking and sequencing.
SS/TR
9
I
AVIN
PVIN
EN
10
11,12
13
I
I
I
I
Supply voltage for control circuitry. Connect to same source as PVIN.
Supply voltage for power stage. Connect to same source as AVIN.
Enable input (High = enabled, Low = disabled)(2)
VOS
14
Output voltage sense pin and connection for the control loop circuitry.
Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane(3). Must be soldered to
achieve appropriate power dissipation and mechanical reliability.
PGND
Exposed
Thermal Pad
15,16
(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
(2) An internal pull-down resistor keeps logic level low, if pin is floating.
(3) See Figure 50.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
–0.3
–0.3
–2
MAX
20
UNIT
AVIN, PVIN
EN, SS/TR, SW (DC)
Pin voltage(2)
VIN+0.3
24.5
7
V
SW (AC), less than 10ns(3)
DEF, FSW, FB, PG, VOS
–0.3
V
Power Good sink current PG
10
mA
°C
°C
Temperature
Tstg
Operating junction temperature range, TJ
Storage temperature range
–40
–65
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) While switching.
7.2 Handling Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(2)
Charged device model (CDM), per AEC Q100-011
Electrostatic
discharge
(1)
V(ESD)
V
(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN TYP
MAX
17
UNIT
V
Supply Voltage, VIN (at AVIN and PVIN)
Output Voltage Range, VOUT (TPS62150A-Q1)
Operating junction temperature, TJ
3
0.9
6
V
–40
125
°C
7.4 Thermal Information
TPS6215xA-Q1
THERMAL METRIC(1)
RGT
16 PINS
45
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.6
17.4
1.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
17.4
4.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014–2019, Texas Instruments Incorporated
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
www.ti.com.cn
ZHCSCG9C –MAY 2014–REVISED JULY 2019
7.5 Electrical Characteristics
over junction temperature range (TJ=-40°C to +125°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY
VIN
Input voltage range
3
17
V
µA
µA
V
IQ
Operating quiescent current
Shutdown current(1)
EN=High, IOUT=0mA, device not switching
EN=Low
17
1.5
2.7
200
160
20
30
25
ISD
VUVLO
Falling Input Voltage (PWM mode operation)
Hysteresis
2.6
0.9
2.8
Undervoltage lockout threshold
mV
TSD
Thermal shutdown temperature
Thermal shutdown hysteresis
°C
CONTROL (EN, DEF, FSW, SS/TR, PG)
High level input threshold voltage (EN,
DEF, FSW)
VH
VL
V
V
Low level input threshold voltage (EN,
DEF, FSW)
0.3
1
EN=VIN or GND; DEF=VOUT or GND;
FSW=GND
ILKG
Input leakage current (EN, DEF, FSW)
Power good threshold voltage
0.01
µA
Rising (%VOUT
)
92%
87%
95% 98%
90% 94%
VTH_PG
Falling (%VOUT
)
VOL_PG
ILKG_PG
ISS/TR
Power good output low
Input leakage current (PG)
SS/TR pin source current
IPG=–2mA
0.07
1
0.3
400
2.7
V
VPG=1.8V
nA
µA
2.3
2.5
POWER SWITCH
V
IN≥6V
VIN=3V
IN≥6V
VIN=3V
90 170
120
40
High-side MOSFET ON-resistance
mΩ
RDS(ON)
V
70
Low-side MOSFET ON-resistance
mΩ
50
ILIMF
High-side MOSFET forward current limit
VIN =12V, TA= 25°C
1.4
0.9
1.7
2.2
A
OUTPUT
VREF
Internal reference voltage
0.8
1
V
nA
V
ILKG_FB
Input leakage current (FB)
VFB=0.8V
100
6.0
Output voltage range (TPS62150A-Q1)
DEF (Output voltage programming)
VIN ≥ VOUT
DEF=0 (GND)
VOUT
DEF=1 (VOUT
)
VOUT+5%
–1.8%
–2.3%
PWM mode operation, VIN ≥ VOUT +1V
Power Save Mode operation, COUT=22µF
VIN=12V, VOUT=3.3V, PWM mode operation
1.8%
2.8%
Output voltage accuracy(2)
VOUT
Load regulation
Line regulation
0.05
0.02
%/A
%/V
3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM
mode operation
(1) Current into AVIN+PVIN pin.
(2) This is the regulation accuracy of the voltage at the FB pin (adjustable version) and of the output voltage (fixed version).
Copyright © 2014–2019, Texas Instruments Incorporated
5
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
www.ti.com.cn
7.6 Typical Characteristics
Figure 1. Quiescent Current
Figure 2. Shutdown Current
Figure 3. High-side Switch Resistance
Figure 4. Low-Side Switch Resistance
6
Copyright © 2014–2019, Texas Instruments Incorporated
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
www.ti.com.cn
ZHCSCG9C –MAY 2014–REVISED JULY 2019
8 Parameter Measurement Information
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
TPS62150AQRGT, Texas Instruments
XFL4020-222MEB, Coilcraft
Standard
IC
17V, 1A Step-Down Converter, VQFN
2.2µH, 0.165 x 0.165 in
10µF, 25V, Ceramic, 1210
22µF, 6.3V, Ceramic, 0805
3300pF, 25V, Ceramic, 0603
depending on Vout
L1
C1
C3
C5
R1
R2
R3
Standard
depending on Vout
100kΩ, Chip, 0603, 1/16W, 1%
Standard
spacing
spacing
VIN
L1
VOUT
PVIN
AVIN
EN
SW
VOS
R3
C1
PG
R1
C3
TPS62150A-Q1
SS/TR
FB
C5
R2
DEF
AGND
PGND
FSW
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Measurement Setup (High Switching Frequency)
spacing
VIN
L1
VOUT
PVIN
AVIN
EN
SW
VOS
R3
C1
PG
R1
R2
C3
TPS62150A-Q1
SS/TR
FB
C5
DEF
AGND
PGND
VOUT
FSW
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Measurement Setup (Low Switching Frequency)
Copyright © 2014–2019, Texas Instruments Incorporated
7
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
www.ti.com.cn
9 Detailed Description
9.1 Overview
The TPS6215xA-Q1 synchronous switched mode power converters are based on DCS-Control™ (Direct Control
with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the
advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the
output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and
provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz or 1.25MHz with a controlled frequency
variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to
sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly
with the load current. Since DCS-Control™ supports both operation modes within one single building block, the
transition from PWM to Power Save Mode is seamless without effects on the output voltage.
9.2 Functional Block Diagram
PG
AVIN
PVIN PVIN
Soft
start
Thermal
Shtdwn
UVLO
PG control
HS lim
comp
EN*
SW
SW
SW
SS/TR
power
control
gate
drive
control logic
DEF*
FSW
comp
LS lim
direct control
&
compensation
VOS
FB
ramp
_
comparator
timer tON
error
amplifier
+
DCS - ControlTM
* This pin is connected to a pull down resistor internally
(see Feature Description section).
AGND
PGNDPGND
Copyright © 2017, Texas Instruments Incorporated
Figure 7. TPS62150A-Q1 (Adjustable Output Voltage)
8
Copyright © 2014–2019, Texas Instruments Incorporated
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
www.ti.com.cn
ZHCSCG9C –MAY 2014–REVISED JULY 2019
Functional Block Diagram (continued)
PG
AVIN
PVIN PVIN
Soft
start
Thermal
Shtdwn
UVLO
PG control
HS lim
comp
EN*
SW
SW
SW
SS/TR
power
control
gate
drive
control logic
DEF*
FSW
comp
LS lim
direct control
&
compensation
VOS
FB*
ramp
_
comparator
timer tON
error
amplifier
+
DCS - ControlTM
* This pin is connected to a pull down resistor internally
(see Feature Description section).
AGND
PGNDPGND
Copyright © 2017, Texas Instruments Incorporated
Figure 8. TPS62153A-Q1 (5V Fixed Output Voltage)
9.3 Feature Description
9.3.1 Pulse Width Modulation (PWM) Operation
The TPS6215xA-Q1 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). PSM operation occurs if the
output current becomes smaller than half the inductor's ripple current.
9.3.2 Power Save Mode Operation
The built-in Power Save Mode of the TPS6215xA-Q1 is entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode, the switching frequency decreases linearly with the load current maintaining high
efficiency. The transition into and out of Power Save Mode happens within the entire regulation scheme and is
seamless in both directions.
Copyright © 2014–2019, Texas Instruments Incorporated
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TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
ZHCSCG9C –MAY 2014–REVISED JULY 2019
www.ti.com.cn
Feature Description (continued)
TPS6215xA-Q1 includes a fixed on-time circuitry. This on-time, in steady-state operation with FSW=Low, can be
estimated as:
spacing
VOUT
tON
=
× 400ns
VIN
(1)
spacing
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such case. Using tON, the
typical peak inductor current in Power Save Mode can be approximated by:
spacing
(VIN -VOUT
)
ILPSM ( peak )
=
×tON
(2)
spacing
When VIN decreases to typically 15% above VOUT, the TPS6215xA-Q1 won't enter Power Save Mode,
regardless of the load current. The device maintains output regulation in PWM mode.
9.3.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set
point. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
(
VIN(min) =VOUT(min) + IOUT RDS( on ) + RL
)
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.
spacing
9.3.4 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must
be set externally to High or Low. The typical threshold values are 0.65V (rising) and 0.45V (falling). An internal
pull-down resistor of about 400kΩ is connected and keeps EN logic low, if Low is set initially and then the pin
gets floating. It is disconnected if the pin is set High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
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Feature Description (continued)
9.3.5 Soft Start / Tracking (SS/TR)
The internal soft start circuitry controls the output voltage slope during startup, avoiding excessive inrush current
and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-impedance
power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of
about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See
Figure 38 and Figure 39 for typical startup operation.
Using very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. The
TPS6215xA-Q1 can start into a pre-biased output. During monotonic pre-biased startup, both of the power
MOSFETs are not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias
voltage. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal shutdown, an internal
resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup
sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see Application and Implementation section).
9.3.6 Current Limit And Short Circuit Protection
The TPS6215xA-Q1 is protected against heavy load and short circuit events. At heavy loads, the current limit
determines the maximum output current. If the current limit is reached, the high-side FET turns off. Avoiding
shoot through current, the low-side FET switches on to allow the inductor current to decrease. The high-side FET
turns on again, only if the current in the low-side FET has decreased below the low-side current limit threshold.
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
spacing
VL
I peak(typ) = ILIMF
+
× tPD
L
(4)
where
ILIMF is the static current limit, specified in the ,
L is the inductor value,
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
spacing
+ (VIN -VOUT )×30ns
I peak(typ) = ILIMF
(5)
9.3.7 Power Good (PG)
The TPS6215xA-Q1 has a built in power good (PG) function to indicate whether the output voltage has reached
its appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain its specified logic low level. TPS6215xA-Q1 features PG=Low when the device is turned off due to EN,
UVLO or thermal shutdown and can be used to actively discharge Vout (see Figure 42). VIN must remain
present for the PG pin to stay Low. If unused, the PG pin may be left floating.
space
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Feature Description (continued)
Table 2. Power Good Pin Logic Table
PG Logic Status
Device State
High Impedance
Low
V
FB ≥ VTH_PG
FB ≤ VTH_PG
√
Enable (EN=High)
V
√
√
√
√
Shutdown (EN=Low)
UVLO
0.7 V < VIN < VUVLO
TJ > TSD
Thermal Shutdown
Power Supply Removal
VIN < 0.7 V
√
space
9.3.8 Pin-Selectable Output Voltage (DEF)
The output voltage of the TPS6215xA-Q1 can be increased by 5% above the nominal voltage by setting the DEF
pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6215xA-Q1 can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.
9.3.9 Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kΩ is internally
connected to the pin, acting the same way as at the DEF Pin (see Pin-Selectable Output Voltage (DEF) above).
9.3.10 Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.
9.3.11 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes Low. When TJ decreases below the hysteresis amount, the converter resumes normal operation, beginning
with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal
shutdown temperature.
9.4 Device Functional Modes
9.4.1 Operation above TJ=125°C
The operating junction temperature of the device is specified up to 125°C. In power supply circuits, the self
heating effect causes that the junction temperature, TJ, is even higher than the ambient temperature TA.
Depending on TA and the load current, the maximum operating TJ can be exceeded. However, the electrical
characteristics are specified up to a TJ of 125°C only. The device operates as long as thermal shutdown
threshold is not triggered.
(1) Maximum allowed voltage is 7V. Therefore it's recommended to connect it to VOUT, not VIN.
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Device Functional Modes (continued)
9.4.2 Operation with VIN < 3V
The device is functional for supply voltages below 3V and above the UVLO threshold. Parameters may differ
from specified values. The minimum VIN value of 3V is not violated by UVLO threshold and hysteresis variations.
9.4.3 Operation with separate EN Control
The EN pin can be connected to VIN or be controlled separately. While the EN control voltage level can be lower
than the actual VIN value, it must not exceed VIN, to avoid damage of the device. This might happen at low VIN,
during startup or power sequencing.
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10 Application and Implementation
10.1 Application Information
TPS62150xA-Q1 are synchronous switch mode step-down converters, able to convert a 3V to 17V input voltage
into a lower, 0.9V to 6V, output voltage, providing up to 1A load current. The following section gives guidance on
choosing external components to complete the power supply design. Application Curves are included for the
typical application shown below.
10.2 Typical Application
space
10.2.1 TPS62150A-Q1 Point-Of-Load Step Down Converter
spacing
2.2 µH
12 V
3.3V / 1A
PVIN
AVIN
EN
SW
VOS
PG
R3
100k
C1
10uF
R1
1.21M
C3
22uF
TPS62150A-Q1
SS/TR
FB
C5
3.3nF
R2
383k
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 9. Typical Schematic for 3.3V Step-Down Converter
spacing
10.2.1.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
external components appropriate. The following design procedure is adequate for whole VIN, VOUT and load
current range of TPS62150A-Q1. Using Table 3, the design procedure needs minimum effort.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62150A-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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Typical Application (continued)
10.2.1.2.2 Programming The Output Voltage
The TPS6215xA-Q1 can be programmed for output voltages from 0.9V to 6V by using a resistive divider from
VOUT to AGND. The voltage at the FB pin is regulated to 800mV. The value of the output voltage is set by the
selection of the resistive divider from Equation 6 (see Figure 5). It is recommended to choose resistor values
which allow a current of at least 2uA, meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values
are recommended for highest accuracy and most robust design. For applications requiring lowest current
consumption, the use of fixed output voltage versions is recommended.
spacing
V
æ
ç
è
ö
OUT
R1 = R2
-1
÷
0.8V
ø
(6)
spacing
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.
10.2.1.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the device's
control loop. The TPS6215xA-Q1 is optimized to work within a range of external components. The LC output
filter's inductance and capacitance must be considered together, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter And Loop Stability). Table 3 can be used to simplify the
output filter component selection.
Table 3. Recommended LC Output Filter Combinations(1)
4.7µF
10µF
22µF
47µF
100µF
200µF
400µF
0.47µH
1µH
√
√
√
√
√
√
√
√
√
(2)
2.2µH
3.3µH
4.7µH
√
√
√
√
(1) The values in the table are nominal values.
(2) This LC combination is the standard value and recommended for most applications.
space
The TPS6215xA-Q1 can be run with an inductor as low as 1µH. FSW should be set Low in this case. However,
for applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is
recommended.
More detailed information on further LC combinations can be found in SLVA463.
10.2.1.2.4 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
spacing
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VOUT
æ
ç
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
÷
ø
1-
VIN(max)
DIL(max) = VOUT
×
L(min) × fSW
(8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and solution size as well. The
following inductors have been used with the TPS6215xA-Q1 and are recommended for use:
Table 4. List of Inductors(1)
Type
Inductance [µH]
Current [A](2)
Dimensions [LxBxH]
mm
MANUFACTURER
XFL4020-102ME_
XFL4020-152ME_
XFL4020-222ME_
IHLP1212BZ-11
IHLP1212BZ-11
SRP4020-3R3M
VLC5045T-3R3N
1.0 µH, ±20%
1.5 µH, ±20%
2.2 µH, ±20%
1.0 µH, ±20%
2.2 µH, ±20%
3.3µH, ±20%
3.3µH, ±30%
4.7
4.2
3.8
4.5
3.0
3.3
4.0
4 x 4 x 2.1
4 x 4 x 2.1
4 x 4 x 2.1
3 x 3.6 x 2
3 x 3.6 x 2
4.8 x 4 x 2
5 x 5 x 4.5
Coilcraft
Coilcraft
Coilcraft
Vishay
Vishay
Bourns
TDK
(1) See Third-Party Products Disclaimer.
(2) Lower of IRMS at 40°C rise or ISAT at 30% drop.
spacing
The inductor value also determines the load current at which Power Save Mode is entered:
1
Iload(PSM )
=
DIL
2
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
10.2.1.2.5 Output Capacitor
The recommended value for the output capacitor is 22uF. The architecture of the TPS6215xA-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use an X7R or X5R dielectric. Using a higher value
can have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode
(see SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
10.2.1.2.6 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input current ripple
further. The input capacitor buffers the input voltage during transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. An RC, low-pass filter from PVIN to AVIN may be
used but is not required.
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10.2.1.2.7 Soft Start Capacitor
A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
spacing
2.5mA
CSS = tSS ×
[F]
1.25V
(10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).
spacing
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
10.2.1.2.8 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the
FB pin tracks the SS/TR pin voltage as described in Equation 11 and shown in Figure 10.
spacing
VFB » 0.64×VSS /TR
(11)
VSS/
TR [V]
1.2
0.8
0.4
VFB [V]
0.2
0.4
0.6
0.8
Figure 10. Voltage Tracking Relationship
Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. Figure 11 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
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VOUT1
PVIN
AVIN
EN
SW
VOS
PG
TPS62150A-Q1
SS/TR
DEF
FB
AGND
PGND
FSW
VOUT2
PVIN
AVIN
EN
SW
VOS
PG
R1
R2
TPS62150A-Q1
SS/TR
DEF
FB
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Sequence for Ratiometric and Simultaneous Startup
spacing
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.
10.2.1.2.9 Output Filter And Loop Stability
The devices of the TPS6215xA-Q1 family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
spacing
1
fLC
=
2p L × C
(12)
spacing
Proven nominal values for inductance and ceramic capacitance are given in Table 3 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which is affected. More information
including a detailed LC stability matrix can be found in SLVA463.
The TPS6215xA-Q1 includes an internal 25pF feedforward capacitor, connected between the VOS and FB pins.
This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of
the feedback divider, per equation Equation 13 and Equation 14:
spacing
1
fzero
=
2p × R × 25pF
1
(13)
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spacing
æ
ö
1
1
1
ç
ç
÷
÷
f pole
=
×
+
2p × 25pF
R
R
è
1
2
ø
(14)
spacing
Though the TPS6215xA-Q1 is stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability versus transient response can be found in SLVA289 and SLVA466.
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10.2.1.3 Application Curves
At VIN=12V, VOUT=3.3V and TA=25°C, FSW=Low, (unless otherwise noted)
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=17V
IOUT=10mA
IOUT=1A
VIN=12V
IOUT=1mA
IOUT=100mA
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
7
8
9
10
11
12
13
14
15
16
17
Input Voltage (V)
G001
G001
FSW = Low
FSW = Low
Figure 12. Efficiency vs. Output Current
Figure 13. Efficiency vs. Input Voltage
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=17V
VIN=12V
IOUT=10mA
IOUT=1A
IOUT=1mA
IOUT=100mA
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
0.1
1
7
8
9
10
11
12
13
14
15
16
17
Output Current (A)
Input Voltage (V)
G001
G001
FSW = High
FSW = High
Figure 14. Efficiency vs. Output Current
Figure 15. Efficiency vs. Input Voltage
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=12V
VIN=17V
IOUT=100mA
IOUT=1mA
VIN=5V
IOUT=10mA
IOUT=1A
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
FSW = Low
FSW = Low
Figure 16. Efficiency vs. Output Current
Figure 17. Efficiency vs. Input Voltage
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100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
VIN=12V
VIN=17V
VIN=5V
IOUT=1A IOUT=100mA IOUT=10mA
IOUT=1mA
50.0
40.0
30.0
20.0
10.0
0.0
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
FSW = High
FSW = High
Figure 18. Efficiency vs. Output Current
Figure 19. Efficiency vs. Input Voltage
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=12V
VIN=17V
IOUT=1A
IOUT=100mA
IOUT=10mA
VIN=5V
IOUT=1mA
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
FSW = High
FSW = High
Figure 20. Efficiency vs. Output Current
Figure 21. Efficiency vs. Input Voltage
3.40
3.35
3.30
3.25
3.20
3.40
3.35
3.30
3.25
3.20
VIN=17V
IOUT=10mA
IOUT=1mA
VIN=12V
VIN=5V
IOUT=1A
IOUT=100mA
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
0.1
1
4
7
10
13
16
Output Current (A)
Input Voltage (V)
G001
G001
VOUT = 3.3 V
L = 2.2 µH
(XFL4020)
COUT = 22 µF
VOUT = 3.3 V
L = 2.2 µH
(XFL4020)
COUT = 22 µF
Figure 22. Output Voltage Accuracy (Load Regulation)
Figure 23. Output Voltage Accuracy (Line Regulation)
Copyright © 2014–2019, Texas Instruments Incorporated
21
TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
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4
3.5
3
4
3.5
3
2.5
2
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
1.5
1
0.5
0
0.5
0
6
8
10
12
Input Voltage (V)
14
16
18
0
0.2
0.4
0.6
0.8
1
Output Current (A)
G000
G000
FSW = Low
VOUT = 5 V
FSW = Low
VOUT = 5 V
Figure 24. Switching Frequency vs Input Voltage
Figure 25. Switching Frequency vs Output Current
4
4
3.5
3
3.5
3
2.5
2
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
1.5
1
0.5
0
0.5
0
4
6
8
10
12
14
16
18
0
0.2
0.4
0.6
0.8
1
Input Voltage (V)
Output Current (A)
G000
G000
FSW = Low
VOUT = 3.3 V
FSW = Low
VOUT = 3.3 V
Figure 26. Switching Frequency vs Input Voltage
Figure 27. Switching Frequency vs Output Current
4
4
3.5
3
3.5
3
2.5
2
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
1.5
1
0.5
0
0.5
0
3
5
7
9
11
13
15
17
0
0.2
0.4
0.6
0.8
1
Input Voltage (V)
Output Current (A)
G000
G000
FSW = Low
VOUT = 1.8 V
FSW = Low
VOUT = 1.8 V
Figure 28. Switching Frequency vs Input Voltage
Figure 29. Switching Frequency vs Output Current
22
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ZHCSCG9C –MAY 2014–REVISED JULY 2019
3
3
2.5
2
2.5
2
1.5
1
1.5
1
IOUT=1A
IOUT=0.5A
0.5
0.5
0
0
3
5
7
9
11
13
15
17
0
0.2
0.4
0.6
0.8
1
Input Voltage (V)
Output Current (A)
G000
G000
FSW = Low
VOUT = 1 V
FSW = Low
VOUT = 1 V
Figure 30. Switching Frequency vs Input Voltage
Figure 31. Switching Frequency vs Output Current
Figure 32. Typical Operation in PWM Mode (IOUT = 1A)
Figure 33. Typical Operation in Power Save Mode (IOUT
10mA)
=
Figure 34. PWM-PSM-Transition
Figure 35. Load Transient Response (0.5 to 1 to 0.5 A)
Copyright © 2014–2019, Texas Instruments Incorporated
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TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
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Figure 36. Load Transient Response of Figure 35,
Rising Edge
Figure 37. Load Transient Response of Figure 35,
Falling Edge
Figure 38. Start Up Into 100mA
Figure 39. Start Up Into 1A
24
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ZHCSCG9C –MAY 2014–REVISED JULY 2019
10.2.2 System Examples
10.2.2.1 Regulated Power LED Supply
The TPS62150A-Q1 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low, avoiding
excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62150A-
Q1. Figure 40 shows an application circuit, tested with analog dimming:
spacing
2.2µH
(4 .. 17) V
PVIN
AVIN
EN
SW
VOS
PG
10uF
22uF
ADIM
TPS62150A-Q1
SS/TR
FB
187k
0.3R
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Single Power LED Supply
spacing
The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.
spacing
VFB = 0.64 × 2.5mA × RSS / TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
10.2.2.2 Inverting Power Supply
The TPS62150A-Q1 can be used as inverting power supply by rearranging external circuitry as shown in
Figure 41.
spacing
10uF
2.2µH
(3 .. 13.7)V
PVIN
AVIN
EN
SW
VOS
PG
10uF
1.21M
383k
TPS62150A-Q1
22uF
SS/TR
FB
3.3nF
DEF
AGND
PGND
-3.3V
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 41. –3.3 V Inverting Power Supply
Copyright © 2014–2019, Texas Instruments Incorporated
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TPS62150A-Q1, TPS62152A-Q1, TPS62153A-Q1
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spacing
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing
VIN + VOUT £VIN max
(16)
spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
10.2.2.3 Active Output Discharge
The TPS6215xA-Q1 pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 42).
spacing
(3 .. 17)V
2.2 µH
Vout / 1A
PVIN
AVIN
EN
SW
TPS62150A-Q1
VOS
PG
R3
10uF
R1
R2
22uF
SS/TR
DEF
FB
3.3nF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Output Discharge Using PG Pin
spacing
The discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For
reliability, keep the maximum current into the PG pin less than 10mA.
10.2.2.4 Various Output Voltages
The TPS62150A-Q1 can be set for different output voltages between 0.9V and 6V. Some examples are shown
below.
spacing
(5 .. 17)V
2.2µH
5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
22uF
TPS62153A-Q1
SS/TR
FB
3.3nF
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 43. 5-V Power Supply Using TPS62153A-Q1 Fixed VOUT Version
spacing
26
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(3.3 .. 17)V
2.2µH
3.3V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
470k
150k
22uF
TPS62150A-Q1
SS/TR
FB
3.3nF
3.3nF
3.3nF
3.3nF
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 44. 3.3V/1A Power Supply
spacing
spacing
spacing
spacing
(3 .. 17)V
2.2 µH
2.5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
390k
180k
22uF
TPS62150A-Q1
SS/TR
FB
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 45. 2.5V/1A Power Supply
(3 .. 17)V
2.2µH
1.8V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
510k
402k
22uF
TPS62150A-Q1
SS/TR
FB
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 46. 1.8V/1A Power Supply
(3 .. 17)V
2.2 µH
1.5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
130k
150k
22uF
TPS62150A-Q1
SS/TR
FB
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 47. 1.5V/1A Power Supply
Copyright © 2014–2019, Texas Instruments Incorporated
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(3 .. 17)V
2.2 µH
1.2V / 1A
PVIN
SW
VOS
PG
AVIN
100k
10uF
EN
75k
22uF
TPS62150A-Q1
SS/TR
FB
3.3nF
150k
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 48. 1.2V/1A Power Supply
spacing
(3 .. 17)V
2.2 µH
1V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
51k
22uF
TPS62150A-Q1
SS/TR
FB
3.3nF
200k
DEF
AGND
PGND
FSW
Copyright © 2016, Texas Instruments Incorporated
Figure 49. 1V/1A Power Supply
spacing
11 Power Supply Recommendations
The TPS6215xA-Q1 devices are designed to operate from a 3 to 17V input voltage supply. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal or supply peak current
limitations, additional bulk capacitance may be required. In the case ringing that is caused by the interaction with
the ceramic input capacitors, an electrolytic or tantalum type capacitor may be needed for damping.
28
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ZHCSCG9C –MAY 2014–REVISED JULY 2019
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6215xA-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. The layout also influences the
thermal performance of the solution by its power dissipation capabilities.
See Figure 50 for the recommended layout of the TPS62150A-Q1, which is designed for common external
ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad.
On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the
system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to the VOUT potential
at the output capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the AGND pin.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.
12.2 Layout Example
space
AGND
C5
R1
R2
SS/TR
AVIN
PVIN
PVIN
PG
SW
SW
SW
VIN
C3
L1
C1
VOUT
GND
Figure 50. Layout Example with TPS62150A-Q1
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13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 5. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
TPS62150A-Q1
TPS62152A-Q1
TPS62153A-Q1
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
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ZHCSCG9C –MAY 2014–REVISED JULY 2019
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
16
13
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
16X
0.05
0.5
0.3
4222419/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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ZHCSCG9C –MAY 2014–REVISED JULY 2019
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222419/B 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Copyright © 2014–2019, Texas Instruments Incorporated
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
34
版权 © 2014–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62150AQRGTRQ1
TPS62150AQRGTTQ1
TPS62152AQRGTRQ1
TPS62153AQRGTRQ1
TPS62153AQRGTTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
PA8IQ
NIPDAU
NIPDAU
NIPDAU
NIPDAU
PA8IQ
152Q1
PA8JQ
PA8JQ
3000 RoHS & Green
3000 RoHS & Green
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62150AQRGTRQ1
TPS62150AQRGTTQ1
TPS62152AQRGTRQ1
TPS62153AQRGTRQ1
TPS62153AQRGTTQ1
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
3000
250
330.0
180.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
3000
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62150AQRGTRQ1
TPS62150AQRGTTQ1
TPS62152AQRGTRQ1
TPS62153AQRGTRQ1
TPS62153AQRGTTQ1
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
3000
250
552.0
552.0
346.0
552.0
552.0
346.0
185.0
346.0
346.0
185.0
36.0
36.0
33.0
36.0
36.0
3000
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS62150AQRGTRQ1
TPS62150AQRGTTQ1
TPS62153AQRGTRQ1
TPS62153AQRGTTQ1
RGT
RGT
RGT
RGT
VQFN
VQFN
VQFN
VQFN
16
16
16
16
3000
250
381
381
381
381
4.83
4.83
4.83
4.83
2286
2286
2286
2286
0
0
0
0
3000
250
Pack Materials-Page 3
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