TPS62184YZFR [TI]

具有电源正常指示功能、1% 精度和可调节软启动功能的 4V 至 17V、6A 同步降压转换器 | YZF | 24 | -40 to 125;


型号：	TPS62184YZFR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示功能、1% 精度和可调节软启动功能的 4V 至 17V、6A 同步降压转换器 \| YZF \| 24 \| -40 to 125 开关软启动输出元件转换器
文件：	总34页 (文件大小：2104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

TPS62184 4V 至 17V、6A、双相降压转换器，具有 AEE™

1 特性

3 说明

•

双相平衡峰值电流模式

输入电压范围：4V 至 17V

输出电压:

TPS62184 是一款适用于薄型电源轨的双相降压 DC-

DC 转换器。它通过使用两个由峰值电流控制的相同

电流平衡相位来进行工作，适合在高度受限的应用中使

用。

•

–

0.9V ≤ VOUT ≤ 1.8 V(6A)，

1.8V ≤ VOUT ≤ 2.5V (5.5A)

2.5V ≤ VOUT ≤ 3.5V (5A)

该器件具有 4V 到 17V 的宽工作输入电压范围，非常

适合通过多节锂离子电池或 12V 电源轨供电运行的系

统。两相可持续提供 6A 输出电流（每相 3A），从而

允许使用薄型外部元件。两相异相运行，这样可显著

减小开关噪声。

•

典型静态电流为 28µA

输出电压精度达 ±1%（脉宽调制 (PWM) 模式）

自动效率提高 (AEE™)

相移操作

TPS62184 可在超轻负载时自动进入节能模式以保持

高效率。并且还集成有自动效率提高功能 (AEE^TM)，

适用于整个占空比范围。

自动节能模式

可调软启动

电源正常输出

欠压闭锁

该器件提供电源正常信号和可调节软启动。其静态电

流典型值为 28µA，并且能够在 100% 模式下运行，即

便在最低输出电压下也不存在占空比限制。

HICCUP 过流保护

过热保护

与 TPS62180/2 引脚到引脚兼容

TPS62184 采用小型 24 凸点、0.5mm 间距 DSBGA

封装。

NanoFree™ 2.10mm x 3.10mm 芯片尺寸球状引脚

栅格阵列 (DSBGA) 封装

器件信息⁽¹⁾

2 应用

器件型号

TPS62184

封装

封装尺寸（标称值）

•

薄型负载点 (POL) 电源

DSBGA (24)

2.10mm x 3.10mm

窄 VDC (NVDC) 供电系统

两/三节锂离子电池

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

间距

超便携式/嵌入式/平板电脑

计算网络解决方案

微型服务器和固态硬盘 (SSD)

4 简化电路原理图

SPACE

效率与输出电流间的关系

22µF

1µH

VIN1

SW1

SW2

3.3V/6A

4 to 17 V

VIN2

470k

22µF

TPS62184

47µF

470k

150k

SS/TR

GND

3.3nF

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCQ5

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

8.3 Feature Description................................................... 8

8.4 Device Functional Modes.......................................... 8

Application and Implementation ........................ 13

9.1 Application Information............................................ 13

9.2 Typical Applications ................................................ 13

9.3 System Examples ................................................... 22

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 7

8.1 Overview ................................................................... 7

8.2 Functional Block Diagram ......................................... 7

10 Power Supply Recommendations ..................... 24

11 Layout................................................................... 25

11.1 Layout Guidelines ................................................. 25

11.2 Layout Example .................................................... 25

12 器件和文档支持 ..................................................... 26

12.1 器件支持................................................................ 26

12.2 商标....................................................................... 26

12.3 静电放电警告......................................................... 26

12.4 术语表 ................................................................... 26

13 机械封装和可订购信息 .......................................... 26

5 修订历史记录

Changes from Original (December 2014) to Revision A

Page

•

Published full Production Data sheet to include Specification tables, Feature Description section, Device Functional

Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 4

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

spacing

6 Pin Configuration and Functions

spacing

24-Pin DSBGA

YZF Package

(Top View - Left, Bottom View - Right)

Pin Functions

PIN⁽¹⁾

DESCRIPTION

NAME

AGND

NUMBER

Analog Ground. Connect on PCB directly with PGND.

Enable input (High = enabled, Low = disabled)

Output voltage feedback. Connect resistive voltage divider to this pin and AGND. On TPS62182,

connect to AGND.

Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain

(requires pull-up resistor)

A3, B3, C3, D3,

E3, F3

PGND

SS/TR

SW1

SW2

Common power ground.

Soft-Start and Tracking Pin. An external capacitor connected to this pin sets the internal voltage

reference rise time.

Switch node for Phase 1 (master), connected to the internal MOSFET switches. Connect inductor 1

between SW1 and output capacitor.

A2, B2, C2

D2, E2, F2

Switch node for Phase 2 (follower), connected to the internal MOSFET switches. Connect inductor 2

between SW2 and output capacitor.

VIN1

VIN2

A1, B1, C1

D1, E1, F1

Supply voltage for Phase 1.

Supply voltage for Phase 2.

Output Voltage Connection

(1) For more information about connecting pins, see Detailed Description and Application Information sections.

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating junction temperature range (unless otherwise noted)

MIN

–0.3

MAX

UNIT

VIN1, VIN2

EN, PG, SW1, SW2

V_IN+ 0.3

Pin voltage range⁽²⁾

V_IN+ 0.3, but

SS/TR

–0.3

≤ 7

FB, VO

Power good sink

current

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground pin.

7.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human Body Model (HBM) ESD stress voltage⁽²⁾

Charge device model (CDM) ESD stress voltage

(1)

V_ESD

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

MIN

TYP

MAX UNIT

Supply voltage range, V_IN

Output voltage range, V_OUT

0.9

3.5

0.9V ≤ V_OUT≤ 1.8V

Maximum Output

current, I_OUT(max)

1.8V ≤ V_OUT≤ 2.5V

2.5V ≤ V_OUT≤ 3.5V

5.5

Operating junction temperature, T_J

–40

125

°C

7.4 Thermal Information

TPS62184

THERMAL METRIC⁽¹⁾

UNIT

YZF (24 PINS)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

61.5

0.3

R_θJCtop

Rθ_JB

ψ_JT

Junction-to-board thermal resistance

10.1

0.1

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

10.1

n/a

R_θJCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

7.5 Electrical Characteristics

Over operating junction temperature range (T_J= –40°C to +125°C) and V_IN= 4 V to 17 V.

Typical values at V_IN= 12 V and T_J= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY

V_IN

Input voltage range

EN = High, I_OUT= 0 mA, Device not switching,

(T_J= –40°C to +85°C)

I_Q

Operating quiescent current

Shutdown current

µA

I_SD

EN = Low (≤ 0.3 V), (T_J= –40°C to +85°C)

Falling input voltage

2.8

3.6

300

160

µA

V_UVLO

3.5

3.7

(1)

Undervoltage lockout threshold

Thermal shutdown

Hysteresis

T_SD

Rising junction temperature

Hysteresis

°C

CONTROL (EN, SS/TR, PG)

V_{H_EN}

V_{L_EN}

I_{LKG_EN}

I_SS/TR

High-level input threshold voltage (EN)

Low-level input threshold voltage (EN)

Input leakage current (EN)

0.97

0.87

0.9

0.01

1.03

0.93

1.2

EN = V_INor GND

µA

SS/TR pin source current

4.5

5.5

Rising (%V_OUT

)

94% 96%

90% 92%

98%

94%

0.3

V_{TH_PG}

Power good threshold voltage

Falling (%V_OUT

)

V_{OL_PG}

I_{LKG_PG}

Power good output low voltage

Input leakage current (PG)

I_PG= -2 mA

100

POWER SWITCH

Phase 1

Phase 2

Phase 1

Phase 2

High-side MOSFET ON-resistance

65 mΩ

45 mΩ

R_DS(ON)

V_IN= 7.5 V

Low-side MOSFET ON-resistance

I_LIM

High-side MOSFET current limit

Phase shift delay time

Each phase, V_IN= 7.5 V

3.5

4.2

5.0

T_PSD

Phase 2 after Phase 1, PWM mode

250

OUTPUT

V_REF

Internal reference voltage

Input leakage current (FB)

0.792

0.8 0.808

I_{LKG_FB}

V_FB= 0.8 V

100

R_DISCHARGEOutput discharge resistance

Output voltage range

EN = Low

V_IN≥ V_OUT

0.9

3.5

PWM Mode, V_IN≥ V_OUT+ 1 V

–1%

Power Save Mode, V_OUT= 3.3 V, I_load≥ 1 mA,

L = 1 µH, C_OUT= 2 x 47 µF, (T_J= –40°C to +85°C)

-1%

Feedback voltage accuracy⁽²⁾

V_OUT

Power Save Mode, V_OUT= 1.8 V, I_load≥ 1 mA,

L = 1 µH, C_OUT= 4 x 47 µF, (T_J= –40°C to +85°C)

Power Save Mode, V_OUT=0.9V, I_load≥ 1 mA,

L = 1 µH, C_OUT= 4 x 47 µF, (T_J= –40°C to +85°C)

–1%

Load regulation

Line regulation

PWM Mode operation

0.06

0.01

0.9

%/A

%/V

4 V ≤ V_IN≤ 17 V, I_OUT= 4 A

Hiccup on time

t_HICCUP

Hiccup off time

(1) The minimum V_INvalue of 4 V is not violated by UVLO threshold and hysteresis variations.

(2) The accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

7.6 Typical Characteristics

Figure 2. Quiescent Current

Figure 3. Shutdown Current

Figure 4. High-Side Switch Resistance

Figure 5. Low-Side Switch Resistance

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

8 Detailed Description

8.1 Overview

The TPS62184 is a high efficiency synchronous switched mode step-down converter based on a peak current

control topology. It is designed for smallest solution size low-profile applications, converting multi-cell Li-Ion

supply voltages to output voltages of 0.9 V to 3.5 V. While an outer voltage loop sets the regulation threshold for

the current loop based on the actual V_OUTlevel, the inner current loop adapts the peak inductor current for every

switching cycle. The regulation network is internally compensated. The switching frequency is set by an OFF-

time control and features Power Save Mode (PSM) and Automatic Efficiency Enhancement (AEE™) to keep the

efficiency high over the whole load current and duty cycle range. The switching frequency is set depending on

V_INand V_OUTand remains unchanged for steady state operating conditions.

The TPS62184 is a dual phase converter, sharing the load current among the phases. Identical in construction,

the follower control loop is connected with a fixed delay to the master control loop. Both the phases use the

same regulation threshold and cycle-by-cycle peak current setpoint. This ensures a phase-shifted as well as

current-balanced operation. Using the advantages of the dual phase topology, a 6-A continuous output current is

provided with high performance and smallest system solution size.

8.2 Functional Block Diagram

VIN2

VIN1

Thermal

Power Save

Mode

PG control

Shutdown

VIN1

HS1

EN*

SS/TR

SW1

SW2

VIN2

power

control

gate

HS2

control logic

drive

phase shift

VIN

HS2

UVLO

HICCUP

follower

t_f

gm_out

delay

V_REF

master

t_m

HS1

VIN

AEE^TM

off-timer

GND

*Pin is connected to a pull down resistor internally

(see Feature Description section)

Figure 6. TPS62184

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

8.3 Feature Description

8.3.1 Enable / Shutdown (EN)

The device starts operation, when V_INis present and Enable (EN) is set High. The EN threshold is 1 V for rising

and 0.9 V for falling voltages, providing a threshold accuracy of ±3%. That makes it suitable for precise switching

on and off in accurate power sequencing arrangements as well as for slowly rising EN control voltage signals

(see Using the Accurate EN Threshold for more details).

The device is disabled by pulling EN Low. A discharge resistor of about 60 Ω is then connected to the output. At

the EN pin, an internal pull down resistor of about 350 kΩ keeps the Low state, if EN gets high impedance or

floating afterwards.

The EN pin can be connected to V_INto always enable the device. A delay of 1 ms, after V_INexceeds V_UVLO

ensures safe operating conditions before the device starts switching. If V_INis already present, a soft start

sequence is initiated about 100 µs after EN is pulled High.

8.3.2 Soft Start / Tracking (SS/TR)

The soft start circuit controls the output voltage slope during startup. This avoids excessive inrush current and

ensures a controlled output voltage rise time. It also prevents unwanted voltage drop from high impedance power

sources or batteries. When EN is set to start device operation, the device starts switching and V_OUTrises with a

slope, controlled by the external capacitor connected to the SS/TR pin. It is not recommended to leave the

SS/TR pin floating, because V_OUTmay overshoot. Typical startup operation is shown in Application Performance

Curves.

The device can track an external voltage (see Tracking). The device can monotonically start into a pre-biased

output.

8.3.3 Power Good (PG)

The TPS62184 has a built in power good (PG) function. The PG pin goes High, when the output voltage has

reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low. The

PG pin is an open drain output that requires a pull-up resistor and can sink typically 2 mA. If not used, the PG pin

can be left floating or grounded.

8.3.4 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) prevents misoperation of the device, if the input voltage drops below the UVLO

threshold. It is set to 3.6 V typically with a hysteresis of typically 300mV. (See also Device Functional Modes).

8.3.5 Thermal Shutdown

The junction temperature T_Jof the device is monitored by an internal temperature sensor. If T_Jexceeds 160°C

(typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. Both the power FETs are turned

off, the discharge resistor is connected to the output and the PG pin goes Low. Once T_Jhas decreased enough,

the device resumes normal operation with Soft Start.

8.4 Device Functional Modes

8.4.1 Pulse Width Modulation (PWM) Operation

The TPS62184 is based on a predictive OFF-time peak current control topology, operating with PWM in

continuous conduction mode for heavier loads. Since the OFF-time is automatically adjusted according to the

actual V_INand V_OUT, it provides highest efficiency over the entire input and output voltage range. The OFF-time is

calculated as:

spacing

V_IN

t_OFF

500ns + 50ns

5V_OUT

(1)

spacing

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

Device Functional Modes (continued)

While the OFF-time is predicted, the ON-time is set depending on the converter's duty cycle and calculated as:

spacing

t_OFF×V_OUT

t_ON

V_IN-V_OUT

(2)

(3)

spacing

Thereby the switching frequency is fixed for a given input and output voltage and is calculated as:

spacing

1- D

V_OUT

V_IN

f_SW

t_OFF

spacing

Both the master and follower phases regulate to the same level of V_OUTwith separate current loops, using the

same peak current setpoint, cycle by cycle. This provides excellent peak current balancing, independent of

inductor dc resistance matching. Since the follower phase operates with a fixed delay to the master phase, also

cycle by cycle, phase shifted operation is obtained.

The device features an automatic transition into Power Save Mode, entered at light loads, running in

discontinuous conduction mode (DCM).

8.4.2 Power Save Mode (PSM) Operation

As the load current decreases, the converter enters Power Save Mode operation. During PSM, the converter

operates with a reduced switching frequency maintaining highest efficiency due to minimum quiescent current.

Power Save Mode is based on a fixed peak current architecture, where the peak current (I_PEAK) is set depending

on V_IN, V_OUT, and L. After each single pulse, a pause time until the internal V_{OUT_Low}level threshold is reached

completes the switching cycle in PSM.

The switching frequency for PSM in one phase operation is calculated as :

spacing

2I_OUT×V_OUT(V_IN-V_OUT)

f_PSM

L× I_P²_EAK×V_IN

(4)

spacing

Equation 4 shows the linear relationship of output current and switching frequency. Typical values of the fixed

peak current are shown in Figure 7.

space

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

Device Functional Modes (continued)

Figure 7. Typical Fixed Peak Current (I_PEAK) in Power Save Mode

space

If the load decreases to very light loads and only one phase is needed, either phase (master or follower) might

be active. The load current level at which Power Save Mode is entered is calculated as follows:

spacing

I_{load (PSM )}= DI_L

(5)

spacing

Equation 7 is used to calculate ΔI_L.

8.4.3 Minimum Duty Cycle and 100% Mode Operation

When the input voltage comes close to the output voltage, the device enters 100% mode and both high-side

FETs are continuously switched on as long as V_OUTremains below its setpoint. The minimum V_INto maintain

output voltage regulation is calculated as:

spacing

DS(ON )

V_{IN (min)}=V_{OUT (min)}+ I_OUT

+ DCR_L1// DCR_L2

(6)

spacing

This allows the conversion of small input to output voltage differences, for example for longest operation time in

battery powered applications. In 100% duty cycle mode, the low-side FET is switched off.

While the maximum ON-time is not limited, the AEE feature, explained in the next section, secures a minimum

ON-time of about 100 ns.

8.4.4 Automatic Efficiency Enhancement (AEE™)

AEE™ provides highest efficiency over the entire input voltage and output voltage range by automatically

adjusting the converter's switching frequency. This is achieved by setting the predictive off-time of the converter.

The efficiency of a switched mode converter is determined by the power losses during the conversion. The

efficiency decreases, if V_OUTdecreases and/or V_INincreases. In order to keep the efficiency high over the entire

duty cycle range (V_OUT/V_INratio), the switching frequency is adjusted while maintaining the ripple current. The

following equation shows the relation between the inductor ripple current, switching frequency and duty cycle.

spacing

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

Device Functional Modes (continued)

V_OUT

V_IN

1- D

DI_L=V_OUT

=V_OUT×

L× f_SW

(7)

spacing

Efficiency increases by decreasing switching losses, preserving high efficiency for varying duty cycles, while the

ripple current amplitude remains low enough to deliver the full output current without reaching current limit. The

AEE™ feature provides an efficiency enhancement for various duty cycles, especially for lower Vout values,

where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates

for the very small duty cycles of high V_INto low V_OUTconversion, which limits the control range in other

topologies.

Figure 8 shows the typical switching frequency over the input voltage range.

space

Figure 8. Typical Switching Frequency vs Input Voltage

space

8.4.5 Phase-Shifted Operation

While, for a buck converter, the input current source provides the average current that is needed to support the

output current, an input capacitance is needed to support pulse currents. One of the natural benefits of a two- (or

multi-) phase converter is the possibility to operate out of phase, which decreases the pulse currents and

switching noise. In PWM mode, the TPS62184 runs with a fixed delay of typically 250 ns between the phases.

This ensures that the phases run phase-delayed, limiting input RMS current and corresponding noise. If in PSM,

both phases run, the phase delay is about 100 ns.

8.4.6 Current Limit, Current Balancing, and Short Circuit Protection

Each phase has a separate integrated peak current limit. While its minimum value limits the output current of the

phase, the maximum number gives the current that must be considered to flow in any operating case. If the

current limit of a phase is reached, the peak current setpoint is unable to increase further. The device provides its

maximum output current. Detecting this heavy load or short circuit condition for about 0.9 ms, the device

switches off for about 5 ms and then restarts again with a soft start cycle. As long as the overload condition is

present, the device hiccups that way, limiting the output power.

The two phases are peak current balanced with a variation within about ±10% at 6-A output current. Since the

control topology does not depend on inductor or output current measurements, the current balancing accuracy is

independent of inductor matching (binning) and does not need matched power routing.

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

Device Functional Modes (continued)

8.4.7 Tracking

V_OUTcan track a voltage that is applied at the SS/TR pin. The tracking range at the SS/TR pin is 50 mV to 1.2 V

and the FB pin voltage tracks this as given in Equation 8:

spacing

V_FB» 0.64×V_{SS /TR}

(8)

spacing

Due to the factor of about 0.64, the minimum output voltage for tracking is 1.25 V. Once the SS/TR pin voltage

reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage and the device goes to

normal regulation. This works for falling tracking voltage as well. If, in this case, the SS/TR voltage decreases,

the device does not sink current from the output. Thus, the resulting decrease of the output voltage may be

slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not

exceed the voltage rating of the SS/TR pin which is V_IN+0.3 V.

Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a

wider tolerance than specified.

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS62184 is a switched mode step-down converter, able to convert a 4-V to 17-V input voltage into a 0.9-V

to 3.5-V output voltage, providing up to 6 A. It needs a minimum amount of external components. Apart from the

LC output filter and the input capacitors only an optional pull-up resistor for Power Good (PG) and a small

capacitor for adjustable soft start are used. To adjust the output voltage, an resistive divider is needed.

9.2 Typical Applications

9.2.1 Typical TPS62184 Application

22µF

1µH

VIN1

VIN2

SW1

SW2

0.9V/6A

V_OUT

4 to 17 V

470k

22µF

TPS62184

47µF

20k

V_FB

SS/TR

GND

160k

3.3nF

Figure 9. Typical 4-V to 17-V Input, 0.9-V Output Converter

9.2.1.1 Design Requirements

The design guideline provides a component selection to operate the device within the recommended operating

conditions. The component selection is given as follows:

Table 1. Components Used for Application Characteristics

REFERENCE NAME

TPS62184YZF

DESCRIPTION / VALUE

2 phase step down converter, 2 x 3 mm WCSP

Inductor XFL4020-102ME, 1 µH ±20%, 4 x 4 x 2.1 mm

Ceramic capacitor GRM21BR61E226ME44, 2 x 22 µF, 25 V, X5R, 0805

Ceramic capacitor GRM21BR60J476ME15, 4 x 47 µF, 6.3 V, X5R, 0805

Ceramic capacitor, 3.3 nF

MANUFACTURER⁽¹⁾

Texas Instruments

Coilcraft

L1, L2

C_IN

muRata

C_OUT

C_SS

muRata

Standard

Chip resistor, value depending on V_OUT

Standard

Chip resistor, value depending on V_OUT

Standard

Chip resistor, 470 kΩ, 0603, 1/16 W, 1%

Standard

(1) See Third-Party Products Disclaimer

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Programming the Output Voltage

The output voltage of the TPS62184 is programmed using an external resistive divider. While the voltage at the

FB pin is regulated to 0.8 V, the output voltage range is specified from 0.9 up to 3.5 V. The value of the output

voltage is set by selection of the resistive divider (from VOUT to FB to AGND) from Equation 9.

spacing

V_OUT

-1

R₂V_FB

(9)

spacing

The current through those resistors contributes to the light load efficiency, which makes larger resistor values

beneficial. However, to get sufficient noise immunity a minimum current of 5 µA is recommended. Using this, the

resistor values are calculated by converting Equation 9 as follows:

spacing

V_FB0.8V

I_FB5mA

R₂=

=160kW

(10)

spacing

Inserting the R₂value in Equation 11, R₁can be obtained.

spacing

V_OUT

V_FB

R₁= R₂×

-1

(11)

spacing

Calculating for V_OUT= 1.0 V gives R₁= 40 kΩ and R₂=160 kΩ.

In case the FB pin gets opened or an over voltage appears at the output, an internal clamp limits the output

voltage to about 7.4 V.

9.2.1.2.2 Output Filter Selection

Since the TPS62184 is compensated internally, it is optimized for a range of external component values, which is

specified below. Table 2 and Table 3 are used to simplify the output filter component selection.

Table 2. Recommended LC Output Filter Combinations for V_OUT≥ 1.8 V⁽¹⁾

2 x 47 µF

4 x 47 µF

6 x 47 µF

8 x 47 µF

0.47 µH

1.0 µH

1.5 µH

√

(1) The values in the table are the nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and

–60%.

Table 3. Recommended LC Output Filter Combinations for V_OUT< 1.8 V⁽¹⁾

2 x 47 µF

4 x 47 µF

6 x 47 µF

8 x 47 µF

0.68 µH

1.0 µH

1.5 µH

√

(1) The values in the table are nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and -40%.

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

For the output capacitors, a voltage rating of 6.3 V and an X5R dielectric are chosen. If space allows for higher

voltage rated capacitors in larger case sizes, the dc bias effect is lowered and the effective capacitance value

increases.

9.2.1.2.3 Inductor Selection

The TPS62184 is designed to work with two inductors of 1 µH nominal. Inductors have to be selected for

adequate saturation current and a low dc resistance (DCR). The minimum inductor current rating I_L(min)that is

needed under static load conditions is calculated using Equation 12 and Equation 13. A current imbalance of

10% at most is incorporated.

spacing

1.1× I_{OUT (max)}DI_L(max)

I_peak(max)= I_L(min)

(12)

spacing

V_OUT

V_{IN (max)}

DI_L(max)=V_OUT

L_(min)× f_SW

(13)

spacing

This calculation gives the minimum saturation current of the inductor needed and an additional margin of about

20% is recommended to cover dynamic overshoot due to load transients. The maximum current limit can be

reached during strong load transient or overload condition. To avoid device over stress due to inductor saturation

in this case, the inductor rating must be as high as the max. current limit of 5A.

For low profile solutions, the physical inductor size and the power losses have to be traded off. Smallest solution

size (for example with chip inductors) are less efficient than bigger inductors with lower losses due to lower DCR

and/or core losses. The following inductors have been tested with the TPS62184:

Table 4. List of Inductors

INDUCTANCE

[µH]

CURRENT RATING

MIN/TYP [A]

DCR MAX

[mΩ]

TYPE

DIMENSIONS (LxBxH) [mm]

MANUFACTURER⁽²⁾

(1)

DFE252012P-1R0M

PIFE32251B-1R0MS

PIME031B-1R0MS

IHLP1212AB-11

1 ±20%

4.3/4.8

4.2/4.7

4.5/5.4

/5.0

2.5 x 2.0 x 1.2

3.2 x 2.5 x 1.2

3.7 x 3.3 x 1.2

3.6 x 3.0 x 1.2

3.6 x 3.0 x 1.5

4.0 x 4.5 x 1.8

4.0 x 4.0 x 2.1

TOKO

CYNTEC

VISHAY

37.5

IHLP1212AE-11

/5.3

VISHAY

744 373 24 010

/>9

WUERTH

COILCRAFT

XAL4020-102ME_

/8.7

14.6

(1) I_SATat 30% drop of inductance (ΔI_L/I_L).

(2) See Third-Party Products Disclaimer

The TPS62184 is not designed to operate with only one inductor.

9.2.1.2.4 Output Capacitor Selection

The TPS62184 provides an output voltage range of 0.9 V to 3.5 V. While stability is a critical criteria for the

output filter selection, the output capacitor value also determines transient response behavior, ripple and

accuracy of V_OUT. Table 5 gives recommendations to achieve various transient design targets using 1-µH

inductors and small sized output capacitors (see Table 1).

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

Table 5. Recommended Output Capacitor Values

OUTPUT

VOLTAGE [V]

TYPICAL TRANSIENT RESPONSE ACCURACY

LOAD STEP [A]

(NOMINAL) CAPACITOR VALUE⁽¹⁾

±mV

±%

4 x 47 µF

6 x 47 µF

2 x 47 µF

4 x 47 µF

8 x 47 µF

2 x 47 µF

4 x 47 µF

8 x 47 µF

0.9⁽²⁾

1.8

2-6-2⁽³⁾

150

120

2-6-2⁽³⁾

170

135

100

3.3

(1) Ceramic capacitors have a dc bias effect where the effective capacitance differs significantly from the nominal value, depending on

package size, voltage rating and dielectric material.

(2) For output voltages < 1.8V an additional feedforward capacitor of 82pF, parallel to R₁is recommended to increase stability margin at

heavy load steps.

(3) The transient load step is tested with 1-µs/step rising/falling slopes.

spacing

The architecture of the TPS62184 allows the use of tiny ceramic output capacitors with low equivalent series

resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low

resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to

use X7R or X5R dielectrics. Using even higher values than demanded for stability and transient response has

further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.

9.2.1.2.5 Input Capacitor Selection

The input current of a buck converter is pulsating. Therefore, a low ESR input capacitor is required to prevent

large voltage transients and provide peak currents. The recommended value for most applications is 2 x 22 µF,

split between the VIN1 and VIN2 inputs and placed as close as possible to these pins and PGND pins. If

additional capacitance is needed, it can be added as bulk capacitance. To ensure proper operation, the effective

capacitance at the VIN pins must not fall below 2 x 2 µF (close) + 10 µF bulk (effective capacitances).

Low ESR multilayer ceramic capacitors are recommended for best filtering. Increasing with input voltage, the dc

bias effect reduces the nominal capacitance value significantly. To decrease input ripple current further, larger

values of input capacitors can be used.

9.2.1.2.6 Soft Start Capacitor Selection

The TPS62184 provides a user programmable soft start time. A constant current source of 5 µA, internally

connected to the SS/TR pin, allows control of the startup slope by connecting a capacitor to this pin. The current

source charges the capacitor and the soft start time is given by:

spacing

5mA

C_SS= t_SS×

1.25V

(14)

spacing

where C_SSis the soft-start capacitance required at the SS/TR pin and t_ssis the resulting soft-start ramp time.

spacing

The SS/TR pin should not be left floating and a minimum capacitance of 220 pF is recommended. Using

Equation 14, and inserting t_SS= 750 µs, a value of 3 nF is calculated. 3.3 nF is chosen as a standard value for

this example.

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

9.2.1.2.7 Using the Accurate EN Threshold

The TPS62184 provides a very accurate EN threshold voltage. This can be used to switch on the device

according to a V_INor another voltage level by using a resistive divider as shown below. The values of R_EN1and

R_EN2, needed to set EN = High at a specific V_INcan be calculated according to Kirchhoff's laws, shown in

Equation 15 and used in the following example:

space

R_EN1+ R_{EN 2}

V_IN=V_{EN _threshold}

R_{EN 2}

(15)

space

V_IN

VIN

R_EN1

R_EN2

Figure 10. Resistive Divider for Controlled EN Threshold

space

For a typical 8-V input rail, the device turn on target value is set to 5.5 V. The current through the resistive divider

is set to 10 µA, which indicates a total resistance of about 800 kΩ. Appropriate standard resistor values, fitting

Equation 15, are R_EN1= 680 kΩ and R_EN2= 150 kΩ. As a result, the device switches on, when V_INhas reached

5.5 V and the current through the divider is 9.6 µA. The device switches off at a threshold of 0.9 V. Using

Equation 15 again, this case gives a level of V_IN= 5.0 V.

Figure 31 to Figure 34 show thresholds and appropriate device behavior with a startup time of about 800 µs.

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

9.2.1.3 Application Performance Curves

V_IN= 12 V, V_OUT= 3.3 V, T_A= 25°C, (unless otherwise noted)

V_OUT= 3.3V

V_OUT= 1.8V

V_OUT= 0.9V

V_OUT= 3.3V

Figure 11. Efficiency vs Load Current

Figure 13. Efficiency vs Load Current

Figure 15. Efficiency vs Load Current

Figure 12. Efficiency vs Input Voltage

V_OUT= 1.8V

Figure 14. Efficiency vs Input Voltage

V_OUT= 0.9V

Figure 16. Efficiency vs Input Voltage

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

Figure 17. Output Voltage vs Output Current (Load

regulation)

Figure 18. Output Voltage vs Input Voltage (Line

regulation)

V_OUT= 0.9V

V_OUT= 3.3V

Figure 19. Maximum Output Current vs Input Voltage

Figure 20. Switching Frequency vs Output Voltage

V_OUT= 0.9V

Figure 21. Startup into 10 Ω (90 mA)

Figure 22. Startup into 0.33 Ω (2.73 A)

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

V_OUT= 0.9V

Figure 23. Startup into 0.135 Ω (6.6 A)

Figure 24. Output Discharge (No load)

I_OUT= 3 A

V_OUT= 0.9V

I_OUT= 50 mA

V_OUT= 0.9V

Figure 25. Typical Operation (PWM)

Figure 26. Typical Operation (PSM)

C_OUT= 6 x 47 µF

V_OUT= 0.9V

C_OUT= 6 x 47 µF

V_OUT= 0.9V

Figure 27. Load Transient Response (PSM-PWM)

Figure 28. Load Transient Response (PWM-PWM)

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

V_OUT= 0.9V

Figure 29. HICCUP at Short Circuit

Figure 30. HICCUP at Short Circuit

V_IN= 5.5 V (Rising), V_IN= 5.0 V (Falling)

Figure 31. Accurate EN Threshold

Figure 32. Accurate EN Threshold Showing V_OUT

V_IN= 5.5 V (Rising)

V_IN= 5.0 V (Falling)

Figure 33. Accurate EN Threshold

Figure 34. Accurate EN Threshold

space

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

9.3 System Examples

Based on Figure 9, the schematics shown in Figure 35 through Figure 39 show different output voltage divider

values to get different V_OUT. Another design target is to have about 5-µA current through the divider.

The values for the voltage divider are derived using the procedure given in Programming the Output Voltage.

While Equation 10 and Equation 11 are used to calculate R2 and R1, the values are aligned with standard

resistor values.

space

22µF

1µH

VIN1

VIN2

SW1

SW2

1.0V/6A

4 to 17 V

470k

22µF

TPS62184

47µF

40k

82p

SS/TR

GND

160k

3.3nF

Figure 35. 1.0-V/6-A Power Supply

space

22µF

3.3nF

1µH

VIN1

VIN2

SW1

1.2V/6A

4 to 17 V

1µH

SW2

470k

TPS62184

47µF

80k

82p

SS/TR

GND

160k

Figure 36. 1.2-V/6-A Power Supply

space

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

System Examples (continued)

22µF

1µH

VIN1

VIN2

SW1

SW2

1.8V/6A

4 to 17 V

470k

22µF

TPS62184

47µF

200k

160k

SS/TR

GND

3.3nF

Figure 37. 1.8-V/6-A Power Supply

space

22µF

1µH

VIN1

SW1

SW2

2.5V/6A

4 to 17 V

1µH

VIN2

470k

22µF

TPS62184

47µF

340k

160k

SS/TR

GND

3.3nF

Figure 38. 2.5-V/6-A Power Supply

space

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

System Examples (continued)

22µF

1µH

VIN1

SW1

SW2

3.3V/6A

4 to 17 V

VIN2

470k

22µF

TPS62184

47µF

470k

150k

SS/TR

GND

3.3nF

Figure 39. 3.3-V/6-A Power Supply

space

10 Power Supply Recommendations

The TPS62184 is designed to operate from a 4-V to 17-V input voltage supply. The input power supply's output

current needs to be rated according to the output voltage and the output current of the power rail application.

TPS62184

www.ti.com.cn

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

11 Layout

11.1 Layout Guidelines

The PCB layout of the TPS62184 demands careful attention to ensure proper operation, thermal profile, low

noise emission and to achieve best performance. A poor layout can lead to issues like poor regulation, stability

and accuracy weaknesses, increased EMI radiation and noise sensitivity. While the TPS62184 provides very

high power density, the PCB layout also contributes significantly to the thermal performance.

11.1.1 PCB layout

A recommended PCB layout for the TPS62184 dual phase solution is shown below. It ensures best electrical and

optimized thermal performance considering the following important topics:

- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides

low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the V_IN

connection, to avoid interference between the input lines.

- The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can be

designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal

behavior.

- The V_OUTregulation loop is closed with C_OUTand its ground connection. If a ground layer or plane is used, a

direct connection by vias, as shown, is recommended. Otherwise the connection of C_OUTto GND must be short

for good load regulation.

- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB pin,

avoiding long trace distance.

11.2 Layout Example

space

VIN2

VIN1

SW2

SW1

CIN2

0805

CIN1

0805

PGND

COUT

0805

CSS

COUT

0805

0402

AGND

VOUT

filled VIA to ground plane

filled VIA to internal or bottom layer

Figure 40. TPS62184 Board Layout

TPS62184

ZHCSDE4A –DECEMBER 2014–REVISED FEBRUARY 2015

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 商标

AEE, NanoFree are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS62184YZFR

TPS62184YZFT

ACTIVE

DSBGA

YZF

3000 RoHS & Green

250 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

ELC184

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS62184YZFR

TPS62184YZFT

DSBGA

YZF

3000

250

330.0

12.4

2.25

3.25

0.81

4.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS62184YZFR

TPS62184YZFT

DSBGA

YZF

3000

250

335.0

25.0

Pack Materials-Page 2

PACKAGE OUTLINE

YZF0024

DSBGA - 0.625 mm max height

SCALE 6.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.625 MAX

SEATING PLANE

0.05 C

0.35

0.15

BALL TYP

1.5 TYP

SYMM

2.5

TYP

D: Max = 3.13 mm, Min = 3.07 mm

E: Max = 2.13 mm, Min = 2.07 mm

0.5

TYP

0.35

24X

0.015

0.25

C A B

0.5 TYP

4219412/A 01/2019

NanoFree Is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. NanoFree^TMpackage configuration.

www.ti.com

EXAMPLE BOARD LAYOUT

YZF0024

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

24X ( 0.245)

(0.5) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:28X

0.05 MAX

0.05 MIN

(

0.245)

METAL

METAL UNDER

SOLDER MASK

EXPOSED

METAL

EXPOSED

METAL

(

0.245)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219412/A 01/2019

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YZF0024

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

(R0.05) TYP

24X ( 0.25)

(0.5)

TYP

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:40X

4219412/A 01/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TPS62184YZFR [TI]

相关型号：

TPS62184YZFT

TPS622

TPS622(A)

TPS622(A,F)

TPS622(B)

TPS622(B,F)

TPS622-A

TPS622-B

TPS62200

TPS62200DBV

TPS62200DBVR

TPS62200DBVRG4