TPS62351YZGR [TI]
800-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER WITH I2C⑩ COMPATIBLE INTERFACE IN CHIP SCALE PACKAGING; 800毫安， 3 MHz的同步降压型转换器I2C⑩兼容接口的芯片级封装
| 型号： | TPS62351YZGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 800-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER WITH I2C⑩ COMPATIBLE INTERFACE IN CHIP SCALE PACKAGING |
| 文件： | 总46页 (文件大小：1401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSP-12
QFN-10
TPS62350, TPS62351
TPS62352, TPS62353, TPS62354
www.ti.com
SLVS540B–MAY 2006–REVISED DECEMBER 2006
800-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER
WITH I2C™ COMPATIBLE INTERFACE IN CHIP SCALE PACKAGING
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
88% Efficiency at 3-MHz Operation
800-mA Output Current at VI = 2.7 V
3-MHz Fixed Frequency Operation
Best in Class Load and Line Transient
Complete 1-mm Component Profile Solution
±2% PWM DC Voltage Accuracy
35-ns Minimum On-Time
The TPS6235x device is
a
high-frequency
synchronous step-down dc-dc converter optimized
for battery-powered portable applications. Intended
for low-power applications, the TPS6235x supports
up to 800-mA load current and allows the use of
small, low cost inductors and capacitors.
The device is ideal for mobile phones and similar
portable applications powered by a single-cell Li-Ion
battery. With an output voltage range adjustable via
I2C interface down to 0.6 V, the device supports
low-voltage DSPs and processors core power
supplies in smart-phones, PDAs, and handheld
computers.
Efficiency Optimized Power-Save Mode
(Light PFM)
•
Transient Optimized Power-Save Mode
(Fast PFM)
•
•
•
•
28-µA Typical Quiescent Current
I2C Compatible Interface up to 3.4 Mbps
Pin-Selectable Output Voltage
The TPS6235x operates at 3-MHz fixed switching
frequency and enters the efficiency optimized
power-save mode operation at light load currents to
maintain high efficiency over the entire load current
range. In the shutdown mode, the current
consumption is reduced to less than 2 µA.
Synchronizable On the Fly to External
Clock Signal
•
Available in a 10-Pin QFN (3 x 3 mm) and
12-Pin NanoFree™ (CSP) Packaging
The serial interface is compatible with Fast/Standard
and High-Speed mode I2C specification allowing
transfers at up to 3.4 Mbps. This communication
interface is used for dynamic voltage scaling with
voltage steps down to 12.5 mV, for reprogramming
the mode of operation (Light PFM, Fast PFM or
Forced PWM) or disable/enabling the output voltage.
APPLICATIONS
•
•
SmartReflex™ Compliant Power Supply
Split Supply DSPs and µP Solutions
OMAP™, XSCALE™
•
•
•
•
Cell Phones, Smart-Phones
PDAs, Pocket PCs
Digital Cameras
Micro DC-DC Converter Modules
EFFICIENCY vs LOAD CURRENT
TYPICAL APPLICATION
100
90
TPS62350YZG
PVIN
AVIN
V
FB
I
80
V
O
C1
SW
70
60
50
40
30
20
10
0
L1
1 mH
PGND
PGND
C2
10 mF
2.7 V .. 5.5 V
A
AGND
A
EN
V
= Roof
O
V
V
= 3.6 V
VSEL
I
V
= Floor
2
O
= 1.35 V
O
SDA
SCL
I C Bus
LPFM/PWM Mode
up to 3.4 Mbips
0.1
1
10
100 1000
SYNC
I
− Output Current − mA
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, SmartReflex, OMAP, PowerPAD are trademarks of Texas Instruments.
XSCALE is a trademark of Intel Corporation.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS62350, TPS62351
TPS62352, TPS62353, TPS62354
www.ti.com
SLVS540B–MAY 2006–REVISED DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
I2C
DEFAULT
OUTPUT
DEFAULT
VALUE
EN_DCDC
BIT(2)
OUTPUT
LSB ADDRESS
PART
PACKAGE
MARKING
VOLTAGE
SYNC
PACKAGE
ORDERING(3)
VOLTAGE(2)
BITS(2)
NUMBER(1)
(2)
RANGE
VSEL0
VSEL1
A1
0
A0
0
TPS62350(4)
TPS62351
0.75 V to 1.5375 V
0.9 V to 1.6875 V
1.05 V
1.35 V
1
0
YES
NO
CSP-12
QFN-10
CSP-12
CSP-12
CSP-12
CSP-12
TPS62350YZG
TPS62351DRC
TPS62351YZG
TPS62352YZG
TPS62353YZG
TPS62354YZG
TPS62350
BNT
1
0
1.10 V
1.50 V
YES
YES
YES
YES
1
0
TPS62351
TPS62352
TPS62353
TPS62354
TPS62352(4)
TPS62353
0.75 V to 1.4375 V
0.75 V to 1.5375 V
0.75 V to 1.5375 V
1.05 V
1.00 V
1.05 V
1.20 V
1.20 V
1.30 V
1
1
1
1
0
0
0
TPS62354(4)
1
0
(1) All devices are specified for operation in the commercial temperature range, –40°C to 85°C.
(2) For customized output voltage range, default output voltage and I2C address, contact the factory.
(3) The YZG package is available in tape and reel. Add R suffix (TPS6235xYZGR) to order quantities of 3000 parts. Add T suffix
(TPS6235xYZGT) to order quantities of 250 parts. For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI website at www.ti.com.
(4) The following registers bits are set by internal hardware logic and not user programmable through I2C:
•
•
•
•
VSEL0[7:6] = 11
VSEL1[7:6] = 11
CONTROL1[4:2] = 100
CONTROL2[7:6] = 10, CONTROL2[4:3] = 00
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNITS
-0.3 V to 7 V
-0.3 V to 7 V
-0.3 V to 7 V
-0.3 V to 4.2 V
Internally limited
150°C
Voltage at AVIN, PVIN(2)
(2)
Voltage at SW
VI
(2)
Voltage at EN, VSEL, SCL, SDA, SYNC
Voltage at FB(2)
Power dissipation
TJ
Maximum operating junction temperature
Storage temperature range
Human body model
Tstg
–65°C to 150°C
2 kV
ESD rating(3) Charge device model
1 kV
Machine model
200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
-40
-40
NOM
MAX UNIT
VI
Input voltage range
5.5
85
V
TA
TJ
Operating temperature range
Operating virtual junction temperature range
°C
°C
125
2
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
DISSIPATION RATINGS(1)
POWER RATING
FOR TA ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
(2)
PACKAGE
RθJA
DRC
YZG
49°C/W
2050 mW
21 mW/°C
9 mW/°C
110°C/W
900 mW
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max) – TA] / θJA
.
(2) This thermal data is measured with high-K board (4 layers board according to JESD51-7 JEDEC standard).
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply with
VI = 3.6 V, EN = VI, VSEL = VI, SYNC = GND, VSEL0[6] bit = 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IO = 0 mA, Fast PFM mode enabled
Device not switching
110
28
150
45
µA
µA
IQ
Operating quiescent current
Shutdown current
IO = 0 mA, Light PFM mode enabled
Device not switching
IO = 0 mA, 3-MHz PWM mode operation
EN = GND, EN_DCDC bit = X
EN = VI, EN_DCDC bit = 0
4.8
0.1
mA
µA
µA
V
2
I(SD)
6.5
V(UVLO) Undervoltage lockout threshold
2.20
2.3
ENABLE, VSEL, SDA, SCL, SYNC
VIH
VIL
Ilkg
High-level input voltage
Low-level input voltage
Input leakage current
1.2
V
V
0.4
1
Input tied to GND or VI
0.01
µA
POWER SWITCH
VI = V(GS) = 3.6 V, YZG package
VI = V(GS) = 3.6 V, DRC package
VI = V(GS) = 2.7 V, DRC package
V(DS) = 6 V
250
275
350
500
500
750
1
rDS(on)
P-channel MOSFET on resistance
mΩ
µA
Ilkg
P-channel leakage current
VI = V(GS) = 3.6 V, YZG package
VI = V(GS) = 3.6 V, DRC package
VI = V(GS) = 2.7 V, DRC package
V(DS) = 6 V
150
165
210
350
350
500
1
rDS(on)
N-channel MOSFET on resistance
mΩ
Ilkg
N-channel leakage current
µA
Ω
R(DIS)
Discharge resistor for power-down sequence
P-MOS current limit
15
1350
1100
-700
675
50
2.7 V ≤ VI ≤ 5.5 V
2.7 V ≤ VI ≤ 5.5 V
2.7 V ≤ VI ≤ 5.5 V
VO = 0 V
1150
900
1600
1300
-900
mA
mA
mA
mA
°C
Sourcing
N-MOS current limit
Sinking
-500
Input current limit under short-circuit conditions
Thermal shutdown
150
Thermal shutdown hysteresis
20
°C
OSCILLATOR
fSW
Oscillator frequency
CONTROL2[4:3] = 00
2.65
2.65
20%
3
3.35
3.35
80%
MHz
MHz
f(SYNC)
Synchronization range
Duty cycle of external clock signal
3
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TPS62350, TPS62351
TPS62352, TPS62353, TPS62354
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply with
VI = 3.6 V, EN = VI, VSEL = VI, SYNC = GND, VSEL0[6] bit = 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
TPS62350
0.75
0.90
0.75
0.75
0.75
1.5375
1.6875
1.4375
1.5375
1.5375
V
V
TPS62351
TPS62352
TPS62353
TPS62354
VO
Output voltage range
V
V
V
ton(MIN) Minimum on-time (P-channel MOSFET)
Resistance into FB sense pin
35
ns
kΩ
700
1000
VI = 3.6 V, VO = 1.35 V, IO(DC) = 0 mA,
PWM operation
–1.5%
1.5%
2%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 0.75 V, 1.05 V, 1.35 V, 1.5375 V
PWM operation
–2%
Output voltage
DC accuracy
VO
VO
VO
VO
TPS62350
TPS62351
TPS62352
TPS62353
2.7 V ≤ VI≤ 5.5 V, IO(DC) = 0 mA
VO = 1.05 V, L = 1 µH, Light PFM
–1%
–2%
4.5%
3%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 1.35 V, L = 1 µH, Fast PFM/PWM
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.05 V, L = 1 µH, Light or Fast PFM/PWM
–2%
4.5%
1.5%
VI = 3.6 V, VO = 1.50 V, IO(DC) = 0 mA,
PWM operation
–1.5%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 0.90 V, 1.10 V, 1.50 V, 1.6875 V
PWM operation
–2%
2%
Output voltage
DC accuracy
2.7 V ≤ VI≤ 5.5 V, IO(DC) = 0 mA,
VO = 1.10 V, L = 1 µH, Light PFM
–1%
–2%
4.5%
4.5%
4.0%
1.5%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.10 V, L = 1 µH, Light or Fast PFM/PWM
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.50 V, L = 1 µH,Light or Fast PFM/PWM
–2%
VI = 3.6 V, VO = 1.20 V, IO(DC) = 0 mA
PWM operation
–1.5%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V,
PWM operation
–2%
2%
Output voltage
DC accuracy
2.7 V ≤ VI≤ 5.5 V, IO(DC) = 0 mA,
VO = 1.05 V, L = 1 µH, Light PFM
–1%
–2%
4.5%
3%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.20 V, L = 1 µH, Fast PFM/PWM
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.05 V, L = 1 µH, Light or Fast PFM/PWM
–2%
4.5%
1.5%
VI = 3.6 V, VO = 1.20 V, IO(DC) = 0 mA,
PWM operation
–1.5%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 0.75 V, 1.00 V, 1.20 V, 1.5375 V,
PWM operation
–2%
2%
Output voltage
DC accuracy
2.7 V ≤ VI≤ 5.5 V, IO(DC) = 0 mA,
VO = 1.00 V, L = 1 µH, Light PFM
–1%
–2%
–2%
4.5%
3%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 1.20 V, L = 1 µH, Fast PFM/PWM
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA
VO = 1.00 V, L = 1 µH, Light or Fast PFM/PWM
4.5%
4
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TPS62352, TPS62353, TPS62354
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply with
VI = 3.6 V, EN = VI, VSEL = VI, SYNC = GND, VSEL0[6] bit = 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI = 3.6 V, VO = 1.30 V, IO(DC) = 0 mA,
PWM operation
–1.5%
1.5%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 0.75 V, 1.05 V, 1.30 V, 1.5375 V,
PWM operation
–2%
2%
Output voltage
DC accuracy
VO
TPS62354
2.7 V ≤ VI≤ 5.5 V, IO(DC) = 0 mA,
VO = 1.05 V, L = 1 µH, Light PFM
–1%
–2%
–2%
4.5%
3%
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.30 V, L = 1 µH, Fast PFM/PWM
2.7 V ≤ VI≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA,
VO = 1.05 V, L = 1 µH, Light or Fast PFM/PWM
4.5%
DC output voltage load regulation
DC output voltage line regulation
IO(DC) = 0 mA to 800mA, PWM operation
–0.0003
0
%/mA
%/V
∆VO
VI = VO + 0.5 V (min 2.7 V) to 5.5 V,
IO(DC) = 300 mA
VO = 0.9 V, IO(DC) = 0 mA, L = 1 µH,
Light PFM operation
33
30
mVPP
mVPP
mVPP
VPP
VO = 1.05 V, IO(DC) = 1 mA , L = 1 µH,
Light PFM operation
Power-save mode ripple voltage
VO = 1.10 V, IO(DC) = 1 mA,
L = 1 µH, Light PFM operation, VSEL0[6] bit = 0
12
VO = 1.35 V, IO(DC) = 1 mA,
L = 1 µH, Fast PFM operation
0.025 VO
Leakage current into SW pin
VI > VO, 0 V ≤ V(SW) ≤ VI, EN = GND
0.01
0.01
1
1
Ilkg
µA
Reverse leakage current into SW pin
VI = open, V(SW) = 6 V, EN = GND
DAC
TPS62350
TPS62351
Resolution
TPS62352
TPS62353
TPS62354
6
Bits
Differential nonlinearity
Assured monotonic by design
±0.8
LSB
TIMING
Setup Time Between Rising EN and Start of I2C
Stream
250
µs
µs
Output voltage settling
TPS62350
From min to max output voltage,
IO(DC) = 500 mA, PWM operation
VO
3
180
170
45
time
Time from active EN to VO
VO = 1.35 V, RL = 5Ω, PWM operation
TPS62350
Time from active EN to VO
VO = 1.05 V, IO(DC) = 0 mA, Light PFM operation
Time from active EN_DCDC bit to VO
VO = 1.5 V, RL = 5Ω, PWM operation
Start-up time
TPS62351
TPS62352
µs
Time from active EN to VO
VO = 1.2 V, RL = 5Ω, PWM operation
175
170
Time from active EN to VO
VO = 1.05 V, IO(DC) = 0 mA, Light PFM operation
5
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
I2C INTERFACE TIMING CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
Standard mode
Fast mode
MIN
MAX
100
UNIT
kHz
400
3.4
3.4
1.7
1.7
kHz
MHz
MHz
MHz
MHz
µs
µs
µs
ns
High-speed mode (write operation), CB– 100 pF max
High-speed mode (read operation), CB– 100 pF max
High-speed mode (write operation), CB– 400 pF max
High-speed mode (read operation), CB– 400 pF max
Standard mode
f(SCL)
SCL Clock Frequency
4.7
Bus Free Time Between a STOP and
START Condition
tBUF
Fast mode
1.3
Standard mode
4
Hold Time (Repeated) START
Condition
tHD, tSTA
Fast mode
600
High-speed mode
160
ns
Standard mode
4.7
µs
µs
ns
Fast mode
1.3
tLOW
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
160
320
ns
4
µs
ns
Fast mode
600
tHIGH
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
60
ns
120
ns
4.7
µs
ns
Setup Time for a Repeated START
Condition
tSU, tSTA
Fast mode
600
High-speed mode
160
ns
Standard mode
250
ns
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
0.9
µs
µs
ns
Fast mode
0
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
0
70
0
20 + 0.1 CB
20 + 0.1 CB
10
150
1000
300
40
ns
ns
Fast mode
ns
tRCL
tRCL1
tFCL
Rise Time of SCL Signal
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
ns
20
80
ns
20 + 0.1 CB
20 + 0.1 CB
10
1000
300
80
ns
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
Fast mode
ns
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
ns
20
160
300
300
40
ns
20 + 0.1 CB
20 + 0.1 CB
10
ns
Fast mode
ns
Fall Time of SCL Signal
Rise Time of SDA Signal
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
ns
20
80
ns
20 + 0.1 CB
20 + 0.1 CB
10
1000
300
80
ns
Fast mode
ns
tRDA
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
ns
20
160
ns
(1) Specified by design. Not tested in production.
6
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
I2C INTERFACE TIMING CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
Standard mode
MIN
MAX
300
300
80
UNIT
ns
20 + 0.1 CB
Fast mode
20 + 0.1 CB
ns
tFDA
Fall Time of SDA Signal
High-speed mode, CB– 100 pF max
High-speed mode, CB– 400 pF max
Standard mode
10
20
ns
160
ns
4
µs
tSU, tSTO Setup Time for STOP Condition
Fast mode
600
160
ns
High-speed mode
ns
CB
Capacitive Load for SDA and SCL
400
pF
I2C TIMING DIAGRAMS
SDA
t
t
BUF
f
t
f
t
t
LOW
t
r
su;DAT
t
t
r
hd;STA
SCL
t
t
t
su;STO
hd;STA
t
su;STA
hd;DAT
HIGH
S
Sr
P
S
Figure 1. Serial Interface Timing Diagram for F/S-Mode
Sr
Sr P
t
fDA
t
rDA
SDAH
t
hd;DAT
t
su;STO
t
t
t
su;DAT
su;STA
hd;STA
SCLH
t
fCL
t
t
rCL1
rCL1
t
rCL
t
t
t
t
HIGH
HIGH
LOW
LOW
See Note A
= MCS Current Source Pull-Up
= R Resistor Pull-Up
See Note A
(P)
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 2. Serial Interface Timing Diagram for HS-Mode
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
PIN ASSIGNMENTS
TPS6235x
QFN−10
TPS6235x
CSP−12
TPS6235x
CSP−12
(TOP VIEW)
(TOP VIEW)
(BOTTOM VIEW)
A1
B1
A2
B2
A3
B3
A3
B3
A2
B2
A1
B1
C1
D1
C2
D2
C3
D3
C3
D3
C2
D2
C1
D1
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
QFN
NO.
CSP
NAME
PVIN
AVIN
1
2
A3
B3
Supply voltage for output power stage.
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
This is the enable pin of the device. Connect this pin to ground forces the device into shutdown
mode. Pulling this pin to VI enables the device. On the rising edge of the enable pin, all the
registers are reset with their default values. This pin must not be left floating and must be
terminated.
EN
7
C2
I
I
VSEL signal is primarily used to scale the output voltage and to set the TPS6235x operation
between active mode (VSEL=HIGH) and sleep mode (VSEL=LOW). The mode of operation can
also be adapted by I2C settings. This pin must not be left floating and must be terminated.
VSEL
5
D2
SDA
SCL
FB
3
4
6
8
C3
D3
D1
C1
I/O Serial interface address/data line
I
I
Serial interface clock line
Output feedback sense input. Connect FB to the converter output.
Analog ground
AGND
Input for synchronization to external clock signal. Synchronizes the converter switching frequency
to an external clock signal. This pin must not be left floating and must be terminated. Connecting
SYNC to static high or low state has no effect on the converter operation.
SYNC
N/A
B2
I
PGND
9
A1 B1
A2
Power ground. Connect to AGND underneath IC.
SW
10
I/O This is the switch pin of the converter and connected to the drain of the internal power MOSFETs.
N/A Internally connected to PGND.
PowerPAD™
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
SYNC
EN
PVIN
N-MOS Current Limit
Compator
_
V
Control
Logic
Registers
DAC
SDA
SCL
Soft-Start
REF
6-Bit
DAC
2
Power Save
Mode
I
C I/F
+
3 MHz
Oscillator + PLL
Comp Low
+
_
Switching
Logic
Sawtooth
Generator
REF
VSEL
EN Discharge
P-MOS Current Limit
Compator
ò
2R
Gate Driver
C
R
-
-
FB
+
+
-
-
SW
Anti
R
(DIS)
Shoot-Through
2C
-
+
+
+
+
+
P
EN Discharge
P
FB
Undervoltage
Lockout
Bias Supply
Comp Low
NOM
+
_
AVIN
A
V
O
Bandgap
V
= 0.4 V
REF
AGND
Thermal
PGND
Shutdown
PARAMETER MEASUREMENT INFORMATION
U1
PVIN
FB
V
I
AVIN
V
O
SW
C1
10 mF
L1
C2
10 mF
PGND
2.7 V .. 6 V
AGND
A
A
V
I
EN
VSEL
SDA
SCL
2
I C Bus
SYNC
List of Components:
U1 = TPS6235x
L1 = FDK MIPSA2520 Series
C1, C2 = TDK C1608X5R0G106MT
Note: The internal registers are set to their default values.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
vs Input voltage
3, 4, 5, 6
7
η
Efficiency
vs Output current
vs Input voltage
8, 9, 12
10, 11
13
DC output voltage
VO
vs Ambient temperature
vs DAC target output voltage
vs Input voltage
Measured output voltage
Quiescent current
14
IQ
15
ISD
Shutdown current
vs Input voltage
16
f(OSC)
Oscillator frequency
vs Input voltage
17
P-channel MOSFET rDS(on)
N-channel MOSFET rDS(on)
Inductor peak current
vs Input voltage
18
rDS(on)
IP
vs Input voltage
19
vs Ambient temperature
20
21, 22, 23, 24, 25, 26
27, 28, 29, 30, 31, 32
Load transient response
Line transient response
33
Combined line and load transient
response
34
PWM operation
35
36
Duty cycle jitter
Power-save mode operation
Dynamic voltage management
Output voltage ramp control
Start-up
37, 38
39, 40
41
42, 43
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
90
LPFM/PWM
LPFM/PWM
80
70
60
50
40
30
20
80
70
60
50
40
30
20
3-MHz PWM
FPFM/PWM
FPFM/PWM
V
= 3.6 V
V
= 3.6 V
I
I
V
= 1.35 V
V
= 1.05 V
O
O
L = 1 mH
= 10 mF
L = 1 mH
C = 10 mF
O
10
0
10
0
C
O
0.1
1
I
10
100
1000
0.1
1
I
10
100
1000
− Output Current − mA
− Output Current − mA
O
O
Figure 3.
Figure 4.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
90
V = 3.6 V
LPFM/PWM
I
V
= 1.35 V
O
C
= 10 mF
O
3-MHz PWM Mode
80
70
60
50
40
30
20
80
70
60
50
40
30
20
L = 2.2 mH
L = 1 mH
3-MHz PWM
FPFM/PWM
V
= 3.6 V
= 1.5 V
I
V
O
L = 1 mH
= 10 mF
10
10
0
C
O
0
0.1
1
I
10
100
1000
1
10
100
1000
− Output Current − mA
I
− Output Current − mA
O
O
Figure 5.
Figure 6.
EFFICIENCY
vs
INPUT VOLTAGE
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.373
1.363
100
90
I
= 500 mA
O
FPFM/PWM Mode
80
70
60
50
40
30
20
I
= 1 mA
1.353
1.343
1.333
1.323
O
I
= 10 mA
O
PWM Mode
I
= 100 mA
O
I
= 200 mA
O
V
V
= 3.6 V
L = 1 mH
C = 10 mF
O
I
L = 1 mH
= 10 mF
V
= 1.35 V
O
FPFM/PWM Mode
= 1.35 V
10
C
O
O
0
0.1
1
10
100
1000
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
I
− Output Current − mA
V − Input Voltage − V
I
O
Figure 7.
Figure 8.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.070
1.065
1.060
0.790
0.785
0.780
0.775
0.770
0.765
0.760
V
= 0.75 V
O
L = 1 mH
= 10 mF
I
= 100 mA
O
C
O
LPFM/PWM Mode
LPFM/PWM Mode
1.055
1.050
1.045
1.040
I
= 100 mA
O
PWM Mode
I
= 10 mA
O
0.755
0.750
0.745
V
V
= 3.6 V
L = 1 mH
= 10 mF
I
= 400 mA
I
O
1.035
1.030
C
0.740
0.735
= 1.05 V
O
O
0.1
1
10
100
1000
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
I
− Output Current − mA
V − Input Voltage − V
I
O
Figure 9.
Figure 10.
DC OUTPUT VOLTAGE
vs
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
INPUT VOLTAGE
1.525
1.520
1.515
1.510
0.930
0.925
0.920
0.915
V = 0.9 V
O
LPFM/PWM Mode
vs
LPFM Optimize Bit
V
= 1.5 V
O
L = 1 mH
= 10 mF
L = 1 mH
= 10 mF
C
I
= 100 mA
O
O
C
O
LPFM/PWM Mode
I
= 100 mA, bit = 1
O
I
= 10 mA, bit = 1
O
I
= 10 mA
1.505
1.500
1.495
1.490
0.910
0.905
0.900
0.895
O
I
= 100 mA
O
I
= 100 mA, bit = 0
O
I
= 400 mA
O
I
= 10 mA, bit = 0
O
1.485
1.480
0.890
0.885
I
= 400 mA, bit = 0
O
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 11.
Figure 12.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
MEASURED OUTPUT VOLTAGE
vs
DAC TARGET OUTPUT VOLTAGE
5
4
3
2
1.360
1.355
1.350
1.345
1.340
1.335
1.330
I
= 100 mA
O
L = 1 mH
= 10 mF
C
O
3-MHz PWM Mode
V
= 2.7 V
T
= 85oC
A
I
T
= 25oC
A
1
0
-1
-2
V
= 3.6 V
I
T
= -40oC
A
V
= 4.5 V
I
V
I
= 3.6 V
I
L = 1 mH
= 10 mF
= 100 mA
-3
-4
O
C
3 MHz PWM Mode
O
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 85
0.85 0.95 1.05
1.25 1.35 1.45
1.55
0.75
1.15
T
− Ambient Temperature − oC
V
− DAC Target Output Voltage − V
A
O
Figure 13.
Figure 14.
QUIESCENT CURRENT
vs
SHUTDOWN CURRENT
vs
INPUT VOLTAGE
INPUT VOLTAGE
50
45
40
10
V
= 1.05 V
O
LPFM Mode
9
8
7
6
5
4
3
2
T
= 25oC
= 85oC
A
T
A
T
= 85oC
A
T
= 25oC
A
35
30
T
= -30oC
A
T
= -40oC
A
25
20
EN = High
EN_DCDC bit = 0
1
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 15.
Figure 16.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
OSCILLATOR FREQUENCY
rDS(on) P-MOSFET
vs
INPUT VOLTAGE
vs
INPUT VOLTAGE
3.15
3.1
450
400
350
300
250
T
T
= -40oC
= 25oC
A
T
= 85oC
A
A
3.05
T
= 25oC
A
3
T
= 85oC
A
2.95
T
= -40oC
200
150
100
A
2.9
2.85
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 17.
Figure 18.
rDS(on) N-MOSFET
vs
INPUT VOLTAGE
INDUCTOR PEAK CURRENT
vs
AMBIENT TEMPERATURE
1.7
275
Closed Loop
V = 4.5 V
I
250
225
200
175
150
125
1.6
1.5
1.4
1.3
1.2
T
= 85oC
A
V = 3.6 V
I
T
= 25oC
A
V = 2.7 V
I
T
= -40oC
A
1.1
1
100
75
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 85
T
A
− Ambient Temperature − oC
V − Input Voltage − V
I
Figure 19.
Figure 20.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT: 50 mA / 400 mA / 50 mA
PWM OPERATION
LOAD TRANSIENT: 50 mA / 400 mA
PWM OPERATION
V = 3.6 V
I
V
= 1.35 V
O
L = 1 mH
= 10 mF
C
O
3-MHz PWM Mode
V = 3.6 V
I
V
= 1.35 V
O
L = 1 mH
= 10 mF
C
O
3-MHz PWM Mode
t − Time = 50 ms/div
t − Time = 5 ms/div
Figure 21.
Figure 22.
LOAD TRANSIENT: 400 mA / 50 mA
PWM OPERATION
LOAD TRANSIENT: 50 mA / 400 mA / 50 mA
FPFM/PWM OPERATION
V = 3.6 V
I
V
= 1.35 V
O
3-MHz PWM Mode
V = 3.6 V
I
L = 1 mH
L = 1 mH
V
= 1.35 V
C
= 10 mF
O
O
C
= 10 mF
O
FPFM/PWM Mode
t − Time = 50 ms/div
Figure 24.
t − Time = 5 ms/div
Figure 23.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT: 50 mA / 400 mA
FPFM/PWM OPERATION
LOAD TRANSIENT: 400 mA / 50 mA
FPFM/PWM OPERATION
V = 3.6 V
I
V
= 1.35 V
O
FPFM/PWM Mode
V = 3.6 V
I
L = 1 mH
= 10 mF
L = 1 mH
V
= 1.35 V
O
C
C
= 10 mF
O
O
FPFM/PWM Mode
t − Time = 10 ms/div
Figure 25.
t − Time = 10 ms/div
Figure 26.
LOAD TRANSIENT: 400 mA / 750 mA / 400 mA
PWM OPERATION
LOAD TRANSIENT: 400 mA / 750 mA
PWM OPERATION
V = 3.6 V
I
V
= 1.35 V
O
3-MHz PWM Mode
V = 3.6 V
I
L = 1 mH
L = 1 mH
V
= 1.35 V
C
= 10 mF
O
O
C
= 10 mF
O
3-MHz PWM Mode
t − Time = 5 ms/div
Figure 28.
t − Time = 50 ms/div
Figure 27.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT: 750 mA / 400 mA
PWM OPERATION
LOAD TRANSIENT: 1 mA / 100 mA / 1 mA
LFPM/PWM OPERATION
V = 3.6 V
I
V = 3.6 V
I
V
= 1.05 V
O
V
= 1.35 V
O
3-MHz PWM Mode
L = 1 mH
L = 1 mH
= 10 mF
C
= 10 mF
O
LPFM Mode
t − Time = 50 ms/div
C
O
t − Time = 5 ms/div
Figure 29.
Figure 30.
LOAD TRANSIENT: 1 mA / 100 mA
LPFM/PWM OPERATION
LOAD TRANSIENT: 100 mA / 1 mA
LPFM/PWM OPERATION
V = 3.6 V
V = 3.6 V
I
LPFM Mode
I
V
= 1.05 V
V
= 1.05 V
O
O
LPFM Mode
L = 1 mH
L = 1 mH
= 10 mF
C
= 10 mF
O
C
O
t − Time = 2 ms/div
t − Time = 2 ms/div
Figure 31.
Figure 32.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
COMBINED LINE/LOAD TRANSIENT
(3.6 V TO 4.2 V, 400 mA TO 800 mA)
PWM OPERATION
LINE TRANSIENT
PWM OPERATION
IO
I
= 50 mA
= 1.35 V
O
L = 1 mH
= 10 mF
500 mA/div
V
O
C
O
3-MHz PWM Mode
V
= 1.35 V
O
3 MHz PWM Mode
t − Time = 100 ms/div
t − Time = 10 ms/div
Figure 33.
Figure 34.
PWM OPERATION
DUTY CYCLE JITTER
V = 3.6 V, V = 1.35 V
I
O
V = 3.6 V, V = 1.35 V
I
= 200 mA
I
O
3-MHz PWM Mode
O
I
= 200 mA
O
L = 1 mH, C = 10 mF
O
L = 1 mH
= 10 mF
3-MHz PWM Mode
C
O
t − Time = 200 ns/div
t − Time = 50 ns/div
Figure 36.
Figure 35.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
POWER SAVE MODE OPERATION
POWER SAVE MODE OPERATION
V = 3.6 V
V = 3.6 V
L = 1 mH
I
L = 1 mH
= 10 mF
I
V
I
= 1.35 V
V = 1.05 V
O
C
= 10 mF
C
O
O
O
= 40 mA
I
= 1 mA
LPFM Mode
FPFM Mode
t − Time = 2.5 ms/div
Figure 37.
DYNAMIC VOLTAGE MANAGEMENT
O
O
t − Time = 40 ms/div
Figure 38.
DYNAMIC VOLTAGE MANAGEMENT
V = 3.6 V
I
V
= 1.05 V (LPFM) / 1.35 V (PWM)
O
V
= 1.35 V
V
= 1.35 V
O
O
V
= 1.05 V
O
V
= 1.05 V
O
PWM
PWM
FPFM
LPFM
V = 3.6 V
I
R
= 5 W
R
= 270 W
L
L
V
= 1.05 V (FPFM) / 1.35 V (PWM)
O
t − Time = 20 ms/div
t − Time = 50 ms/div
Figure 39.
Figure 40.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
RAMP CONTROL
START UP
V = 3.6 V
I
V
I
= 0.75 V / 1.5 V (PWM)
V = 3.6 V
I
O
= 0 mA
O
V
= 1.05 V (LPFM)
O
I
= 0 mA
V
= 1.5 V
O
O
Slew Rate = 4.5 mV/ms
V
= 0.75 V
O
t − Time = 50 ms/div
t − Time = 50 ms/div
Figure 41.
Figure 42.
START UP
V = 3.6 V
I
V
= 1.35 V (PWM)
O
R
= 5 W
L
t − Time = 50 ms/div
Figure 43.
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
DETAILED DESCRIPTION
Operation
The TPS6235x is a synchronous step-down converter typically operating with a 3-MHz fixed frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter operates in
power-save mode with pulse frequency modulation (PFM). The device integrates two power-save modes
optimized either for ultra-high efficiency at light load (light PFM) or for transient response when turning in PWM
operation (fast PFM). Both power-save modes automatically transition to PWM operation when the load current
increases.
The TPS6235x integrates an I2C compatible interface allowing transfers up to 3.4 Mbps. This communication
interface can be used for dynamic voltage scaling with voltage steps down to 12.5 mV, for reprogramming the
mode of operation (light PFM, fast PFM or forced PWM) or disable/enabling the output voltage for instance. For
more details, refer to the I2C interface and register description section.
During PWM operation, the converter uses a unique fast response, voltage mode, control scheme with input
voltage feed-forward. This achieves best-in-class load and line response and allows the use of tiny inductors
and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel
MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic
turns off the switch. The operating frequency is set to 3 MHz and can be synchronized on-the-fly to an external
oscillator or to a master dc/dc converter (refer to application examples).
The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the
inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up
conditions where the output voltage is low.
Power-Save Mode : Fast PFM
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintains high efficiency.
In fast PFM mode, the converter only operates when the output voltage trips below a set threshold voltage (VO
nominal). It ramps up the output voltage with several pulses and goes into power-save mode when the inductor
current reaches zero. As a consequence in power-save mode the average output voltage is slightly higher than
its nominal value in PWM mode. The fast PFM mode is optimized for fast response when transitioning between
pulse skipping and PWM operation.
PFM Mode at Light Load
PFM Ripple
Comp Low Threshold = V NOM
PWM Mode at Heavy Load
O
Figure 44. Operation in PFM Mode and Transfer to PWM Mode
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DETAILED DESCRIPTION (continued)
Power-Save Mode : Light PFM
With decreasing load current, the device can also automatically switch into light PFM pulse skipping operation in
which the power stage operates intermittently based on load demand. The advantage of the light PFM is much
lower IQ (28 µA) and drastically higher efficiency compared with fast PFM in low output loads.
In light PFM mode, the converter only operates when the output voltage trips below a set threshold voltage
(VOnominal). It ramps up the output voltage with one or several pulses and goes back into power-save mode. As
a consequence in power-save mode the average output voltage is slightly higher than its nominal value in PWM
mode.
In order to get a proper transition between light PFM and PWM operation, the output voltage ripple (in light PFM
mode) has been made proportional to the input voltage. It is possible to reduce the output voltage ripple by
setting the LIGHTPFM OPTIMIZE (VSEL0[6] or VSEL1[6]) bit low. However, this is only practical in applications
operating with a 1-µH (typical) inductor, with a load current less than VI / 25 Ω and which do not require the
auto-mode transition function.
When operating with a 2.2-µH (typical) inductor, the LIGHTPFM OPTIMIZE (VSEL0[6] or VSEL1[6]) bit should
always be set to low. In this case, the auto-mode transition is fully functional without any restriction on the load
current.
Mode Selection and Frequency Synchronization
The TPS6235x can be synchronized to an external clock signal by the SYNC pin. Pulling the SYNC pin to a
static state high or low state has no effect on the converter's operation.
Depending on the settings of CONTROL1 register the device can be operated in either the fixed frequency PWM
mode or in the automatic PWM and power-save mode. In this mode, the converter operates in fixed frequency
PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency
over a wide load current range. For more details, see the CONTROL1 register description.
The fixed frequency PWM mode has the tightest regulation and the best line/load transient performance.
Furthermore, this mode of operation allows simple filtering of the switching frequency for noise-sensitive
applications. In fixed frequency PWM mode, the efficiency is lower compared to the power-save mode during
light loads. It is possible to switch from power-save mode (light or fast PWM) to forced PWM mode during
operation either via the VSEL signal or by re-programming the CONTROL1 register. This allows adjustments to
the converters operation to match the specific system requirements leading to more efficient and flexible power
management.
When the synchronization is enabled (CONTROL2[5]=1), the mode is set to fixed-frequency operation and the
P-channel MOSFET turn on is synchronized to the falling edge of the external clock. This creates the ability for
multiple converters to be connected together in a master-slave configuration for frequency matching of the
converters (see the application section for more details).
When CONTROL1[1:0]=00 and VSEL signal is low, the converter operates according to MODE0 bit and the
synchronization is disabled regardless of EN_SYNC and HW_nSW bits.
Soft Start
The TPS6235x has an internal soft-start circuit that limits the inrush current during start-up. This prevents
possible input voltage drops when a battery or a high-impedance power source is connected to the input of the
converter. The soft start is implemented as a digital circuit increasing the switch current in steps of typically
350 mA, 675 mA, 1000 mA, and the typical switch current limit of 1350 mA. The current limit transitions to the
next step every 256 clocks (≈ 88µs). To be able to switch from 675 mA to 1000 mA current limit step, the output
voltage needs to be higher than 0.5 x VO(NOM) (otherwise the parts keeps operating at 675 mA current limit). This
mechanism is used to limit the output current under short circuit conditions. Therefore, the start-up time depends
on the output capacitor and load current.
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DETAILED DESCRIPTION (continued)
Enable
The device starts operation when EN pin is set high and starts up with the soft start. This signal is gated by the
EN_DCDC bit defined in register VSEL0 and VSEL1. On rising edge of the EN pin, all the registers are reset
with their default values. Enabling the converter's operation via the EN_DCDC bit does not affect internal
register settings. This allows the output voltage to be programmed to other values than the default voltage
before starting up the converter. For more details, see the VSEL0/1 register description.
Pulling the EN pin, VSEL0[6] bit or VSEL1[6] bit low forces the device into shutdown, with a shutdown current as
defined in the electrical characteristics table. In this mode, the P and N-channel MOSFETs are turned off, the
internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. When
an output voltage is present during shutdown mode, which is caused by an external voltage source or super
capacitor, the reverse leakage is specified under electrical characteristics. For proper operation, the EN pin must
be terminated and must not be left floating.
In addition, depending on the setting of CONTROL2[6] bit, the device can actively discharge the output capacitor
when it turns off. The integrated discharge resistor has a typical resistance of 15 Ω. The required time to
discharge the output capacitor at VO depends on load current and the output capacitance value.
Voltage and Mode Selection
The TPS6235x features a pin-selectable output voltage. VSEL is primarily used to scale the output voltage
between active (VSEL=HIGH) and sleep mode (VSEL=LOW). For maximum flexibility, it is possible to reprogram
the operating mode of the converter (e.g. fixed frequency PWM, fast PFM or light PFM) associated with VSEL
signal via the I2C interface
VSEL output voltage and mode selection is defined as following:
VSEL = LOW:DC/DC output voltage determined by VSEL0 register value. DC/DC mode of operation is
determined by MODE0 bit in CONTROL1 register
VSEL = HIGH:DC/DC output voltage determined by VSEL1 register value. DC/DC mode of operation is
determined by MODE1 bit in CONTROL1 register.
Undervoltage Lockout
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions.
Short-Circuit Protection
As soon as the output voltage falls below 50% of the nominal output voltage, the converter current limit is
reduced by 50% of the nominal value. Because the short-circuit protection is enabled during start-up, the device
does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal
output voltage. This needs to be considered when a load acting as a current sink is connected to the output of
the converter.
Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C typical, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature falls below 130°C typical again.
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THEORY OF OPERATION
Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS6235x device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps
in write mode). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.2 V (typical).
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred
to as HS-mode. The TPS6235x device supports 7-bit addressing; 10-bit addressing and general call address are
not supported.
The TPS6235x device has a 7-bit address with the 2 LSB bits factory programmable allowing up to four dc/dc
converters to be connected to the same bus. The 5 MSBs are 10010.
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, see Figure 45. All I2C-compatible devices should recognize
a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse, see Figure 46. All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge, see Figure 47, by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link
with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high, see Figure 45. This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address
Attempting to read data from register addresses not listed in this section results in FFh being read out.
H/S-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
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THEORY OF OPERATION (continued)
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start
conditions are used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
DATA
CLK
S
P
Start
Stop
Condition
Condition
Figure 45. START and STOP Conditions
DATA
CLK
Data Line
Change of Data Allowed
Stable;
Data Valid
Figure 46. Bit Transfer on the Serial Interface
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
START
Acknowledgement
Condition
Figure 47. Acknowledge on the I2C Bus
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THEORY OF OPERATION (continued)
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
1
2
7
8
9
1
2
3 − 8
9
S
or
Sr
Sr
or
P
ACK
ACK
Clock Line Held Low While
Interrupts are Serviced
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Figure 48. Bus Protocol
TPS6235x I2C Update Sequence
The TPS6235x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6235x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6235x. TPS6235x performs an
update on the falling edge of the LSB byte.
When the TPS6235x is in hardware shutdown (EN pin tied to ground) the device can not be updated via the I2C
interface. Conversely, the I2C interface is fully functional during software shutdown (EN_DCDC bit=0).
7
8
8
1
1
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A
P
“0” Write
A = Acknowledge
S = START condition
P = STOP condition
From Master to TPS6235x
From TPS6235x to Master
Figure 49. "Write" Data Transfer Format in F/S-Mode
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THEORY OF OPERATION (continued)
7
8
7
8
1
1
1
1
1
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
“1” Read
A
S
= Acknowledge
= START condition
FromMaster to TPS6235x
FromTPS6235x to Master
Sr = REPEATEDSTART condition
= STOPcondition
P
Figure 50. "Read" Data Transfer Format in F/S-Mode
F/S Mode
HS Mode
F/S Mode
HS-MASTER CODE
SLAVE ADDRESS
R/W
S
A
Sr
A
REGISTER ADDRESS
A
DATA
A/A
P
Data Transferred
”0” (write)
HS Mode Continues
Sr Slave Address
(n x Bytes + Acknowledge)
Figure 51. Data Transfer Format in H/S-Mode
Slave Address Byte
MSB
LSB
X
1
0
0
1
0
A1
A0
The slave address byte is the first byte received following the START condition from the master device. The first
five bits (MSBs) of the address are factory preset to 10010. The next two bits (A1, A0) of the address are device
option dependent. For example, TPS62350 is factory preset to 00 and TPS62351 is preset to 10. Up to 4
TPS62350 type of devices can be connected to the same I2C-Bus. See the ordering information table for more
details.
Register Address Byte
MSB
LSB
0
0
0
0
0
0
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS6235x,
which contains the address of the register to be accessed. The TPS6235x contains four 8-bit registers
accessible via a bidirectional I2C-bus interface. All internal registers have read and write access.
Table 1. Register Description
Name
Description
VSEL0 (read / write)
VSEL1 (read / write)
CONTROL1 (read / write)
CONTROL2 (read / write)
00
01
10
11
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Voltage Scaling Management
In order to reduce the power consumption of the processor core, the TPS6235x can scale its output voltage.
There are two different strategies: 1) by software or 2) by hardware. It can be selected by the HW_nSW bit
(more information of the control and value bit mentioned below is shown in the Register Description section).
Synchronized Scaling Hardware Strategy (HW_nSW = 1)
The application processor programs via I2C the output voltages associated with the two states of VSEL signal:
floor (VSEL0) and roof (VSEL1) values. The application processor also writes the DEFSLEW value in the
CONTROL2 register to control the output voltage ramp rate.
These two registers can be continuously updated via I2C to provide the appropriate output voltage according to
the VSEL input. The voltage changes with the selected ramp rate immediately after writing to the VSEL0 or
VSEL1 register.
In PFM mode, when the output voltage is programmed to a lower value by toggling VSEL signal from high to
low, PWROK is defined as low, while the output capacitor is discharged by the load until the converter starts
pulsing to maintain the voltage within regulation.
In multiple-step mode, PWROK is defined as low while the output voltage is ramping up or down. Under all other
operating conditions, PWROK is defined to be low when the output voltage is below -1.5% of the target value.
V
NOM
(ROOF)
V
NOM
(FLOOR)
Output Voltage Change Initiated
Comp Low Threshold: V
(ROOF)
NOM
PWROK
Figure 52. PWROK Operation (Transition to a Lower Voltage)
Table 2 shows the output voltage states depending on VSEL0, VSEL1 registers, and VSEL signal.
Table 2. Synchronized Scaling Hardware Strategy Overview (HW_nSW = 1)
VSEL PIN
Low
VSEL0 REGISTER
No action
VSEL1 REGISTER
No action
OUTPUT VOLTAGE
Floor
Low
Write new value
No action
No action
Change to new value
No change stays at floor voltage
Roof
Low
Write
High
No action
No action
High
Write new value
No action
No action
No change stays at roof voltage
Change to new value
High
Write new value
Direct Scaling Software Strategy (HW_nSW = 0)
The digital processor writes the output voltage needed directly to the register VSEL1 via I2C interface. The
application processor also writes the DEFSLEW value in the CONTROL2 register to control the output voltage
ramp rate.
The voltage changes with the selected ramp rate after setting the GO bit in CONTROL2 register. This bit is reset
when the output voltage has reached its target value. In this mode, the output voltage change is independent of
VSEL signal and VSEL0 register is not used.
In PFM mode, when the output voltage is programmed to a lower value, PWROK is defined as low while the
output capacitor is discharged by the load until the converter starts pulsing to maintain the voltage within
regulation.
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In multiple-step mode, PWROK is defined as low while the output voltage is ramping up or down. Under all other
operating conditions, PWROK is defined to be low when the output voltage is below -1.5% of the target value.
Voltage Ramp Control
The TPS6235x offers a voltage ramp rate control that can operate in two different modes:
•
•
Multiple-Step Mode
Single-Step Mode
The mode is selected via DEFSLEW control bits in the CONTROL2 register.
Single-Step Voltage Scaling Mode (default), DEFSLEW[2:0] = [111]
In single-step mode, the TPS6235x ramps the output voltage with maximum slew-rate when transitioning
between the floor and the roof voltages (switch to a higher voltage).
When switching between the roof and the floor voltages (transition to a lower voltage), the ramp rate control is
dependent on the mode selection (see CONTROL1 register) associated with the target register (Forced PWM,
Fast, or Light PFM).
Table 3 shows the ramp rate control when transitioning to a lower voltage with DEFSLEW set to immediate
transition.
Table 3. Ramp Rate Control vs. Target Mode
Mode Associated with
Target Voltage
HW_nSW
Output Voltage Ramp Rate
Forced PWM
Fast PFM
X
X
X
Immediate
Time to ramp down depends on output capacitance and load current
Time to ramp down depends on output capacitance and load current
Light PFM
For instance, when the output is programmed to transition to a lower voltage with Light or Fast PFM operation
enabled, the TPS6235x ramps down the output voltage without controlling the ramp rate or having intermediate
micro-steps. The required time to ramp down the voltage depends on the capacitance present at the output of
the TPS6235x and on the load current. From an overall system perspective, this is the most efficient way to
perform dynamic voltage scaling.
Multiple-Step Voltage Scaling Mode, DEFSLEW[2:0] = [000] to [110]
In multiple-step mode the TPS6235x controls the output voltage ramp rate regardless of the HW_nSW bit and of
the mode of operation (e.g. Forced PWM, Fast PFM, or Light PFM). The voltage ramp control is done by
adjusting the time between the voltage micro-steps.
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REGISTER DESCRIPTION
VSEL0 REGISTER (READ/WRITE)
MSB
LSB
0
Memory location: 00
Reset state: X1XX XXXX – See the Ordering
Information Table
7
6
5
4
3
2
1
VOLTAGE STEP MULTIPLIER, VSM0
6-bit unsigned binary linear coding.
Code effective from 0 to 63 decimal
LIGHTPFM OPTIMIZE
0 : LightPFM optimized for 2.2-mH inductor
1 : LightPFM optimized for 1-mH inductor (default)
This bit is internally mapped by VSEL1[6]. Writing a
value in VSEL0[6] automatically updates VSEL1[6].
EN_DCDC
This bit gates the external EN pin signal
0 : Device in shutdown regardless of EN signal
1 : Device enabled when EN pin tied high (default)
This bit is internally mapped by VSEL1[7]. Writing a
value in VSEL0[7] automatically updates VSEL1[7].
Output voltage = Minimum Output Voltage + (Voltage Step Multiplier 0 x 12.5 mV)
VSEL1 REGISTER (READ/WRITE)
MSB
7
LSB
0
Memory location: 01
Reset state: X1XX XXXX – See the Ordering
Information Table
6
5
4
3
2
1
VOLTAGE STEP MULTIPLIER, VSM1
6-bit unsigned binary linear coding.
Code effective from 0 to 63 decimal
LIGHTPFM OPTIMIZE
0 : LightPFM optimized for 2.2-mH inductor
1 : LightPFM optimized for 1-mH inductor (default)
This bit is internally mapped by VSEL0[6]. Writing a
value in VSEL1[6] automatically updates VSEL0[6].
EN_DCDC
This bit gates the external EN pin signal
0 : Device in shutdown regardless of EN signal
1 : Device enabled when EN pin tied high (default)
This bit is internally mapped by VSEL0[7]. Writing a
value in VSEL1[7] automatically updates VSEL0[7].
Output voltage = Minimum Output Voltage + (Voltage Step Multiplier 1 x 12.5 mV)
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CONTROL1 REGISTER (READ/WRITE)
MSB
LSB
0
Memory location: 02
Reset state: 0001 0000
7
6
5
4
3
2
1
MODE0
This bit defines the mode of operation for VSEL low
0 : Light PFM with auto. transition to PWM (default)
1 : Fast PFM with auto. transition to PWM
MODE1
This bit defines the mode of operation for VSEL high
0 : Forced PWM (default)
1 : Fast PFM with auto. transition to PWM
MODE_CTRL
00 : Operation follows MODE0, MODE1 (default)
01 : Light PFM with auto. transition to PWM (VSEL independent)
10 : Forced PWM (VSEL independent)
11 : Fast PFM with auto. transition to PWM (VSEL independent)
HW_nSW
0 : Output voltage controlled by software to the value defined
in VSEL1.
1 : Output voltage controlled by VSEL pin (default)
EN_SYNC
0 : Disable synchronization to external clock signal (default)
1 : Enable synchronization to external clock signal
RESERVED (00)
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CONTROL2 REGISTER (READ/WRITE)
MSB
LSB
Memory location: 03
Reset state: 0000 0111
7
6
5
4
3
2
1
0
DEFSLEW
DEFSLEW defines the output voltage ramp rate
000 : 0.15 mV/ms
001 : 0.3 mV/ms
010 : 0.6 mV/ms
011 : 1.2 mV/ms
100 : 2.4 mV/ms
101 : 4.8 mV/ms
110 : 9.6 mV/ms
111 : Immediate (default)
PLL_MULT
PLL_MULT defines the synchronization clock multiplier ratio
00 : x1 - f(SYNC) = 3 MHz 12ꢀ (default)
01 : x2 - f(SYNC) = 1.5 MHz 12ꢀ
10 : x3 - f(SYNC) = 1 MHz 12ꢀ
11 : x4 - f(SYNC) = 750 kHz 12ꢀ
PWROK (READ ONLY)
0 : Indicates that the output voltage is below its target regulation
voltage. This bit is zero if the converter is disabled.
1 : Indicates that the output voltage is within its nominal range
OUTPUT_DISCHARGE
0 : The dc/dc output capacitor is not actively discharged
when the converter is disabled (default).
1 : The dc/dc output capacitor is actively discharged when the
converter is disabled.
GO
This bit is only valid when HW_nSW = 0
0 : No change in the output voltage (default).
1 : The output voltage is changed with the ramp rate defined
in DEFSLEW.
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APPLICATION INFORMATION
Output Filter Design (Inductor and Output Capacitor)
The TPS6235x step-down converter has an internal loop compensation. Therefore, the external L-C filter must
be selected to work with the internal compensation.
The device has been designed to operate with inductance values between a minimum of 0.7 µH and maximum
of 6.2 µH. The internal compensation is optimized to operate with an output filter of L = 1 µH and CO = 10 µF.
Such an output filter has its corner frequency at:
1
1
ƒ +
+
+ 50.3 kHz
c
Ǹ
2p ǸL C
2p 1 mH 10 mF
O
(1)
Selecting a larger output capacitor value (e.g., 22 µF) is less critical because the corner frequency moves to
lower frequencies with fewer stability problems. The possible output filter combinations are listed in Table 4.
Regardless of the inductance value, operation is recommended with 10-µF output capacitor in applications with
di
ǒ Ǔ
dt
high-load transients
(e.g., ≥ 1600 mA/µs).
Table 4. Output Filter Combinations
INDUCTANCE (L)
OUTPUT CAPACITANCE (CO)
OUTPUT CAPACITANCE (CO)
FOR STABLE LOOP OPERATION
FOR OPTIMIZED TRANSIENT PERFORMANCE
1.0 µH
2.2 µH
≥ 10 µF (ceramic capacitor)
≥ 4.7 µF (ceramic capacitor)
≥ 10 µF (ceramic capacitor)
≥ 22 µF (ceramic capacitor)
The inductor value also has an impact on the pulse skipping operation. The transition into power-save mode
begins when the valley inductor current drops below a level set internally. Lower inductor values result in higher
ripple current which occurs at lower load currents. This results in a dip in efficiency at light load operations.
Inductor Selection
Even though the inductor does not influence the operating frequency, the inductor value has a direct effect on
the ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor
ripple current (∆IL) decreases with higher inductance and increases with higher VI or VO.
V
V * V
DI
O
I
O
L
DI
+
DI
+ I
)
L
L(MAX)
O(MAX)
2
V
L ƒ
sw
I
(2)
where:
fSW = switching frequency (3 MHz typical)
L = inductor value
∆IL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger
values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater
core losses, and lower output current capability.
The total losses of the coil consist of both the losses in the dc resistance (R(DC)) and the following
frequency-dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS62350 converters.
33
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
Table 5. List of Inductors
MANUFACTURER
SERIES
MIPSA2520
VLF3010AT
LPS3010
DIMENSIONS
FDK
TDK
2.5 × 2.0 × 1.2 = 6 mm3
2.8 × 2.6 × 1 = 7.28 mm3
3 × 3 × 1 = 9 mm3
Coilcraft
LPS3015
3 × 3 × 1.5 = 13.5 mm3
Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS6235x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance overtemperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of
the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
V * V
O
I
O
1
DV
+
) ESR , maximum for high V
ǒ
Ǔ
O
I
V
L ƒ
8 C ƒ
sw
sw
I
O
(3)
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the
output capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation
delays. The typical output voltage ripple is 2% of the nominal output voltage VO.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 10-µF capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part.
Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The output
capacitor must supply all of the load current during the time between the application of the load transient and the
turn on of the P-channel MOSFET. VO immediately shifts by an amount equal to ∆I(LOAD) × ESR, where ESR is
the effective series resistance of CO. ∆I(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value.
During this recovery time, VO is monitored for settling time, overshoot, or ringing that helps judge the converter
stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis must be performed over the input voltage
range, load current range, and temperature range.
34
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TPS62352, TPS62353, TPS62354
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
Layout Considerations
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6235x device demands careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground
path. Therefore, use wide and short traces for the main current paths as indicated in bold on Figure 53.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (FB) should be connected right to the output capacitor and routed away from
noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring
connected to the reference ground.
TPS6235x
L1
AVIN
PVIN
SYNC
EN
V
O
SW
FB
V
I
C2
C1
VSEL
SDA
SCL
AGND
PGND
Figure 53. Layout Diagram
Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS6235x device is 125°C. The thermal
resistance of the 12-pin CSP package (YZG) is RθJA = 110°C/W. Specified regulator operation is assured to a
maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 360 mW. More
power can be dissipated if the maximum ambient temperature of the application is lower or if the PowerPAD™
package (DRC) is used.
125oC - 85oC
T MAX - T
J
A
= 360 mW
=
P MAX =
110oC/W
D
R
qJA
(4)
35
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TPS62352, TPS62353, TPS62354
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SLVS540B–MAY 2006–REVISED DECEMBER 2006
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
CHIP SCALE PACKAGE
(TOP VIEW)
A3
B3
A2
B2
A1
B1
YMLLLLS
TPS6235x
D
C3
D3
C2
D2
C1
D1
A1
E
Code:
•
•
•
Y — 2 digit date code
LLLL - lot trace code
S - assembly site code
PACKAGE DIMENSIONS
The dimensions for the YZG package are shown in Table 6. See the package drawing at the end of this data
sheet.
Table 6. YZG Package Dimensions
Packaged Devices
D
E
TPS6235xYZG
2.23 ±0.05 mm
1.41 ±0.05 mm
36
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PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2007
PACKAGING INFORMATION
Orderable Device
TPS62350YZGR
TPS62350YZGT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DSBGA
YZG
12
3000 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
DSBGA
YZG
12
250 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TPS62351DRCR
TPS62351YZGR
PREVIEW
ACTIVE
SON
DRC
YZG
10
12
3000
TBD
Call TI
Call TI
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS62351YZGT
ACTIVE
DSBGA
YZG
12
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS62352DRCR
TPS62352YZGR
PREVIEW
ACTIVE
SON
DRC
YZG
10
12
3000
TBD
Call TI
Call TI
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS62352YZGT
TPS62353YZGR
TPS62353YZGT
TPS62354YZGR
TPS62354YZGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZG
YZG
YZG
YZG
YZG
12
12
12
12
12
250 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
3000 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2007
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
Reel
Diameter Width
(mm)
Reel
A0 (mm)
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
B0 (mm)
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
K0 (mm)
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
TPS62350YZGR
TPS62350YZGT
TPS62351YZGR
TPS62351YZGT
TPS62352YZGR
TPS62352YZGT
TPS62353YZGR
TPS62353YZGT
TPS62354YZGR
TPS62354YZGT
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
12 UNITIVE
177
8
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
PKGORN
T1TR-MS
P
177
177
177
177
177
177
177
177
177
8
8
8
8
8
8
8
8
8
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
PKGORN
T1TR-MS
P
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS62350YZGR
TPS62350YZGT
TPS62351YZGR
TPS62351YZGT
TPS62352YZGR
TPS62352YZGT
TPS62353YZGR
TPS62353YZGT
TPS62354YZGR
TPS62354YZGT
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
YZG
12
12
12
12
12
12
12
12
12
12
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
UNITIVE
187.0
187.0
187.0
187.0
187.0
187.0
195.2
195.2
195.2
195.2
187.0
187.0
187.0
187.0
187.0
187.0
193.7
193.7
193.7
193.7
25.6
25.6
25.6
25.6
25.6
25.6
34.9
34.9
34.9
34.9
Pack Materials-Page 3
D: 2.24 mm + 30 µm
E: 1.47 mm + 30 µm
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