TPS62400_14 [TI]
2.25MHz 400mA/600mA Dual Step-Down Converter In Small 3x3mm QFN Package;
| 型号： | TPS62400_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.25MHz 400mA/600mA Dual Step-Down Converter In Small 3x3mm QFN Package |
| 文件： | 总41页 (文件大小：1443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
www.ti.com
SLVSA67 –FEBRUARY 2010
2.25-MHz 400-mA/600-mA DUAL STEP-DOWN CONVERTER
Check for Samples: TPS62404-Q1
1
FEATURES
•
•
•
•
•
•
•
Qualified for Automotive Applications
•
•
•
•
•
EasyScale™ Optional One-Pin Serial Interface
High Efficiency—Up to 95%
Power Save Mode at Light Load Currents
180° Out of Phase Operation
VIN Range From 2.5 V to 6 V
2.25-MHz Fixed Frequency Operation
Output Current 400 mA and 600 mA
Adjustable Output Voltage From 0.6 V to VIN
Output Voltage Accuracy in PWM Mode ±1%
Typical 32-mA Quiescent Current for Both
Converters
•
•
100% Duty Cycle for Lowest Dropout
Available in a 10-Pin QFN (3mm×3mm)
Pin Selectable Output Voltage Supports
Simple Dynamic Voltage Scaling
DESCRIPTION
The TPS6240x device series are synchronous dual step-down DC-DC converters optimized for battery powered
portable applications. They provide two independent output voltage rails powered by 1-cell Li-Ion or 3-cell
NiMH/NiCD batteries. The devices are also suitable to operate from a standard 3.3-V or 5-V voltage rail.
With the EasyScale™ serial interface the output voltages can be modified during operation. The fixed output
voltage versions TPS62401, TPS62402, TPS62403, and TPS62404 support one pin controlled simple Dynamic
Voltage Scaling for low power processors.
The TPS6240x operates at 2.25-MHz fixed switching frequency and enters the power save mode operation at
light load currents to maintain high efficiency over the entire load current range. For low noise applications the
devices can be forced into fixed frequency PWM mode by pulling the MODE/DATA pin high. In the shutdown
mode, the current consumption is reduced to 1.2-mA, typical. The devices allow the use of small inductors and
capacitors to achieve a small solution size.
The TPS62400 is available in a 10-pin leadless package (3mm×3mm QFN)
100
TPS62404
VIN 2.5 V – 6 V
90
VIN
FB 1
2.2 mH
V
: 1.575 V
out1
400 mA
10 mF
80
70
60
50
40
30
20
10
0
SW1
V
OUT2
= 1.8 V
V
= 3.6 V
MODE/DATA = 0
DEF_1
IN
10 mF
EN_1
EN_2
V
OUT1
= 1.575 V
2.2 mH
V
: 3.3 V
out2
600 mA
SW2
MODE/
DATA
10 mF
ADJ2
GND
0.01
0.1
1
10
100
1000
I
OUT
mA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
SLVSA67 –FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PART
NUMBER
DEFAULT OUTPUT
OUTPUT
CURRENT
QFN
PACKAGE
PACKAGE
MARKING
TJ
ORDERING(2)
(1)
VOLTAGE
OUT1
OUT2
400mA
600mA
TPS62400
TPS62401
Adjustable
DRC
DRC
TPS62400QDRCQ1
PREVIEW
DEF_1 = High 1.1V
Fixed
default
OUT1
400mA
600mA
400mA
600mA
400mA
600mA
400mA
600mA
DEF_1 = Low 1.575V
Fixed default 1.8V
DEF_1 = High 1.8V
DEF_1 = Low 1.2V
Fixed default 3.3V
DEF_1 = High 1.1V
DEF_1 = Low 1.575V
Fixed default 2.8V
DEF_1 = High 1.9V
DEF_1 = Low 1.575V
Fixed default 3.3V
TPS62401QDRCQ1
TPS62402QDRCQ1
TPS62403QDRCQ1
TPS62404QDRCQ1
PREVIEW
OUT2
OUT1
Fixed
default
TPS62402
TPS62403
TPS62404
DRC
DRC
DRC
PREVIEW
PREVIEW
OET
–40°C to
125°C
OUT2
OUT1
OUT2
OUT1
OUT2
Fixed
default
Fixed
default
(1) Contact TI for other fixed output voltage options.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 7
UNIT
V
(2)
Input voltage range on VIN
Voltage range on EN, MODE/DATA, DEF_1
current into MODE/DATA
–0.3 to VIN +0.3, ≤ 7
≤ 0.5
V
mA
V
Voltage on SW1, SW2
–0.3 to 7
Voltage on ADJ2, FB1
–0.3 to VIN +0.3, ≤ 7
150
V
TJ(max)
Tstg
Maximum operating junction temperature
Storage temperature range
°C
°C
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE
RqJA
POWER RATING FOR TA ≤ 25°C
DERATING FACTOR ABOVE TA = 25°C
DRC
49°C/W
2050mW
21mW/°C
2
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Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
www.ti.com
SLVSA67 –FEBRUARY 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VIN
TJ
Supply voltage
2.5
0.6
-40
6
VIN
125
V
V
Output voltage range for adjustable voltage
Operating junction temperature
°C
ELECTRICAL CHARACTERISTICS
VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA = TJ = –40°C to 125°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
2.5
6.0
29
V
One converter, IOUT = 0mA. PFM mode
enabled (Mode = 0) device not switching,
EN1 = 1 OR EN2 = 1
19
32
mA
Two converter, IOUT = 0mA. PFM mode
enabled (Mode = 0) device not switching,
EN1 = 1 AND EN2 = 1
48
mA
IQ
Operating quiescent current
IOUT = 0mA, MODE/DATA = GND, for one
converter, VOUT 1.575V(1)
23
mA
IOUT = 0mA, MODE/DATA = VIN, for one
converter, VOUT 1.575V
3.6
mA
(1)
EN1, EN2 = GND, VIN = 3.6V(2)
1.2
0.1
3
1
ISD
Shutdown current
mA
EN1, EN2 = GND, VIN ramped from 0V to
3.6V(3)
Falling
Rising
1.5
2.35
2.4
VUVLO
Undervoltage lockout threshold
V
ENABLE EN1, EN2
VIH
High-level input voltage, EN1, EN2
1.2
0
VIN
0.4
1.0
V
V
VIL
Low-level input voltage, EN1, EN2
Input bias current, EN1, EN2
IIN
EN1, EN2 = GND or VIN
0.05
mA
DEF_1 INPUT
DEF_1 pin is a digital input at TPS62401
fixed output voltage option
VDEF_1H
VDEF_1L
DEF_1 high level input voltage
0.9
0
VIN
V
DEF_1 pin is a digital input at TPS62401
fixed output voltage option
DEF_1 low level input voltage
Input bias current DEF_1
0.4
1.0
V
IIN
DEF_1 GND or VIN
0.01
0.01
mA
MODE/DATA
VIH
VIL
High-level input voltage, MODE/DATA
Low-level input voltage, MODE/DATA
Input bias current, MODE/DATA
Acknowledge output voltage high
Acknowledge output voltage low
1.2
0
VIN
0.4
1.0
VIN
0.4
V
V
IIN
MODE/DATA = GND or VIN
mA
V
VOH
VOL
Open drain, via external pullup resistor
Open drain, sink current 500mA
0
V
INTERFACE TIMING
tStart
Start time
2
2
ms
ms
tH_LB
High time low bit, logic 0 detection
Signal level on MODE/DATA pin is > 1.2V
Signal level on MODE/DATA pin < 0.4V
200
400
2x
tH_LB
tL_LB
Low time low bit, logic 0 detection
ms
(1) Device is switching with no load on the output, L = 3.3mH, value includes losses of the coil
(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not
powered down.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid
until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
SLVSA67 –FEBRUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA = TJ = –40°C to 125°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tL_HB
tH_HB
TEOS
Low time high bit, logic 1 detection
Signal level on MODE/DATA pin < 0.4V
2
200
ms
2x
tL_HB
High time high bit, logic 1 detection
End of Stream
Signal level on MODE/DATA pin is > 1.2V
TEOS
400
ms
ms
2
Duration of acknowledge condition
(MODE/DATE line pulled low by the
device)
tACKN
VIN 2.5V to 6V
400
520
ms
tvalACK
ttimeout
POWER SWITCH
Acknowledge valid time
2
ms
ms
Timeout for entering power save mode MODE/DATA Pin changes from high to low
520
P-Channel MOSFET on-resistance,
Converter 1,2
RDS(ON)
ILK_PMOS
RDS(ON)
VIN = VGS = 3.6V
VDS = 6.0V
280
620
1
mΩ
mA
P-Channel leakage current
N-Channel MOSFET on-resistance
Converter 1,2
VIN = VGS = 3.6V
200
6
450
mΩ
Includes N-Chanel leakage current,
VIN = open, VSW = 6.0V, EN = GND(4)
ILK_SW1/SW2 Leakage current into SW1/SW2 pin
7.5
mA
OUTPUT 1
OUTPUT 2
0.68
0.85
0.8
1.0
150
20
0.92
1.15
Forward Current Limit
PMOS and NMOS
ILIMF
TSD
2.5V ≤ VIN ≤ 6.0V
A
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
°C
°C
Thermal shutdown hysteresis
Oscillator frequency
OSCILLATOR
fSW
2.5V ≤ VIN ≤ 6V
2.0
0.6
2.25
600
2.5
VIN
MHz
OUTPUT
VOUT
Adjustable output voltage range
Reference voltage
V
Vref
mV
Voltage positioning active,
MODE/DATA = GND,
1.01
VOUT
VOUT (PFM)
–1.5%
–1%
2.5%
1%
device operating in PFM mode,
(6) (7)
VIN = 2.5V to 5.0V
MODE/DATA = GND;
DC output voltage accuracy adjustable
and fixed output voltage(5)
device operating in PWM Mode,
0%
0%
VIN = 2.5V to 6.0V(7)
VIN = 2.5V to 6.0V, Mode/Data = VIN
Fixed PWM operation,
,
VOUT(PWM)
–1%
1%
0.5
0mA < IOUT1 < 400mA ; 0mA < IOUT2
<
600mA(8)
DC output voltage load regulation
Start-up time
PWM operation mode
Activation time to start switching(9)
%/A
ms
tStart up
tRamp
170
750
VOUT Ramp UP time
Time to ramp from 5% to 95% of VOUT
ms
(4) On pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND.
(5) Output voltage specification does not include tolerance of external voltage programming resistors
(6) Configuration L typ 2.2mH, COUT typ 20mF, see parameter measurement information, the output voltage ripple in PFM mode depends on
the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance.
(7) In Power Save Mode, PWM operation is typically entered at IPSM = VIN/32Ω.
(8) For VOUT > 2V, VIN min = VOUT +0.5V
(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) AND the other converter is already
enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or
EN2=1) a value of typ 80 ms for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps
VOUT
.
4
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
www.ti.com
SLVSA67 –FEBRUARY 2010
PIN ASSIGNMENTS
1
2
3
4
5
10
9
ADJ2
MODE/DATA
VIN
SW2
EN2
GND
EN1
SW1
8
7
FB1
6
DEF_1
Top view DRC package
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
(QFN)
NAME
Input to adjust output voltage of converter 2. In adjustable version (TPS62400) connect a external resistor
divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. At fixed output
voltage version (TPS62401) this pin MUST be directly connected to the output. If EasyScale Interface is
used for converter 2, this pin must be directly connected to the output, too.
ADJ2
1
I
This Pin has 2 functions:
1. Operation Mode selection: With low level, Power Save Mode is enabled where the device operates
in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN to
high forces the device to operate in PWM mode over the whole load range.
MODE/DATA
2
I/0
2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both
converters. The pin has an open drain output to provide an acknowledge condition if requested. The
current into the open drain output stage may not exceed 500mA. The interface is active if either EN1
or EN2 is high.
VIN
3
4
Supply voltage, connect to VBAT, 2.5V to 6V
Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward
capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions or
when the Interface is used, this pin is connected to an internal resistor divider network.
FB1
I
I
This pin defines the output voltage of converter 1. The pin acts either as analog input for output voltage
setting via external resistors (TPS62400), or digital input to select between two fixed default output
voltages (TPS62401, TPS62402, TPS62403, TPS62404).
For the TPS62400, an external resistor network needs to be connected to this pin to adjust the default
output voltage.
DEF_1
5
Using the fixed output voltage device options this pin selects between two fixed default output voltages,
see table ordering information
SW1
6
7
I/O
I
Switch Pin of Converter1. Connect to Inductor
Enable Input for Converter1, active high
GND for both converters; connect this pin to the PowerPAD™
Enable Input for Converter 2, active high
Switch Pin of Converter 2. Connect to Inductor.
Connect to GND
EN1
GND
8
EN2
9
I
SW2
10
I/O
PowerPAD™
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
SLVSA67 –FEBRUARY 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VIN
PMOS Current
Limit Comparator
Converter 1
VIN
FB_VOUT
Thermal
Shutdown
Softstart
VREF +1%
Skip Comp.
FB_VOUT
VREF- 1%
EN1
Skip Comp. Low
VREF
Gate Driver
Control
Stage
Ext. res. network
Error Amp.
Internal
compensated
FB
VOUT1
DEF1
Int. Resistor
Network
PWM
Comp.
SW1
Cff 25pF
MODE
Register
RI 1
Sawtooth
Generator
DEF1_High
GND
RI..N
DEF1_Low
FB1
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
Note 1
CLK 0°
Reference
Load Comparator
2.25MHz
Oscillator
Easy Scale
Interface
ACK
Mode/
DATA
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180°
MOSFET
Open drain
VIN
FB_VOUT
Converter 2
Int. Resistor
Network
VREF +1%
Skip Comp.
Register
FB_VOUT
VREF- 1%
DEF2
Note 2
Skip Comp. Low
VREF
Gate Driver
Control
Stage
Cff 25pF
Error Amp.
RI 1
Internal
compensated
PWM
Comp.
RI..N
SW2
MODE
FB_VOUT2
ADJ2
EN2
Sawtooth
Generator
GND
Thermal
Shutdown
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
CLK 180°
Softstart
Load Comparator
GND
(1) In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the
error amplifier
(2) To set the output voltage of Converter 2 via EasyScale™ Interface, ADJ2 pin must be directly connected to VOUT2
6
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Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
www.ti.com
SLVSA67 –FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION
TPS62400
VIN 2.5 V – 6 V
FB 1
SW1
VIN
L
1
V
C
OUT1
IN
2.2 mH
LSP4018
10 mF
R11
R12
COUT1 2x10 mF
GRM21BR61A106K
DEF_1
EN_1
EN_2
L
2
V
OUT2
SW2
2.2 mH
LSP4018
C
ff2
33 pF
R21
R22
COUT2 2x10 mF
GRM21BR61A106K
MODE/
DATA
ADJ2
GND
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS AND FIGURES
FIGURE NO.
Efficiency TPS62401 VOUT1 = 1.1V
Efficiency TPS62401 VOUT1 = 1.575V
Efficiency VOUT 2 = 1.8V
1
2
3
Efficiency TPS62400 VOUT2 = 3.3V
Efficiency TPS62402
4
5
Efficiency TPS62403
6
Efficiency
vs VIN
7,8
9
DC Output Accuracy VOUT1 = 1.1V
DC Output Accuracy VOUT2 = 3.3V
DC Output Accuracy VOUT2 = 1.8V
DC Output Accuracy VOUT1 1.575V, L = 2.2mH, COUT = 22mF
DC Output Accuracy VOUT1 1.575V, L = 3.3mH, COUT = 10mF
FOSC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
vs VIN
Iq for one converter
Iq for both converters, not switching
RDSON PMOS
vs VIN
vs VIN
RDSON NMOS
Light Load Output Voltage Ripple in Power Save Mode
Output Voltage Ripple in Forced PWM Mode
Output Voltage Ripple in PWM Mode
Forced PWM/ PFM Mode Transition
Load Transient Response PFM/PWM
Load Transient Response PWM Operation
Line Transient Response
Startup Timing One Converter
TPS62401 DEF1_pin Function for Output Voltage Selection
Copyright © 2010, Texas Instruments Incorporated
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TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
SLVSA67 –FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
FIGURE NO.
Typical Operation VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V
Typical Operation VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V
Typical Operation VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V
VOUT1 Change With EasyScale
28
29
30
31
32
33
34
35
36
37
38
39
40
Dynamic Voltage Positioning
Soft Start
EasyScale™ Protocol Overview
EasyScale Protocol Without Acknowledge
EasyScale Protocol Including Acknowledge
EasyScale – Bit Coding
MODE/DATA PIN: Mode Selection
MODE/DATA Pin: Power Save Mode / Interface Communication
Typical Application Circuit 1.5V / 2.85V Adjustable Outputs, low PFM
voltage ripple optimized
Typical Application Circuit 1.5V / 2.85V Adjustable Outputs
TPS62401 Fixed 1.575V/1.8 V Outputs, low PFM voltage ripple optimized
TPS62401 Fixed 1.1V/1.8 V Outputs, low PFM voltage ripple optimized
TPS62401 Fixed 1.575V/1.8 V Outputs
41
42
43
44
45
46
47
48
Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin
TPS62403 1.575V/2.8V Outputs
Layout Diagram
PCB Layout
EFFICIENCY TPS62401 VOUT1 = 1.1V
EFFICIENCY TPS62401 VOUT1 = 1.575V
100
100
90
80
70
60
50
40
30
20
10
0
V
= 1.1 V
V
= 1.575 V
OUT1
OUT1
90
80
70
60
V
= 2.7 V
IN
V
= 2.7 V
IN
V
= 2.7 V
V
= 2.7 V
IN
IN
V
= 3.6 V
V
= 3.6 V
IN
IN
V
= 3.6 V
V
= 3.6 V
50
IN
IN
= 5 V
V
= 5 V
V
= 5 V
IN
IN
V
= 5 V
V
IN
40
30
20
IN
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
10
0
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
I
mA
I
mA
OUT
OUT
Figure 1.
Figure 2.
8
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Product Folder Link(s) :TPS62404-Q1
TPS62400-Q1, TPS62401-Q1
TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
www.ti.com
SLVSA67 –FEBRUARY 2010
EFFICIENCY VOUT 2 = 1.8V
EFFICIENCY TPS62400 VOUT 2 = 3.3V
100
90
100
V
90
= 1.8 V
OUT2
V
= 3.3 V
OUT2
V
= 3.6 V
IN
V
= 3.6 V
80
70
60
80
70
60
IN
V
= 2.7 V
V
= 2.7 V
IN
IN
V
= 5 V
IN
V
= 3.6 V
V
= 3.6 V
V
= 5 V
IN
IN
IN
50
40
30
50
40
30
20
V
= 5 V
V
= 5 V
IN
IN
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
20
10
0
10
0
0.01
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
I
mA
OUT
I
OUT
mA
Figure 3.
Figure 4.
EFFICIENCY TPS62402 VOUT1/VOUT2
EFFICIENCY TPS62403 VOUT1/VOUT2
100
90
100
90
80
70
60
50
VI = 3.7 V
VI = 4.2 V
VO2 = 3.3 V
V
= 2.8 V
OUT2
V
= 3.3 V
IN
MODE/DATA = Low
V
= 3.6 V
IN
MODE/DATA = low
80
70
60
50
40
30
20
VI = 3.7 V
VI = 4.2 V
VO1 = 1.8 V
V
= 2.8 V
= 3.3 V
= 3.6 V
OUT2
V
IN
TPS62403
Efficiency V
VI = 3.7 V
VI = 4.2 V
V
MODE/DATA = Low
/V
,
IN
OUT1 OUT2
MODE/DATA = high
MODE/DATA = 0,
DEF_1 = 0
VO2 = 1.8 V
MODE/DATA = High
VI = 3.7 V
VI = 4.2 V
V
V
V
= 1.575 V
VO1 = 1.2 V
MODE/DATA = Low
OUT1
40
30
= 3.3 V
V
V
V
= 1.575 V
OUT1
= 3.3 V
IN
IN
VI = 3.7 V
VI = 4.2 V
= 3.6 V
IN
VO2 = 1.2 V
MODE/DATA = High
MODE/DATA = low
= 3.6 V
VI = 3.7 V
VI = 4.2 V
VO2 = 3.3 V
IN
MODE/DATA = high
20
10
0
MODE/DATA = High
10
0
0.01
0.1
1
10
- mA
100
1000
0.01
0.1
1
10
100
1000
I
OUT
I
- Output Current - mA
O
Figure 5.
Figure 6.
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EFFICIENCY vs VIN
EFFICIENCY vs VIN
= 100 mA
100
95
100
90
MODE/DATA = 0
= 3.3 V
I
MODE/DATA = 0
= 1.575 V
OUT
V
V
OUT
OUT
I
= 10 mA
OUT
90
I
= 10 mA
OUT
85
80
75
70
65
60
I
OUT
= 1 mA
80
I
= 1 mA
OUT
I
= 200 mA
OUT
70
60
50
55
50
2
3
4
5
6
3
4
5
6
V
- V
VIN - V
IN
Figure 7.
Figure 8.
DC OUTPUT ACCURACY VOUT2 = 3.3V
DC OUTPUT ACCURACY VOUT1 = 1.1V
3.400
3.350
1.150
1.125
V
= 3.3V
V
= 1.1 V
OUT2
OUT1
MODE/DATA = low, PFM Mode, voltage positioning active
= 4.2 V
MODE/DATA = low, PFM Mode, voltage positioning active
V
V
= 5 V
IN
IN
PWM Mode
Operation
PWM Mode
Operation
V
= 4.2 V
V
= 3.6 V
IN
IN
V
= 2.7 V
= 2.7 V
V
= 3.6 V
= 3.6 V
IN
IN
3.300
1.100
V = 5 V
IN
V
= 4.2 V
V
= 3.6 V
V
V
V = 4.2 V
IN
IN
IN
IN
IN
MODE/DATA = high, forced PWM Mode
MODE/DATA = high, forced PWM Mode
3.250
3.200
1.075
1.050
0.01
0.10
1
10
100
1000
0.01
0.10
1
10
100
1000
I
- mA
OUT
I
- mA
OUT
Figure 9.
Figure 10.
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DC OUTPUT ACCURACY VOUT1 = 1.575V,
L = 2.2mH, COUT = 22mF
DC OUTPUT ACCURACY VOUT2 = 1.8V
1.854
1.836
1.650
1.625
V
= 1.575 V
OUT1
V
= 1.8 V
OUT2
MODE/DATA = low, PFM Mode, voltage positioning active
MODE/DATA = low, PFM Mode, voltage positioning active
V
= 4.2 V
IN
PWM Mode
Operation
PWM Mode
Operation
1.600
1.575
1.550
1.818
V
= 5 V
V
= 3.6 V
V
= 4.2 V
IN
IN
IN
V
V
= 2.7 V
= 4.2 V
IN
V
= 3.6 V
IN
V
= 2.7 V
IN
1.800
1.782
V
= 5 V
V
= 3.6 V
V
= 4.2 V
IN
V
= 2.7 V
V
= 3.6 V
IN
V
= 2.7 V
IN
IN
IN
IN
IN
MODE/DATA = high, forced PWM Mode
MODE/DATA = high, forced PWM Mode
1.525
1.500
1.764
1.746
0.01
0.10
1
I
10
100
1000
0.01
0.10
1
10
100
1000
- mA
OUT
I
- mA
OUT
Figure 11.
Figure 12.
DC OUTPUT ACCURACY VOUT1 = 1.575V,
L = 3.3mH, COUT = 10mF
FOSC vs VIN
1.650
1.625
2.5
V
= 1.575 V
OUT1
2.45
MODE/DATA = low, PFM Mode, voltage positioning active
2.4
V
= 4.2 V
IN
2.35
2.3
PWM Mode
Operation
1.600
1.575
1.550
V
= 2.7 V
IN
V
= 3.6 V
IN
-40°C
2.25
2.2
V
= 3.6 V
V
= 4.2 V
IN
V
= 2.7 V
IN
IN
MODE/DATA = high, forced PWM Mode
25°C
85°C
2.15
2.1
1.525
1.500
2.05
2
0.01
0.10
1
I
10
100
1000
2.5
4.5
5.5
6
3
3.5
4
5
- mA
OUT
V
- V
IN
Figure 13.
Figure 14.
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Iq FOR ONE CONVERTER, NOT SWITCHING
Iq FOR BOTH CONVERTERS, NOT SWITCHING
24
23
42
40
38
36
34
32
85°C
25°C
22
21
85°C
25°C
20
19
-40°C
-40°C
18
17
30
28
2.5
3
3.5
4
4.5
- V
5
5.5
6
2.5
3
3.5
4
4.5
- V
5
5.5
6
V
IN
V
IN
Figure 15.
Figure 16.
RDSON NMOS vs VIN
RDSON PMOS vs VIN
0.55
0.5
0.3
0.25
0.45
0.4
0.2
85°C
0.35
0.3
85°C
25°C
0.15
25°C
-40°C
0.25
0.1
-40°C
0.2
0.05
0.15
2.5
3
3.5
4
4.5
- V
5
5.5
6
2.5
3
3.5
4
4.5
- V
5
5.5
6
V
V
IN
IN
Figure 17.
Figure 18.
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LIGHT LOAD OUTPUT VOLTAGE RIPPLE
IN POWER SAVE MODE
OUTPUT VOLTAGE RIPPLE
IN FORCED PWM MODE
Power Save Mode
Mode/Data = high,
forced PWM MODE operation
Mode/Data = low
IOUT = 10mA
IOUT = 10mA
VOUT = 1.8V 20mV/Div
VOUT = 1.8V 20mV/Div
Inductor current 100mA/Div
Inductor current 100mA/Div
Time base - 400 ns/Div
Time base - 10 ms/Div
Figure 19.
Figure 20.
OUTPUT VOLTAGE RIPPLE
IN PWM MODE
FORCED PWM/PFM MODE TRANSITION
PWM MODE OPERATION
MODE/DATA 1V/Div
Forced PWM
Mode
VOUT = 1.8V
IOUT = 400mA
VOUT ripple 20mV/Div
Enable Power Save Mode
Entering PFM Mode
Voltage positioning active
VOUT 20mV/Div
Inductor current 200mA/Div
VOUT = 1.8V
IOUT = 20mA
Time base - 200 ms/Div
Time base - 200 ns/Div
Figure 21.
Figure 22.
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LOAD TRANSIENT RESPONSE PFM/PWM
LOAD TRANSIENT RESPONSE PWM OPERATION
MODE/DATA = high
VOUT = 1.575V
50mV/Div
VOUT = 1.575V
50mV/Div
MODE/DATA = low
PWM Mode operation
Voltage positioning in PFM
PWM Mode operation
Mode reduces voltage drop
during load step
IOUT 200mA/Div
IOUT 200mA/Div
IOUT1 = 360mA
IOUT1 = 360mA
IOUT= 40mA
IOUT= 40mA
Time base - 50 ms/Div
Time base - 50 ms/Div
Figure 24.
Figure 23.
LINE TRANSIENT RESPONSE
STARTUP TIMING ONE CONVERTER
EN1 / EN2 5V/Div
VIN = 3.8V
VIN 3.6V to 4.6V
VIN 1V/Div
MODE/DATA = high
IOUT1 max = 400mA
VOUT1
500mV/Div
VOUT 1.575
IOUT 200mA
SW1 1V/Div
VOUT 50mV/Div
Icoil 500mA/Div
Time base - 400 ms/Div
Figure 25.
Time base - 200 ms/Div
Figure 26.
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SLVSA67 –FEBRUARY 2010
TPS62401DEF1_PIN FUNCTION FOR OUTPUT VOLTAGE
SELECTION
TYPICAL OPERATION VIN = 3.6V,
VOUT1 = 1.575V, VOUT2 = 1.8V
DEF_1 pin
2V/Div
VIN = 3.6V, MODE/DAT = low
IOUT1 = 40mA
SW1 5V/Div
VOUT1 = 1.575V
I
coil1 200mA/Div
VOUT1
VOUT1 = 1.1V
SW2 5V/Div
500mV/Div
Icoil2 200mA/Div
Icoil 500mA/Div
VIN 3.6V,
VOUT1: 1.575V
OUT2: 1.8V
IOUT1 = IOUT2 = 200mA
V
Time base - 100 ms/Div
Time base - 100 ns/Div
Figure 27.
Figure 28.
TYPICAL OPERATION VIN = 3.6V,
VOUT1 = 1.8V, VOUT2 = 3.0V
TYPICAL OPERATION VIN = 3.6V,
VOUT1 = 1.2V, VOUT2 = 1.2V
SW1 5V/Div
SW1 5V/Div
Icoil1 200mA/Div
I
coil1 200mA/Div
SW2 5V/Div
SW2 5V/Div
Icoil2 200mA/Div
VIN 3.6V,
OUT1: 1.2V
VIN 3.6V,
Icoil2 200mA/Div
V
VOUT1: 1.8V
VOUT2: 3.0V
VOUT2: 1.2V
IOUT1 = IOUT2 = 200mA
IOUT1 = IOUT2 = 200mA
Time base - 100 ns/Div
Figure 29.
Time base - 100 ns/Div
Figure 30.
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VOUT1 CHANGE WITH EASYSCALE
MODE/DATA
2V/Div
VOUT1: 1.5V
VOUT1: 200mV/Div
VIN 3.8V
ACKN = off
IOUT1 = 150mA
REG_DEF_1_Low
VOUT1: 1.1V
Time base - 100 ms/Div
Figure 31.
DETAILED DESCRIPTION
OPERATION
The TPS62400 includes two synchronous step-down converters. The converters operate with typically 2.25MHz
fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Safe Mode is
enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse
Frequency Modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input RMS current.
Converter 1
In the adjustable output voltage version TPS62400 the converter 1 default output voltage can be set via an
external resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can
be set in the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage
VOUT1. It feeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale™ serial Interface. This makes the
device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
In the fixed default output voltage version TPS62401, the DEF_1 Pin is configured as a digital input. The
converter 1 defaults to 1.1V or 1.575V depending on the level of DEF_1 pin. If DEF_1 is low the default is
1.575V; if high, the default is 1.1V. With the EasyScale™ interface, the output voltage for each DEF_1 Pin
condition (high or low) can be changed.
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Converter 2
In the adjustable output voltage version TPS62400, the converter 2 output voltage is set by an external resistor
divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF.
In fixed output voltage version TPS62401, the default output voltage is fixed to 1.8V. In this case, the ADJ2 pin
must be connected directly to the converter 2 output voltage VOUT2
.
It is also possible to change the output voltage of converter 2 via the EasyScale™ Interface. In this case, the
ADJ2 Pin must be directly connected to converter 2 output voltage VOUT2 and no external resistors may be
connected.
POWER SAVE MODE
The Power Save Mode is enabled with Mode/Data Pin set to low for both converters. If the load current of a
converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power
Save Mode of a converter is independent from the operating condition of the other converter. During Power Save
Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent
current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically
1.01×VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average inductor current is monitored. The device
changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1
for each converter.
Equation 1: Average output current threshold to enter PFM Mode
VIN
+
DCDC
I
OUT_PFM_enter
32 W
(1)
Equation 2: Average output current threshold to leave PFM Mode
VIN
+
DCDC
I
OUT_PFM_leave
24 W
(2)
In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single
threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip
comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of typ.
1ms and provides current to the load and the output capacitor. Therefore the output voltage will increase and the
device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied
by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device
starts switching again.
The Power Save Mode is left and PWM Mode entered in case the output current exceeds the current
IOUT_PFM_leave or if the output voltage falls below a second comparator threshold, called skip comparator low
(Skip Comp Low) threshold. This skip comparator low threshold is set to -2% below nominal Vout, and enables a
fast transition from Power Save Mode to PWM Mode during a load step.
In Power Save Mode the quiescent current is reduced typically to 19mA for one converter and 32mA for both
converters active. This single skip comparator threshold method in Power Save Mode results in a very low output
voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing
output capacitor values will minimize the output ripple. The Power Save Mode can be disabled through the
MODE/DATA pin set to high. Both converters will then operate in fixed PWM mode. Power Save Mode
Enable/Disable applies to both converters.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step,
and the voltage increase at a load throw-off. This improves load transient behavior.
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At light loads, in which the converter operates in PFM Mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a
load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Smooth
Fast load transient
increased load
+1%
PFM Mode
light load
PFM Mode
light load
V
OUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
COMP_LOW threshold -2%
Figure 32. Dynamic Voltage Positioning
Soft Start
The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 33.
EN
95%
5%
V
OUT
t
t
Startup
RAMP
Figure 33. Soft Start
100% Duty Cycle Low Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage,
and can be calculated as:
ǒRDSon
LǓ
Vin
+ Vout
) Iout
) R
max
max
max
min
(3)
with:
Ioutmax = maximum output current plus inductor ripple current
RDSonmax = maximum P-channel switch RDSon.
RL = DC resistance of the inductor
Voutmax = nominal output voltage plus maximum output voltage tolerance
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With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current, maintaining high efficiency.
Under-Voltage Lockout
The under-voltage lockout circuit prevents the device from malfunctioning at low input voltages, and from
excessive discharge of the battery, and disables the converters. The under-voltage lockout threshold is typically
1.5V; maximum of 2.35V. In case the default register values are overwritten by the Interface, the new values in
the registers REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage
does not fall below the under-voltage lockout threshold, independent of whether the converters are disabled.
MODE SELECTION
The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin interface
to receive serial data from a host to set the output voltage. This is described in the EasyScale™ Interface
section.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operates in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light
load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
In case the operation mode is changed from forced PWM mode (MODE/DATA = high) to Power Save Mode
Enable (MODE/DATA = 0), the Power Save Mode is enabled after a delay time of ttimeout , which is max. 520ms.
The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1.
ENABLE
The device has a separate EN pin for each converter to start up each converter independently. If EN1 and EN2
are set to high, the corresponding converter starts up with soft start as previously described.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically
1.2mA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is
switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.
DEF_1 PIN FUNCTION
The DEF_1 pin is dedicated to converter 1 and makes the output voltage selection very flexible to support
dynamic voltage management.
Depending on the device version, this pin works either as:
1. Analog input for adjustable output voltage setting (TPS62400):
–
Connecting an external resistor network to this pin adjusts the default output voltage to any value starting
from 0.6V to VIN
2. Digital input for fixed default output voltage selection (TPS62401):
–
In case this pin is tied to low level, the output voltage is set according to the value in register
REG_DEF_1_Low. The default voltage will be 1.575V. If tied to high level, the output voltage is set
according to the value in register REG_DEF_1_High. The default value in this case is 1.1V. Depending
on the level of Pin DEF_1, it selects between the two registers REG_DEF_1_Low and REG_DEF_1_High
for output voltage setting. Each register content (and therefore output voltage) can be changed
individually via the EasyScale™ interface. This makes the device very flexible in terms of output voltage
setting; see Table 4.
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180° OUT-OF-PHASE OPERATION
In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths
the input current. This feature reduces the surge current drawn from the supply.
SHORT-CIRCUIT PROTECTION
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it is turned off and the NMOS switch is turned on. The PMOS only turns
on again, once the current in the NMOS decreases below the NMOS current limit.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
EasyScale™: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
General
EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC
converters. The interface is based on a master – slave structure, where the master is typically a microcontroller
or application processor. Figure 34 and Table 3. give an overview of the protocol. The protocol consists of a
device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte
consists of five bits for information, two address bits, and the RFA bit. RFA bit set to high indicates the Request
For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale™ compared to other one pin interfaces is that its bit detection is in a large extent
independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to
160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires no additional pin.
Protocol
All bits are transmitted MSB first and LSB last. Figure 35 shows the protocol without acknowledge request (bit
RFA = 0), Figure 36 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
Mode/Data pin need be pulled high for at least tStart before the bit transmission starts with the falling edge. In
case the Mode/Data line was already at high level (forced PWM Mode selection), no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS
.
Addressable Registers
Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for
each register are available. Table 1 shows the addressable registers to set the output voltage when DEF_1 pin
works as digital input. In this case, converter 1 has a related register for each DEF_1 Pin condition, and one
register for converter 2. With a high/low condition on pin DEF_1 (TPS62401) either the content of register
REG_DEF_1_high/REG_DEF1_low is selected. The output voltage of converter 1 is set according to the values
in Table 4.
Table 2 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In
this case one register is available for each converter. The output voltage of converter 1 is set according to the
values in Table 5. For converter 2, the available voltages are shown in Table 6. To generate these output
voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board
space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is
enabled (EN1 or EN2 is high). After the startup-time tStart (170ms) the interface is ready for data reception.
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Table 1. Addressable Registers for default Fixed Output Voltage Options (PIN DEF_1 = digital input)
DEVICE
REGISTER
DESCRIPTION
DEF_1
PIN
A1
A0
D4
D3
D2
D1
D0
REG_DEF_1_High Converter 1 output voltage setting for
DEF_1 = High condition. The content of
High
0
1
Output voltage setting, see
Table 4
the register is active with DEF1_ Pin high.
TPS62401,
TPS62402,
TPS62403,
TPS62404
REG_DEF_1_Low Converter 1 output voltage setting for
DEF_1 = Low condition.
Low
0
1
1
0
0
1
Output voltage setting, see
Table 4
REG_DEF_2
Converter 2 output voltage
Not
applicable
Output voltage setting, see
Table 6
Don’t use
Table 2. Addressable Registers for Adjustable Output Voltage Options (PIN DEF_1 = analog input)
DEVICE
REGISTER
REG_DEF_1_High
REG_DEF_1_Low
REG_DEF_2
DESCRIPTION
A1 A0
D4
D3 D2 D1
D0
not available
Converter 1 output voltage setting
Converter 2 output voltage
Don’t’ use
0
1
1
0
0
1
see Table 5
see Table 6
TPS62400
Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can
be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 34
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 34
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between tLow and tHigh a 0 or 1 is detected.
Acknowledge
The Acknowledge condition is only applied if:
•
•
•
Acknowledge is requested by a set RFA bit
The transmitted device address matches with the device address of the device
16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is 520ms maximum . The Acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was
detected. The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address, or not-correctly-received protocol, no-acknowledge condition is applied;
thus, the internal MOSFET is not turned on and the external pullup resistor pulls MODE/DATA pin high after
tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
NOTE
The acknowledge condition may only be requested in case the master device has an open
drain output.
In case of a push-pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the
current to 500 mA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
MODE Selection
Because the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to
determine when it has to decode the bit stream or to change the operation mode.
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The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device also stays in forced PWM mode during the entire protocol reception time.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at
least ttimeout, the device gets an internal timeout and Power Save Mode operation is enabled.
A protocol sent within this time is ignored because the falling edge for the Mode change is first interpreted as
start of the first bit. In this case it is recommended to send the protocol first, and then change at the end of the
protocol to Power Save Mode.
DATA IN
Device Address
DATABYTE
D4 D3 D2
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
RFA A1
A0
D1 D0
EOS Start
EOS
0
1
0
0
1
1
1
0
DATA OUT ACK
Figure 34. EasyScale™ Protocol Overview
Table 3. EasyScale™ Bit Description
BYTE
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
DESCRIPTION
Device
Address
Byte
7
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
RFA
A1
IN
IN
IN
IN
IN
IN
IN
IN
IN
0 MSB device address
6
1
5
0
4
0
4Ehex
3
1
2
1
1
1
0
0 LSB device address
Databyte
7(MSB)
Request For Acknowledge, if high, Acknowledge condition will applied by the device
6
Address Bit 1
Address Bit 0
Data Bit 4
5
A0
4
D4
3
D3
Data Bit 3
2
1
D2
Data Bit 2
D1
Data Bit 1
0(LSB)
D0
Data Bit 0
ACK
OUT
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open drain output, Line needs to be pulled high by the host with a pullup
resistor.
This feature can only be used if the master has an open drain output stage. In case
of a push pull output stage Acknowledge condition may not be requested!
tStart
tStart
Address Byte
DATA Byte
DATA IN
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
D0
1
TEOS
TEOS
0
Figure 35. EasyScale™ Protocol Without Acknowledge
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tStart
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DATA IN
DA7
DA0
0
D0
1
RFA
1
0
TEOS
tvalACK
Acknowledge
true, Data Line
ACKN
tACKN
pulled down by
device
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
Acknowledge
false, no pull
down
Figure 36. EasyScale™ Protocol Including Acknowledge
t
t
t
t
Low
Low
High
High
Low Bit
High Bit
(Logic 1)
(Logic 0)
Figure 37. EasyScale™ – Bit Coding
MODE/DATA
t
timeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 38. MODE/DATA PIN: Mode Selection
t
t
Address Byte
Start DATA Byte
Start
MODE/DATA
T
EOS
t
T
EOS
timeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 39. MODE/DATA Pin: Power Save Mode/Interface Communication
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Table 4. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input (TPS62401)
TPS62401 OUTPUT
TPS62401 OUTPUT
VOLTAGE [V]
D4 D3 D2 D1 D0
VOLTAGE [V]
REGISTER REG_DEF_1_LOW
REGISTER REG_DEF_1_HIGH
0
1
2
3
4
5
6
7
8
0.8
0.825
0.85
0.875
0.9
0.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.925
0.95
0.975
1.0
0.925
0.95
0.975
1.0
1.025
1.050
1.075
1.1(default TPS62401,
TPS62403)
9
1.025
1.125
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.050
1.150
1.075
1.175
1.1
1.2
1.125
1.225
1.150
1.25
1.175
1.275
1.2 (default TPS62402)
1.3
1.225
1.25
1.325
1.350
1.275
1.3
1.375
1.4
1.325
1.350
1.375
1.4
1.425
1.450
1.475
1.5
1.425
1.450
1.475
1.5
1.525
1.55
1.575
1.6
1.525
1.55
1.7
1.8 (default TPS62402)
1.9 (default TPS624024)
1.575 (default TPS62401,
TPS62403, TPS62404)
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Table 5. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input (Adjustable, TPS62400)
TPS62400 OUTPUT VOLTAGE [V]
REGISTER REG_DEF_1_LOW
D4 D3 D2 D1 D0
0
VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default
TPS62400)
0
0
0
0
0
0.6V with DEF_1 connected to VOUT1 (default TPS62400)
1
0.825
0.85
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
0.875
0.9
4
5
0.925
0.95
6
7
0.975
1.0
8
9
1.025
1.050
1.075
1.1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.125
1.150
1.175
1.2
1.225
1.25
1.275
1.3
1.325
1.350
1.375
1.4
1.425
1.450
1.475
1.5
1.525
1.55
1.575
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Table 6. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT
)
OUTPUT VOLTAGE [V]
D4 D3 D2 D1 D0
FOR REGISTER REG_DEF_2
0
VOUT2 Adjustable with resistor network and Cff on ADJ2 pin
(default TPS62400)
0
0
0
0
0
0.6V with ADJ2 pin directly connected to VOUT2 (default
TPS62400)
1
0.85
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
0.9
3
0.95
4
1.0
5
1.05
6
1.1
7
1.15
8
1.2
9
1.25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.7
1.8 (default TPS62401)
1.85
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8 (default TPS62403)
2.85
3.0
3.3 (default TPS62402, TPS62404)
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APPLICATION INFORMATION
OUTPUT VOLTAGE SETTING
Converter1 Adjustable Default Output Voltage Setting: TPS62400
The output voltage can be calculated to:
R
11
ǒ1 ) Ǔwith an internal reference voltage V
V
+ V
typical 0.6V
OUT
REF
REF
R
12
(4)
To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ.
The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to
choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor
or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feedforward capacitor is
not necessary.
Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404).
The output voltage VOUT1 is selected with DEF_1 pin.
Pin DEF_1 = low:
TPS62401, TPS62403, TPS62404 = 1.575V
TPS62402 = 1.2V
Pin DEF_1 = high:
TPS62401, TPS62403 = 1.1V
TPS62402: = 1.8V
TPS62404: = 1.9V
Converter 2 Adjustable Default Output Voltage Setting TPS62400:
The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same
recommendations apply as for converter1. In addition to that, a 33pF feedforward Capacitor Cff2 for good load
transient response should be used. The output voltage can be calculated to:
R
21
ǒ1 ) Ǔwith an internal reference voltage V
V
+ V
typical 0.6V
OUT
REF
REF
R
22
(5)
Converter 2 Fixed Default Output Voltage Setting
ADJ2 pin must be directly connected with VOUT2
TPS62401, VOUT2 default = 1.8V
TPS62403, VOUT2 default = 2.8V
TPS62402, VOUT2 default = 3.3V
TPS62404, VOUT2 default = 3.3V
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TPS62400
VIN 3.3 V – 6 V
FB 1
SW1
VIN
L
1
V
= 1.5 V
OUT1
C
IN
2.2 mH
I
up to 400 mA
R11
270 kW
OUT1
10 mF
DEF_1
C
22 mF
OUT1
R12
180 kW
EN_1
EN_2
L
2
V
= 2.85 V
OUT2
SW2
I
up to 600 mA
3.3 mH
OUT2
MODE/
DATA
C
ff2
33 pF
R21
825 kW
ADJ2
GND
C
22 mF
OUT2
R22
220 kW
Figure 40. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage Ripple Optimized
TPS62400
VIN 3.3 V – 6 V
FB 1
VIN
L
1
V
= 1.5 V
OUT1
C
SW1
IN
I
up to 400 mA
2.2 mH
OUT1
R11
270 kW
10 mF
C
10 mF
OUT1
DEF_1
R12
180 kW
EN_1
EN_2
L
2
V
= 2.85
OUT2
SW2
I
up to 600 mA
3.3 mH
OUT2
C
R21
825 kW
ff2
33 pF
MODE/
DATA
C
10 mF
OUT2
ADJ2
GND
R22
220 kW
Figure 41. Typical Application Circuit 1.5V/2.85V Adjustable Outputs
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SLVSA67 –FEBRUARY 2010
TPS62401
VIN 2.5 V – 6 V
FB 1
SW1
VIN
2.2 mH
V
= 1.575 V
OUT1
400 mA
10 mF
22 mF
DEF_1
EN_1
EN_2
2.2 mH
V
= 1.8 V
OUT2
600 mA
SW2
MODE/
DATA
22 mF
ADJ2
GND
Figure 42. TPS62401 Fixed 1.575V/1.8V Outputs, low PFM Voltage Ripple Optimized
TPS62401
VIN 2.5 V – 6 V
FB 1
SW1
VIN
2.2 mH
V
= 1.1 V
OUT1
400 mA
10 mF
DEF_1
EN_1
22 mF
EN_2
2.2 mH
V
= 1.8 V
OUT2
600 mA
SW2
MODE/
DATA
22 mF
ADJ2
GND
Figure 43. TPS62401 Fixed 1.1V/1.8V Outputs, low PFM Ripple Voltage Optimized
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TPS62401
VIN 2.5 V – 6 V
FB 1
SW1
VIN
2.2 mH
V
= 1.575 V
OUT1
400 mA
10 mF
10 mF
DEF_1
EN_1
EN_2
2.2 mH
V
= 1.8 V
OUT2
600 mA
SW2
MODE/
DATA
10 mF
ADJ2
GND
Figure 44. TPS62401 Fixed 1.575V/1.8V Outputs
TPS62401/03
VIN 2.5 V – 6 V
10 µF
Processor
VIN
FB 1
SW1
L1
Vout 1 400 mA:
V
V
Core
DEF_1 = 0: 1.575 V
DEF_1 = 1: 1.1V
10 µF
EN_1
DEF_1
SW2
Core_Sel
L2
Vout 2 600 mA:
EN_2
V
I/O
TPS62401 : 1.8 V
TPS62403 : 2.8 V
10 µF
MODE /
DATA
ADJ2
GND
Figure 45. Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin
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TPS62404-Q1
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SLVSA67 –FEBRUARY 2010
TPS62403
VIN 2.5 V – 6 V
VIN
FB 1
SW 1
2.2 µH
Vout 1: 1.575 V
400 mA
10 mF
10 µF
DEF _1
EN _1
EN _2
3.3 µH
Vout 2: 2.8 V
600 mA
SW 2
10 µF
MODE/
DATA
ADJ 2
GND
Figure 46. TPS62403 1.575V/2.8V Outputs
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The converters are designed to operate with a minimum inductance of 1.75mH and minimum capacitance of 6mF.
The device is optimized to operate with inductors of 2.2mH to 4.7mH and output capacitors of 10mF to 22mF.
Inductor selection
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance
should be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
Vout
Vin
1 *
DI + Vout
L
L ƒ
(6)
DI
L
I
+ I
)
outmax
Lmax
2
(7)
with:
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Take into consideration that the core material from inductor to inductor differs and this
difference has an impact on the efficiency.
Refer to Table 7 and the typical application circuit examples for possible inductors.
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TPS62402-Q1, TPS62403-Q1
TPS62404-Q1
SLVSA67 –FEBRUARY 2010
www.ti.com
Table 7. List of Inductors
DIMENSIONS [mm3]
INDUCTOR TYPE
MIPW3226
LPS3010
SUPPLIER
FDK
3.2×2.6×1.0
3×3×0.9
Coilcraft
TDK
2.8×2.6×1.0
2.8x2.6×1.4
3×3×1.4
VLF3010
VLF3014
TDK
LPS3015
Coilcraft
Coilcraft
3.9×3.9×1.7
LPS4018
Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic
capacitors with a typical value of 10mF to 22mF, without having large output voltage under and overshoots during
heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are
therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors are not recommended due to their wide variation in capacitance.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as:
Vout
Vin
L ƒ
1 *
1
I
+ Vout
RMSCout
Ǹ
2 3
(8)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and
discharging the output capacitor:
Vout
Vin
L ƒ
1 *
1
ǒ
) ESRǓ
DVout + Vout
8 Cout ƒ
(9)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Higher output capacitors like 22mF values minimize the voltage ripple in PFM Mode and tighten DC
output accuracy in PFM Mode.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interference with other
circuits in the system. An input capacitor of 10mF is sufficient.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI problems. It is critical to provide a low-inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths as indicated in bold in Figure 47.
The input capacitor should be placed as close as possible to the IC pins VIN and GND, the inductor and output
capacitor as close as possible to the pins SW1 and GND.
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TPS62404-Q1
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SLVSA67 –FEBRUARY 2010
Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each
converter use a common Power GND node and a different node for the signal GND to minimize the effects of
ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the
common path to the GND PIN, which returns the small signal components and the high current of the output
capacitors, as short as possible to avoid ground noise. The output voltage sense lines (FB 1, DEF_1, ADJ2)
should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW1
and SW2 lines). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace
must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring
between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
TPS62400
VIN 3 V – 6 V
VIN
EN_1
C
IN
EN_2
10 mF
MODE/
DATA
FB 1
L
L
2
1
SW2
SW1
3.3 mH
3.3 mH
C
ff2
33 pF
R21
R22
R11
R12
C
C
OUT2
OUT1
DEF_1
ADJ2
PowerPAD
GND
Figure 47. Layout Diagram
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TPS62404-Q1
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www.ti.com
C
OUT1
CIN
GND Pin
connected
with Power
Pad
COUT2
Figure 48. PCB Layout
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS62404QDRCRQ1
ACTIVE
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62404QDRCRQ1
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRC 10
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS62404QDRCRQ1
3000
Pack Materials-Page 2
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