TPS62405-Q1 [TI]
具有单总线接口的汽车类、双通道固、定输出电压、400mA 和 600mA、2.25MHz 降压转换器;
| 型号： | TPS62405-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单总线接口的汽车类、双通道固、定输出电压、400mA 和 600mA、2.25MHz 降压转换器 转换器 |
| 文件： | 总44页 (文件大小：1592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
TPS6240x-Q1 2.25-MHz 400-mA and 600-mA Dual Step-Down Converter
1 Features
3 Description
The TPS6240x-Q1 family of devices are synchronous
dual step-down DC-DC converters optimized for
battery-powered portable applications and automotive
systems. They provide two independent output
voltage rails powered by rechargeable batteries or
standard 3.3-V or 5-V voltage rail.
1
•
Qualified for automotive applications
•
AEC-Q100 qualified with the following results:
–
Device temperature grade 1: –40°C to 125°C
operating junction temperature range
–
–
Device HBM ESD classification level H2
Device CDM ESD classification level C4B
The EasyScale™ serial interface allows output-
voltages modification during operation. The fixed-
output-voltage versions, TPS62402-Q1,
TPS62404-Q1, and TPS62405-Q1 support one-pin-
controlled simple dynamic voltage scaling for low-
power processors.
•
•
•
•
•
•
High efficiency—up to 95%
VIN Range from 2.5 V to 6 V
2.25-MHz Fixed-frequency operation
Output current 400 mA and 600 mA
Adjustable output voltage from 0.6 V to VIN
The TPS6240x-Q1 operates at 2.25-MHz fixed
switching frequency and enters the power-save mode
operation at light load currents to maintain high
efficiency over the entire load-current range. For low-
noise applications, one can force the devices into
fixed-frequency PWM mode by pulling the
MODE/DATA pin high. The shutdown mode reduces
the current consumption to 1.2-μA, typical. The
devices allow the use of small inductors and
capacitors to achieve a small solution size.
Pin selectable output voltage supports simple
dynamic voltage scaling
•
•
•
•
•
EasyScale™ optional one-pin serial interface
Power-save mode at light load currents
180° Out-of-phase operation
Output-voltage accuracy in PWM mode ±1%
Typical 32-μA quiescent current for both
converters
(1)
Device Information
•
100% Duty cycle for lowest dropout
PART NUMBER
TPS62400-Q1
TPS62402-Q1
TPS62404-Q1
TPS62405-Q1
PACKAGE
BODY SIZE (NOM)
2 Applications
•
•
Infotainment and cluster
ADAS
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
TPS62402-Q1
TPS62402-Q1 Efficiency versus Output Current,
VOUT1 and VOUT2
100
VIN 2.5 V to 6 V
FB1
VIN
VIN = 3.7 V
2.2 µH
VOUT1 = 1.2 V
400 mA
VIN = 4.2 V
SW1
10 µF
90
VOUT2 = 3.3 V
MODE/DATA = Low
80
10 µF
DEF_1
70
60
EN1
EN2
VIN = 3.7 V
50
VIN = 4.2 V
2.2 µH
VOUT1 = 1.2 V
VOUT2 = 3.3 V
600 mA
40
MODE/DATA = Low
SW2
VIN = 3.7 V
VIN = 4.2 V
30
VOUT2 = 1.2 V
VIN = 3.7 V
MODE/
DATA
MODE/DATA = High
VIN = 4.2 V
10 µF
20
V
OUT2 = 3.3 V
ADJ2
GND
MODE/DATA = High
10
0
0.01
0.1
1
10
100
1000
Output Current (mA)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Table of Contents
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 14
9.5 Programming........................................................... 16
10 Application and Implementation........................ 23
10.1 Application Information.......................................... 23
10.2 Typical Application ............................................... 23
10.3 System Examples ................................................ 31
11 Power Supply Recommendations ..................... 33
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 Layout Example .................................................... 34
13 Device and Documentation Support ................. 35
13.1 Device Support...................................................... 35
13.2 Related Links ........................................................ 35
13.3 Support Resources ............................................... 35
13.4 Trademarks........................................................... 35
13.5 Electrostatic Discharge Caution............................ 35
13.6 Glossary................................................................ 35
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements ............................................... 8
7.7 Switching Characteristics.......................................... 8
7.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2015) to Revision F
Page
•
Changed TPS62404-Q1, OUT1 from DEF_1 = Low 1.575 V to DEF_1 = Low 1.2 V............................................................ 4
Changes from Revision D (October 2014) to Revision E
Page
•
•
Changed the Handling Ratings table to the ESD Ratings table and move storage temperature to the Absolute
Maximum Ratings table ......................................................................................................................................................... 6
Changed test conditions and MIN, TYP, and MAX values for the TPS62405-Q1 oscillator frequency in the Switching
Characteristics table .............................................................................................................................................................. 8
Changes from Revision C (October 2014) to Revision D
Page
•
Changed oscillator specification from 1.6 MHz to 2 MHz minimum switching frequency and to 1.7 MHz for VIN≤ 3 V......... 8
Changes from Revision B (May 2013) to Revision C
Page
•
•
•
•
Changed the data sheet to meet the new TI standard format................................................................................................ 1
Changed the VDEF_1H and VDEF_1L Test Conditions ................................................................................................................ 7
Changed fSW 2.5 V ≤ VIN ≤ 6 V MIN value From: 2 MHz to 1.6 MHz ..................................................................................... 8
Added fSW with Test Conditions 3.25 V ≤ VIN ≤ 6 V................................................................................................................ 8
Changes from Revision A (March, 2013) to Revision B
Page
•
Changed TPS62405-Q1, OUT1 from DEF_1 = High 1.9 V to DEF_1 = High 1.925 V and DEF_1 = Low 1.575 V to
DEF_1 = Low 1.215 V. Changed OUT2 from Fixed default 5 V to Fixed default 3.35 V. ..................................................... 4
•
Added the part number to the Device column of Table 1..................................................................................................... 17
2
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
•
•
•
•
•
•
•
•
•
•
•
Added 1.215 (default TPS62405-Q1) in row 16, Table 4..................................................................................................... 20
Added part number to Table 4.............................................................................................................................................. 20
Removed TPS62405-Q1 from Table 4................................................................................................................................. 20
Added 1.925 (default TPS62405-Q1) in row 31, Table 4. ................................................................................................... 20
Added part number to row 31, Table 4................................................................................................................................. 22
Added part number to Converter 1 Fixed Default Output-Voltage Setting heading ............................................................ 24
Added voltage for TPS62402-Q1 to Converter 1 Fixed for DEF_1 = low ............................................................................ 24
Changed voltage from 1.2 V to 1.215 V for Pin DEF_1 = low.............................................................................................. 24
Added part number TPS62405-Q1 for Pin DEF_1 = high.................................................................................................... 24
Added part number and voltage to Converter 2 Fixed Default Output-Voltage Setting section........................................... 24
Changed TPS62405-Q1, VOUT2 default = 5 V to 3.35 V....................................................................................................... 24
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
5 Device Comparison Table
PART NUMBER
DEFAULT OUTPUT VOLTAGE(1)
OUTPUT CURRENT
VOUT1
VOUT2
IOUT1
IOUT2
400 mA
600 mA
TPS62400-Q1
Adjustable
DEF_1 = High 1.8 V
DEF_1 = Low 1.2 V
Fixed default 3.3 V
VOUT1
VOUT2
VOUT1
VOUT2
VOUT1
VOUT2
Fixed default
Fixed default
Fixed default
IOUT1
IOUT2
IOUT1
IOUT2
IOUT1
IOUT2
400 mA
600 mA
400 mA
600 mA
400 mA
600 mA
TPS62402-Q1
TPS62404-Q1
TPS62405-Q1
DEF_1 = High 1.9 V
DEF_1 = Low 1.2 V
Fixed default 3.3 V
DEF_1 = High 1.925 V
DEF_1 = Low 1.215 V
Fixed default 3.35 V
(1) Contact TI for other fixed-output-voltage options.
4
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
6 Pin Configuration and Functions
DRC Package
10-Pin VSON With Thermal Pad
Bottom View
10
9
1
2
3
4
5
SW2
EN2
GND
EN1
SW1
ADJ2
MODE/DATA
VIN
Thermal
Pad
8
7
FB1
6
DEF_1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Input to adjust output voltage of converter 2. In the adjustable-output version (TPS62400-Q1), an external
resistor network must connect to this pin to set the VOUT2 output voltage between 0.6 V and VIN (see
Figure 6). In the fixed-output-voltage version (TPS62402-Q1, TPS62404-Q1, and TPS62405-Q1), this pin
must connect directly to the output. If using the EasyScale interface-on converter 2, this pin must also
connect directly to the output.
ADJ2
1
I
This pin defines the output voltage of converter 1. The pin acts either as analog input for output voltage
setting via external resistors (TPS62400-Q1), or digital input to select between two fixed default output
voltages (TPS62402-Q1, TPS62404-Q1, and TPS62405-Q1).
DEF_1
5
I
For the TPS62400-Q1, an external resistor network must connect to this pin to adjust the default output
voltage (see Figure 6).
When using the fixed-output-voltage device options, this pin selects between two fixed default output
voltages, see the Device Comparison Table .
EN1
EN2
7
9
I
I
Enable input for converter 1, active-high
Enable input for converter 2, active-high
Direct feedback voltage sense input of converter 1, connect directly to VOUT1. An internal feedforward
capacitor connects between this pin and the error amplifier. In the case of fixed-output-voltage versions or
when using the EasyScale interface, this pin connects to an internal resistor divider network.
FB1
4
8
I
GND
—
GND for both converters; connect this pin to the thermal pad.
This pin has two functions:
1. Operation-mode selection: With low level, enables power-save mode where the device operates in
PFM mode at light loads and automatically enters PWM mode at heavy loads. Pulling this PIN to
high forces the device to operate in PWM mode over the whole load range.
MODE/DATA
2
I/O
2. EasyScale interface function: One-wire serial interface to change the output voltage of both
converters. The pin has an open-drain output to provide an acknowledge condition if requested. The
current into the open-drain output stage may not exceed 500 μA. The EasyScale interface is active
if either EN1 or EN2 is high.
SW1
6
10
3
I/O
I/O
I
Switch pin of converter 1. Connect to inductor
Switch pin of converter 2. Connect to inductor
Input pin, connect to supply or battery voltage, 2.5 V to 6 V
Connect to GND
SW2
VIN
Thermal pad
—
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
Input voltage(2)
Voltage
VIN
7
EN, MODE/DATA, DEF_1
SW1, SW2
VIN + 0.3, ≤ 7
V
7
VIN + 0.3, ≤ 7
≤ 0.5
V
ADJ2, FB1
V
Current
MODE/DATA
mA
°C
°C
Maximum operating junction temperature, TJmax
Storage temperature, Tstg
150
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
Corner pins (1, 5, 6, and 10)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
6
UNIT
V
VIN
TJ
Supply voltage
2.5
0.6
Output voltage range for adjustable voltage
Operating junction temperature
VIN
125
V
–40
°C
7.4 Thermal Information
TPS6240x-Q1
THERMAL METRIC(1)
UNIT
DRC (10 PINS)
RθJA
Junction-to-ambient thermal resistance
42.7
46.9
18.1
0.5
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18.3
3.1
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
7.5 Electrical Characteristics
VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to
125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN Input voltage range
2.5
6
V
One converter, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = 1 or EN2 = 1
19
32
29
Two converters, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = EN2 = 1
μA
48
IQ
Operating quiescent current
No load on the output, MODE/DATA = GND, for one
converter, VOUTx = 1.575 V(1)
23
No load on the output, MODE/DATA = VIN, for one
converter, VOUTx = 1.575 V(1)
3.6
mA
EN1, EN2 = GND, VIN = 3.6 V(2)
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V(3)
1.2
0.1
1.5
3
1
ISD
Shutdown current
μA
Falling
Rising
2.35
2.4
VUVLO
Undervoltage lockout threshold
V
ENABLE EN1, EN2
VIH
VIL
IIN
High-level input voltage range, EN1, EN2
1.2
0
VIN
0.4
1
V
V
Low-level input voltage range, EN1, EN2
Input bias current, EN1, EN2
EN1, EN2 = GND or VIN
0.05
0.01
0.01
μA
DEF_1 INPUT
VDEF_1H
DEF_1 high-level digital input voltage range
0.9
0
VIN
0.4
1
V
V
TPS62402-Q1, TPS62404-Q1, TPS62405-Q1 only
DEF_1 = GND or VIN
VDEF_1L
DEF_1 low-level digital input voltage range
Input bias current DEF_1
IIN
μA
MODE/DATA
VIH
VIL
High-level input voltage range, MODE/DATA
Low-level input voltage range, MODE/DATA
Input bias current, MODE/DATA
1.2
0
VIN
0.4
1
V
V
IIN
MODE/DATA = GND or VIN
μA
V
VOH
VOL
Acknowledge output voltage high
Open drain, through external pullup resistor
Open drain, sink current 500 μA
VIN
0.4
Acknowledge output voltage low
0
V
POWER SWITCH
P-channel MOSFET on-resistance, converter
1,2
rDS(on)
VIN = VGS = 3.6 V
VDS = 6 V
280
620
1
mΩ
μA
ILK_PMOS
rDS(on)
P-channel leakage current
N-channel MOSFET on-resistance converter
1,2
VIN = VGS = 3.6 V
200
6
450
mΩ
Includes N-channel leakage current,
VIN = open, VSW = 6 V, EN = GND(4)
ILK_SW1/SW2 Leakage current into SW1 or SW2 pin
7.5
μA
VOUT1
0.68
0.85
0.8
1
0.92
1.15
Forward current limit
PMOS and NMOS
ILIMF
2.5 V ≤ VIN ≤ 6 V
A
VOUT2
TSD
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
20
ºC
ºC
Thermal shutdown hysteresis
OUTPUT
VOUTx
Vref
Adjustable output 1 or output 2 voltage
range
0.6
VIN
V
Reference voltage
600
mV
(1) Device is switching with no load on the output, L1 = L2 = 3.3 μH, value includes losses of the coil.
(2) These values are valid after enabling the device one time (EN1 or EN2 = high) and maintaining supply voltage VIN
.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid
until enabling the device the first time (EN1 or EN2 = high). After the first enable, Note 3 becomes valid.
(4) An internal resistor of 1 MΩ connects pins SW1 and SW2 to GND.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Electrical Characteristics (continued)
VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to
125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage positioning active,
MODE/DATA = GND,
VOUTx(PFM)
–1.5%
1%
2.5%
device operating in PFM mode,
VIN = 2.5 V to 5 V(6)(7)
DC output voltage accuracy adjustable and
fixed output voltage(5)
MODE/DATA = GND;
device operating in PWM mode,
–1%
–1%
0%
0%
1%
VIN = 2.5 V to 6 V(7)
VOUTx(PWM)
VIN = 2.5 V to 6 V, MODE/DATA = VIN
Fixed PWM operation,
,
1%
0.5
0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA(8)
PWM operation mode
DC output voltage load regulation
%/A
(5) Output voltage specification does not include tolerance of external voltage-programming resistors.
(6) Configuration L1 or L2 typ. 2.2 μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM mode
depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.
(7) In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.
(8) For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
INTERFACE TIMING
tStart
Start time
2
μs
μs
μs
μs
μs
μs
tH_LB
tL_LB
tL_HB
tH_HB
tEOS
High-time low bit, logic 0 detection
Low-time low bit, logic 0 detection
Low-time high bit, logic 1 detection
High-time high bit, logic 1 detection
End of stream
Signal level on MODE/DATA pin is > 1.2 V
Signal level on MODE/DATA pin < 0.4 V
Signal level on MODE/DATA pin < 0.4 V
Signal level on MODE/DATA pin is > 1.2 V
2
2 x tH_LB
2
200
400
200
400
2 x tL_HB
2
Duration of acknowledge condition
(MODE/DATE line pulled low by the
device)
tACKN
VIN 2.5 V to 6 V
400
520
μs
tvalACK
ttimeout
Acknowledge valid time
2
μs
μs
Time-out for entering power-save mode MODE/DATA pin changes from high to low
520
7.7 Switching Characteristics
VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to
125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR
2.5 V ≤ VIN ≤ 6 V; TPS62400-Q1
1.7
2
2.3
2.3
2.2
2.7
2.7
adjustable version(1)
3.0 V ≤ VIN ≤ 6 V; TPS62400-Q1,
fSW
Oscillator frequency
MHz
TPS62402-Q1, TPS62404-Q1(1)
3.6 V ≤ VIN ≤ 5.1 V; TPS62405-Q1
2.06
2.49
fixed output voltage version(1)
OUTPUT
tStart up
Start-up time
Activation time to start switching(2)
170
750
μs
μs
Time to ramp from 5% to 95% of
VOUTx
tRamp
VOUTx ramp-up time
(1) For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
(2) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) with the other converter already
enabled (for example, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = 0) to active mode (EN1
and/or EN2 = 1), a typical value of typ 80 μs for ramp up of internal circuits must be added. After tStart, the converter starts switching and
ramps VOUTx
.
8
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
7.8 Typical Characteristics
2.5
24
2.45
23
2.4
85°C
22
2.35
2.3
25°C
21
20
19
–40°C
2.25
2.2
–40°C
25°C
2.15
85°C
2.1
18
17
2.05
2
2.5
4.5
5.5
6
3
3.5
4
5
2.5
3
3.5
4
4.5
5
5.5
6
VIN (V)
VIN (V)
Figure 1. fSW versus VIN
Figure 2. IQ for One Converter, Not Switching
0.55
0.5
42
40
38
36
34
32
0.45
0.4
85°C
25°C
0.35
0.3
85°C
25°C
–40°C
0.25
30
28
–40°C
0.2
0.15
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
VIN (V)
5
5.5
6
VIN (V)
Figure 4. rDS(on) PMOS versus VIN
Figure 3. IQ for Both Converters, Not Switching
0.3
0.25
0.2
85°C
25°C
0.15
–40°C
0.1
0.05
2.5
3
3.5
4
4.5
5
5.5
6
VIN (V)
Figure 5. rDS(on) NMOS versus VIN
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
8 Parameter Measurement Information
TPS62400-Q1
VIN 2.5 V to 6 V
FB1
VIN
L1
VOUT1
CIN
SW1
10 µF
2.2 µH
LSP4018
R11
R12
COUT1 2 × 10 µF
GRM21BR61A106K
DEF_1
EN1
EN2
L2
VOUT2
SW2
2.2 µH
LSP4018
C
ff2
33 pF
R21
R22
COUT2 2 × 10 µF
MODE/
DATA
GRM21BR61A106K
ADJ2
GND
Figure 6. Measurement Circuit
10
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
9 Detailed Description
9.1 Overview
The TPS62400-Q1 device includes two synchronous step-down converters. The converters operate with typically
2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. With the power-
safe mode enabled, the converters automatically enter power-save mode at light load currents and operate in
PFM (pulse frequency modulation).
During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input-
voltage feedforward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns
on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET turns off
and the N-channel MOSFET turns on. If the current in the N-channel MOSFET is above the N-MOS current limit
threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input rms current.
9.1.1 Converter 1
In the adjustable output-voltage version, TPS62400-Q1 device, one can set the converter 1 default output
voltage with an external resistor network on the DEF_1 pin, which operates as an analog input. In this case, one
can set the output voltage in the range of 0.6 V to VIN V. The FB1 pin must directly connect to the converter 1
output voltage VOUT1. It feeds back the output voltage directly to the regulation loop.
One can also change the output voltage of converter 1 with the EasyScale serial Interface. This makes the
device very flexible for output-voltage adjustment. In this case, the device uses an internal resistor network.
In the fixed default output voltage version, TPS62402-Q1 for example, the DEF_1 pin configuration is as a digital
input. Converter 1 defaults to 1.2 V or 1.8 V, depending on the level of the DEF_1 pin. If DEF_1 is low, the
default is 1.2 V; if high, the default is 1.8 V. With the EasyScale interface, one can change the output voltage for
each DEF_1 pin condition (high or low).
9.1.2 Converter 2
In the adjustable output-voltage version, TPS62400-Q1 device, an external resistor divider connected to ADJ2
pin sets the converter 2 output voltage. The converter uses an external feedforward capacitor of 33 pF.
For example, in the fixed output-voltage version TPS62402-Q1, the fixed default output voltage is fixed to 3.3 V.
In this case, the ADJ2 pin must connect directly to the converter 2 output voltage, VOUT2
.
It is also possible to change the output voltage of converter 2 via the EasyScale interface. In this case, the ADJ2
pin must connect directly to converter 2 output voltage VOUT2, with no connection of external resistors permitted.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
9.2 Functional Block Diagram
VIN
PMOS Current
Limit Comparator
Converter 1
VIN
FB_VOUT
Thermal
Shutdown
Softstart
VREF +1%
Skip Comp.
FB_VOUT
EN1
VREF- 1%
Skip Comp. Low
VREF
Ext. res. network
Error Amp.
Gate Driver
Control
Stage
Internal
FB
VOUT1
DEF1
Int. Resistor
Network
PWM
Comp.
compensated
SW1
Cff 25pF
MODE
Register
RI 1
Sawtooth
Generator
DEF1_High
DEF1_Low
GND
RI..N
FB1
Average
Current Detector
Skip Mode Entry
See (1)
NMOS Current
Limit Comparator
CLK 0°
Reference
Load Comparator
2.25MHz
Oscillator
Easy Scale
Interface
ACK
MODE/
DATA
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180°
MOSFET
Open drain
VIN
FB_VOUT
Converter 2
Int. Resistor
Network
VREF +1%
Skip Comp.
Register
FB_VOUT
VREF- 1%
DEF2
See (2)
VREF
Skip Comp. Low
Gate Driver
Control
Stage
Cff 25pF
Error Amp.
RI 1
Internal
compensated
PWM
Comp.
RI..N
SW2
MODE
FB_VOUT2
ADJ2
EN2
Sawtooth
Generator
GND
Thermal
Shutdown
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
CLK 180°
Softstart
Load Comparator
GND
(1) In the fixed output-voltage version, the DEF_1 pin connects to an internal digital input and disconnects from the error
amplifier.
(2) To set the output voltage of converter 2 through the EasyScale™ interface, the ADJ2 pin must directly connect to
VOUT2
.
12
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
9.3 Feature Description
9.3.1 Enable
The device has a separate EN pin for each converter to start up each converter independently. If EN1 or EN2 is
set to high, the corresponding converter starts up with soft start.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2
μA. In this mode, the P- and N-channel MOSFETs turn off and the entire internal control circuitry switches off.
For proper operation, terminate the EN1 and EN2 pins, do not leave them floating.
9.3.2 DEF_1 Pin Function
The DEF_1 pin, dedicated to converter 1, makes the output voltage selection very flexible to support dynamic
voltage management.
Depending on the device version, this pin works either as:
1. Analog input for adjustable output voltage setting (TPS62400-Q1):
–
Connecting an external resistor network to this pin adjusts the default output voltage to any value starting
from 0.6 V to VIN.
2. Digital input for fixed default output voltage selection (TPS62402-Q1 for example):
–
Having this pin tied to a low level sets the output voltage according to the value in register
REG_DEF_1_Low. The default voltage is 1.2 V. Having the pin tied to a high level sets the output voltage
according to the value in register REG_DEF_1_High. The default value in this case is 1.8 V. The level of
the DEF_1 pin selects between the two registers, REG_DEF_1_Low and REG_DEF_1_High, for the
output-voltage setting. One can change the content of each register (and therefore output voltage)
individually through the EasyScale interface. This makes the device very flexible in terms of output
voltage setting; see Table 4.
9.3.3 180° Out-of-Phase Operation
In PWM mode, the converters operate with a 180° turnon phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from turning on simultaneously, and therefore smooths the
input current. This feature reduces the surge current drawn from the supply.
9.3.4 Short-Circuit Protection
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it turns off and the NMOS switch turns on. The PMOS only turns on again
once the current in the NMOS decreases below the NMOS current limit.
9.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs turn off. The device continues its operation when the junction
temperature falls below the thermal-shutdown hysteresis.
9.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
9.3.6.1 General
The EasyScale interface is a simple but very flexible one-pin interface to configure the output voltage of both DC-
DC converters. A master-slave structure is the basis of the interface, where the master is typically a
microcontroller or application processor. Figure 9 and Table 3 give an overview of the protocol. The protocol
consists of a device-specific address byte and a data byte. The device-specific address byte is fixed to 4E hex.
The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high
indicates the request-for-acknowledge condition. The acknowledge condition only applies after correct reception
of the protocol.
The advantage of the EasyScale interface compared to other one-pin interfaces is that its bit detection is to a
large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kb/s and
up to 160 kb/s. Furthermore, the interface shares the MODE/DATA pin and requires no additional pin.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Feature Description (continued)
9.3.6.2 Protocol
Transmission of all bits is MSB first and LSB last. Figure 10 shows the protocol without the acknowledge request
(bit RFA = 0) and Figure 11 shows the protocol with the acknowledge request (bit RFA = 1).
Prior to both bytes, device address byte and data byte, one must apply a start condition. For this, pull the
MODE/DATA pin high for at least tStart before the bit transmission starts with the falling edge. In case the
MODE/DATA line was already at a high level (forced PWM mode selection), the device requires no application of
a start condition prior to the device address byte.
Close the transmission of each byte with an end-of-stream condition for at least tEOS
.
9.4 Device Functional Modes
9.4.1 Power-Save Mode
Setting the MODE/DATA pin to low for both converters enables power-save mode. If the load current of a
converter decreases, this converter enters power-save-mode operation automatically. The transition of a
converter to power-save mode is independent from the operating condition of the other converter. During power-
save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum
quiescent current to maintain high efficiency. The converter positions the output voltage in PFM mode to typically
1% above nominal VOUTx. This voltage positioning feature minimizes voltage drops caused by a sudden load
step.
In order to optimize the converter efficiency at light load, the device monitors average inductor current. The
device changes from PWM mode to power-save mode if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold, which one can calculate using Equation 1 for each converter,
depends on VIN.
Equation 1: Average output current threshold to enter PFM mode
V
IN
IOUTx _PFM_ enter
=
32 W
(1)
Equation 2: Average output current threshold to leave PFM mode
V
IN
IOUTx _PFM_leave
=
24 W
(2)
To keep the output-voltage ripple in power-save mode low, a single threshold comparator (skip comparator)
monitors the output voltage. As the output voltage falls below the skip-comparator threshold (skip comp) of 1%
above nominal VOUTx, the corresponding converter starts switching for a minimum time period of typically 1 μs
and provides current to the load and the output capacitor. Therefore, the output voltage increases and the device
maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment, all switching activity stops and the quiescent current reduces to minimum. The output capacitor supplies
the load until the output voltage has dropped below the threshold again. Hereupon, the device starts switching
again.
The converter leaves power-save mode and enters PWM mode if the output current exceeds the IOUT_PFM_leave
current or if the output voltage falls below a second comparator threshold, called the skip-comparator-low (Skip
Comp Low) threshold. This skip-comparator-low threshold is 2% below nominal VOUTx and enables a fast
transition from power-save mode to PWM mode during a load step.
Power-save mode typically reduces the quiescent current to 19 μA for one converter and 32 μA for both
converters active. This single-skip comparator threshold method in power-save mode results in a very low
output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.
Increasing output capacitor values minimizes the output ripple. One can disable the power-save mode by setting
the MODE/DATA pin to high. Both converters then operate in fixed PWM mode. Power-save mode enable or
disable applies to both converters.
14
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
Device Functional Modes (continued)
9.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage under- and overshoots at load steps from light to heavy load and from heavy to
light. Power-save-mode operation activates dynamic voltage positioning and provides more headroom for both
the voltage drop at a load step and the voltage increase when a load is switched off, which improves load-
transient behavior.
At light loads, in which the converter operates in PFM mode, the output voltage regulation is typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to 2% below the nominal value and enters PWM mode. During a
load transition from heavy load to light load, the device also minimizes voltage overshoot because of active
regulation turning on the N-channel switch.
Smooth
Fast load transient
increased load
+1%
PFM Mode
light load
PFM Mode
light load
VOUTx_NOM
PWM Mode
medium, heavy load
PWM Mode
PWM Mode
medium, heavy load
medium, heavy load
COMP_LOW threshold –2%
Figure 7. Dynamic Voltage Positioning
9.4.1.2 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during startup. Figure 8 shows
control of the output-voltage ramp-up during soft start. The device is able to start into a pre-biased output
capacitor.
ENx
95%
5%
VOUTx
tRamp
tStartup
Figure 8. Soft Start
9.4.1.3 100% Duty-Cycle Low-Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This is particularly useful in battery-
powered applications to achieve longest operation time by taking full advantage of the whole battery-voltage
range. The minimum input voltage to maintain regulation depends on the load current and output voltage, which
one can calculate as:
V
= VOUTxmax + IOUTxmax ´ r
(
+ RL
)
INmin
DS(on)max
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Device Functional Modes (continued)
with
•
•
•
•
IOUTxmax = maximum output current plus inductor ripple current
rDS(on)max = maximum P-channel switch rDS(on)
RL = dc resistance of the inductor
VOUTxmax = nominal output voltage plus maximum output-voltage tolerance
(3)
With decreasing load current, the device automatically switches into pulse-skipping operation, in which the power
stage operates intermittently based on load demand. Running cycles periodically minimizes the switching losses,
and the device runs with a minimum quiescent current, maintaining high efficiency.
9.4.1.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunction at low input voltages and from excessive
discharge of the battery, and disables the converters. The undervoltage lockout threshold is typically 1.5 V and a
maximum of 2.35 V. In case the interface overwrites the default register values, the new values in the registers
REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall
below the undervoltage lockout threshold, independent of disabling of the converters.
9.4.2 Mode Selection
The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides mode selection) a one-pin interface
to receive serial data from a host to set the output voltage, as described in the EasyScale Interface section.
Connecting this pin to GND enables the automatic PWM and power-save-mode operation. The converters
operate in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads,
maintaining high efficiency over a wide load-current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light
load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-
save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
In the case of changing the operation mode from forced PWM mode (MODE/DATA = high) to power-save mode
(MODE/DATA = 0), enabling the power-save mode occurs after a delay time of ttimeout, which is 520 μs maximum.
Setting the MODE/DATA to 1 enables forced-PWM-mode operation immediately.
9.5 Programming
9.5.1 Addressable Registers
Three registers with a data content of five bits are addressable. With 5-bit data content, 32 different values for
each register are available. Table 1 shows the addressable registers to set the output voltage when the DEF_1
pin works as a digital input. In this case, converter 1 has a related register for each DEF_1 pin condition, and one
register for converter 2. A high or low condition on pin DEF_1 (TPS62402-Q1, TPS62404-Q1, and
TPS62405-Q1) selects either the content of register REG_DEF_1_High or REG_DEF_1_Low, thus setting the
output voltage of converter 1 according to the values in Table 4.
Table 2 shows the addressable registers if the DEF_1 pin acts as an analog input with external resistors
connected. In this case, one register is available for each converter. The values in Table 5 set the output voltage
of converter 1. Table 6 shows the available voltages for converter 2. Use of a precise internal resistor divider
network to generate these output voltages makes external resistors unnecessary (less board space) and
provides higher output-voltage accuracy. Enabling at least one of the converters (EN1 or EN2 is high) activates
the interface. After the start-up time tStart (170 μs), the interface is ready for data reception.
16
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
Programming (continued)
Table 1. Addressable Registers for Default Fixed-Output Voltage Options (PIN DEF_1 = Digital Input)
DEVICE
REGISTER
DESCRIPTION
DEF_1
PIN
A1
A0
D4
D3
D2
D1
D0
REG_DEF_1_High
Converter 1 output voltage setting for
DEF_1 = High condition. The content of the
register is active with the DEF_1 pin high.
High
0
1
Output voltage setting, see Table 4
TPS62402-Q1,
TPS62404-Q1,
TPS62405-Q1
REG_DEF_1_Low
REG_DEF_2
Converter 1 output voltage setting for
DEF_1 = Low condition.
Low
0
1
1
0
0
1
Output voltage setting, see Table 4
Output voltage setting, see Table 6
Converter 2 output voltage
Not
applicable
Do not use
Table 2. Addressable Registers for Adjustable-Output Voltage Options (PIN DEF_1 = Analog Input)
DEVICE
REGISTER
REG_DEF_1_High
REG_DEF_1_ Low
REG_DEF_2
DESCRIPTION
A1
A0
D4
D3
D2
D1
D0
Not available
Converter 1 output-voltage setting
Converter 2 output voltage
Do not use
0
1
1
0
0
1
See Table 5
See Table 6
TPS62400-Q1
9.5.1.1 Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between the low time and high
time of the low or high bit (tL_xB and tH_xB). Bit detection can be simplified to:
High bit: tH_HB > tL_HB, but with tH_HB at least 2× tL_HB, see Figure 9.
Low bit: tL_LB > tH_LB, but with tL_LB at least 2× tH_LB, see Figure 9.
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Detection
of a 0 or 1 depends on the relation between tL_xB and tH_xB
.
9.5.1.2 Acknowledge
The device only applies the acknowledge condition if all of the following occurs:
•
•
•
A set RFA bit requests an acknowledge
The transmitted device address matches with the device address of the device
Correct reception of 16 bits occurred
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is 520 μs maximum. The acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET turns on after tvalACK, on detection of the last falling edge of the protocol. The
master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and reading back a 0.
In case of an invalid device address, or not-correctly-received protocol, application of a no-acknowledge
condition does not occur; thus, the internal MOSFET does not turn on, and the external pullup resistor pulls the
MODE/DATA pin high after tvalACK. One can use the MODE/DATA pin again after the acknowledge condition
ends.
NOTE
The master device must have an open-drain output in order to request the acknowledge
condition.
In case of a push-pull output stage, TI recommends using a series resistor in the MODE/DATA line to limit the
current to 500 μA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
9.5.1.3 Mode Selection
Use of the MODE/DATA pin for two functions, interface and mode selection, necessitates a determination of
when to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device also stays in forced PWM mode during the entire protocol reception time.
With a falling edge on the MODE/DATA pin, the device starts bit decoding. If the MODE/DATA pin stays low for
at least ttimeout, the device gets an internal time-out and enables power-save-mode operation.
The device ignores a protocol sent within this time because the first interpretation of a falling edge for the mode
change is at the start of the first bit. In this case, TI recommends sending the protocol first, and then changing to
power-save mode at the end of the protocol.
DATA IN
Device Address
DATABYTE
D4 D3 D2
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
RFA A1
A0
D1 D0
EOS Start
EOS
0
1
0
0
1
1
1
0
DATA OUT ACK
Figure 9. EasyScale Protocol Overview
Table 3. EasyScale Bit Description
BYTE
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
DESCRIPTION
Device
address
byte
7
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
RFA
A1
IN
IN
IN
IN
IN
IN
IN
IN
IN
0 MSB device address
6
1
5
0
4
0
4E hex
3
1
2
1
1
1
0
0 LSB device address
Data
byte
7 (MSB)
Request for acknowledge; if high, the device applies an acknowledge condition.
6
Address bit 1
Address bit 0
Data bit 4
5
A0
4
D4
3
D3
Data bit 3
2
1
D2
Data bit 2
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
OUT
Acknowledge condition active 0, the device applies this condition only in the case of
a set RFA bit. Open-drain output, the host must pull the line high with a pullup
resistor.
One can only use this feature if the master has an open-drain output stage. In case
of a push-pull output stage, do not request an acknowledge condition.
tStart
tStart
Address Byte
DATA Byte
DATA IN
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
0
D0
1
tEOS
tEOS
Figure 10. EasyScale Protocol Without Acknowledge
18
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
tStart
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DATA IN
DA7
DA0
0
D0
1
RFA
1
0
tEOS
t
valACK
Acknowledge
true, Data Line
pulled down by
device
ACKN
t
ACKN
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
Acknowledge
false, no pull
down
Figure 11. EasyScale Protocol Including Acknowledge
tH_LB
tH_HB
tL_LB
tL_HB
Low Bit
(Logic 0)
High Bit
(Logic 1)
Figure 12. EasyScale – Bit Coding
MODE/DATA
ttimeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 13. MODE/DATA PIN: Mode Selection
tStart
tStart
Address Byte
DATA Byte
MODE/DATA
tEOS
tEOS
ttimeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 14. MODE/DATA Pin: Power-Save-Mode and Interface Communication
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Table 4. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input (TPS62402-Q1)
TPS62402-Q1 OUTPUT
TPS62402-Q1 OUTPUT
VOLTAGE [V]
D4 D3 D2 D1 D0
VOLTAGE [V]
REGISTER REG_DEF_1_LOW
REGISTER REG_DEF_1_HIGH
0
1
0.8
0.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.825
0.85
0.925
0.95
2
3
0.875
0.9
0.975
1.0
4
5
0.925
0.95
1.025
1.050
1.075
1.1
6
7
0.975
1.0
8
9
1.025
1.050
1.075
1.1
1.125
1.150
1.175
1.2
10
11
12
13
14
15
16
1.125
1.150
1.175
1.225
1.25
1.275
1.3
1.2 (default TPS62402-Q1)
1.215 (default TPS62405-Q1)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.225
1.325
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.25
1.350
1.275
1.375
1.3
1.4
1.325
1.425
1.350
1.450
1.375
1.475
1.4
1.5
1.425
1.525
1.450
1.55
1.475
1.575
1.5
1.6
1.525
1.55
1.7
1.8 (default TPS62402-Q1)
1.575 (default TPS62404-Q1)
1.9 (default TPS62404-Q1)
1.925 (default TPS62405-Q1)
20
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
Table 5. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input (Adjustable, TPS62400-Q1)
TPS62400-Q1 OUTPUT VOLTAGE [V]
REGISTER REG_DEF_1_LOW
D4 D3 D2 D1 D0
0
VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default
TPS62400-Q1)
0
0
0
0
0
0.6 V with DEF_1 connected to VOUT1 (default TPS62400-Q1)
1
0.825
0.85
0.875
0.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
0.925
0.95
0.975
1
6
7
8
9
1.025
1.05
1.075
1.1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.125
1.15
1.175
1.2
1.225
1.25
1.275
1.3
1.325
1.35
1.375
1.4
1.425
1.45
1.475
1.5
1.525
1.55
1.575
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Table 6. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT2
)
OUTPUT VOLTAGE [V]
D4 D3 D2 D1 D0
FOR REGISTER REG_DEF_2
0
VOUT2 Adjustable with resistor network and Cff on ADJ2 pin
(default TPS62400-Q1)
0
0
0
0
0
0.6 V with ADJ2 pin directly connected to VOUT2 (default
TPS62400-Q1)
1
0.85
0.9
0.95
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.7
1.8
1.85
2
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.85
3
3.3 (default TPS62402-Q1, TPS62404-Q1)
3.35 (default TPS62405-Q1)
22
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
10 Application and Implementation
NOTE
Information in the following application sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS6240x-Q1 family of devices are synchronous dual step-down DC-DC converters. The devices provide
two independent output voltage rails. The following information provides guidance on selecting external
components to complete the application design.
10.2 Typical Application
TPS62400-Q1
VIN 2.5 V to 6 V
FB1
VIN
L1
VOUT1
CIN
SW1
10 µF
2.2 µH
LSP4018
R11
R12
COUT1 2 × 10 µF
GRM21BR61A106K
DEF_1
EN1
EN2
L2
VOUT2
SW2
2.2 µH
LSP4018
C
ff2
33 pF
R21
R22
COUT2 2 × 10 µF
MODE/
DATA
GRM21BR61A106K
ADJ2
GND
10.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
external components appropriate. The following design procedure is adequate for whole VIN, VOUTx and load
current range of the TPS6240x-Q1 family of devices.
10.2.2 Detailed Design Procedure
10.2.2.1 Output Voltage Setting
10.2.2.1.1 Converter 1 Adjustable Default Output-Voltage Setting: TPS62400-Q1
Calculate the output voltage as:
R11
æ
ö
VOUT1 = VREF ´ 1+
ç
÷
R12
è
ø
where
•
VREF = 0.6-V (typical) internal reference voltage
(4)
23
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
Typical Application (continued)
To keep the operating current to a minimum, TI recommends selecting R12 within a range of 180 kΩ to 360 kΩ.
The sum of R12 and R11 must not exceed approximately 1 MΩ. For output voltages higher than 3.3 V, TI
recommends choosing lower values than 180 kΩ for R12. Route the DEF_1 line away from noise sources, such
as the inductor or the SW1 line. The FB1 line requires a direct connection to the output capacitor. A feedforward
capacitor is not necessary.
10.2.2.1.2 Converter 1 Fixed Default Output-Voltage Setting (TPS62402-Q1, TPS62404-Q1, and
TPS62405-Q1)
The DEF_1 pin selects output voltage VOUT1
.
Pin DEF_1 = low:
•
•
•
TPS62402-Q1 = 1.2 V
TPS62404-Q1 = 1.575 V
TPS62405-Q1 = 1.215 V
Pin DEF_1 = high:
•
•
•
TPS62402-Q1 = 1.8 V
TPS62404-Q1 = 1.9 V
TPS62405-Q1 = 1.925 V
10.2.2.1.3 Converter 2 Adjustable Default Output-Voltage Setting (TPS62400-Q1):
One can set the output voltage of converter 2 by an external resistor network. For converter 2, the same
recommendations apply as for converter 1. In addition to that, use a 33-pF feedforward capacitor Cff2 for good
load transient response. Calculate the output voltage as:
R21
æ
ö
VOUT2 = VREF ´ 1+
ç
÷
R22
è
ø
where
•
VREF = 0.6-V (typical) internal reference voltage
(5)
10.2.2.1.4 Converter 2 Fixed Default Output-Voltage Setting
ADJ2 pin must be directly connected with VOUT2
:
•
•
•
TPS62402-Q1, VOUT2 default = 3.3 V
TPS62404-Q1, VOUT2 default = 3.3 V
TPS62405-Q1, VOUT2 default = 3.35 V
10.2.2.2 Output Filter Design (Inductor and Output Capacitor)
The converters operate with a minimum inductance of 1.75 μH and minimum capacitance of 6 μF. The device
operation is optimum with inductors of 2.2 μH to 4.7 μH and output capacitors of 10 μF to 22 μF.
24
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
Typical Application (continued)
10.2.2.2.1 Inductor Selection
Select the inductor based on its ratings for dc resistance and saturation current. The dc resistance of the inductor
directly influences the efficiency of the converter. Therefore, select an inductor with lowest dc resistance for
highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation-current rating of
the inductor must be higher than the maximum inductor current as calculated with Equation 7. TI makes this
recommendation because during heavy load transients, the inductor current rises above the calculated value.
VOUTx
1-
V
IN
DIL = VOUTx
´
L ´ fSW
where
•
•
•
ΔIL = peak-to-peak inductor ripple current
L = inductor value
fSW = switching frequency (2.25 MHz typical)
(6)
(7)
DIL
ILmax = IOUTxmax
+
2
where
•
ILmax = maximum inductor current and the highest inductor current occurs at maximum VIN
Open-core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Take into consideration that the core material from inductor to inductor differs, and this
difference has an impact on the efficiency.
See Table 7 and the typical application circuit examples for possible inductors.
Table 7. List of Inductors
DIMENSIONS [mm]
3.2 × 2.6 × 1
3 × 3 × 0.9
INDUCTOR TYPE
MIPW3226
LPS3010
SUPPLIER
FDK
Coilcraft
TDK
2.8 × 2.6 × 1
2.8 x 2.6 × 1.4
3 × 3 × 1.4
VLF3010
VLF3014
TDK
LPS3015
Coilcraft
Coilcraft
3.9 × 3.9 × 1.7
LPS4018
10.2.2.2.2 Output-Capacitor Selection
The advanced fast-response voltage-mode control scheme of the converters allows the use of tiny ceramic
capacitors with a typical value of 10 μF to 22 μF, without having large output-voltage under- and overshoots
during heavy load transients. Ceramic capacitors with low ESR values result in lowest output-voltage ripple, and
TI therefore recommends them. The output capacitor requires either X7R or X5R dielectric. TI does not
recommend Y5V and Z5U dielectric capacitors because of their wide variation in capacitance.
If using ceramic output capacitors, the capacitor rms ripple-current rating always meets the application
requirements. The rms ripple current can be calculated as:
VOUTx
1-
V
1
IN
IRMSCOUTx = VOUTx
´
´
L ´ fSW
2 ´
3
(8)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and
discharging the output capacitor:
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
VOUTx
1-
æ
ö
÷
ø
V
1
IN
DVOUTx = VOUTx
´
´
+ ESR
ç
L ´ fSW
8 ´ COUTx ´ fSW
è
where the highest output-voltage ripple occurs at the highest input voltage, VIN.
(9)
At light load currents, the converters operate in power-save mode and the output-voltage ripple depends on the
output-capacitor value. The internal comparator delay and the external capacitor set the output-voltage ripple.
Higher output capacitors like 22 μF values minimize the voltage ripple in PFM mode and tighten dc output
accuracy in PFM mode.
10.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, the device requires a low-ESR
input capacitor to prevent large voltage transients that can cause misbehavior of the device or interference with
other circuits in the system. An input capacitor of 10 μF is sufficient.
26
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
10.2.3 Application Curves
100
90
100
90
VIN = 3.6 V
VIN = 3.6 V
80
70
60
80
70
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.6 V
VIN = 5 V
60
VIN = 3.6 V
VIN = 5 V
50
40
30
50
VIN = 5 V
VIN = 5 V
40
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
30
20
20
10
0
10
0
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
Output Current (mA)
Output Current (mA)
VOUT2 = 1.8 V
VOUT2 = 3.3 V
Figure 15. Efficiency
Figure 16. TPS62400-Q1 Efficiency
100
95
100
90
IOUT2 = 100 mA
IOUT1 = 10 mA
90
IOUT2 = 10 mA
85
80
IOUT2 = 1 mA
80
IOUT1 = 1 mA
IOUT1 = 200 mA
75
70
65
60
70
60
50
55
50
2
3
4
5
6
3
4
5
6
VIN (V)
VIN (V)
VOUT2 = 3.3 V
MODE/DATA = 0
VOUT1 = 1.575 V
MODE/DATA = 0
Figure 18. Efficiency versus VIN
Figure 17. Efficiency versus VIN
3.400
3.350
1.854
1.836
1.818
MODE/DATA = low, PFM Mode, voltage positioning active
MODE/DATA = low, PFM Mode, voltage positioning active
VIN = 5 V
PWM Mode
Operation
PWM Mode
Operation
VIN = 5 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 4.2 V
VIN = 3.6 V
VIN = 2.7 V
VIN = 4.2 V
3.300
1.800
1.782
VIN = 5 V
MODE/DATA = high, forced PWM Mode
VIN = 4.2 V
VIN = 3.6 V
VIN = 5 V
VIN = 3.6 V
VIN = 2.7 V
MODE/DATA = high, forced PWM Mode
3.250
3.200
1.764
1.746
0.01
0.10
1
10
100
1000
0.01
0.10
1
10
100
1000
IOUT2 (mA)
IOUT2 (mA)
VOUT2 = 3.3 V
Figure 19. DC Output Accuracy
VOUT2 = 1.8 V
Figure 20. DC Output Accuracy
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
1.650
1.650
1.625
MODE/DATA = low, PFM Mode, voltage positioning active
1.625
MODE/DATA = low, PFM Mode, voltage positioning active
VIN = 4.2 V
VIN = 4.2 V
PWM Mode
Operation
PWM Mode
Operation
1.600
1.600
VIN = 2.7 V
VIN = 3.6 V
VIN = 3.6 V
VIN = 2.7 V
VIN = 2.7 V
1.575
1.550
1.575
1.550
VIN = 3.6 V
VIN = 4.2 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 2.7 V
MODE/DATA = high, forced PWM Mode
MODE/DATA = high, forced PWM Mode
1.525
1.500
1.525
1.500
0.01
0.10
1
10
100
1000
0.01
0.10
1
10
100
1000
IOUT1 (mA)
IOUT1 (mA)
VOUT1 = 1.575 V
L1 = 2.2 μH
COUT1 = 22 μF
VOUT1 = 1.575 V
L1 = 3.3 μH
COUT1 = 10 μF
Figure 21. DC Output Accuracy
Figure 22. DC Output Accuracy
VOUTx = 1.8 V, 20 mV/Div
VOUTx = 1.8 V, 20 mV/Div
Inductor current 100 mA/Div
Inductor current 100 mA/Div
Time base – 400 ns/Div
Time base – 10 µs/Div
Forced PWM mode
MODE/DATA = high
IOUTx = 10 mA
Power save mode
MODE/DATA = low
IOUTx = 10 mA
Figure 24. Output-Voltage Ripple in Forced-PWM Mode
Figure 23. Light-Load Output-Voltage Ripple in Power-
Save Mode
MODE/DATA 1 V/Div
Forced PWM
Mode
VOUTx ripple 20 mV/Div
Inductor current 200 mA/Div
Time base – 200 ns/Div
Enable Power Save Mode
Entering PFM Mode
Voltage positioning active
VOUTx 20 mV/Div
Time base – 200 µs/Div
PWM mode
VOUTx = 1.8 V
IOUTx = 400 mA
VOUTx = 1.8 V
IOUTx = 20 mA
Figure 25. Output-Voltage Ripple in PWM Mode
Figure 26. Forced PWM-to-PFM Mode Transition
28
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
VOUT1 = 1.575 V
50 mV/Div
VOUT1 = 1.575 V
50 mV/Div
Voltage positioning in PFM
PWM Mode operation
Mode reduces voltage drop
during load step
IOUT1 200 mA/Div
IOUT1 200 mA/Div
IOUT1 = 360 mA
IOUT1 = 360 mA
IOUT1 = 40 mA
IOUT1 = 40 mA
Time base – 50 µs/Div
Time base – 50 µs/Div
MODE/DATA = low
PWM mode
MODE/DATA = high
Figure 27. Load-Transient Response, PFM-to-PWM
Figure 28. Load-Transient Response, PWM Operation
EN1, EN2 5 V/Div
VIN 1 V/Div
VOUT1
500 mV/Div
SW1 1 V/Div
VOUT1 50 mV/Div
Icoil 500 mA/Div
Time base – 400 µs/Div
Time base – 200 µs/Div
MODE/DATA = low
VIN = 3.6 to 4.6 V
IOUT1 = 200 mA
VOUT1 = 1.575 V
VIN = 3.8 V
IOUT1max = 400 mA
Figure 29. Line-Transient Response
Figure 30. Start-up Timing, One Converter
DEF_1 pin
2 V/Div
SW1 5 V/Div
I
200 mA/Div
coil1
VOUT1 = 1.8 V
VOUT1
SW2 5 V/Div
500 mV/Div
VOUT1 = 1.2 V
I
coil2
200 mA/Div
Icoil 500 mA/Div
Time base – 100 µs/Div
Time base – 100 ns/Div
VIN = 3.6 V
VOUT1 = 1.575 V
VOUT2 = 1.8 V
VIN = 3.6 V
MODE/DATA = low
IOUT1 = 40 mA
IOUT1 = IOUT2 = 200 mA
Figure 32. Typical Operation
Figure 31. TPS62402-Q1 DEF1_PIN Function for Output-
Voltage Selection
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
SW1 5 V/Div
SW1 5 V/Div
200 mA/Div
I
coil1
I
200 mA/Div
coil1
SW2 5 V/Div
SW2 5 V/Div
I
200 mA/Div
coil2
I
200 mA/Div
coil2
Time base – 100 ns/Div
Time base – 100 ns/Div
VIN = 3.6 V
VOUT1 = 1.8 V
VOUT2 = 3 V
VIN = 3.6 V
VOUT1 = 1.2 V
VOUT2 = 1.2 V
IOUT1 = IOUT2 = 200 mA
IOUT1 = IOUT2 = 200 mA
Figure 33. Typical Operation
Figure 34. Typical Operation
MODE/DATA
2 V/Div
1.5 V
V
OUT1
V
200 mV/Div
OUT1
V
1.1 V
OUT1
Time base – 100 µs/Div
VIN = 3.8 V
ACKN = off
REG_DEF_1_Low
IOUT1 = 150 mA
Figure 35. VOUT1 Change With EasyScale Interface
30
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
10.3 System Examples
TPS62402-Q1
VIN 2.5 V to 6 V
FB1
VIN
2.2 µH
VOUT1 = 1.2 V
400 mA
SW1
10 µF
22 µF
DEF_1
EN1
EN2
2.2 µH
VOUT2 = 3.3 V
600 mA
SW2
MODE/
DATA
22 µF
ADJ2
GND
Figure 36. TPS62402-Q1 Fixed 1.2-V and 3.3-V Outputs, Low PFM Ripple Voltage Optimized
TPS62402-Q1
VIN 2.5 V to 6 V
FB1
VIN
2.2 µH
VOUT1 = 1.8 V
400 mA
10 µF
SW1
DEF_1
EN1
22 µF
EN2
2.2 µH
VOUT2 = 3.3 V
SW2
600 mA
MODE/
DATA
22 µF
ADJ2
GND
Figure 37. TPS62402-Q1 Fixed 1.8-V and 3.3-V Outputs, Low PFM Ripple Voltage Optimized
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
System Examples (continued)
TPS62404-Q1
VIN 2.5 V to 6 V
VIN
FB1
L1
VOUT1 = 1.575 V
400 mA
10 µF
SW1
2.2 µH
COUT1
10 µF
DEF_1
EN1
EN2
L2
VOUT2 = 3.3 V
600 mA
SW2
2.2 µH
MODE/
COUT2
10 µF
DATA
ADJ2
GND
Figure 38. TPS62404-Q1 Fixed 1.575-V and 3.3-V Outputs
VIN 2.5 V to 6 V
TPS62402-Q1
FB1
TPS62405-Q1
Processor
VIN
L1
VOUT1 400 mA:
VCore
SW1
10 µF
TPS62402-Q1 DEF_1 = 0: 1.2 V
TPS62402-Q1 DEF_1 = 1: 1.8 V
TPS62405-Q1 DEF_1 = 0: 1.215 V
TPS62405-Q1 DEF_1 = 1: 1.925 V
10 µF
EN1
EN2
DEF_1
SW2
VCore_Sel
VI/O
L2
VOUT2 600 mA:
TPS62402-Q1: 3.3 V
TPS62405-Q1: 3.35 V
10 µF
MODE/
DATA
ADJ2
GND
Figure 39. Dynamic Voltage Scaling on VOUT1 Controlled by DEF_1 Pin
32
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
System Examples (continued)
TPS62405-Q1
VIN 2.5 V to 6 V
VIN
FB1
2.2 µH
VOUT1 = 1.215 V
SW1
10 µF
400 mA
10 µF
DEF_1
EN1
EN2
3.3 µH
VOUT2 = 3.35 V
SW2
600 mA
10 µF
MODE/
DATA
ADJ2
GND
Figure 40. TPS62405-Q1 1.215-V and 3.35 Outputs
11 Power Supply Recommendations
This device has no special recommendation for the power supply. TI recommends to use the values listed in the
Recommended Operating Conditions.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
www.ti.com
12 Layout
12.1 Layout Guidelines
•
•
As for all switching power supplies, the layout is an important step in the design.
Place the input capacitor as close as possible to the IC pins VIN and GND, then place the inductor and output
capacitor as close as possible to the pins SW1 and GND.
•
•
Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each
converter, use a common power GND node and a different node for the signal GND to minimize the effects of
ground noise.
Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common
path to the GND PIN, which returns the small signal components and the high current of the output
capacitors, as short as possible to avoid ground noise.
•
•
•
Connect the output voltage-sense lines (FB 1, DEF_1, ADJ2) right to the output capacitor and route them
away from noisy components and traces (for example, the SW1 and SW2 lines).
If operating the EasyScale interface with high transmission rates, route the MODE/DATA trace away from the
ADJ2 line to avoid capacitive coupling into the ADJ2 pin.
A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
12.2 Layout Example
CIN
L2
L1
CO2
CO1
Figure 41. Layout Diagram
34
Submit Documentation Feedback
Copyright © 2010–2020, Texas Instruments Incorporated
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1
www.ti.com
SLVSA67F –FEBRUARY 2010–REVISED APRIL 2020
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TPS62400-Q1
TPS62402-Q1
TPS62404-Q1
TPS62405-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
EasyScale, the EasyScale, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2020, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62400QDRCRQ1
TPS62402QDRCRQ1
TPS62404QDRCRQ1
TPS62405QDRCRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SHI
NIPDAU
NIPDAU
NIPDAU
SJS
OET
SJT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62400-Q1, TPS62402-Q1, TPS62404-Q1 :
Catalog: TPS62400, TPS62402, TPS62404
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62400QDRCRQ1
TPS62402QDRCRQ1
TPS62404QDRCRQ1
TPS62405QDRCRQ1
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000
3000
3000
3000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62400QDRCRQ1
TPS62402QDRCRQ1
TPS62404QDRCRQ1
TPS62405QDRCRQ1
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000
3000
3000
3000
367.0
367.0
356.0
367.0
367.0
367.0
356.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
TPS62410DRCTG4
2.25MHZ 2x800mA Dual Step-Down Converter with 1-Wire Interface in QFN 10-VSON -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明