TPS62442 [TI]
采用 QFN 封装的 2.75V 至 6V 双路 2A 或 3A/1A 降压转换器;
| 型号： | TPS62442 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 QFN 封装的 2.75V 至 6V 双路 2A 或 3A/1A 降压转换器 转换器 |
| 文件： | 总38页 (文件大小：2706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62441, TPS62442
ZHCSPA9A –NOVEMBER 2021 –REVISED MAY 2023
TPS6244x 具有可调频率和1% 精度并采用QFN 封装的2.75V 至6V 双通道降压
转换器
1 特性
3 说明
• 功能安全型
TPS6244x 系列是一款引脚对引脚双路 1A、双路 2A
和 3A/1A 高效且易于使用的同步降压直流/直流转换
器。该器件系列基于峰值电流模式控制拓扑。这些器件
专为电机驱动器和机器人等工业应用而设计。低阻开关
可在高温环境下支持高达 3A 的持续输出电流和高达
4A 的最大总输出电流。用户可通过外部方式在
1.8MHz 至4MHz 范围内调节开关频率，亦可在该频率
范围内将其同步至外部时钟。在 PWM/PFM 模式下，
TPS6244x 会在轻负载情况下自动进入省电模式，从而
在整个负载范围内维持高效率。TPS6244x 可在 PWM
模式下提供1% 的输出电压精度，这有助于实现具有高
输出电压精度的电源设计。
– 可提供用于功能安全系统设计的文档
• 0.6V 至5.5V 双通道输出电压
• 1A/1A、2A/2A、3A/1A 输出电流
• 输入电压范围为2.75V 至6V
• 1% 反馈电压精度（PWM 工作模式）
• TJ = -40°C 至+150°C
• 两个精密使能输入可实现：
– 用户定义的欠压锁定
– 准确排序
• 具有窗口比较器的两个电源正常输出
• 1.8MHz 至4MHz 可调开关频率
• 可选择与外部时钟同步
• 可选展频时钟
• 强制PWM 或PWM/PFM 操作
• 可选择高达200µF 的补偿网络
• 22µA 静态电流
• 180° 相移运行
• 100% 占空比模式
• 有源输出放电
• 热关断保护
• 2.3mm x 2.7mm QFN 封装
TPS6244x 提供了可调节电压版本，采用 VQFN 封
装。
封装信息
封装(1)
封装尺寸（标称值）
器件型号
TPS62441
TPS62442
RQR（VQFN，14） 2.30 mm x 2.70 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 电机驱动器/无人机控制器
• 机器人HMI
• 测试和测量
• 机器视觉
• 串式逆变器
100
95
90
85
80
75
70
65
60
55
L1
0.47 µH
VIN
TPS6244x
VOUT1
COUT1
2.75 V - 6 V
VIN1
SW1
CFF1
VIN2
EN1
R1
R2
CIN1, CIN2
FB1
2 × 10
µF
2 × 4.7 µF
EN2
L2
0.47 µH
MODE/SYNC
SW2
VOUT2
COUT2
CFF2
V+
R3
R4
FB2
2 × 10
µF
COMP/FSET
R5
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
RCF
50
PG1
45
V+
40
100m
R6
1m
10m
Load (A)
100m
1
PG2
GND
D000
GND
效率与输出电流间的关系；VOUT = 3.3V；PWM/PFM；
fsw = 2.25MHz
原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEQ8
TPS62441, TPS62442
ZHCSPA9A –NOVEMBER 2021 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
9.2 Functional Block Diagram......................................... 11
9.3 Feature Description...................................................11
9.4 Device Functional Modes..........................................14
10 Application and Implementation................................16
10.1 Application Information........................................... 16
10.2 Typical Application.................................................. 17
10.3 Power Supply Recommendations...........................27
10.4 Layout..................................................................... 27
11 Device and Documentation Support..........................29
11.1 Device Support........................................................29
11.2 Documentation Support.......................................... 29
11.3 接收文档更新通知................................................... 29
11.4 支持资源..................................................................29
11.5 Trademarks............................................................. 29
11.6 静电放电警告...........................................................29
11.7 术语表..................................................................... 29
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................8
7.7 Typical Characteristics................................................8
8 Parameter Measurement Information............................9
8.1 Schematic................................................................... 9
9 Detailed Description......................................................10
9.1 Overview...................................................................10
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2021) to Revision A (May 2023)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSEQ8
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5 Device Comparison Table
DEVICE NUMBER
FEATURES
OUTPUT VOLTAGE
2 × 1-A output current
VOUT discharge
TPS62441RQRR
adjustable
2 × 2-A or 3-A and 1-A output current
VOUT discharge
TPS62442RQRR
adjustable
6 Pin Configuration and Functions
Top view
GND
9
EN2
10
EN1
8
VIN1
SW1
7
6
5
4
VIN2 11
SW2
12
MODE
/SYNC
PG2 13
COMP
/FSET
14
PG1
1
3
2
FB2
GND
FB1
图6-1. 14-Pin QFN RQR Package Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
This pin is the enable pin of converter 1. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN1
8
I
I
This pin is the enable pin of converter 2. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN2
10
FB1
FB2
3
1
I
Voltage feedback input for converter 1. Connect the resistive output voltage divider to this pin.
Voltage feedback input for converter 2. Connect the resistive output voltage divider to this pin.
Open-drain power-good output of converter 1
I
PG1
PG2
SW1
SW2
4
O
O
13
6
Open-drain power-good output of converter 2
This pin is the switch pin of converter 1 and is connected to the internal power MOSFETs.
This pin is the switch pin of converter 2 and is connected to the internal power MOSFETs.
12
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high, the
device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also be
used to synchronize the device to an external frequency. See the electrical characteristics for the
detailed specification for the digital signal applied to this pin for external synchronization.
MODE/SYNC
COMP/FSET
5
I
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally synchronized.
Do not leave this pin floating.
14
Power supply input. Make sure the input capacitor is connected as close as possible between pin
VIN1 and GND. Connect VIN1 to VIN2.
VIN1
VIN2
7
—
—
Power supply input. Make sure the input capacitor is connected as close as possible between pin
VIN2 and GND. Connect VIN2 to VIN1.
11
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English Data Sheet: SLUSEQ8
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ZHCSPA9A –NOVEMBER 2021 –REVISED MAY 2023
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表6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
GND
2, 9
Ground pins. The GND pins are internally connected.
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
V
VIN1, VIN2
SW1, SW2 (DC)
VIN + 0.3
10
V
SW1, SW2 (AC, less than 10ns)(3)
V
Pin voltage(2)
FB1, FB2
4
V
–0.3
–0.3
–0.3
–65
PG1, PG2, COMP/FSET
EN1, EN2, MODE/SYNC
VIN + 0.3
6.5
V
V
Tstg
Storage temperature
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins (2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN1, VIN2 Input voltage range
2.75
6
V
VOUT1 ,
Output voltage range
VOUT2
0.6
0.32
8
5.5
0.9
V
L1, L2
Effective inductance
0.47
10
μH
μF
COUT1 ,
COUT2
Effective output capacitance(1)
200
CIN1, CIN2 Effective input capacitance on each pin (1)
10
μF
kΩ
mA
°C
RCF
4.5
0
100
2
ISINK_PG
TJ
Sink current at PG pin
Junction temperature
150
–40
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
7.4 Thermal Information
TPS6244x
(JEDEC)
14 PINS
68.7
TPS6244x
(EVM)
THERMAL METRIC(1)
UNIT
14 PINS
53.9
RθJA
Junction-to-ambient thermal resistance
°C/W
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UNIT
7.4 Thermal Information (continued)
TPS6244x
(JEDEC)
14 PINS
50.8
TPS6244x
(EVM)
14 PINS
n/a
THERMAL METRIC(1)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
15.1
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.5
1.9
ΨJT
14.9
20.1
ΨJB
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN1 or EN2 = VIN, no load, device not
switching, TJ = 25°C, MODE = GND, one
converter enabled
IQ
Quiescent current
27
66
38
80
µA
µA
µA
µA
EN1 or EN2 = VIN, no load, device not
switching, MODE = GND, one converter
enabled
IQ
IQ
IQ
Quiescent current
Quiescent current
Quiescent current
22
EN1 = EN2 = VIN, no load, device not
switching, TJ = 25°C, MODE = GND, both
converters enabled
EN1 = EN2 = VIN, no load, device not
switching, MODE = GND, both converters
enabled
33
ISD
ISD
Shutdown current
Shutdown current
EN1 = EN2 = Low, at TJ = 25°C
2
µA
µA
EN1 = EN2 = GND, Nominal value at TJ =
25°C, Max value at TJ = 150°C
1.5
26
VIN rising
VIN falling
TJ rising
TJ falling
2.5
2.3
2.6
2.5
170
15
2.75
2.6
V
V
VUVLO
Under voltage lock out threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL and INTERFACE
Input-threshold voltage at EN1, EN2,
rising edge
VEN,IH
1.06
0.96
1.1
1.0
1.15
V
Input-threshold voltage at EN1, EN2,
falling edge
VEN,IL
IEN,LKG
VIH
1.05
450
V
nA
V
Input leakage current into EN1, EN2
VIH = VIN or VIL = GND
High-level input-threshold voltage at
MODE/SYNC
1.1
Low-level input-threshold voltage at
MODE/SYNC
VIL
0.3
700
300
V
ILKG
tDelay
Input leakage current into MODE/SYNC
Enable delay time
nA
µs
Time from ENx high to device starts
switching; VIN applied already
110
200
100
Enable delay time if one converter
already enabled
Time from ENx high to device starts
switching; VIN applied already
tDelay
µs
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English Data Sheet: SLUSEQ8
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7.5 Electrical Characteristics (continued)
Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time from device starts switching to
power good; device not in current limit
tRamp
fSYNC
Output voltage ramp time
0.7
1.1
1.5
ms
Frequency range on MODE/SYNC pin for
synchronization
2
0
4
MHz
kΩ
V
Resistance from COMP/FSET to GND for internal frequency setting with
2.5
logic low
f = 2.25 MHz
internal frequency setting with
f = 2.25 MHz
Voltage on COMP/FSET for logic high
VIN
96.5%
94.5%
107%
UVP power good threshold voltage;
dc level
VTH_PG
VTH_PG
rising (%VFB
)
94%
92%
99%
97%
UVP power good threshold voltage;
dc level
falling (%VFB
)
)
OVP power good threshold voltage;
dc level
rising (%VFB
)
104%
110%
107%
VTH_PG
OVP power good threshold voltage;
dc level
falling (%VFB
102% 104.5%
0.07
VPG,OL
IPG,LKG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.3
V
100
nA
for a high-level to low-level transition on
the power good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB1
VFB2
,
Feedback voltage
0.6
V
IFB1,LKG,
IFB2,LKG
Input leakage current into FB
Feedback voltage accuracy
Feedback voltage accuracy
VFB = 0.6 V
1
80
1%
nA
VFB1
,
,
,
PWM, VIN ≥VOUT + 1 V
–1%
VFB2
VFB1
VFB2
PFM, VIN ≥VOUT + 1 V, VOUT ≥1.5 V,
2.5%
–1%
Co,eff ≥22µF, L = 0.47µH
VFB1
VFB2
PFM, VIN ≥VOUT + 1 V, 1V ≤ VOUT
1.5 V, Co,eff ≥47µF, L = 0.47µH
<
Feedback voltage accuracy
-1%
2.5%
Load regulation
PWM
0.05
0.02
50
%/A
%/V
Ω
Line regulation
PWM, IOUT = 1 A, VIN ≥VOUT + 1 V
RDIS
fSW
fSW
fSW
Output discharge resistance
150
4
see the FSET pin functionality about
setting the switching frequency
PWM Switching frequency range
PWM Switching frequency
1.8
2.025
2.25
2.25
MHz
MHz
with COMP/FSET tied to GND or VIN
2.475
17%
75
using a resistor from COMP/FSET to
GND
PWM Switching frequency tolerance
–16%
ton,min
ton,min
Minimum on-time of high-side FET
Minimum on-time of low-side FET
High-side FET on-resistance
50
30
55
25
1
ns
ns
VIN ≥3.3 V
100
50
VIN ≥5 V
VIN ≥5 V
mΩ
mΩ
µA
RDS(ON)
Low-side FET on-resistance
High-side MOSFET leakage current
Low-side MOSFET leakage current
86
1
205
µA
DC value, for TPS62442;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
3.8
4.7
5.5
A
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7.5 Electrical Characteristics (continued)
Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC value, for TPS62441;
ILIMH
High-side FET switch current limit
Low-side FET negative current limit
2.1
2.6
3.1
A
VIN = 3 V to 6 V
DC value
ILIMNEG
A
–1.8
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Synchronization clock frequency range
(MODE/SYNC)
Nominal fSW determined through COMP/
FSET
fSW +
20%
f(SYNC)
fSW
MHz
Synchronization clock duty cycle range
(MODE/SYNC)
D(SYNC)
45%
55%
7.7 Typical Characteristics
105
40
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-40.0
-10.0
20.0
Junction Temperature (°C)
50.0
80.0
110.0
140.0
-40.0
-10.0
20.0
Junction Temperature (°C)
50.0
80.0
110.0
140.0
D020
D021
图7-1. Rds(on) of High-Side Switch
图7-2. Rds(on) of Low-Side Switch
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English Data Sheet: SLUSEQ8
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8 Parameter Measurement Information
8.1 Schematic
L1
0.47 µH
VIN
TPS6244x
VOUT1
2.75 V - 6 V
VIN1
VIN2
EN1
SW1
CFF1
COUT1
R1
R2
CIN1, CIN2
FB1
2 × 10
µF
2 × 4.7 µF
EN2
L2
0.47 µH
MODE/SYNC
SW2
VOUT2
COUT2
CFF2
V+
R3
R4
FB2
2 × 10
µF
COMP/FSET
R5
RCF
PG1
V+
R6
PG2
GND
GND
图8-1. Measurement Setup
表8-1. List of Components
DESCRIPTION
REFERENCE
MANUFACTURER (1)
IC
L1, L2
CIN1, CIN2
COUT1, COUT2
RCF
TPS62442RQRR
Texas Instruments
0.47-µH inductor DFE252012PD
4.7 µF / 6.3 V
Murata
Murata
Murata
any
2 × 10 µF / 6.3 V
8.06 kΩ
10 pF
CFF1, CFF2
R1
any
Depending on VOUT
Depending on VOUT
Depending on VOUT
Depending on VOUT
100 kΩ
any
R2
any
R3
any
R4
any
R5, R6
any
(1) See the Third-Party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS6244x synchronous dual switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated. To optimize the bandwidth of the control loop to the wide
range of output capacitance that can be used with TPS6244x, the internal compensation has two settings. See
COMP/FSET. One of the two compensation settings is chosen either by a resistor from COMP/FSET to GND, or
by the logic state of this pin. The regulation network achieves fast and stable operation with small external
components and low-ESR ceramic output capacitors. The devices can be operated without a feedforward
capacitor on the output voltage divider, however, using a typically 10-pF feed forward capacitor improves
transient response.
The devices support forced fixed-frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a range of
1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. External synchronization can only be used when there is a resistor from
COMP/FSET to GND. When COMP/FSET is directly tied to GND or VIN, the TPS6244x cannot be synchronized
externally. The TPS6244x allows for a change from internal clock to external clock during operation. When the
MODE pin is set to a logic low level, the device operates in power save mode (PFM) at low output current and
automatically transfers to fixed frequency PWM mode at higher output current. In PFM mode, the switching
frequency decreases linearly based on the load to sustain high efficiency down to very low output current. When
a converter switches from PFM to PWM operation, there can be a maximum delay of one clock cycle because in
this case, the converter has to synchronize to the other converter to achieve 180 degrees phase shift.
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9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at EN1 and EN2 is compared to a fixed threshold of 1.1 V for a rising voltage. This
comparison allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
The precise enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of EN1 and EN2.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS6244x starts operation when the rising threshold is exceeded. For proper operation, the enable (EN) pin
must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown, with
a shutdown current of typically 1.5 μA. In this mode, the internal high-side and low-side MOSFETs are turned off
and the entire internal control circuitry is switched off.
The enable delay time is defined from EN1 or EN2 going high to when the converter starts switching. The
converter is enabled first, the internal bandgap is started, and bias currents and configuration bits are read, so its
start-up delay time is longer than for the converter being enabled when this is already done.
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9.3.2 COMP/FSET
This pin allows to set three different parameters:
• Internal compensation settings for the control loop (two settings available)
• The switching frequency in PWM mode from 1.8 MHz to 4 MHz
• Enable/ disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. The resistor must
be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting
is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not
leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on time and minimum off time.
Example:
1V
V
IN
= 5.5V; V
= 1
Duty Cycle =
= 0.2
5.5V
OUT
1
t
=
× 0.2
on, min
f
s
1
1
f
=
× 0.2 =
× 0.2 = 2.67MHz
sw, max
t
0.075μs
on, min
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in 表9-1, up to the maximum of 200-µF effective capacitance in both
compensation ranges. If the capacitance of an output changes during operation, for example, when load
switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the
minimum capacitance on the output. With large output capacitance, the compensation must be done based on
that large capacitance to get the best load transient response. Compensating for large output capacitance but
placing less capacitance on the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
18 MHz × kΩ
fs MHz
R
kΩ =
− 0.18k
(1)
(2)
CF
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
Space
60 MHz × kΩ
fs MHz
R
kΩ =
− 0.6k
CF
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
Space
180 MHz × kΩ
R
kΩ =
− 1.8k
(3)
CF
fs MHz
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表9-1. Switching Frequency, Compensation, and Spread Spectrum Clocking
MINIMUM
OUTPUT
CAPACITANCE
MINIMUM
OUTPUT
CAPACITANCE
FOR VOUT < 1 V
MINIMUM OUTPUT
CAPACITANCE
RCF
COMPENSATION
SWITCHING FREQUENCY
FOR 1 V ≤VOUT < 3.3 V FOR VOUT ≥3.3
V
for smallest output capacitance
(comp setting 1)
10
1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
according to 方程式1
11 µF
11 µF
7 µF
7 µF
5 µF
5 µF
kΩ.. 4.5 kΩ
SSC disabled
for smallest output capacitance
(comp setting 1)
1.8 MHz (33 kΩ) .. 4 MHz (18 kΩ)
according to 方程式2
33 kΩ.. 18 kΩ
SSC enabled
for best transient response
(larger output capacitance)
(comp setting 2)
100
1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)
according to 方程式3
30 µF
11 µF
30 µF
18 µF
7 µF
15 µF
5 µF
kΩ.. 45 kΩ
SSC disabled
for smallest output capacitance
(comp setting 1)
tied to GND
tied to VIN
internally fixed 2.25 MHz
internally fixed 2.25 MHz
SSC disabled
for best transient response
(larger output capacitance)
(comp setting 2)
18 µF
15 µF
SSC enabled
Refer to 节10.1.2.2.2 for further details on the output capacitance required depending on the output voltage.
A too-high resistor value for RCF is decoded as "tied to VIN", a value below the lowest range as "tied to GND".
The minimum output capacitance in 表9-1 is for capacitors close to the output of the device. If the capacitance is
distributed, a lower compensation setting can be required.
9.3.3 MODE/SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The
MODE/SYNC pin allows the user to force PWM mode when set high. The pin also allows the user to apply an
external clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET,
the specifications for the minimum on time and minimum off time have to be observed when setting the external
frequency. For use with external synchronization on the MODE/SYNC pin, the internal switching frequency must
be set by RCF to a similar value of the externally applied clock. This makes sure that, if the external clock fails,
the switching frequency stays in the same range and the compensation settings are still valid. When there is no
resistor from COMP/FSET to GND but the pin is pulled high or low, external synchronization is not possible. If
the device is externally synchronized, both converters are forced to run on that clock frequency preserving 180°
phase relation. The internally generated spread spectrum clocking is turned off while running on an external
clock.
9.3.4 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
9.3.5 Power-Good Output (PG)
Power good is an open-drain output driven by a window comparator. PG is held low when the device is:
• Disabled
• In undervoltage lockout
• In thermal shutdown
• Not in soft start
When the output voltage is in regulation hence, within the window defined in the electrical characteristics, the
output is high impedance.
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表9-2. PG Status
DEVICE STATUS
VIN < 2 V
EN
X
PG STATE
undefined
low
low
VIN ≥2 V
2 V ≤VIN ≤UVLO OR in thermal shutdown OR VOUT not in
high
high
low
regulation OR device in soft start
VOUT in regulation
high impedance
9.3.6 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs of both converters
are turned off and PG goes low. When TJ decreases below the hysteresis amount of typically 20°C, the
converters resume normal operation, beginning with soft start. When both converters are in a PFM pause, the
thermal shutdown is not active. After the PFM pause, the device needs up to 9 µs to detect a too high junction
temperature. If the PFM burst is shorter than this delay, the device does not detect a too high junction
temperature. As long as one converter is in PWM, thermal shutdown is always active.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS6244x has two operating modes. Forced PWM mode is discussed in this section and PWM/PFM as
discussed in 节9.4.2.
With the MODE/SYNC pin set to high, the TPS6244x operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS6244x follows the frequency applied to the pin. The frequency must be in a range the device can operate at,
taking the minimum on time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of approximately 0.8 A. When the peak inductor current
drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time
of typically 30 ns is reached, the TPS6244x skips switching cycles while it approaches 100% mode. In 100%
mode, the device keeps the high-side switch on continuously. The high-side switch stays turned on as long as
the output voltage is below the target. In 100% mode, the low side switch is turned off. The maximum dropout
voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series resistance of the
inductor and the load current.
9.4.4 Current Limit and Short-Circuit Protection
The TPS6244x is protected against overload and short circuit events. The converter is not switching with the
fixed frequency when in current limit. The converter resumes the fixed frequency operation when the converter
leaves current limit condition. If the inductor current exceeds the current limit, ILIMH, the high-side switch is turned
off and the low-side switch is turned on to ramp down the inductor current. The high-side switch turns on again
only if the current in the low-side switch has decreased below the low-side current limit. This can cause bursts or
single pulses between the high-side and low-side current limit. Due to internal propagation delay, the actual
current can exceed the static current limit. The dynamic current limit is given as:
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V
L
I
= I
+
× t
PD
(4)
peak typ
LIMH
L
where
• ILIMH is the static current limit as specified in the electrical characteristics.
• L is the effective inductance at the peak current.
• VL is the voltage across the inductor (VIN –VOUT).
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
− V
L
IN
OUT
I
= I
+
× 50ns
(5)
peak typ
LIMH
9.4.5 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active after the TPS6244x has been enabled at least once since the supply voltage was applied.
The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage
lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output
discharge is not activated during a current limit or foldback current limit event.
9.4.6 Soft Start
The internal soft-start circuitry controls the output voltage slope during start-up. This action avoids excessive
inrush current and ensures a controlled output voltage rise time. This action also prevents unwanted voltage
drops from high impedance power sources or batteries. When EN1 and EN2 are set high, the device starts
switching after tDelay. The output voltage is ramped with a slope defined by tRamp
.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS6244x is adjustable. The output voltage can be programmed for output voltages
from 0.6 V to 5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600
mV. The value of the output voltage is set by the selection of the resistor divider from 方程式 6. TI recommends
to choose resistor values, which allows a current of at least 6 µA, meaning the value of R2 mu×–st not exceed
100 kΩ. TI recommends lower resistor values for highest accuracy and most robust design.
V
OUT
R = R ×
− 1
(6)
1
2
V
FB
10.1.2 External Component Selection
10.1.2.1 Inductor Selection
The TPS6244x is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.
Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on
efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple, which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly.
The inductor selection is affected by several effects like the following:
• Inductor ripple current
• Output ripple voltage
• PWM-to-PFM transition point
• Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR).
THe following equation calculates the maximum inductor current.
ΔI
L max
2
I
= I
+
(7)
(8)
L max
OUT max
V
OUT
V
OUT × 1 −
V
IN
1
ΔI
=
×
f
L max
L
min
sw
where
• IL(max) is the maximum inductor current.
• ΔIL(max) is the peak-to-peak inductor ripple current.
• Lmin is the minimum inductance at the operating point.
表10-1. Typical Inductors
NOMINAL
SWITCHING
FREQUENCY
DIMENSIONS [L × B
× H] mm
TYPE
INDUCTANCE [µH]
CURRENT [A](1)
FOR DEVICE
MANUFACTURER(2)
DFE201210U-
R47M
0.47 µH, ±20%
0.68 µH, ±20%
see data sheet
see data sheet
TPS62442
TPS62441
2.25 MHz
2.25 MHz
2.0× 1.2 × 1.0
2.0 × 1.2 × 1.0
Murata
Murata
DFE201210U-
R68M
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TYPE
表10-1. Typical Inductors (continued)
NOMINAL
SWITCHING
FREQUENCY
DIMENSIONS [L × B
× H] mm
INDUCTANCE [µH]
CURRENT [A](1)
FOR DEVICE
MANUFACTURER(2)
DFE201610E-
R47M#
0.47 µH, ±20%
see data sheet
TPS62442
2.25 MHz
2.0 × 1.6 × 1.0
Murata
XEL3515-561ME
XFL4015-701ME
XFL4015-471ME
0.56 µH, ±20%
0.70 µH, ±20%
0.47 µH, ±20%
4.5
5.3
5.4
TPS62442
TPS62442
TPS62442
2.25 MHz
2.25 MHz
2.25 MHz
3.5 × 3.2 × 1.5
4.0 × 4.0 × 1.6
4.0 × 4.0 × 1.6
Coilcraft
Coilcraft
Coilcraft
TFM201610ALM-
R47MTAA
0.47 µH, ±20%
5.8
TPS62442
2.25 MHz
2.0 × 1.6 × 1.0
TDK
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third-Party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. TI recommends to add a margin of about 20%. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.2.2 Capacitor Selection
10.1.2.2.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.2.2.2 Output Capacitor
The architecture of the TPS6244x allows the use of tiny ceramic output capacitors with low-equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, use X7R or X5R
dielectric. Using a higher value has advantages like smaller voltage ripple and a tighter DC output accuracy in
power save mode. By changing the device compensation with a resistor from COMP/FSET to GND, the device
can be compensated in three steps based on the minimum capacitance used on the output. The maximum
capacitance is 200 µF in any of the compensation settings.
10.2 Typical Application
L1
0.47 µH
VIN
TPS6244x
VOUT1
COUT1
2.75 V - 6 V
VIN1
SW1
CFF1
VIN2
EN1
R1
R2
CIN1, CIN2
FB1
2 × 10
µF
2 × 4.7 µF
EN2
L2
0.47 µH
MODE/SYNC
SW2
VOUT2
COUT2
CFF2
V+
R3
R4
FB2
2 × 10
µF
COMP/FSET
R5
RCF
PG1
V+
R6
PG2
GND
GND
图10-1. Typical Application Schematic
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10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
V
OUT
R = R ×
− 1
(9)
1
2
V
FB
With VFB = 0.6 V:
表10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
VOUT
R1, R3
R2, R4
CFF1, CFF2
EXACT OUTPUT VOLTAGE
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
1.101 V
1.2 V
39.2 kΩ
68 kΩ
1.5 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.803 V
2.5 V
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to 表8-1.
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D000
D002
D004
D001
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-2. Efficiency Versus Output Current
图10-3. Efficiency Versus Output Current
100
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
VIN = 2.75 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D003
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-4. Efficiency Versus Output Current
图10-5. Efficiency Versus Output Current
100
95
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
VIN = 2.75 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D005
VOUT = 1.2 V
PFM
TA = 25°C
VOUT = 1.2 V
PWM
TA = 25°C
图10-6. Efficiency Versus Output Current
图10-7. Efficiency Versus Output Current
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10.2.3 Application Curves (continued)
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D006
D007
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图10-8. Efficiency Versus Output Current
图10-9. Efficiency Versus Output Current
90
85
80
75
70
65
60
55
50
45
40
85
80
75
70
65
60
55
50
45
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D008
D009
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图10-10. Efficiency Versus Output Current
图10-11. Efficiency Versus Output Current
3.36
3.35
3.34
3.33
3.32
3.31
3.3
3.36
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.29
3.28
3.27
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D010
D011
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-12. Output Voltage Versus Output Current
图10-13. Output Voltage Versus Output Current
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10.2.3 Application Curves (continued)
1.84
1.836
1.832
1.828
1.824
1.82
1.84
1.836
1.832
1.828
1.824
1.82
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.816
1.812
1.816
1.812
1.808
1.804
1.8
1.808
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.804
1.8
1.796
1.792
1.796
1.792
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D012
D014
D016
D013
D015
D017
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-14. Output Voltage Versus Output Current
图10-15. Output Voltage Versus Output Current
1.2275
1.225
1.2225
1.22
1.21
1.2075
1.205
1.2025
1.2
1.2175
1.215
1.2125
1.21
1.1975
1.195
1.1925
1.19
1.2075
1.205
1.2025
1.2
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.1875
1.185
1.1825
1.1975
1.195
1.1925
100m
1m
10m
Ouput Current (A)
100m
1
100m
1m
10m
Ouput Current (A)
100m
1
VOUT = 1.2 V
PFM
TA = 25°C
VOUT = 1.2 V
PWM
TA = 25°C
图10-16. Output Voltage Versus Output Current
1.03
图10-17. Output Voltage Versus Output Current
1.0075
1.005
1.0025
1
0.9975
0.995
0.9925
0.99
1.0275
1.025
1.0225
1.02
1.0175
1.015
1.0125
1.01
0.9875
0.985
0.9825
0.98
0.9775
0.975
0.9725
0.97
1.0075
1.005
1.0025
1
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
0.9975
0.995
0.9925
0.9675
100m
1m
10m
Ouput Current (A)
100m
1
100m
1m
10m
Ouput Current (A)
100m
1
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图10-18. Output Voltage Versus Output Current
图10-19. Output Voltage Versus Output Current
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10.2.3 Application Curves (continued)
0.634
0.63
0.606
0.605
0.604
0.603
0.602
0.601
0.6
0.626
0.622
0.618
0.614
0.61
0.599
0.598
0.597
0.596
0.595
0.594
0.606
0.602
VIN = 2.75 V
VIN = 3.3 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
0.598
VIN = 4.0 V
0.594
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D018
D019
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图10-20. Output Voltage Versus Output Current
图10-21. Output Voltage Versus Output Current
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-23. Load Transient Response
图10-22. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-24. Load Transient Response
图10-25. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-26. Load Transient Response
图10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-28. Load Transient Response
图10-29. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-31. Load Transient Response
图10-30. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 3.3 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 3.3 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-33. Line Transient Response
图10-32. Line Transient Response
VOUT = 1.8 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.8 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-35. Line Transient Response
图10-34. Line Transient Response
VOUT = 1.2 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.2 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-37. Line Transient Response
图10-36. Line Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.0 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.0 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-39. Line Transient Response
图10-38. Line Transient Response
VOUT = 0.6 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 0.6 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-41. Line Transient Response
图10-40. Line Transient Response
VOUT = 3.3 V
IOUT = 3 A
图10-43. Output Voltage Ripple
PWM
TA = 25°C
VOUT = 3.3 V
IOUT = 0.3 A
图10-42. Output Voltage Ripple
PFM
TA = 25°C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
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10.2.3 Application Curves (continued)
VOUT = 1.8 V
IOUT = 0.3 A
PFM
TA = 25°C
VOUT = 1.8 V
IOUT = 3 A
PWM
TA = 25°C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
图10-44. Ouput Voltage Ripple
图10-45. Output Voltage Ripple
VOUT = 3.3 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.8 V
IOUT1 = 2 A
PWM
TA = 25°C
VIN = 5.0 V
VIN = 5.0 V
IOUT2 = 2 A
图10-46. Start-Up Timing
图10-47. Start-Up Timing
VOUT = 1.2 V
IOUT1 = 1 A
PWM
TA = 25°C
VIN = 5.0 V
VOUT = 1.0 V
IOUT1 = 3 A
PWM
TA = 25°C
IOUT2 = 3 A
VIN = 5.0 V
图10-48. Start-Up Timing
图10-49. Start-Up Timing
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10.2.3 Application Curves (continued)
VOUT = 0.6 V
IOUT1 = 3 A
PWM
TA = 25°C
VIN = 5.0 V
图10-50. Start-Up Timing
10.3 Power Supply Recommendations
The TPS6244x device family has no special requirements for its input power supply. The output current of the
input power supply must be rated according to the supply voltage, output voltage, and output current of the
TPS6244x.
10.4 Layout
10.4.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6244x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both line and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See 图 10-51 for the recommended layout of the TPS6244x, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops which conduct an
alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB must be connected with short wires and not nearby high dv/dt signals (for example SW).
As they carry information about the output voltage, they must be connected as close as possible to the actual
output voltage (at the output capacitor). The FB resistors, R1, R2 as well as R3, R4 must be kept close to the IC
and connect directly to those pins and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread
the heat into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS62442EVM-122 User's Guide.
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10.4.2 Layout Example
图10-51. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, TPS62442EVM-122 User's Guide
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62441RQRR
TPS62442RQRR
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RQR
RQR
14
14
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
62441
441
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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OTHER QUALIFIED VERSIONS OF TPS62441, TPS62442 :
Automotive : TPS62441-Q1, TPS62442-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62441RQRR
TPS62442RQRR
VQFN-
HR
RQR
RQR
14
14
3000
3000
180.0
8.4
2.6
3.0
1.2
4.0
8.0
Q1
VQFN-
HR
180.0
8.4
2.6
3.0
1.2
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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17-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62441RQRR
TPS62442RQRR
VQFN-HR
VQFN-HR
RQR
RQR
14
14
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RQR 14
2.3 x 2.7, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229224/A
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PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014B
2.4
2.2
A
B
PIN 1 INDEX AREA
2.8
2.6
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.5
0.875
0.675
2X
(0.1) TYP
4
7
4X (0.2 MIN)
10X 0.5
3
1
8
(0.8 MIN)
PKG
1
0.525
0.325
1.125
0.925
10
5X
0.575
0.375
6X
11
14
PIN 1 ID
(45°X 0.125)
0.3
0.2
0.1
14X
C
A B
0.05
C
4229193/A 11/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014B
(2.075)
(0.7375)
(R0.05) TYP
14
11
2X (0.975)
1
10
(1.225)
(2.425) (2.125)
PKG
8
3
14X (0.25)
7
4
6X (0.675)
5X (0.625)
10X (0.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4229193/A 11/2022
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014B
(2.075)
(0.7375)
(R0.05) TYP
14
11
2X (0.975)
1
10
(1.225)
(2.425) (2.125)
PKG
8
3
14X (0.25)
7
4
6X (0.675)
5X (0.625)
10X (0.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 18X
4229193/A 11/2022
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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