TPS62510_16 [TI]
High Efficiency Step-Down Converter;
| 型号： | TPS62510_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Efficiency Step-Down Converter |
| 文件： | 总24页 (文件大小：2063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62510
www.ti.com
SLVS651–MAY 2006
1.5-A, LOW V HIGH EFFICIENCY STEP-DOWN CONVERTER
I
FEATURES
DESCRIPTION
•
1.8-V to 3.8-V Input Voltage Range
The TPS62510 family are high-efficiency step-down
converters targeted for operation from a 1.8-V to
3.8-V input voltage rail, ideally suited for 2-cell
Alkaline or NiMHd applications. The TPS62510 is
also ideal as a point-of-load regulator running from a
fixed 3.3-V, 2.5-V or 1.8-V input voltage rail. The
converter operates in fixed frequency PWM mode
switching at 1.5 MHz with the MODE pin high.
Pulling the MODE pin low enables the high efficiency
mode. In high efficiency mode, the device operates
with a 1.5 MHz fixed frequency PWM at nominal load
current, and automatically enters the Power Save
Mode at light load currents. For maximum system
reliability, the converter features Output Voltage
Tracking using the OVT pin to allow sequencing, and
to allow for the output voltage to track an external
voltage applied to this pin.
•
Up to 96% High Efficiency Synchronous
Step-Down Converter
•
•
1.5-MHz Fixed Frequency PWM Operation
1% Output Voltage Accuracy in Fixed
Frequency PWM Mode
•
Power Save Mode Operation for High
Efficiency Over the Entire Load Current
Range
•
•
•
22-µA Quiescent Current
Fixed and Adjustable Output Voltage
Output Voltage Tracking (OVT) for Reliable
Sequencing
•
Available in a 10-Pin QFN (3 x 3 mm) Package
APPLICATIONS
•
•
•
•
•
•
Portable Devices (Mobile Phone, PDA)
2-Cell NiMHd/Alkaline Applications
Hard Disc Drives
Point-Of-Load Regulation
Notebook Computers
WiMAX and WLAN Applications
V
I
V
O
95
L1
TPS62510
VI = 1.9 V
1.8 V to 3.8 V
1.5 V to 1.5 A
2.2 mH
10
1
(Mode Low)
90
PVIN
AVIN
EN
SW
FB
C3
22 pF
R1
Rf 1 W
9
VI = 2.4 V
C1
22 mF
4
8
3
2
85
300 kW
C2
22 mF
(Mode Low)
Cf
100 nF
80
6
PG
R2
200 kW
75
5
OVT
AGND
PGND
VI = 1.9 V
(Mode High)
70
7
MODE
VI = 2.4 V
VI = 3.2 V
(Mode High)
65
(Mode Low)
VI = 3.2 V
60
(Mode High)
55
V
= 1.2 V
O
50
0.01
0.1
1
10
100
1 k
10 k
I
L
- Load Current- mA
Figure 1. Typical Application
Figure 2. Efficiency vs Load Current
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS62510
www.ti.com
SLVS651–MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
10-PIN QFN PACKAGE(1)
TA
VOLTAGE OPTION
PACKAGE MARKING
(DRC)
Adjustable
Fixed(2)
TPS62510DRC
BQA
-40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
(2) Contact the local sales office for fixed output voltage options.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 4
UNIT
VS
Supply voltage at PVIN, AVIN
Voltage at EN, MODE, OVT, FB, PG(2)
Voltage at SW(2)
V
V
V
–0.3 to 4
-0.3 to VI + 0.3
Continuous total power dissipation
Continuous Power Dissipation
Operating junction temperature range
Storage temperature,
See the Dissipation Rating Table
TJ
-40 to 150
-65 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS(1)
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
RTHJA
DRC
50 °C/W
2 W
1.1 W
0.8 W
(1) See the electrical graphs regarding power dissipation.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX
3.8
UNIT
V
VI
Input voltage range on pins PVIN and AVIN
Output voltage range
VO
IO
0.6
VI
V
Output current, VI = 1.8 V to 3.6 V
Inductor value
Input capacitor value(1)
Output capacitance value(1)
Operating ambient temperature
Operating junction temperature
1500
mA
µH
µF
µF
°C
°C
L
2.2
10
22
CI
CO
TA
TJ
-40
85
–40
125
(1) See the application section for more information.
2
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
ELECTRICAL CHARACTERISTICS
VIN = 3.3 V, OVT = EN = VIN, MODE = GND, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range
1.8
3.8
30
V
Power Save Mode quiescent current
AVIN + PVIN
FB = FB nominal + 5%, MODE = low
22
µA
I(q)
PWM Mode quiescent current into AVIN
Shutdown current into PVIN + AVIN
Undervoltage lockout threshold on AVIN
Undervoltage lockout hysteresis
Thermal shutdown threshold
MODE = high
4.4
0.1
5
5
mA
µA
V
I(SD)
EN = low, SW = GND
(1)
UVLO
V(AVIN) falling
1.55
150
160
20
1.58
mV
°C
°C
Increasing junction temperature
VI = 1.8 V to 3.8 V
T(SD)
Thermal shutdown hysteresis
CONTROL SIGNALS EN, MODE
VIH
VIL
IIB
High level input voltage
Low level input voltage
Input bias current
1.2
V
V
0.4
0.1
0.01
µA
MHz
MODE synchronization range
1.15
75
2.25
f(sync)
Duration of high or low level for synchronization
signal(2)
ns
OUTPUT VOLTAGE TRACKING (OVT)
IIB
Input bias current
OVT offset voltage
0.001
0.05
15
µA
VOS
VOS = V(OVT) - V(FB), 0.1 V < V(OVT) < 0.5 V
Feedback voltage rising
-15
mV
POWER GOOD (PG)
Power Good threshold
-7% VO
2% VO
-5% VO -3% VO
V
V
V(th)
Power Good Hysteresis
Low level voltage
7% VO
0.3
VOL
I(PG) = 1 mA
V(PG) = 3.8 V
V
Ilkg
Power Good leakage current
1
120
80
100
nA
OUTPUT
VI = V(GS) = 1.8 V
VI = V(GS) = 3.3 V
VI = 3.6 V
330
170
10
rDS(on)
Ilkg
P-channel MOSFET on-resistance
P-channel leakage current
mΩ
µA
VI = V(GS) = 1.8 V
VI = V(GS) = 3.3 V
V(DS) = 3.6 V
200
130
10
rDS(on)
N-channel MOSFET on-resistance
mΩ
Ilkg
IF
N-channel leakage current
Forward current limit (P- and N-channel)
Oscillator frequency
µA
A
1.8 V < VI < 3.8 V
MODE = high
1.75
1.3
2.00
1.5
2.25
1.7
fs
MHz
V
Vref
Reference voltage
0.6
VI = VO + 0.3 V ; 0 mA ≤ IO ≤ 1.5 A
MODE = low (PFM / PWM)
-2
-1
5
(3)
VFB
Feedback regulation voltage
%
VI = VO + 0.3 V ; 0 mA ≤ IO ≤ 1.5 A
MODE = high (forced PWM operation)
1
IFB
Feedback bias current
V(FB) = 0.6 V, EN = high
0.001
0
0.05
µA
%/V
%/A
µs
Line Regulation
VI = VO + 0.3 V (min 1.8 V) to 3.8 V; IO = 800 mA
IO = 10 mA to 1500 mA
Load Regulation
0.1
tSS
Soft start time
VO ramping from 5% to 95% of nominal value
VI > VO, 0 V ≤ V(SW) ≤ VI
750
1000
23
Leakage resistance from SW pin to GND
Leakage resistance from FB pin to GND
700
17
kΩ
EN = low
(1) The undervoltage lockout threshold is detected at the AVIN pin. Current through the RC filter causes a UVLO trip at higher VI
(2) The minimum and maximum duty cycle applied to the MODE pin is calculated as:
D(min) = 75 ns × f(sync) and D(max) = 1 - 75 ns × f(sync)
.
(3) When using the output voltage tracking function, the feedback regulates to the voltage applied to OVT as long as the OVT < 0.6 V.
3
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
PIN ASSIGNMENT
DRC Package
(Top View)
1
10
SW
PVIN
2
9
PGND
AGND
FB
AVIN
3
8
PG
4
7
MODE
5
6
OVT
EN
A. The exposed Thermal Die is connected to AGND.
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
NO.
1
SW
Switch pin of the converter. The inductor is connected here.
Power ground for the converter
PGND
AGND
2
3
Analog ground connection
Feedback voltage sense input. Connect directly to VO or to the midpoint of an external voltage divider for
the adjustable version.
FB
4
5
6
7
I
I
Output Voltage Tracking input. The signal applied to this pin is used as reference voltage overiding the
internal reference voltage when it is below the internal 0.6-V reference. If this feature is not used, the
OVT pin is connected to VI.
OVT
EN
Enable pin. A logic high enables the regulator, a logic low disables the regulator. This pin needs to be
terminated and not left floating.
I
This pin is used to force fixed frequency PWM operation or to synchronize the device to an external clock
signal. With MODE = high, the device is forced into 1.5-MHz fixed frequency PWM operation. With
MODE = low, the device automatically enters the Power Save Mode at light load currents.
MODE
I
Power Good indication. This is a open drain output that is low when the device is disabled or the output
voltage drops 10% below target.
PG
8
9
O
Power supply for control circuitry. Must be connected to the same voltage supply as PVIN through RC
filter.
AVIN
PVIN
10
Input voltage for the power stage. VIN must be connected to the same voltage supply as AVIN.
Connect the PowerPAD to analog ground AGND.
PowerPAD™
C2
4
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
FUNCTIONAL BLOCK DIAGRAM
PG
MODE
PVIN
Q3
PLL
High Side
Current
Sense
Summing
Comparator
1.5 MHz
SawTooth
Q1
0.6 V
VOUT
Generator
(See Note A)
MOSFET Driver
Loop
Anti Shoot Through
Converter Control
Logic
EN
SW
Compensation
Error Amplifier
R1
FB
V
ref
0.6 V
R2
Q2
PFM
Analog
Comparator
Softstart
V
ref
0.6 V
Low Side
Current
Sense
PFM/PWM
Transition
V
V
- 2%
ref
ref
0.6 V
Bandgap
AVIN
R3
Undervoltage
Lockout
Output Voltage
Thermal Shutdown
Tracking
R4
0.6 V
Q4
EN
AGND
OVT
PGND
A. R1 and R2 are only used for the fixed output voltage version.
5
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
3, 4(1)
5, 6
7
η
Efficiency
vs Load current
vs Input voltage
vs Temperature
I(q)
f
No load quiescent current
Frequency
Line transient response
8(1)
Load transient response (mode = high)
Load transient response (mode = low)
Falling load transient (mode = low)
Rising load transient (mode = low)
Power Save Mode Operation, VOUT
Start-up, VOUT
9(1)
10(1)
11(1)
12(1)
13(1)
14(1)
15
rDS(on)
P-CHannel (PMOS)
vs Input voltage
N-Channell (NMOS)
vs Input voltage
16
FB Offset
vs Input Voltage on OVT
17
(1) Generated with the circuit in Figure 1 with L1 = 2.2 µH (Wuerth 74455022).
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
95
VI = 1.9 V
VI = 3.2 V
(Mode Low)
(Mode Low)
95
90
85
80
75
70
65
60
90
VI = 2.4 V
(Mode Low)
85
80
VI = 3.2 V
VI = 1.9 V
75
70
65
60
(Mode High)
(Mode High)
VI = 3.6 V
(Mode Low)
VI = 2.4 V
VI = 3.2 V
(Mode Low)
(Mode High)
VI = 3.6 V
(Mode High)
VI = 3.2 V
(Mode High)
V
= 2.5 V
O
55
55
V
= 1.2 V
O
50
50
0.01
0.1
1
10
100
1 k
10 k
0.01
0.1
1
10
100
1 k
10 k
I
L
- Load Current- mA
I
L
- Load Current- mA
Figure 4.
Figure 3.
6
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
NO LOAD QUIESCENT CURRENT
NO LOAD QUIESCENT CURRENT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
30
28
26
24
6
Mode = Low
Mode = High
o
5
25 C
o
85 C
o
85 C
4
3
2
o
o
22
20
18
16
14
12
10
-40 C
25 C
o
-40 C
1
0
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 5.
Figure 6.
FREQUENCY
vs
TEMPERATURE
LINE TRANSIENT RESPONSE
1610
1600
1590
1580
VI = 3.8 V
V = 3 V to 3.6 V
I
(500 mV/div)
VI = 3.3 V
1570
1560
1550
1540
1530
1520
1510
VI = 1.8 V
V
O
(50 mV/div AC Coupled)
-40
-20
0
20
40
60
80
t - Time = 500 ms/div
o
Temperature - C
Figure 7.
Figure 8.
7
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
LOAD TRANSIENT RESPONSE MODE = HIGH
LOAD TRANSIENT MODE = LOW
V
O
(20 mV/div)
V
O
(50 mV/div)
I
= 150 mA to 1300 mA
L
I
= 150 mA to 1300 mA
L
(500 mA/div)
(500 mA/div)
t - Time = 1 ms/div
t - Time = 1 ms/div
Figure 9.
Figure 10.
FALLING LOAD TRANSIENT RESPONSE MODE = LOW
RISING LOAD TRANSIENT RESPONSE MODE = LOW
V
O
V
O
(50 mV/div)
(50 mV/div)
I
L
= 150 mA to 1300 mA
I
L
= 1300 mA to 150 mA
(500 mA/div)
(500 mA/div)
t - Time = 20 ms/div
Figure 11.
t - Time = 20 ms/div
Figure 12.
8
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
POWER SAVE MODE OPERATION
SOFT START-UP
V
= 1.8 V
O
V
(EN)
V
(20 mV/div)
O
(5 V/div)
V
(2 V/div)
V
= 1.8 V
(SW)
O
(1 V/div)
I
and I
(AVIN)
(PVIN)
I
= 150 mA (500 mA/div)
L
(500 mA/div)
t - Time = 200 ms/div
t - Time = 2 ms/div
Figure 13.
Figure 14.
PMOS rDS(on)
vs
INPUT VOLTAGE
NMOS rDS(on)
vs
INPUT VOLTAGE
0.2
0.25
0.2
0.15
o
85 C
o
0.15
85 C
o
25 C
o
0.1
25 C
0.1
o
o
-20 C
-20 C
0.05
0.05
0
0
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 15.
Figure 16.
9
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
FB OFFSET
vs
VOLTAGE ON VOUT
15
10
5
o
o
25 C
-40 C
o
85 C
0
-5
-10
0
OVT £ 0.6 V,
V = 2.4 V,
I
I
= 1 mA
O
0
0.1
0.2
0.3
0.4
0.5
0.6
Voltage on OVT - V
Figure 17.
10
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
DETAILED DESCRIPTION
The TPS62510 has two target areas of operation. The high efficiency area is defined when the MODE pin is
held low. In this condition, the converter operates at typically 1.5-MHz fixed frequency PWM (pulse width
modulation) at moderate to heavy load currents. At light load currents, the converter automatically enters power
save mode and operates with PFM (pulse frequency modulation). Low noise operation is defined when the
MODE pin is held high. In this condition, the converter is forced into fixed frequency PWM mode and runs at
1.5 MHz. The converter is capable of delivering 1.5-A output current.
The TPS62510 can also be synchronized to an external clock in the frequency range between 1.15 MHz and
2.25 MHz. Synchronization is aligned with the falling edge of the incoming clock signal. This allows simple
synchronization of two step-down converters running 180° out of phase reducing overall input RMS current.
During PWM operation, the converters use a unique fast response voltage mode control scheme with input
voltage feed-forward to achieve good line, and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded.
After the adaptive dead time, which is used to prevent shoot through current, the N-channel MOSFET rectifier is
turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the
N-channel rectifier, and turning on the P-channel switch.
Power Save Mode operation (MODE)
When the MODE pin is connected to GND, the device automatically enters the power save mode when the
average output current reaches the appropriate threshold. This reduces the switching frequency and minimum
quiescent current, maintaining efficiency over the entire load current range. For low noise operation, the device
can be forced into fixed frequency PWM mode operating at 1.5 MHz over the entire load current range. This is
done by pulling the Mode pin high.
Many applications require a low output ripple voltage during power save mode. This is accomplished by a single
threshold PFM comparator which allows control of the output voltage ripple in power save mode. The larger the
output capacitor value, the smaller the output voltage ripple (see Figure 13). During power save mode, the
device monitors the output voltage with the PFM comparator. As soon as the output voltage falls below the
nominal output voltage, the device starts switching for a minimum of 1 µs (typical), or until the output voltage is
above the nominal output voltage.
Power Save Mode Transition Thresholds
To achieve an accurate transition into and out of power save mode, the device monitors the average inductor
current which is equal to the average output current. The device enters power save mode when the average
output current is ≤ I(PFM enter) as calculated in Equation 1.
VIN
I
=
(PFM enter)
22 W
(1)
The device leaves the power save mode when the output current is ≥ I(PFM enter)
.
VIN
I
=
(PFM leave)
17 W
(2)
To minimize any delay times during a load transients, the device enters PWM mode when the output voltage is
2% below the nominal value, and the PFM/PWM transition comparator trips.
Output Voltage Tracking (OVT)
In applications where a processor or FPGA is powered, it is important that the I/O voltage and core voltage
start-up in a controlled way to avoid possible processor and FPGA latch-up. To implement this, the TPS62510
has an Output Voltage Tracking feature where the internal reference voltage for the error amplifier follows the
voltage applied to OVT, until OVT reaches Vref. Vref is the nominal internal reference voltage, typically 0.6 V. The
tracking feature is available with the fixed output voltage version as well as with the adjustable output voltage
version. Figure 18 shows a typical application where an external voltage (V1) is applied to OVT pin using a
resistor divider.
11
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
DETAILED DESCRIPTION (continued)
V
L1
V2
I
TPS62510
1.8 V to 3.8 V
1.5 V to 1.5 A
2.2 mH
1
10
PVIN
AVIN
EN
SW
C3
22 pF
R1
Rf 1 W
C2
9
4
8
3
2
C1
300 kW
FB
22 mF
10 mF
6
Cf
PG
R2
100 nF
200 kW
V1
5
OVT
AGND
Output of External
DC-DC Converter
e.g. I/O Rail
R3
7
300 kW
MODE
PGND
R4
200 kW
Figure 18. Output Voltage Tracking, V2 Tracks V1
In this application, the output voltage (V2) of the TPS6251x tracks the voltage (V1) as long as the OVT voltage
is smaller then the internal device reference voltage, Vref = 0.6 V. Depending on the resistor divider (R3, R4), the
tracking can be adjusted. V2 can rise faster, at the same timer, or slower than V1.
V1
V2
R3
R1
<
R4
R2
Time
Figure 19. V2 Comes Up Before V1
Simultaneous tracking is achieved when the resistor divider (R3/R4) is equal to the resistor divider of the
TPS65210.
R3
V2 - V
1.5 V - 0.6 V
ref
=
=
= 1.5
R4
V
0.6 V
ref
(3)
V2
R4
R3 + R4
V2
200 k
300 k + 200 k
1.5 V
V2
= V
x
= V1 x
x
= V1
x
= V1
(tracking)
(OVT)
V
V
0.6 V
ref
ref
(4)
Equation 3 and Equation 4 are used with the fixed and adjustable version of the TPS6251x. If V2 needs to rise
before V1, then R4 must be increased as shown in Figure 20.
V1
V2
R3
R1
=
R4
R2
Time
Figure 20. Simultaneous Tracking of V2 and V1
12
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
DETAILED DESCRIPTION (continued)
If V2 needs to rise after V1, then R4 must be decreased as shown in Figure 21.
V1
V2
R3
R1
>
R4
R2
Time
Figure 21. V2 Comes Up After V1
Soft Start
The converter has an internal soft start circuit that limits the inrush current during start-up. The soft start is
realized by using a low current to control the output of the error amplifier during startup. The soft start time is
typically 750 µs to ramp the output voltage to 95% of the final target value. There is a short delay of typically
120 µs between the converter being enabled and switching activity actually starting. See the typical soft start
characteristic shown in Figure 14.
100% Duty Cycle Low Dropout Operation
The TPS62510 converter offers a low input to output voltage difference while maintaining operation with the use
of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the entire
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load
current and output voltage, and in Equation 5.
V min = V min + I max x
I O O
r
max + R
(
)
L
DS(on)
(5)
with:
IOmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = dc resistance of the inductor
VOmin = nominal output voltage minus 2% tolerance limit
Power Good
The power good output can be used for sequencing purposes, enabling a separate regulator once the output
voltage is reached, or to indicate that the output voltage is in regulation. When the device is disabled, the PG pin
is pulled low by the internal open-drain output transistor. Internally, the TPS62510 compares the feedback
voltage FB to the nominal reference voltage of typically 0.6 V. If the feedback voltage is more than 95% of this
value then the power good output goes high impedance. If the feedback voltage is less than 90% of the
reference voltage then PG pin is pulled low.
Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages. It disables the
converter. The UVLO circuit monitors the AVIN pin, the falling threshold is set internally to 1.55 V with 150-mV
hysteresis. Note that when the dc-dc converter is running, there is an input current at the AVIN pin, which is up
to 5 mA when in PWM mode. This current must be taken into consideration if an external RC filter is used at the
VCC pin to remove switching noise from the TPS62510 internal analog circuitry supply.
13
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
DETAILED DESCRIPTION (continued)
Short-Circuit Protection
The TPS62510 monitors the forward current through both the high-side and low-side power devices. This
enables the converter to limit the short-circuit current, which helps to protect the device and other circuits
connected to its output.
Thermal Shutdown
As soon as the device's junction temperature exceeds 160°C (typical), all switching activity ceases and both
high-side and low-side power transistors are off. The device continues operation once the temperature fall to
20°C (typical) below its thermal shutdown threshold of 160°C.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering, and minimizing the interference with other circuits caused by high input
voltage spikes. The converter needs a ceramic input capacitor of 22 µF. The input capacitor may be increased
without any limit for better input voltage filtering. The AVIN pin is separated from the power input of the
converter. Note that the filter resistor may affect the undervoltage lockout threshold since up to 5 mA can flow
via this resistor into the AVIN pin when the converter runs in PWM mode.
Table 1. Input Capacitor Selection
Capacitor Value
22 µF
Case Size
1206
Component Supplier
TDK C3216X5R0J226M
Comments
Ceramic
22 µF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
Output Filter Design (Inductor and Output Capacitor)
The TPS62510 step-down converter has an internal loop compensation. Therefore, the external L-C filter must
be selected to work with the internal compensation.
The internal compensation is optimized to operate with an output filter of L = 2.2 µH with an output capacitor of
CO = 22 µF. The output filter has its corner frequency per Equation 6:
1
1
=
= 22.8 kHz
ƒ
=
c
2p x L x C
2p x 2.2 mH x 22 mF
O
(6)
with
L = 2.2 µH
CO = 22 µF
As a general rule of thumb, the product LxC should not move over a wide range when selecting a different
output filter. This is because the internal compensation is designed to work with a certain output filter corner
frequency, as calculated in Equation 6. This is especially important when selecting smaller inductor or output
capacitor values that move the corner frequency to higher frequencies. However, when selecting the output filter
a low limit for the inductor value exists due to other internal circuit limitations. The minimum inductor value for
the TPS62510 should be kept at 2.2µH. Selecting a larger capacitor value is less critical because the corner
frequency drops, causing fewer stability issues.
14
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
Table 2. Output Capacitor Selection
L
CO
2.2 µH
3.3 µH
≥ 22 µF (ceramic capacitor)
≥ 22 µF (ceramic capacitor)(1)
(1) For output currents < 800 mA, a 10-µF output capacitor is sufficient.
Setting the Output Voltage Using the Feedback Resistor Divider
The external resistor divider sets the output voltage of the converter.
The output voltage is calculated as:
R1
V
O
= 0.6 V x 1 +
(
)
R2
(7)
with:
R1 + R2 ≤ 1 MΩ, and the internal reference voltage is Vref typical = 0.6 V.
To keep the operating quiescent current to a minimum, a high impedance feedback divider is selected with
R1 + R2 ≤ 1 MΩ. The sum of R1 and R2 should not be greater than 1 MΩ to avoid possible noise related
regulation issues. A feedforward capacitor is needed across the upper feedback resistor to place a zero at a
frequency of 25 kHz in the control loop. After selecting the feedback resistor values, the feedforward capacitor is
calculated as:
1
1
=
C1 =
2p x
ƒ
x R1
2p x 25 kHz x R1
z
(8)
with:
R1 = upper resistor of voltage divider, and C1 = upper capacitor of voltage divider.
Select the capacitor value that is closest to the calculated value. This capacitor is only needed when setting the
output voltage with the external divider.
Inductor Selection
For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially at
high switching frequencies where the core material has a higher impact on the efficiency. The inductor value
determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current, and
the lower the conduction losses of the converter. However, larger inductor values cause slower load transient
response. Usually, the inductor ripple current as calculated in Equation 9, should be around 20% of the average
output current.
To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the
converter plus the inductor ripple current calculated in Equation 9:
V
O
1 -
V
DI
I
L
I
L
max = I max +
O
DI = V
L
x
O
2
L x
ƒ
(9)
with:
f = Switching frequency (1.5 MHz typical)
L = Inductor value
∆IL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current occurs at maximum VI.
A more conservative approach is to select the inductor current rating just for the maximum typical switch current
limit of the converter of 2 A. See Table 3 for inductor recommendations.
15
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
Table 3. Inductor Recommendations
Inductor Value
Component Supplier
Dimensions
I(SAT) / R(DC)
2.2 µH
2.2 µH
2.2 µH
2.2 µH
2.2 µH
2.2 µH
2.2 µH
2.2 µH
Sumida CDRH2D18/HP 4R7
Wuerth 744045002
Sumida CDRH3D14
Sumida CDRH4D22
Sumida CDRH4D28
Coilcraft MSS5131
Coilcraft DO1608
3.2 mm x 3.2 mm x 2 mm
4.5 mm x 3.2 mm x 2.6 mm
4 mm x 4 mm x 1.8 mm
5 mm x 5 mm x 2.4 mm
5 mm x 5 mm x 3 mm
1.6 A / 60 mΩ
1.6 A / 110 mΩ
1.75 A / 69 mΩ
1.8 A / 25.4 mΩ
2 A / 31.3 mΩ
1.9 A / 23 mΩ
2.3 A / 28 mΩ
2.3 A / 28 mΩ
5.1 mm x 5.1 mm x 3.1 mm
6.6 mm x 4.45 mm x 2.92 mm
6.6 mm x 4.45 mm x 2.92 mm
Wuerth 74455022
Layout Guidelines
C1
L1
V
V
TPS62510
PVIN
SW
I
O
22 mF
2.2 mH
1.8 V to 3.8 V
1.5 V to 1.5 A
1
10
C3
22 pF
Rf 1 W
9
4
8
3
R1
C2
22 mF
AVIN
FB
300 kW
6
5
7
Cf
100 nF
EN
PG
R2
200 kW
OVT
AGND
2
MODE
PGND
Figure 22. Layout Guidelines
1. Place and route the power components first (C1, L1, C2).
2. The input capacitor (C1) must be placed as close as possible from PVIN to PGND.
3. The inductor must be placed as close as possible to the switch pin.
4. All ground connections (shown in bold) must be on a common ground plane or form a star ground.
5. Analog ground (AGND) and power ground (PGND) as well as the device PowerPAD™ must be tight
together.
6. The feedback network (R1, C3, R2) must be routed away from the inductor (L1) and should be grounded to
the PowerPAD™.
7. The feedback network must sense and regulate the output voltage across the output capacitor to minimize
load regulation.
16
Submit Documentation Feedback
TPS62510
www.ti.com
SLVS651–MAY 2006
APPLICATION INFORMATION
Typical Application
V
I
V
L1
O
TPS62510
1.8 V to 3.8 V
2.2 mH
1.5 V to 1.5 A
1
10
PVIN
AVIN
EN
SW
C3
22 pF
Rf 1 W
R1
9
4
8
3
C2
C1
FB
300 kW
22 mF
22 mF
Cf
100 nF
6
5
7
PG
R2
200 kW
OVT
AGND
2
MODE
PGND
Figure 23. Adjustable Version Programmed to 1.5 V
V
I
V
L1
O
TPS62510
1.8 V to 3.8 V
2.2 mH
1.5 V to 1.5 A
1
10
PVIN
AVIN
EN
SW
C3
R1
Rf 1 W
22 pF
9
C2
4
8
3
C1
300 kW
FB
22 mF
22 mF
Cf
100 nF
6
5
7
V
I
PG
R2
200 kW
OVT
AGND
R3
500 kW
2
MODE
PGND
Power Good
Figure 24. Adjustable Version Programmed to 1.5 V Using Power Good
17
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
TPS62510DRCR
TPS62510DRCRG4
TPS62510DRCT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
10
10
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
SON
SON
DRC
DRC
DRC
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS62510DRCTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS62510DRCR
TPS62510DRCT
DRC
DRC
10
10
SITE 41
SITE 41
3.3
3.3
3.3
3.3
1.1
1.1
8
8
12
12
Q2
Q2
180
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS62510DRCR
TPS62510DRCT
DRC
DRC
10
10
SITE 41
SITE 41
346.0
190.0
346.0
212.7
29.0
31.75
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
TPS62560DRV
1.2A SWITCHING REGULATOR, 2250kHz SWITCHING FREQ-MAX, PDSO6, 2 X 2 MM, 0.80 MM HEIGHT, PLASTIC, SON-6
TI
©2020 ICPDF网 联系我们和版权申明