TPS62665 [TI]
1000-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING; 1000毫安， 6 MHz的高效率降压转换器芯片级封装
| 型号： | TPS62665 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1000-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING |
| 文件： | 总27页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSP-6
TPS6266x
www.ti.com
SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
1000-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER
IN CHIP SCALE PACKAGING
Check for Samples: TPS6266x
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
•
•
•
91% Efficiency at 6MHz Operation
The TPS6266x device is
a
high-frequency
31mA Quiescent Current
synchronous step-down dc-dc converter optimized for
battery-powered portable applications. Intended for
low-power applications, the TPS6266x supports up to
1000mA peak load current, and allows the use of low
cost chip inductor and capacitors.
Wide VIN Range From 2.3V to 5.5V
6MHz Regulated Frequency Operation
Best in Class Load and Line Transient
±2% Total DC Voltage Accuracy
Automatic PFM/PWM Mode Switching
Low Ripple Light-Load PFM Mode
Fast Turn-On Time, <60-ms Start-Up Time
With a wide input voltage range of 2.3V to 5.5V, the
device supports applications powered by Li-Ion
batteries with extended voltage range. Different fixed
voltage output versions are available from 1.2V to
2.3V.
Integrated Active Power-Down Sequencing
(Optional)
The TPS6266x operates at a regulated 6-MHz
switching frequency and enters the power-save mode
operation at light load currents to maintain high
efficiency over the entire load current range.
•
•
Current Overload and Thermal Shutdown
Protection
Three Surface-Mount External Components
Required (One MLCC Inductor, Two Ceramic
Capacitors)
The PFM mode extends the battery life by reducing
the quiescent current to 31mA (typ) during light load
and
standby
operation.
For
noise-sensitive
•
Complete Sub 1-mm Component Profile
Solution
Total Solution Size <12 mm2
applications, the device can be forced into fixed
frequency PWM mode by pulling the MODE pin high.
In the shutdown mode, the current consumption is
reduced to less than 1mA.
•
•
Available in a 6-Pin NanoFree™ (CSP)
The TPS6266x is available in an 6-pin chip-scale
package (CSP).
APPLICATIONS
•
•
•
•
Cell Phones, Smart-Phones
PDAs, Pocket PCs
Portable Hard Disk Drives
DC/DC Micro Modules
100
90
80
70
60
50
40
30
500
450
V = 3.6 V,
I
V
= 1.8 V
O
400
350
300
250
200
150
100
Efficiency
PFM/PWM Operation
V
V
OUT
TPS62661
VIN
BAT
L
3.0 V .. 5.5 V
1.8 V @ 1000mA
SW
0.47 mH
C
I
FB
Power Loss
PFM/PWM Operation
EN
C
O
4.7 mF
4.7 mF
20
10
0
MODE
GND
50
0
0.1
1
10 100
- Load Current - mA
1000
I
Figure 1. Smallest Solution Size Application
O
Figure 2. Efficiency vs Load Current
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS6266x
SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PACKAGE
MARKING
CHIP CODE
PART
NUMBER
OUTPUT
VOLTAGE
DEVICE
SPECIFIC FEATURE
(3)
TA
PACKAGE
ORDERING(2)
TPS62660
TPS62661(4)
TPS62665(4)
1.8V
1.8V
1.2V
TPS62660YFF
OO
-40°C to 85°C
Fast start-up time
YFF-6
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The YFF package is available in tape and reel. Add an R suffix (TPS62660YFFR) to order quantities of 3000 parts. Add a T suffix
(TPS62660YFFT) to order quantities of 250 parts.
(3) Internal tap points are available to facilitate output voltages in 25mV increments.
(4) Product preview.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Voltage at VIN, SW(2)
Voltage at FB(2)
–0.3 V to 7 V
–0.3 V to 3.6 V
–0.3 V to VI + 0.3 V
1000 mA
VI
IO
(2)
Voltage at EN, MODE
Peak output current
Power dissipation
Operating temperature range(3)
Maximum operating junction temperature
Storage temperature range
Human body model
Internally limited
–40°C to 85°C
150°C
TA
TJ (max)
Tstg
–65°C to 150°C
2 kV
(4)
ESD rating
Charge device model
1 kV
Machine model
200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (qJA), as given by the following equation: TA(max)= TJ(max)–(qJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
(4) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS(1)
POWER RATING
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
(2)
(2)
PACKAGE
RqJA
RqJB
T
YFF-6
125°C/W
53°C/W
800mW
8mW/°C
(1) Maximum power dissipation is a function of TJ(max), qJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / qJA
(2) This thermal data is measured with high-K board (4 layers board according to JESD51-7 JEDEC standard).
.
2
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Product Folder Link(s): TPS6266x
TPS6266x
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SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = -40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 1.8V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
VI
IQ
Input voltage range
2.3
5.5
55
V
mA
mA
mA
V
IO = 0mA. Device not switching
31
7.6
Operating quiescent current
IO = 0mA, PWM mode
EN = GND
I(SD)
Shutdown current
0.2
1
UVLO
Undervoltage lockout threshold
2.05
2.1
ENABLE, MODE
VIH
VIL
Ilkg
High-level input voltage
1.0
V
V
Low-level input voltage
Input leakage current
0.4
1
Input connected to GND or VIN
0.01
mA
POWER SWITCH
VI = V(GS) = 3.6V, PWM mode
VI = V(GS) = 2.5V, PWM mode
V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C
VI = V(GS) = 3.6V, PWM mode
VI = V(GS) = 2.5V, PWM mode
V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C
2.3V ≤ VI ≤ 4.8V, Open loop
270
350
mΩ
mΩ
mA
P-channel MOSFET on
resistance
rDS(on)
Ilkg
rDS(on)
Ilkg
TPS6266x
P-channel leakage current, PMOS
1
140
200
mΩ
mΩ
mA
N-channel MOSFET on
resistance
TPS6266x
N-channel leakage current, NMOS
P-MOS current limit
2
1400
1500
19
1750
mA
Input current limit under short-circuit
conditions
VO shorted to ground
mA
Thermal shutdown
140
10
°C
°C
Thermal shutdown hysteresis
OSCILLATOR
fSW
Oscillator frequency
TPS6266x IO = 0mA, PWM mode
5.4
6
6.6
MHz
OUTPUT
2.3V ≤ VI ≤ 2.7V, 0mA ≤ IO ≤ 600mA
2.7V ≤ VI ≤ 3.0V, 0mA ≤ IO ≤ 800mA
3.0V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 1000mA
PFM/PWM operation
0.98×VNOM
0.98×VNOM
0.98×VNOM
VNOM
VNOM
VNOM
1.03×VNOM
1.04×VNOM
1.02×VNOM
V
V
V
Regulated DC output
voltage
3.0V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 1000mA
PFM/PWM operation
V(OUT)
TPS6266x
2.3V ≤ VI ≤ 2.7V, 0 mA ≤ IO ≤ 600mA
2.7V ≤ VI ≤ 3.0V, 0 mA ≤ IO ≤ 800mA
3.0V ≤ VI ≤ 5.5V, 0 mA ≤ IO ≤ 1000mA
PWM operation
Line regulation
VI = VO + 0.5V (min 2.3V) to 5.5V, IO = 200 mA
VI = 3.6V, IO = 0m A to 1000 mA
0.13
–0.00025
480
%/V
%/mA
kΩ
Load regulation
Feedback input resistance
TPS62660 IO = 1mA
20
mVPP
IO = 1mA
Power-save mode ripple
voltage
ΔVO
TPS62661 L = 1mH (muRata LQM2MPN1R0NG0)
CO = 10mF 4V 0402 (muRata GRM155R60G106M)
9
mVPP
TPS62665 IO = 1mA
24
120
55
mVPP
ms
TPS62660 IO = 0mA, Time from active EN to VO
TPS62661 RL = 2Ω, Time from active EN to VO
Start-up time
ms
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SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
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PIN ASSIGNMENTS
TPS62660
CSP-6
(TOP VIEW)
TPS62660
CSP-6
(BOTTOM VIEW)
VIN
EN
A2
B2
C2
A1
B1
C1
A1
A2
B2
VIN
EN
MODE
SW
MODE
B1
C1
SW
FB
GND
C2 GND
FB
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
FB
NO.
C1
A2
I
I
Output feedback sense input. Connect FB to the converter’s output.
Power supply input.
VIN
SW
B1
I/O
This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode. Pulling
this pin to VI enables the device. This pin must not be left floating and must be terminated.
EN
B2
I
This is the mode selection pin of the device. This pin must not be left floating and must be terminated.
MODE = LOW: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents.
MODE
GND
A1
C2
I
MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced.
Ground pin.
–
FUNCTIONAL BLOCK DIAGRAM
MODE
EN
VIN
Undervoltage
Lockout
Bias Supply
VIN
Soft-Start
Negative Inductor
Current Detect
Bandgap
V
= 0.8 V
Power Save Mode
Switching Logic
REF
Current Limit
Detect
Thermal
Shutdown
Frequency
Control
R
1
FB
-
Gate Driver
SW
Anti
Shoot-Through
R
V
2
REF
+
GND
4
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Product Folder Link(s): TPS6266x
TPS6266x
www.ti.com
SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION
TPS6266x
L
SW
VIN
VO
FB
EN
CI
VI
CO
MODE
GND
List of components:
•
•
•
L = MURATA LQM21PN1R0NGR
CI = MURATA GRM155R60J475M (4.7mF, 6.3V, 0402, X5R)
CO = MURATA GRM155R60J475M (4.7mF, 6.3V, 0402, X5R)
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Load current
vs Input voltage
3, 4, 5, 6
h
Efficiency
7
Peak-to-peak output ripple current
vs Load current
8, 9
Combined line/load transient
response
10, 11
12, 13, 14, 15, 16,
17, 18, 19, 20, 21, 22
Load transient response
AC load transient response
DC output voltage
23, 24, 25
26, 27
28, 29
30
VO
vs Load current
PFM/PWM boundaries
No load quiescent current
Switching frequency
IQ
fs
vs Input voltage
vs Input voltage
vs Input voltage
vs Input voltage
31
P-channel MOSFET rDS(on)
N-channel MOSFET rDS(on)
PWM operation
32
rDS(on)
33
34
Power-save mode operation
Mode change response
Over-current fault operation
Start-up
35
36, 37
38
39, 40
EFFICIENCY
vs
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
100
90
V
= 1.8 V (TPS62661)
O
V
= 1.8 V (TPS62660)
O
L = muRata LQM2MPN1R0NG0
90
80
70
60
50
80
70
60
50
V = 3.6 V
I
V
= 3.6 V
I
PFM/PWM Operation
PFM/PWM Operation
V = 2.7 V
I
V = 2.7 V
I
V
= 4.2 V
I
PFM/PWM Operation
PFM/PWM Operation
PFM/PWM Operation
V
= 4.2 V
I
PFM/PWM Operation
40
30
20
10
40
30
20
10
V = 3.6 V
I
Forced PWM Operation
V = 3.6 V
I
Forced PWM Operation
0
0
0.1
1
10
100
1000
0.1
1
10
100
1000
I
- Load Current - mA
I
- Load Current - mA
O
O
Figure 3.
Figure 4.
6
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SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
EFFICIENCY
vs
LOAD CURRENT
LOAD CURRENT
100
90
80
70
60
50
40
30
20
10
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
L = Aircoil (0.5 mH, DCR = 20 mW)
V = 2.7 V
I
V = 3.6 V
V
= 1.2 V
I
O
V
= 1.8 V (TPS62660)
PFM/PWM Operation
O
PFM/PWM Operation
V = 3.6 V
I
PFM/PWM Operation
L = muRata LQM21PN1R0
V = 4.2 V
I
PFM/PWM Operation
L = muRata LQM21PN0R54
0
1
10
100
1000
0.1
1
10
100
1000
I
- Load Current - mA
I
- Load Current - mA
O
O
Figure 5.
Figure 6.
EFFICIENCY
vs
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
INPUT VOLTAGE
LOAD CURRENT
30
28
26
24
22
20
18
16
14
12
10
8
100
98
V
= 1.8 V (TPS62660)
V
= 1.8 V (TPS62660)
O
O
PFM/PWM Operation
96
94
V = 4.8 V
I
92
I
= 300 mA
90
88
86
84
82
80
78
O
V = 3.6 V
I
I
= 100 mA
O
V = 2.5 V
I
I
= 1 mA
O
6
76
74
72
4
2
0
70
0
50 100 150 200 250 300 350 400 450 500 550 600
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
I
- Load Current - mA
V - Input Voltage - V
I
O
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
LOAD CURRENT
COMBINED LINE/LOAD TRANSIENT RESPONSE
12
11
10
9
V = 4.2 V
I
V = 3.6 V
I
8
7
V = 2.9 V
I
6
5
50 to 350 mA Load Step
4
3
V
= 1.8V (TPS62661)
O
2
3.3 to 3.9 V Line Step
L = 1µH (muRata LQM2MPN1R0NG0)
= 10µF 4V 0402 X5R (muRata GRM155R60G106M)
C
O
1
V = 3.6 V,
I
0
V
= 1.8 V (TPS62660)
MODE = Low
O
0
50 100 150 200 250 300 350 400 450 500 550 600
I
- Load Current - mA
O
t - Time - 5 µs/div
Figure 9.
Figure 10.
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
COMBINED LINE/LOAD TRANSIENT RESPONSE
0 to 150 mA Load Step
50 to 350 mA Load Step
2.7 to 3.3 V Line Step
V = 3.6 V,
I
MODE = Low
V
= 1.8 V (TPS62660)
O
V = 3.6 V,
I
MODE = Low
V
= 1.8 V (TPS62660)
O
t - Time - 2 ms/div
t - Time - 5 ms/div
Figure 11.
Figure 12.
8
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SLVS871A –FEBRUARY 2010–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
50 to 350 mA Load Step
50 to 350 mA Load Step
V = 2.7 V,
I
V = 3.6 V,
I
V
= 1.8 V (TPS62660)
V
= 1.8 V (TPS62660)
MODE = Low
O
MODE = Low
O
t - Time - 5 µs/div
Figure 13.
t - Time - 5 µs/div
Figure 14.
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
150 to 500 mA Load Step
50 to 350 mA Load Step
V = 3.6 V,
I
V = 4.8 V,
I
V
= 1.8 V (TPS62660)
O
V
= 1.8 V (TPS62660)
MODE = Low
MODE = Low
O
t - Time - 5 µs/div
Figure 16.
t - Time - 5 µs/div
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
150 to 500 mA Load Step
150 to 500 mA Load Step
V
V
= 2.7 V,
I
V = 4.8 V,
I
= 1.8 V (TPS62660)
MODE = Low
O
V
= 1.8 V (TPS62660)
MODE = Low
O
t - Time - 5 µs/div
Figure 17.
t - Time - 5 µs/div
Figure 18.
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
400 to 1000mA Load Step
50 to 350 mA Load Step
V = 3.6 V,
I
V = 3.6 V,
I
MODE = Low
V
= 1.2 V
V
= 1.8 V (TPS62660)
MODE = Low
O
O
t - Time - 5 µs/div
t - Time - 5 µs/div
Figure 19.
Figure 20.
10
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE
IN PFM/PWM OPERATION
LOAD TRANSIENT RESPONSE
IN PFM/PWM OPERATION
V = 3.6 V,
I
V
= 1.2 V
O
200 to 600 mA Load Step
5 to 200 mA Load Step
V = 3.6 V,
I
MODE = Low
V
= 1.2 V
MODE = Low
O
t - Time - 5 µs/div
Figure 21.
t - Time - 5 µs/div
Figure 22.
AC LOAD TRANSIENT RESPONSE
AC LOAD TRANSIENT RESPONSE
VI = 3.6 V,
VO = 1.8 V (TPS62661)
MODE = Low
VI = 3.6 V,
VO = 1.8 V (TPS62660)
10 to 350 mA Load Sweep
10 to 350 mA Load Sweep
L = muRata LQM2MPN1R0NG0,
MODE = Low
CO = 10μF 4V 0402 (muRata GRM155R60G106M)
t - Time - 10 µs/div
t - Time - 10 µs/div
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
vs
AC LOAD TRANSIENT RESPONSE
LOAD CURRENT
1.836
1.818
V
= 1.8 V (TPS62660)
O
V = 4.8 V
V = 3.6 V
I
I
V
V
= 3.6 V,
= 1.2 V
I
O
1.8
1.782
1.764
V = 2.5 V
10 to 375 mA Load Sweep
I
PFM/PWM Operation, V = 3.6 V
I
MODE = Low
t - Time - 10 µs/div
0.1
1
10
100
1000
I
- Load Current - mA
O
Figure 25.
Figure 26.
DC OUTPUT VOLTAGE
vs
LOAD CURRENT
PFM/PWM BOUNDARIES
1.224
1.212
1.2
220
200
180
160
140
120
100
V
= 1.8 V (TPS62660)
V
= 1.2 V
Always PWM
O
O
V = 4.8 V
PFM/PWM Operation
I
V = 3.6 V
I
PFM to PWM
Mode Change
The Switching Mode
Changes at These Borders
V = 3.6 V
I
80
60
V = 2.5 V
I
1.188
1.176
40
20
0
PWM to PFM
Mode Change
Always PFM
0.1
1
10
100
1000
2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
I
- Load Current - mA
V - Input Voltage - V
I
O
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
vs
PFM/PWM BOUNDARIES
INPUT VOLTAGE
50
45
40
35
260
240
220
200
180
160
140
120
100
Always PWM
V
= 1.2 V
T
= 85°C
O
A
PFM to PWM
Mode Change
T
= 25°C
A
30
25
The Switching Mode
Changes at These Borders
T
= -40°C
20
15
10
A
80
60
40
20
0
PWM to PFM
Mode Change
5
0
Always PFM
2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 29.
Figure 30.
SWITCHING FREQUENCY
vs
P-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
INPUT VOLTAGE
6.5
450
TPS62660
PWM Mode Operation
425
6
I
= 0 mA
O
400
375
I
= 600 mA
O
5.5
5
I
I
= 500 mA
T
= 85°C
O
A
= 400 mA
O
350
T
= 25°C
A
I
= 300 mA
O
325
300
4.5
4
I
= 150 mA
O
T
= -40°C
A
I
= 50 mA
O
275
250
225
200
175
3.5
3
2.5
V
= 1.8V (TPS62660)
2
O
150
125
1.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
N-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
PWM OPERATION
300
275
250
225
200
175
TPS62660
PWM Mode Operation
V = 3.6 V,
I
V
I
= 1.8 V (TPS62660),
O
= 100 mA
O
T
= 85°C
A
T
= 25°C
A
T
A
= -40°C
150
125
100
75
MODE = High
50
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
t - Time - 50 ns/div
V - Input Voltage - V
I
Figure 33.
Figure 34.
POWER-SAVE MODE OPERATION
MODE CHANGE RESPONSE
V = 3.6 V, V = 1.8 V (TPS62660),
I
O
I
= 40 mA
O
V = 3.6 V,
I
V
I
= 1.8 V (TPS62660),
O
= 40 mA
O
MODE = Low
t - Time - 1 µs/div
t - Time - 250 ns/div
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
MODE CHANGE RESPONSE
OVER-CURRENT FAULT OPERATION
V = 3.6 V, V = 1.8 V (TPS62660),
I
O
I
= 40 mA
O
750 to 1800 mA Load Sweep
V = 3.6 V,
I
V
= 1.8 V (TPS62660)
MODE = Low
O
t - Time - 2 µs/div
t - Time - 1 µs/div
Figure 37.
Figure 38.
START-UP
START-UP
V = 3.6 V,
V = 3.6 V,
I
I
V
I
= 1.8 V (TPS62660),
V
= 1.8 V (TPS62661),
R = 2Ω
L
O
O
= 0 mA
O
MODE = Low
MODE = Low
L = muRata LQM2MPN1R0NG0
t - Time - 20 µs/div
t - Time - 10 µs/div
Figure 39.
Figure 40.
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DETAILED DESCRIPTION
OPERATION
The TPS6266x is a synchronous step-down converter typically operates at a regulated 6-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6266x converter
operates in power-save mode with pulse frequency modulation (PFM).
The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line
response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of
each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the
output voltage until the main comparator trips, then the control logic turns off the switch.
One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response
to change in VO is essentially instantaneous, which explains the transient response. The absence of a traditional,
high-gain compensated linear loop means that the TPS6266x is inherently stable over a range of L and CO.
Although this type of operation normally results in a switching frequency that varies with input voltage and load
current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of
operating conditions.
Combined with best in class load and line transient response characteristics, the low quiescent current of the
device (ca. 31mA) allows to maintain high efficiency at light load, while preserving fast transient response for
applications requiring tight output regulation.
SWITCHING FREQUENCY
The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of
50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The
intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.
6MHz by a frequency locked loop.
When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls
below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather
than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at
low duty cycles.
When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can
be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).
This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation
delay, hence increasing the switching frequency.
POWER-SAVE MODE
If the load current decreases, the converter will enter Power Save Mode operation automatically. During
power-save mode the converter operates in discontinuous current (DCM) single-pulse PFM mode, which
produces low output ripple compared with other PFM architectures.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the
inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input
voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state.
PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.
As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and
the transition between PFM and PWM is seamless.
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PFM Mode at Light Load
PFM Ripple
Nominal DC Output Voltage
PWM Mode at Heavy Load
Figure 41. Operation in PFM Mode and Transfer to PWM Mode
MODE SELECTION
The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the
automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at
moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide
load current range.
Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The
advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching
frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save
mode during light loads.
For additional flexibility, it is possible to switch from power-save mode to forced PWM mode during operation.
This allows efficient power management by adjusting the operation of the converter to the specific system
requirements.
ENABLE
The device starts operation when EN is set high and starts up with the soft start as previously described. For
proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1mA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off.
SOFT START
The TPS62660/62 has an internal soft-start circuit that limits the inrush current during start-up. This limits input
voltage drops when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of
the output voltage. This mode of operation continues for c.a. 100ms after enable. Should the output voltage not
have reached its target value by this time, such as in the case of heavy load, the soft-start transitions to a second
mode of operation.
The converter then operates in a current limit mode, specifically the P-MOS current limit is set to half the nominal
limit, and the N-channel MOSFET remains on until the inductor current has reset. After a further 100 ms, the
device ramps up to the full current limit operation if the output voltage has risen above 0.5V (approximately).
Therefore, the start-up time mainly depends on the output capacitor and load current.
The TPS62661 device starts-up immediately into a nominal current limit mode thereby ramping-up the output
voltage with maximum speed (<60ms typ.). The start-up time mainly depends on the output capacitor and load
current.
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OUTPUT CAPACITOR DISCHARGE
The TPS6266x device can actively discharge the output capacitor when it turns off. The integrated discharge
resistor has a typical resistance of 15 Ω. The required time to discharge the output capacitor at the output node
depends on load current and the output capacitance value.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6266x device
have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1V input voltage.
SHORT-CIRCUIT PROTECTION
The TPS6266x integrates a P-channel MOSFET current limit to protect the device against heavy load or short
circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned
off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle
basis.
As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal
value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half
of its nominal current limit until the output voltage exceeds approximately 0.5V. This needs to be considered
when a load acting as a current sink is connected to the output of the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature again falls below typically 130°C.
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APPLICATION INFORMATION
INDUCTOR SELECTION
The TPS62660 series of step-down converters have been optimized to operate with an effective inductance
value in the range of 0.3mH to 1.3mH and with output capacitors in the range of 4.7mF to 10mF. The internal
compensation is optimized to operate with an output filter of L = 0.47mH and CO = 4.7mF. Larger or smaller
inductor values can be used to optimize the performance of the device for specific operation conditions. For more
details, see the CHECKING LOOP STABILITY section.
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.
V
V * V
DI
O
I
O
L
DI +
DI
+ I
)
L
L(MAX)
O(MAX)
2
V
L ƒ
sw
I
(1)
with: fSW = switching frequency (6 MHz typical)
L = inductor value
ΔIL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following
frequency-dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS62660 converters.
Table 1. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
LQM21PN1R0NGR
LQM21PNR54MG0
LQM2MPN1R0NG0
ELGTEAR82NA
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 1.0 max. height
2.0 x 1.6 x 1.0 max. height
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 1.0 max. height
MURATA
PANASONIC
TOKO
MDT2012-CX1R0A
MIPS2012D1R0-X2
FDK
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OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6266x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. For best performance, the device should be operated with a minimum effective output
capacitance of 1.6mF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
impedance.
At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load
transitions. A 4.7mF capacitor typically provides sufficient bulk capacitance to stabilize the output during large
load transitions. The typical output voltage ripple is 1% of the nominal output voltage VO.
The output voltage ripple during PFM mode operation can be kept very small. The PFM pulse is time controlled,
which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting
PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the
inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once.
Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 4.7-mF capacitor is sufficient. If the application exhibits a noisy or
erratic switching frequency, the remedy will probably be found by experimenting with the value of the input
capacitor.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6266x devices demand careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low
inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. In order to get an optimum ESL step, the output voltage feedback point (FB) should be taken in the
output capacitor path, approximately 1mm away for it. The feed-back line should be routed away from noisy
components and traces (e.g. SW line).
MODE
VIN
CI
L
ENABLE
CO
GND
VOUT
Figure 42. Suggested Layout (Top)
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THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS6266x devices is 105°C. The thermal
resistance of the 6-pin CSP package (YFF-6) is RqJA = 125°C/W. Regulator operation is specified to a maximum
ambient temperature TA of 85°C. Therefore, the maximum steady state power dissipation is about 160 mW.
TJ(MAX) - TA
105°C - 85°C
P
=
=
= 160 mW
D(MA)
RθJA
125°C/W
(2)
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
CHIP SCALE PACKAGE
(TOP VIEW)
A2
B2
C2
A1
B1
C1
YMSCC
LLLL
D
A1
Code:
•
•
•
•
YM — Year Month date Code
S — Assembly site code
CC— Chip code
E
LLLL — Lot trace code
CHIP SCALE PACKAGE DIMENSIONS
The TPS6266x device is available in an 6-bump chip scale package (YFF, NanoFree™). The package
dimensions are given as:
•
•
D = 1.30 ±0.03 mm
E = 0.926 ±0.03 mm
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NOTE: Page numbers of current version may differ from previous versions.
Changes from Original (February 2010) to Revision A
Page
•
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2010
PACKAGING INFORMATION
Orderable Device
TPS62660YFFR
TPS62660YFFT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DSBGA
YFF
6
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
DSBGA
YFF
6
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS62661YFFR
TPS62661YFFT
PREVIEW
PREVIEW
DSBGA
DSBGA
YFF
YFF
6
6
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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