TPS626751YFDR [TI]
500mA、6MHz 高效降压转换器，Vout=1.2V | YFD | 6 | -40 to 85;
| 型号： | TPS626751YFDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500mA、6MHz 高效降压转换器，Vout=1.2V | YFD | 6 | -40 to 85 开关 转换器 |
| 文件： | 总38页 (文件大小：1974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62671, TPS62672, TPS62674
TPS62675, TPS626751, TPS626765, TPS62679
SLVS952G –APRIL 2010–REVISED JANUARY 2017
TPS6267x 500-mA/650-mA, 6-MHz High-Efficiency Step-Down Converter
in Low Profile Chip Scale Packaging (Height < 0.4mm)
1 Features
3 Description
The
TPS6267x
devices
are
high-frequency
1
•
92% Efficiency at 6MHz Operation
17μA Quiescent Current
synchronous step-down dc-dc converters optimized
for small battery-powered applications. Intended for
low-power applications, the TPS6267x supports up to
650-mA load current and allows the use of low cost
chip inductor and capacitors.
•
•
•
•
•
•
•
•
•
•
Wide VIN Range From 2.3V to 4.8V
6MHz Regulated Frequency Operation
Spread Spectrum, PWM Frequency Dithering
Best in Class Load and Line Transient
±2% Total DC Voltage Accuracy
Low Ripple Light-Load PFM Mode
≥35dB VIN PSRR (1kHz to 10kHz)
Simple Logic Enable Inputs
With a wide input voltage range of 2.3V to 4.8V, the
device supports applications powered by Li-Ion
batteries with extended voltage range. Different fixed
voltage output versions are available from 1.05V to
2.1V. The TPS6267x operates at a regulated 6-MHz
switching frequency and enters the power-save mode
operation at light load currents to maintain high
efficiency over the entire load current range.
Supports External Clock Presence Detect Enable
Input
The PFM mode extends the battery life by reducing
the quiescent current to 17μA (typ) during light load
operation. For noise-sensitive applications, the device
has PWM spread spectrum capability providing a
lower noise regulated output, as well as low noise at
the input. These features, combined with high PSRR
and AC load regulation performance, make this
device suitable to replace a linear regulator to obtain
better power conversion efficiency.
•
•
Three Surface-Mount External Components
Required (One 0603 MLCC Inductor, Two 0402
Ceramic Capacitors)
Complete Sub 0.33-mm Component Profile
Solution
Total Solution Size <10 mm2
•
•
Available in a 6-Pin NanoFree™ (CSP)
Ultra-Thin Packaging, 0.4 mm Max. Height
Device Information(1)
2 Applications
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.22mm x 0.85mm
1.22mm x 0.85mm
•
•
•
Cell Phones, Smart-Phones
TPS62671,
TPS62672,
TPS62674,
TPS62675,
TPS626751,
TPS626765
CMOS Camera Module, Optical Data Module
DSBGA (6)
Digital TV, WLAN, GPS and Bluetooth™
Applications
•
Embedded Power Supply
TPS62679
PicoStar (6)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
V
V
OUT
1.8 V @ 500mA
TPS62671
BAT
2.3 V .. 4.8 V
L
Efficiency vs Output Current
SW
VIN
0.47 mH
150
100
V
V
= 3.6 V,
= 1.8 V
I
90
80
70
60
50
40
30
20
10
0
135
120
105
90
C
I
O
FB
EN
C
O
Efficiency
PFM/PWM Operation
2.2 mF
4.7 mF
MODE
GND
75
60
45
Power Loss
PFM/PWM Operation
30
15
0
0.1
1
10
- Load Current - mA
100
1000
I
O
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62671, TPS62672, TPS62674
TPS62675, TPS626751, TPS626765, TPS62679
SLVS952G –APRIL 2010–REVISED JANUARY 2017
www.ti.com
Table of Contents
10.3 Feature Description............................................... 15
10.4 Device Functional Modes...................................... 17
11 Application and Implementation........................ 19
11.1 Application Information.......................................... 19
11.2 Typical Applications .............................................. 19
12 Power Supply Recommendations ..................... 26
13 Layout................................................................... 27
13.1 Layout Guidelines ................................................. 27
13.2 Layout Example .................................................... 27
14 Device and Documentation Support ................. 28
14.1 Device Support .................................................... 28
14.2 Documentation Support ....................................... 28
14.3 Related Links ........................................................ 28
14.4 Trademarks........................................................... 28
14.5 Electrostatic Discharge Caution............................ 28
14.6 Glossary................................................................ 28
1
2
3
4
5
6
7
8
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
8.1 Absolute Maximum Ratings ...................................... 5
8.2 Handling Ratings....................................................... 5
8.3 Recommended Operating Conditions....................... 5
8.4 Thermal Information.................................................. 5
8.5 Electrical Characteristics........................................... 6
8.6 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 13
9
10 Detailed Description ........................................... 14
10.1 Overview ............................................................... 14
10.2 Functional Block Diagram ..................................... 14
15 Mechanical, Packaging, and Orderable
Information ........................................................... 29
5 Revision History
Changes from Revision F (June 2014) to Revision G
Page
•
•
Changed status from Product Mix to Production Data .......................................................................................................... 1
TPS62672 released to Production ......................................................................................................................................... 4
Changes from Revision E (April 2010) to Revision F
Page
•
•
•
•
•
•
•
•
•
Added Device Information table and included device TPS626765 ........................................................................................ 1
Deleted the Ordering Information table and replaced with the Device Comparison Table; Ordering Info is in the POA ...... 4
Changed "Terminal" to "Pin" in 3 places ............................................................................................................................... 4
Changed the notes in the Handling Ratings table and added values in the MIN column ..................................................... 5
Added column in Thermal Information table for the TPS60679 device and changed "TERMINALS" to "PINS" .................. 5
Added TIMING row to the Electrical Characteristics table .................................................................................................... 8
Changed formatting of Typical Characteristics section to 6 graphs per page. ...................................................................... 9
Added the 3rd-party products disclaimer.............................................................................................................................. 28
Changed the location of References from Applications to Related Documentation ........................................................... 28
Changes from Revision D (July 2011) to Revision E
Page
•
•
Added device TPS626751 to Ordering Info table................................................................................................................... 4
Added Preview devices TPS62673, TPS62676 to Ordering Info table.................................................................................. 4
Changes from Revision C (April 2011) to Revision D
Page
•
•
•
•
Changed from "600-mA" to "650-mA" in document title......................................................................................................... 1
Changed description text from "600-mA" to "650-mA" load current....................................................................................... 1
Changed IO specification for TPS62675 from "600 mA" MAX to "650 mA "........................................................................... 5
Changed VOUT specification Condition statement from "600 mA" to "650 mA" for TPS62675 .............................................. 8
2
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Product Folder Links: TPS62671 TPS62672 TPS62674 TPS62675 TPS626751 TPS626765 TPS62679
TPS62671, TPS62672, TPS62674
TPS62675, TPS626751, TPS626765, TPS62679
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SLVS952G –APRIL 2010–REVISED JANUARY 2017
Changes from Revision B (January 2011) to Revision C
Page
•
•
Changed devices TPS62671 and TPS62675 to Production status in Ordering Info table..................................................... 4
Added copyright attribution for spectrum illustrations........................................................................................................... 16
Changes from Revision A (November 2010) to Revision B
Page
•
Changed device TPS62679 to Production status, and changed TPS62671 to Product Preview status in the Ordering
Info table................................................................................................................................................................................. 4
Changes from Original (April 2010) to Revision A
Page
•
•
•
Changed Figure 3 image in Typical Char. graphs.................................................................................................................. 9
Changed Figure 45 image in the Typical Char. graphs........................................................................................................ 11
Changed Figure 40 image in the Typical Char. graphs........................................................................................................ 24
Copyright © 2010–2017, Texas Instruments Incorporated
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TPS62671, TPS62672, TPS62674
TPS62675, TPS626751, TPS626765, TPS62679
SLVS952G –APRIL 2010–REVISED JANUARY 2017
www.ti.com
6 Device Comparison Table
PART NUMBER
TPS62671YFD
TPS62672YFD
TPS62674YFD
TPS62675YFD
TPS626751YFD
TPS626765YFD
TPS62679ZYFM
OUTPUT VOLTAGE
1.8 V
DEVICE SPECIFIC FEATURE
PWM Spread Spectrum Modulation (SSM)
PWM Spread Spectrum Modulation (SSM)
PWM SSM, PWM Operation Only, Output Discharge
PWM Spread Spectrum Modulation (SSM)
PWM SSM, Output Discharge
PACKAGE MARKING
NZ
1BCS
PN
OB
E3
1.5 V
1.26 V
1.2 V
1.2 V
1.05 V
PWM SSM, Output Discharge
EH
-
1.26 V
PWM SSM, Extended Start-Up Time, Output Discharge
7 Pin Configuration and Functions
TPS6267x
CSP-6
(TOP VIEW)
TPS6267x
CSP-6
(BOTTOM VIEW)
A2
B2
C2
A1
B1
C1
VIN
EN
A1
A2
B2
VIN
EN
MODE
SW
MODE
B1
C1
SW
FB
GND
C2 GND
FB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
FB
NO.
C1
A2
I
I
Output feedback sense input. Connect FB to the converter’s output.
Power supply input.
VIN
SW
B1
I/O
This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode.
Pulling this pin to VI enables the device. If an external clock (4MHz to 27MHz) is detected the device will
automatically power up. This pin must not be left floating and must be terminated.
EN
B2
I
This is the mode selection pin of the device. This pin must not be left floating and must be terminated.
MODE = LOW: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-
load currents and in pulse frequency modulation mode (PFM) at light load currents.
MODE
GND
A1
C2
I
MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced.
Ground pin.
–
4
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TPS62675, TPS626751, TPS626765, TPS62679
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SLVS952G –APRIL 2010–REVISED JANUARY 2017
8 Specifications
8.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–40
MAX
6
UNIT
V
Voltage at VIN(2), SW(3)
Voltage at FB(3)
Input
Voltage
3.6
V
(3)
Voltage at EN, MODE
VI + 0.3
85
V
TA
TJ
Operating temperature range(4)
°C
°C
Operating junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operation above 4.8V input voltage for extended periods may affect device reliability.
(3) All voltage values are with respect to network ground terminal.
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
8.2 Handling Ratings
MIN
–65
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
Human Body Model (HBM) ESD stress voltage(1)
Charge device model (CDM) ESD stress voltage(2)
Machine Model (MM) ESD Stress Voltage(3)
kV
VESD
–1
1
kV
–200
200
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) The machine model is a 200pF capacitor discharged directly into ech pin.
8.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VI
IO
L
Input voltage range
Output current range
Inductance
2.3
0
4.8(1)
500
650
1.8
V
TPS62671,TPS62674, TPS62679
mA
mA
µH
µF
µF
°C
TPS62672,TPS62675, TPS626751, TPS626765
0
0.3
0.8
0.8
–40
–40
Output capacitance (PFM/PWM operation)
Output capacitance (PWM operation)
Ambient temperature
2.5
2.5
10
CO
10
TA
TJ
+85
+125
Operating junction temperature
°C
(1) Operation above 4.8V input voltage for extended periods may affect device reliability.
8.4 Thermal Information
TPS62679
TPS6267X
THERMAL METRIC(1)
UNIT
YFM (6 PINS)
YFD (6 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
125
RθJC(top)
RθJB
-
53
-
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
-
RθJC(bot)
-
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2010–2017, Texas Instruments Incorporated
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TPS62671, TPS62672, TPS62674
TPS62675, TPS626751, TPS626765, TPS62679
SLVS952G –APRIL 2010–REVISED JANUARY 2017
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8.5 Electrical Characteristics
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 1.8V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
IO = 0mA. Device not switching
IO = 0mA, PWM mode
MIN
TYP
MAX UNIT
TPS62671
TPS62672
TPS62675
TPS62679
TPS626751
TPS626765
17
40
μA
Operating
quiescent current
IQ
TPS62671
TPS62672
TPS626751
TPS626765
5.5
5.0
mA
mA
TPS62674
TPS62679
IO = 0mA, PWM mode
EN = GND
I(SD)
Shutdown current
0.2
1
μA
UVLO
Undervoltage lockout threshold
2.05
2.1
V
ENABLE, MODE
High-level input
voltage
VIH
VIL
Ilkg
1.0
V
V
TPS62671
TPS62672
TPS62675
TPS626751
TPS626765
Low-level input
voltage
0.4
1.5
Input leakage
current
Input connected to GND or VIN
0.01
μA
High-level input
voltage
(ENABLE)
1.26
1.0
V
V
V
VIH
High-level input
voltage (MODE)
TPS62674
TPS62679
Low-level input
voltage
0.54
(ENABLE)
VIL
Low-level input
voltage (MODE)
TPS62679
0.4
1.5
V
Input leakage
current
TPS62674
TPS62679
Ilkg
Input connected to GND or VIN
0.01
5
μA
pF
Input capacitance
(ENABLE)
CIN
Clock presence
detect frequency
4
27 MHz
60%
TPS62674
TPS62679
EXTCLK
Clock presence
detect duty cycle
40%
6
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TPS62675, TPS626751, TPS626765, TPS62679
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SLVS952G –APRIL 2010–REVISED JANUARY 2017
Electrical Characteristics (continued)
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 1.8V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
POWER SWITCH
TEST CONDITIONS
MIN
TYP
MAX UNIT
VI = V(GS) = 3.6V. PWM mode
VI = V(GS) = 2.5V. PWM mode
170
230
mΩ
mΩ
P-channel MOSFET on
resistance
rDS(on)
Ilkg
P-channel leakage current,
PMOS
V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C
1
μA
VI = V(GS) = 3.6V. PWM mode
VI = V(GS) = 2.5V. PWM mode
120
180
mΩ
mΩ
N-channel MOSFET on
resistance
rDS(on)
N-channel leakage current,
NMOS
Ilkg
V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C
2
μA
Discharge resistor for power-
down sequence
rDIS
TPS62674, TPS626751, TPS626765, TPS62679
70
150
Ω
TPS62671
2.3V ≤ VI ≤ 4.8V. Open
TPS62674
900
1000
1150
1250
mA
loop
TPS62679
P-MOS current limit
TPS62672
2.3V ≤ VI ≤ 4.8V. Open
loop
TPS62675
TPS626751
TPS626765
1000
1100
12
mA
mA
Input current limit under short-
circuit conditions
VO shorted to ground
Thermal shutdown
140
10
°C
°C
Thermal shutdown hysteresis
OSCILLATOR
TPS62671
TPS62672
TPS62675 IO = 0mA. PWM operation
TPS626751
Oscillator center
frequency
5.4
4.9
6
6.6 MHz
6.0 MHz
fSW
TPS626765
Oscillator center
frequency
TPS62674
IO = 0mA. PWM operation
TPS62679
5.45
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Electrical Characteristics (continued)
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 1.8V, EN =
1.8V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
2.3V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 500 mA
PFM/PWM operation
0.98×VNO
1.03×
V
VNOM
VNOM
VNOM
VNOM
VNOM
VNOM
VNOM
M
TPS62671 2.3V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
TPS62679 PFM/PWM operation
0.98×VNO
1.04×
V
VNOM
M
2.3V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PWM operation
0.98×VNO
1.02×
V
VNOM
M
Regulated DC
output voltage
2.3V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 500 mA
PWM operation
0.98×VNO
1.02×
V
TPS62674
VOUT
VNOM
M
0.98×VNO
M
2.3V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 650 mA
PFM/PWM operation
1.03×
V
TPS62672
TPS62675
TPS626751
TPS626765
VNOM
2.3V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 650 mA
PWM operation
0.98×VNO
M
1.02×
V
VNOM
Line regulation
Load regulation
VI = VO + 0.5V (min 2.3V) to 5.5V, IO = 200 mA
IO = 0mA to 500 mA. PWM operation
0.23
–0.00045
480
%/V
%/mA
kΩ
Feedback input resistance
TPS62671 IO = 1mA, VO = 1.8 V
14
mVPP
TPS62672
TPS62675
TPS626751 IO = 1mA, VO = 1.2 V
TPS626765
Power-save
mode ripple
voltage
ΔVO
16
mVPP
TPS62679
TIMING
TPS62671 IO = 0mA, Time from active EN to VO
130
125
μs
μs
TPS62674
TPS626751 IO = 0mA, Time from EXTCLK clock active to VO
TPS626765
Start-up time
IO = 0mA, Time from EXTCLK clock active to VO
L = 1μH DCR = 240mΩ 0603 (TY
CKP1608S1R0)
CO = 2.2μF 4V 0402 (TY AMK105BJ225MP)
TPS62679
430
1.2
μs
IO = 0mA, Time from EXTCLK clock inactive to
VO down
CO = 4.7μF 6.3V 0402 (Murata
ms
GRM155R60J475M)
TPS62674
Shutdown time
IO = 0mA, Time from EXTCLK clock inactive to
TPS62679
VO down
L = 1μH DCR = 240mΩ 0603 (TY
CKP1608S1R0)
600
μs
CO = 2.2μF 4V 0402 (TY AMK105BJ225MP)
8
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SLVS952G –APRIL 2010–REVISED JANUARY 2017
8.6 Typical Characteristics
100
100
V
= 1.8 V
V
= 1.2 V
O
O
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
V = 2.7 V
I
PFM/PWM Operation
V = 3.6 V
I
PFM/PWM Operation
V = 3.6 V
I
PFM/PWM Operation
V = 4.2 V
I
PFM/PWM Operation
V = 4.2 V
I
PFM/PWM Operation
V = 2.7 V
I
PFM/PWM Operation
V = 3.6 V
I
Forced PWM
V = 3.6 V
I
Forced PWM
10
0
10
0
0.1
1
10
- Load Current - mA
100
1000
0.1
1
10
- Load Current - mA
100
1000
I
O
I
O
Figure 2. Efficiency vs Load Current
Figure 1. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
V
= 1.05 V
V
= 1.26 V
O
O
V = 2.7 V
I
PFM/PWM Operation
V = 2.7 V
I
80
70
60
50
PWM Operation
V = 3.6 V
I
V = 3.6 V
I
PFM/PWM Operation
PWM Operation
V = 4.2 V
I
PFM/PWM Operation
V
= 4.2 V
40
30
20
10
I
PWM Operation
V = 3.6 V
I
Forced PWM
0
0.1
1
10
100
1000
1
10
100
- Load Current - mA
1000
I
- Load Current (mA)
O
I
O
G000
Figure 3. Efficiency vs Load Current
Figure 4. Efficiency vs Load Current
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
90
88
86
84
82
80
78
76
74
V
V
= 3.6 V,
I
= 10 mA
I
O
= 1.2 V,
L = muRata LQM21PN1R0NGR
O
I
= 300 mA
O
PFM/PWM Opreation
I
= 100 mA
O
L = muRata LQM21PN1R0MC0
L = muRata LQM18PN1R5-B35
I
= 1 mA
O
V
= 1.2 V
O
PFM/PWM Operation
72
70
1
10
100
- Load Current - mA
1000
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7
I
O
V - Input Voltage - V
I
Figure 5. Efficiency vs Load Current
Figure 6. Efficiency vs Input Voltage
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Typical Characteristics (continued)
20
22
20
V
= 1.2 V
V
= 1.8 V
O
18
16
14
12
10
8
O
V = 2.7 V
18
16
14
12
10
8
I
V = 3.6 V
V = 3.6 V
I
I
V = 4.5 V
I
V = 4.5 V
I
V = 2.7 V
6
I
6
4
4
2
2
0
0
0
20 40 60 80 100 120 140 160 180 200
- Load Current - mA
0
20 40 60 80 100 120 140 160 180 200
- Load Current - mA
I
I
O
O
Figure 7. Peak-To-Peak Output Ripple Voltage vs Load
Current
Figure 8. Peak-To-Peak Output Ripple Voltage vs Load
Current
1.836
1.224
V
= 1.2 V
V
= 1.8 V
O
PFM/PWM Operation
O
PFM/PWM Operation
V = 4.5 V
I
1.818
1.212
V = 3.6 V
I
V = 4.5 V
I
V = 3.6 V
I
1.800
1.782
1.764
1.2
1.188
1.176
V = 2.7 V
I
V = 2.7 V
I
0.1
1
10
- Load Current - mA
100
1000
0.1
1
10
I - Load Current - mA
O
100
1000
I
O
Figure 9. DC Output Voltage vs Load Current
Figure 10. DC Output Voltage vs Load Current
1.285
100
V
= 1.8 V
O
Always PWM
V
= 1.26 V
O
PWM Operation
90
80
70
60
50
40
30
PFM to PWM
Mode Change
The switching mode changes
at these borders
1.273
1.260
V
= 4.5 V
I
V
= 3.6 V
I
Always PFM
PWM to PFM
Mode Change
V
= 2.7 V
I
1.247
1.235
20
10
0
0.1
1
10
- Load Current - mA
100
1000
2.7
3
3.3
3.6
3.9
V - Input Voltage - V
4.2
4.5
4.8
I
I
O
Figure 11. DC Output Voltage vs Load Current
Figure 12. PFM/PWM Boundaries
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Typical Characteristics (continued)
200
28
26
V
= 1.2 V
O
180
160
140
120
100
80
T
= 85°C
A
Always PWM
24
22
20
18
16
14
12
10
8
T
= 25°C
A
PFM to PWM
Mode Change
The switching mode changes
at these borders
PWM to PFM
Mode Change
T
= -40°C
A
60
Always PFM
6
40
20
0
4
2
0
2.7
2.7
3
3.3
3.6
3.9
V - Input Voltage - V
4.2
4.5
4.8
3
3.3
3.6
3.9
V - Input Voltage - V
4.2
4.5
4.8
I
I
Figure 14. Quiescent Current vs Input Voltage
Figure 13. PFM/PWM Boundaries
6.5
6
6.5
I
= 150 mA
O
V
= 1.2 V
O
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
I
Ranging from 0 to 500 mA
O
I
= 500 mA
O
5.5
5
I
= 400 mA
O
I
= 300 mA
O
4.5
4
3.5
3
V
= 1.8 V
O
2.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
V - Input Voltage - V
V - Input Voltage - V
I
I
Figure 16. PWM Switching Frequency vs Input Voltage
Figure 15. PWM Switching Frequency vs Input Voltage
6.5
85
I
= 10 mA
V = 3.6 V,
V
= 1.2 V
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
O
PFM Operation
I
O
V = 2.7 V
I
6
5.5
5
V
= 1.8 V
O
V = 4.5 V
I
I
= 400 mA
O
PWM Operation
4.5
4
V = 3.6 V
I
3.5
3
I
= 150 mA
O
PWM Operation
2.5
2
1.5
1
0.5
0
5
0
0.01
0.1
1
10
f - Frequency - kHz
100
1000
0
20
40
60
- Load Current - mA
80
100 120 140 160
I
O
Figure 18. PSRR vs Frequency
Figure 17. PFM Switching Frequency vs Input Voltage
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Typical Characteristics (continued)
100 m
100 m
90 m
80 m
70 m
V
= 1.2 V
= 12 Ω
V = 3.6 V
O
I
90 m
80 m
70 m
60 m
50 m
40 m
30 m
20 m
R
V
= 1.2 V
= 12 Ω
L
O
R
L
60 m
50 m
40 m
30 m
20 m
10 m
1 n
V
= 4.2 V
I
V
= 2.7 V
I
V
= 3.6 V
I
10 m
1 n
0
Span = 4 MHz
f - Frequency - MHz
40
4.65
Span = 250 kHz
7.15
f - Frequency - MHz
Figure 19. Spurious Output Noise (PWM Mode) vs
Frequency
Figure 20. Spurious Output Noise (PWM Mode) vs
Frequency
4 m
120 m
V
= 1.8 V
V
= 1.8 V
R = 12 Ω
L
110 m
100 m
90 m
80 m
70 m
60 m
50 m
40 m
30 m
20 m
10 m
O
O
3.5 m
3 m
R
= 150 Ω
L
2.5 m
2 m
V
= 3.6 V
I
V
= 3.6 V
I
1.5 m
1 m
V
= 4.2 V
I
V
= 2.7 V
I
V
= 4.2 V
I
V
= 2.7 V
I
500 m
40 n
1.2 n
0
Span = 1 MHz
10
0
Span = 10 MHz
100
f - Frequency - MHz
f - Frequency - MHz
Figure 21.
Figure 22.
10
1
V = 3.6 V,
I
I
= 1 mA
O
(PFM Mode)
V
= 1.8 V
O
I
= 10 mA (PFM Mode)
O
0.1
I
= 150 mA (PWM Mode)
O
0.01
0.001
0.1
1
10
f - Frequency - kHz
100
1000
Figure 23. Output Spectral Noise Density vs Frequency
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9 Parameter Measurement Information
TPS6267x
L
SW
VIN
V
O
FB
EN
V
C
I
I
C
O
MODE
GND
Figure 24. Measurement Setup
List of components:
•
•
•
L = MURATA LQM21PN1R0NGR
CI = MURATA GRM155R60J225ME15 (2.2μF, 6.3V, 0402, X5R)
CO = MURATA GRM155R60J475M (4.7μF, 6.3V, 0402, X5R)
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10 Detailed Description
10.1 Overview
The TPS6267x synchronous step-down converters typically operate at a regulated 6-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6267x converters operate
in power-save mode with pulse frequency modulation (PFM). The converters use a unique frequency locked ring
oscillating modulator to achieve best-in-class load and line response and allow the use of tiny inductors and
small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET
switch is turned on and the inductor current ramps up rising the output voltage until the main comparator trips,
then the control logic turns off the switch.
One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response
to change in VO is essentially instantaneous, which explains the transient response. The absence of a traditional,
high-gain compensated linear loop means that the TPS6267x is inherently stable over a range of L and CO.
Although this type of operation normally results in a switching frequency that varies with input voltage and load
current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of
operating conditions. Combined with best in class load and line transient response characteristics, the low
quiescent current of the device (ca. 17μA) allows to maintain high efficiency at light load, while preserving fast
transient response for applications requiring tight output regulation.
Using the YFD package allows for a low profile solution size (0.4mm max height, including external components).
The recommended external components are stated within the application information. The maximum output
current is 500/650mA when these specific low profile external components are used.
10.2 Functional Block Diagram
MODE
EN
VIN
Undervoltage
Lockout
Bias Supply
VIN
Soft-Start
Negative Inductor
Current Detect
Bandgap
V
= 0.8 V
Power Save Mode
Switching Logic
REF
Current Limit
Detect
Thermal
Shutdown
Frequency
Control
R
1
FB
-
Gate Driver
SW
Anti
Shoot-Through
R
V
REF
2
+
GND
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10.3 Feature Description
10.3.1 Switching Frequency
The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of
50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The
intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.
6MHz by a frequency locked loop.
When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls
below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather
than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at
low duty cycles.
When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can
be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).
This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation
delay, hence increasing the switching frequency.
10.3.2 Power Save Mode
If the load current decreases, the converter will enter Power Save Mode operation automatically (does not apply
for TPS62674). During power-save mode the converter operates in discontinuous current (DCM) single-pulse
PFM mode, which produces low output ripple compared with other PFM architectures.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the
inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input
voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state.
PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.
As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and
the transition between PFM and PWM is seamless.
PFM Mode at Light Load
PFM Ripple
Nominal DC Output Voltage
PWM Mode at Heavy Load
Figure 25. Operation in PFM Mode and Transfer to PWM Mode
10.3.3 Mode Selection
The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the
automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at
moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide
load current range.
Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The
advantage is that the converter modulates its switching frequency according to a spread spectrum PWM
modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications. In this
mode, the efficiency is lower compared to the power-save mode during light loads. Notice that the TPS62674
device only permits PWM operation and required the MODE input to be tied high.
For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation. This
allows efficient power management by adjusting the operation of the converter to the specific system
requirements.
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Feature Description (continued)
10.3.4 Spread Spectrum, PWM Frequency Dithering
The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar
to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to
comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in
cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that
is focused on specific frequencies.
Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or regulated, based on the output load. This method of conversion
creates large components of noise at the frequency of operation (fundamental) and multiples of the operating
frequency (harmonics).
The spread spectrum architecture varies the switching frequency by ca. ±10% of the nominal switching frequency
thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The
frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.
0 dBV
F
Dfc
ENV,PEAK
Dfc
Non-modulated harmonic
F
1
Side-band harmonics
window after modulation
0 dBVref
B = 2×fm ×(1+ mf )= 2×(Dfc + fm )
Bh = 2×fm ×(1+ mf ×h)
B = 2×fm ×(1+ mf )= 2×(Dfc + fm )
Figure 26. Spectrum of a Frequency Modulated
Sin. Wave with Sinusoidal Variation in Time
Figure 27. Spread Bands of Harmonics in
(1)
Modulated Square Signals
The above figures show that after modulation the sideband harmonic is attenuated compared to the non-
modulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the
modulation index (mf) the larger the attenuation.
δ ´ ƒc
mƒ
=
ƒm
(1)
With:
fc is the carrier frequency
fm is the modulating frequency (approx. 0.008*fc)
δ is the modulation ratio (approx 0.1)
Dƒc
d =
ƒc
(2)
The maximum switching frequency fc is limited by the process and finally the parameter modulation ratio (δ),
together with fm , which is the side-band harmonics bandwidth around the carrier frequency fc. The bandwidth of
a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as:
B = 2 ´ ¦m ´ 1 + m = 2 ´ D¦ + ¦m
(
)
(
)
¦
c
(3)
(1) Spectrum illustrations and formulae (Figure 26 and Figure 27) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC
COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005. See References section for full citation.
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Feature Description (continued)
fm < RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are
added in the input filter and the measured value is higher than expected in theoretical calculations.
fm > RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the
measurements match with the theoretical calculations.
10.3.5 Short-Circuit Protection
The TPS6267x integrates a P-channel MOSFET current limit to protect the device against heavy load or short
circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned
off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle
basis.
As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal
value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half
of its nominal current limit until the output voltage exceeds approximately 0.5V. This needs to be considered
when a load acting as a current sink is connected to the output of the converter.
10.3.6 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature again falls below typically 130°C.
10.4 Device Functional Modes
10.4.1 Soft Start
The TPS6267x has an internal soft-start circuit that limits the inrush current during start-up. This limits input
voltage drops when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of
the output voltage. This mode of operation continues for c.a. 100μs after enable. Should the output voltage not
have reached its target value by this time, such as in the case of heavy load, the soft-start transitions to a second
mode of operation.
The converter then operates in a current limit mode, specifically the P-MOS current limit is set to half the nominal
limit, and the N-channel MOSFET remains on until the inductor current has reset. After a further 100 μs, the
device ramps up to the full current limit operation if the output voltage has risen above 0.5V (approximately).
Therefore, the start-up time mainly depends on the output capacitor and load current.
10.4.2 Enable
The TPS6267x device starts operation when EN is set high and starts up with the soft start as previously
described. For proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin Low, forces the device into shutdown with a shutdown quiescent current of typically 0.1μA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off.
When an external clock signal (EXTCLK), 4MHz to 27MHz, is applied to the TPS62674 or TPS62679, the DC/DC
converter powers-up automatically within approx. 120μs (TPS62674) or 450μs (TPS62679). When the external
clock signal is stopped, the DC/DC converter is powered down and the output capacitor is discharged actively.
10.4.3 Active Output Discharge
The TPS62674, TPS626751, TPS626765 and TPS62679 actively discharge the output capacitor when turned off.
The integrated discharge resistor has a typical resistance of 70 Ω. The required time to discharge the output
capacitor at the output node depends on load current and the output capacitance value.
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Device Functional Modes (continued)
10.4.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6267x device
have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1V input voltage.
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11 Application and Implementation
11.1 Application Information
TPS6267x are high frequency step-down converters. They can convert from a 2.3V to 4.8V input source to
various fixed output voltages, providing up to 500mA. Needing a minimum amount of external components, the
design procedure is easy to do and usually done by choosing input and output capacitor as well as an
appropriate inductor which is described in the sections below.
11.2 Typical Applications
11.2.1 TPS6267x Point-Of-Load Supply
V
V
OUT
1.8 V @ 500mA
TPS62671
VIN
BAT
2.3 V .. 4.8 V
L
SW
0.47 mH
C
I
FB
EN
C
O
2.2 mF
4.7 mF
MODE
GND
Figure 28. 1.8V/0.5A Power Supply Using TPS62671
11.2.1.1 Design Requirements
The TPS6267x devices are optimized to work with the external components as shown in Figure 28, providing
stable operation for the input voltage and load current range up to 500mA. Connecting the MODE pin to GND
provides PWM/PFM operation.
11.2.1.2 Detailed Design Procedure
11.2.1.2.1 Inductor Selection
The TPS6267x series of step-down converters have been optimized to operate with an effective inductance
value in the range of 0.3μH to 1.8μH and with output capacitors in the range of 2.2μF to 4.7μF. The internal
compensation is optimized to operate with an output filter of L = 0.47μH and CO = 2.2μF. Larger or smaller
inductor values can be used to optimize the performance of the device for specific operation conditions. For more
details, see the CHECKING LOOP STABILITY section.
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.
V
V * V
DI
O
I
O
L
DI +
DI
+ I
)
L
L(MAX)
O(MAX)
2
V
L ƒ
sw
I
(4)
With:
fSW = switching frequency (6 MHz typical)
L = inductor value
ΔIL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC), and the following frequency-
dependent components:
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Typical Applications (continued)
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS6267x converters.
Table 1. List of Inductors(1)
MANUFACTURER
SERIES
LQM21PN1R0NGR
DIMENSIONS (in mm)
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 0.55 max. height
2.0 x 1.2 x 0.55 max. height
1.6 x 0.8 x 0.4 max. height
1.6 x 0.8 x 0.33 max. height
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 1.0 max. height
1.6 x 0.8 x 1.0 max. height
1.6 x 0.8 x 0.55 max. height
1.6 x 0.8 x 0.4 max. height
1.6 x 0.8 x 0.33 max. height
2.0 x 1.2 x 1.0 max. height
2.0 x 1.2 x 0.6 max. height
2.0 x 1.2 x 1.0 max. height
LQM21PNR47MC0
MURATA
LQM21PN1R0MC0
LQM18PN1R5-B35
LQM18PN1R5-A62
PANASONIC
SEMCO
ELGTEAR82NA
CIG21L1R0MNE
BRC1608T1R0M6, BRC1608TR50M6
CKP1608L1R5M
TAIYO YUDEN
CKP1608U1R5M
CKP1608S1R0M, CKP1608S1R5M
NM2012NR82, NM2012N1R0
MLP2012SR82T
TDK
TOKO
MDT2012-CR1R0A
(1) See Third-Party Products Disclaimer
11.2.1.2.2 Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS6267x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. For best performance, the device should be operated with a minimum effective output
capacitance of 0.8μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
impedance.
At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load
transitions. A 2.2μF or 4.7μF ceramic capacitor typically provides sufficient bulk capacitance to stabilize the
output during large load transitions. The typical output voltage ripple is 1% of the nominal output voltage VO.
For best operation (i.e. optimum efficiency over the entire load current range, proper PFM/PWM auto transition),
the TPS6267x requires a minimum output ripple voltage in PFM mode. The typical output voltage ripple is ca. 1%
of the nominal output voltage VO. The PFM pulses are time controlled resulting in a PFM output voltage ripple
and PFM frequency that depends (first order) on the capacitance seen at the converter's output.
11.2.1.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 1 or 2.2-μF capacitor is sufficient. If the application exhibits a
noisy or erratic switching frequency, the remedy will probably be found by experimenting with the value of the
input capacitor.
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Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
11.2.1.2.4 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
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11.2.1.3 Application Curves
V = 3.6 V,
I
V = 3.6 V,
I
V
= 1.8 V
V = 1.8 V
O
O
30 to 300 mA Load Step
30 to 300 mA Load Step
2.7V to 3.3V Line Step
3.3V to 3.9V Line Step
MODE = Low
MODE = Low
Figure 29. Combined Line/Load Transient Response
Figure 30. Combined Line/Load Transient Response
V = 3.6 V,
V = 3.6 V,
I
I
V
= 1.2 V
V
= 1.2 V
O
50 to 350 mA Load Step
O
5 to 150 mA Load Step
MODE = Low
MODE = Low
Figure 31. Load Transient Response in PFM/PWM
Operation
Figure 32. Load Transient Response in PFM/PWM
Operation
V = 2.7 V,
V = 4.8 V,
I
I
V
= 1.2 V
V = 1.2 V
O
50 to 350 mA Load Step
50 to 350 mA Load Step
O
MODE = Low
MODE = Low
Figure 33. Load Transient Response in PFM/PWM
Operation
Figure 34. Load Transient Response in PFM/PWM
Operation
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V = 3.6 V,
V = 2.7 V,
I
I
V
= 1.2 V
V
= 1.2 V
O
O
150 to 500 mA Load Step
150 to 500 mA Load Step
MODE = Low
MODE = Low
Figure 35. Load Transient Response in PWM/PWM
Operation
Figure 36. Load Transient Response in PWM/PWM
Operation
V = 4.8 V,
V = 3.6 V,
I
I
V
= 1.2 V
V = 1.8 V
O
O
150 to 500 mA Load Step
5 to 150 mA Load Step
MODE = Low
MODE = Low
Figure 37. Load Transient Response in PWM/PWM
Operation
Figure 38. Load Transient Response in PFM/PWM
Operation
V = 3.6 V,
V = 3.6 V,
I
I
V
= 1.8 V
V = 1.8 V
O
O
50 to 350 mA Load Step
150 to 500 mA Load
MODE = Low
MODE = Low
Figure 39. Load Transient Response in PFM/PWM
Operation
Figure 40. Load Transient Response in PWM/PWM
Operation
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V = 3.6 V,
I
V = 3.6 V,
I
V
= 1.2 V
V = 1.8 V
O
O
5 to 300 mA Load Sweep
5 to 300 mA Load Sweep
MODE = Low
MODE = Low
Figure 41. AC Load Transient Response
Figure 42. AC Load Transient Response
V = 3.6 V,
V = 3.6 V,
I
I
V
I
= 1.2 V,
V
I
= 1.2 V,
O
O
= 200 mA
= 150 mA
O
O
MODE = Low
MODE = Low
Figure 43. Typical PWM Mode Operation
Figure 44. PWM Mode Operation - SSFM Modulation
V = 3.6 V, V = 1.2V, I = 40 mA
I
O
O
V = 3.6 V,
I
V
I
= 1.8 V,
O
= 0 mA
O
MODE = Low
MODE = Low
Figure 45. Typical Power Save Mode Operation
Figure 46. Start-Up
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V = 3.6 V,
V = 3.6 V,
I
I
V
I
= 1.2 V,
V
I
= 1.2 V,
O
O
= 0 mA
= 0 mA
O
O
MODE = Low
MODE = High
Figure 47. Start-Up
Figure 48. Start-Up (RF Clock)
V = 3.6 V,
I
V
I
= 1.2 V,
= 0 mA,
O
O
C
= 4.7uF 6.3V X5R (0402)
O
MODE = High
Figure 49. Shut-Down (RF Clock)
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11.2.2 1.26V CMOS Sensor Embedded Power Solution — Featuring Sub 0.4mm Profile
V
V
OUT
1.26 V @ 500 mA
TPS62674
VIN
BAT
2.3 V .. 4.8 V
L
SW
FB
1.5 mH
C
O
C
I
MODE
2.2 mF
1 mF
L = muRata LQM18PN1R5-B35
CI = muRata GRM153R60J105M
EN
GND
EXTCLK
CO = muRata GRM153R60G225M
Figure 50. 1.26V CMOS Sensor Embedded Power Solution — Featuring Sub 0.4mm Profile
11.2.2.1 Design Requirements
A CMOS sensor power supply providing a voltage of 1.26V is needed. The profile height mustn't exceed 0.4mm
and the device is enabled/switched off by external clock signal.
11.2.2.2 Detailed Design Procedure
See previous Detailed Design Procedure. To provide 1.26V, the TPS62674 or TPS62679 can be used. The
inductor can be chosen from Table 1, selecting low profile device. Startup and shut down sequence with external
clock are shown below.
11.2.2.3 Application Curves
V = 3.6 V,
I
TPS62679
V
= 1.26 V,
= 0 mA
O
I
O
V = 3.6 V,
I
V
I
= 1.26 V,
O
= 0 mA
O
L = TY CKP1608S1R0,
= TY AMK105BJ225MP
L = TY CKP1608S1R0,
= TY AMK105BJ225MP
C
O
C
O
MODE = Low
MODE = Low
Figure 51. Start-Up (RF Clock)
Figure 52. Shut-Down (RF Clock)
12 Power Supply Recommendations
The power supply of TPS6267X devices needs to have appropriate current rating to support input and output
voltage range for the maximum load current.
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13 Layout
13.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6267x devices demand careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low
inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.
The ground pins of the dc/dc converter must be strongly connected to the PCB ground (i.e. reference potential
across the system). These ground pins serve as the return path for both the control circuitry and the synchronous
rectifier. Furthermore, due to its high frequency switching circuitry, it is imperative for the input capacitor to be as
close to the SMPS device as possible, and that there is an unbroken ground plane under the TPS6267x and its
external passives. Additionally, minimizing the area between the SW pin trace and inductor will limit high
frequency radiated energy. The feed-back line should be routed away from noisy components and traces (e.g.
SW line).
The output capacitor carries the inductor ripple current. While not as critical as the input capacitor, an unbroken
ground connection from this capacitor’s ground return to the inductor, input capacitor and SMPS device will
reduce the output voltage ripple and it’s associated ESL step. This is a critical aspect to achieve best loop and
frequency stability.
High frequency currents tend to find their way on the ground plane along a mirror path directly beneath the
incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that
layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back
through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There
should be a group of vias in the surrounding of the dc/dc converter leading directly down to an internal ground
plane. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the
PCB (i.e. onto which the components are located).
13.2 Layout Example
MODE
VIN
CI
L
ENABLE
CO
GND
VOUT
Figure 53. Suggested Layout (Top)
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14 Device and Documentation Support
14.1 Device Support
14.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
14.2 Documentation Support
14.2.1 Related Documentation
14.2.1.1 References
"EMI Reduction in Switched Power Converters Using Frequency Modulation Techniques", in IEEE
TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 4, NO. 3, AUGUST 2005, pp 569-576 by
Josep Balcells, Alfonso Santolaria, Antonio Orlandi, David González, Javier Gago.
14.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TPS62671
TPS62672
TPS62674
TPS62675
TPS626751
TPS626765
TPS62679
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
14.4 Trademarks
NanoFree is a trademark of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
14.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62671YFDR
TPS62671YFDT
TPS62672YFDR
TPS62672YFDT
TPS62674YFDR
TPS62674YFDT
TPS626751YFDR
TPS626751YFDT
TPS62675YFDR
TPS62675YFDT
TPS626765YFDR
TPS626765YFDT
TPS62679ZYFMR
TPS62679ZYFMT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSLGA
DSLGA
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFM
YFM
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
NZ
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
CUNIPD
CUNIPD
NZ
1BCS
1BCS
PN
PN
E3
E3
OB
OB
EH
EH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62671YFDR
TPS62671YFDT
TPS62672YFDR
TPS62672YFDT
TPS62674YFDR
TPS62674YFDT
TPS626751YFDR
TPS626751YFDT
TPS62675YFDR
TPS62675YFDT
TPS626765YFDR
TPS626765YFDT
TPS62679ZYFMR
TPS62679ZYFMT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSLGA
DSLGA
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFM
YFM
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.03
1.04
1.04
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.53
1.41
1.41
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.56
0.21
0.21
2.0
2.0
4.0
4.0
4.0
4.0
2.0
2.0
2.0
2.0
2.0
4.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62671YFDR
TPS62671YFDT
TPS62672YFDR
TPS62672YFDT
TPS62674YFDR
TPS62674YFDT
TPS626751YFDR
TPS626751YFDT
TPS62675YFDR
TPS62675YFDT
TPS626765YFDR
TPS626765YFDT
TPS62679ZYFMR
TPS62679ZYFMT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSLGA
DSLGA
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFD
YFM
YFM
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
182.0
182.0
182.0
210.0
182.0
210.0
182.0
210.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
185.0
182.0
185.0
182.0
185.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
35.0
20.0
35.0
20.0
35.0
20.0
20.0
20.0
20.0
20.0
20.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
D: Max = 1.33 mm, Min = 1.27 mm
E: Max = 0.956 mm, Min =0.896 mm
PACKAGE OUTLINE
YFD0006
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.4 MAX
C
SEATING PLANE
0.05 C
0.175
0.125
SYMM
C
B
A
0.8
TYP
SYMM
D: Max = 1.33 mm, Min = 1.27 mm
E: Max = 0.956 mm, Min =0.896 mm
0.4
TYP
1
2
0.25
0.15
6X
0.015
C A B
0.4
TYP
4219510/A 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFD0006
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X ( 0.225)
1
2
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
0.05 MIN
(
0.225)
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
(
0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219510/A 11/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFD0006
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
6X ( 0.25)
2
1
A
B
(0.4)
TYP
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219510/A 11/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2023, Texas Instruments Incorporated
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