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TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

TPS62745 面向低功耗无线应用的双节超低 I_Q降压转换器

1 特性

3 说明

1

•

3.3V 至 10V 的输入电压 (V_IN) 范围

400nA 静态电流典型值

TPS62745 是一款高效超低功耗同步降压转换器，针

对低功耗无线应用进行了优化。其提供的稳压输出仅

消耗 400nA 的静态电流。该器件由两节可再充电的锂

离子电池（锂电池主要化学成分是 Li-SOCl2、Li-

SO2、Li-MnO2）或者四到六节碱性电池供电。该器

件的输入电压范围高达 10V，因此也可以通过 USB 端

口和薄膜太阳能模块供电。输出电压通过四个 VSEL

引脚设置，TPS62745 的电压范围为 1.8V 至

3.3V；TPS627451 的电压范围为 1.3V 至 2.8V。

TPS62745 搭配使用小型输出电容，特有低输出纹波

电压和低噪声。由引脚 EN_VIN_SW 控制的内部输入

电压开关将电源电压连接至引脚 VIN_SW。此开关专

用于外部分压器，按比例降低外部 ADC 的输入电压。

当电源电压低于欠压锁定阈值时，此开关会自动断开。

TPS62745 采用小型 12 引脚 3mm × 2mm WSON 封

装。

•

负载电流 >15µA 时的效率高达 90%

输出电流高达 300mA

射频 (RF) 友好型 DCS-Control™

低输出纹波电压

16 种可选输出电压：

–

1.8V 至 3.3V (TPS62745)

1.3V 至 2.8V (TPS627451)

•

集成输入电压开关

VOUT 集成放电功能

漏极开路电源正常输出

采用微型 3.3µH 或 4.7µH 电感

小型 3mm x 2mm WSON 封装

2 应用

•

Bluetooth® 低功耗、消费类电子产品用射频

(RF4CE)、短距离低功耗通信技术 (Zigbee)

器件信息⁽¹⁾

器件型号

TPS62745

TPS627451

封装

封装尺寸（标称值）

•

工业用仪表计量

WSON

3mm x 2mm

能量采集

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

4 典型应用电路原理图

空白

TPS62745

VIN = 3.3 V to 10 V

4.7 µH

L

VOUT = 1.8 V

效率与输出电流间的关系；Vo = 3.3V

VIN

CIN

SW

COUT

10 µF

100

90

80

70

60

50

10 µF

EN

VOUT

PG

EN_VIN_SW

VIN_SW

VSEL1

VSEL2

VSEL3

VSEL4

40

GND

V_IN= 4.0V

30

20

10

0

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1P

10P

100P

1m

10m

100m

Output Current (A)

D001

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSC68

TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

9.4 Device Functional Modes........................................ 12

9.5 VOUT Discharge..................................................... 12

9.6 Internal Current Limit .............................................. 12

10 Application and Implementation........................ 13

10.1 Application Information.......................................... 13

10.2 Typical Application ............................................... 13

10.3 System Examples ................................................ 21

11 Power Supply Recommendations ..................... 25

12 Layout................................................................... 25

12.1 Layout Guidelines ................................................. 25

12.2 Layout Example .................................................... 25

13 器件和文档支持 ..................................................... 26

13.1 器件支持 ............................................................... 26

13.2 相关链接................................................................ 26

13.3 社区资源................................................................ 26

13.4 商标....................................................................... 26

13.5 静电放电警告......................................................... 26

13.6 Glossary................................................................ 26

14 机械、封装和可订购信息....................................... 26

1

2

3

4

5

6

7

8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

典型应用电路原理图................................................. 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

8.1 Absolute Maximum Ratings ...................................... 5

8.2 ESD Ratings ............................................................ 5

8.3 Recommended Operating Conditions....................... 5

8.4 Thermal Information ................................................. 6

8.5 Electrical Characteristics........................................... 6

8.6 Timing Characteristics............................................... 8

8.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 10

9.1 Overview ................................................................. 10

9.2 Functional Block Diagram ....................................... 10

9.3 Feature Description................................................. 10

9

5 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2015) to Revision A

Page

•

已更改状态至“量产数据” ........................................................................................................................................................ 1

2

TPS62745, TPS627451

www.ti.com.cn

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

6 Device Comparison Table⁽¹⁾

Device Number

TPS62745

Output voltage range

marking

PD5I

1.8 V to 3.3 V in 100-mV steps

1.3 V to 2.8 V in 100-mV steps

TPS627451

PD6I

(1) For all available packages, see the orderable addendum at the end of the datasheet.

7 Pin Configuration and Functions

DSS Package

12-Pin WSON

Top View

1

2

3

4

5

6

12

11

10

9

VIN

SW

EN

VSEL1

VSEL2

VSEL3

VSEL4

PG

GND

EN_VIN_SW

VOUT

8

7

VIN_SW

Pin Functions

I/O

DESCRIPTION

NAME

NO.

V_INpower supply pin. Connect this pin close to the VIN terminal of the input capacitor. A

ceramic capacitor of 4.7 µF from this pin to GND is required.

VIN

1

PWR

OUT

PWR

This is the switch pin which is connected to the internal MOSFET switches. Connect the

inductor to this terminal.

SW

2

3

GND supply pin. Connect this pin close to the GND terminal of the input and output

capacitor.

GND

This pin connects / disconnects the internal switch from VIN to pin VIN_SW. With

EN_VIN_SW = Low, the switch is open. With EN_VIN_SW = High, the switch is closed

connecting VIN with VIN_SW. If not used, the pin should be tied to GND.

EN_VIN_SW

4

IN

Feedback pin for the internal feedback divider network and regulation loop. Connect this pin

directly to the output capacitor with a short trace.

VOUT

5

6

IN

This is the output of a switch connecting VIN with VIN_SW when EN_VIN_SW = High. If not

used, leave this pin open.

VIN_SW

OUT

PG

7

8

OUT

IN

This is an open drain power good output.

VSEL4

VSEL3

VSEL2

VSEL1

9

IN

Output voltage selection pins. See Table 1 and Table 2 for V_OUTselection. These pins must

be terminated.

10

11

IN

High level enables the devices, low level turns the device into shutdown mode. This pin must

be terminated.

EN

12

IN

EXPOSED

THERMAL

PAD

Not electrically connected to the IC. Connect this pad to GND and use it as a central GND

plane.

NC

3

TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Table 1. Output Voltage Setting for TPS62745

Device

VOUT / V

1.8

VSEL4

VSEL 3

VSEL 2

VSEL 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.9

2.0

2.1

2.2

2.3

2.4

2.5

TPS62745

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

Table 2. Output Voltage Setting for TPS627451

Device

VOUT / V

1.3

VSEL4

VSEL 3

VSEL 2

VSEL 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.4

1.5

1.6

1.7

1.8

1.9

2.0

TPS627451

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

4

TPS62745, TPS627451

www.ti.com.cn

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

8 Specifications

8.1 Absolute Maximum Ratings

(1)

Over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX

12

UNIT

V

VIN

SW, VIN_SW⁽²⁾

V_IN+0.3

6

V

EN

V

Voltage

EN_VIN_SW, VSEL1-4

V

PG

6

V

VOUT

3.6

V

Power Good Sink Current

V_INSwitch Output Current

Junction temperature, T_J

Storage temperature, T_stg

PG

10

mA

°C

VIN_SW

10

–40

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The DC voltage on the SW pin must not exceed 3.6 V

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

10

UNIT

V

Supply voltage V_IN

3.3

Output current I_OUT

V_OUT+ 0.7 V ≤ V_IN≤ 10 V

300

6.2

mA

µH

µF

Effective inductance

2.8

3

4.7

10

Capacitance connected to VIN pin

Total effective capacitance connected to

5

10

22

µF

(1)

VOUT pin

Operating junction temperature range, T_J

Operating ambient temperature range, T_A

–40

125

85

°C

(1) Due to the DC bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied.

This is why the capacitance is specified to allow the selection of the smallest capacitor required with the DC bias effect for this type of

capacitor in mind. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required.

5

TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

8.4 Thermal Information

TPS62745

DSS

THERMAL METRIC⁽¹⁾

UNIT

12 PINS

61.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

70.9

25.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.9

ψ_JB

25.7

R_θJC(bot)

7.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_IN= 6 V, T_J= –40°C to 125°C typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

V_OUT+ 0.7 V ≤ V_IN≤ 10 V ; min 3.3 V, whichever

value is higher

V_IN

Input voltage range

3.3

10

1960

1200

V

EN = V_IN, device not switching; I_OUT= 0 µA;

V_OUT= 2 V; T_J= –40°C to 85°C

I_Q

Operating quiescent current

400

130

nA

EN = GND, shutdown current into V_IN

;

T_J= -40°C to 85°C

I_SD

Shutdown current

nA

V

EN = GND, shutdown current into V_IN; T_J= 60°C

Rising V_IN; T_J= –40°C to 85°C

830

3.3

3.1

V_{TH_UVLO+}

V_{TH_UVLO-}

3.1

2.9

Undervoltage lockout

threshold

Falling V_IN; T_J= –40°C to 85°C

INPUTS (EN, EN_VIN_SW, VSEL1-4)

V_{IH TH}

V_{IL TH}

High level input voltage

Low level input voltage

V

_{TH_UVLO-}≤ V_IN≤ 10 V

1.2

V

0.35

10

T_J= 25°C

Input bias current; except EN

I_IN

T_J= 60°C

20

nA

T_J= –40°C to 85°C

T_J= 25°C

50

20

I_IN

Input bias current for EN pin

T_J= 60°C

40

T_J= –40°C to 85°C

100

POWER SWITCHES

High side MOSFET on-

0.6

0.5

0.98

0.85

720

resistance

R_DS(ON)

V_IN= 4 V, I = 140 mA

Ω

Low side MOSFET on-

resistance

High side MOSFET DC switch

current limit

480

600

I_LIMF

3.6 V ≤ V_IN≤ 10 V; device not in soft start

mA

Low side MOSFET DC switch

current limit

6

TPS62745, TPS627451

www.ti.com.cn

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

Electrical Characteristics (continued)

V_IN= 6 V, T_J= –40°C to 125°C typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT DISCHARGE SWITCH (VOUT)

R_{DSCH_VOUT}MOSFET on-resistance

EN = GND, I_OUT= –10 mA into VOUT pin

T_J= 25°C

25

40

60

100

500

Ω

I_{IN_VOUT}

Bias current into VOUT pin⁽¹⁾EN = V_IN, V_OUT= 2 V

nA

T_J= –40°C to 85°C

INPUT VOLTAGE SWITCH (VIN_SW)

R_DS(ON)

MOSFET on-resistance

EN_VIN_SW = High, I_{VIN_SW}= 1 mA

85

160

20

5

Ω

EN_VIN_SW = GND; leakage from VIN to VIN_SW

when pulled to GND; T_J= –40°C to 85°C

I_{VIN_SW_LKG}VIN-switch leakage current

-20

95

nA

mA

I_{VIN_SW}

POWER GOOD OUTPUT (PG)

V_{TH_PG+}Power good threshold voltage Rising output voltage on VOUT pin

VIN-switch current

97.5

3

%

Power good threshold

hysteresis

V_{TH_HYS}

Falling output voltage on VOUT pin

3.3 V ≤ V_IN≤ 10 V, EN = GND,

current into PG pin I_PG= 4 mA

V_OL

V_OH

Low level output threshold

High level output threshold

0.3

6

V

3.3 V ≤ V_IN≤ 10 V, EN = high,

current into PG pin I_PG= 0 mA

Bias current into power good

PG pin is high impedance, VOUT = 2 V,

EN = V_IN, I_OUT= 0 mA; T_J= –40°C to 85°C

I_{IN_PG}

20

nA

OUTPUT

I_{LIM_softstart}

Switch current limit during soft Current limit is reduced during soft start,

40

1.8

1.3

110

180

3.3

2.8

mA

V

start

T_J= –40°C to 85°C

For TPS627450; output voltages are selected with

pins VSEL1 - 4

Output voltage range

For TPS627451; output voltages are selected with

pins VSEL1 - 4

PFM mode, I_OUT= 0 mA, V_OUT+ 0.6 V ≤ V_IN≤ 10 V;

min 3.3 V, whichever value is higher;

T_J= –40°C to 85°C

-2.5

–2

0

2.5

2

Output voltage accuracy

%

V_VOUT

PWM Mode, V_OUT+ 0.7 V ≤ V_IN≤ 10 V; min 3.3 V,

whichever value is higher; T_J= –40°C to 85°C

0

0.005

0.001

0.015

DC output voltage load

regulation

V_OUT= 2.0 V; I_OUT= 2 mA to 80 mA (PFM mode)

%/mA

%/V

DC output voltage load

regulation

V_OUT= 2.0 V; I_OUT= 150 mA to 300 mA (PWM

mode)

DC output voltage line

regulation

V_OUT= 2.0 V, I_OUT= 300 mA, 4 V ≤ V_IN≤ 10 V

(1) A 50-MΩ (typical) internal resistor divider is internally connected to the VOUT pin

7

TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

8.6 Timing Characteristics

V_IN= 6 V, T_J= –40°C to 125°C typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

t_delay

UVLO delay time

response time of UVLO circuit

200

µs

INPUT VOLTAGE SWITCH (VIN_SW)

VIN-switch turn-on settling

Time from EN_VIN_SW = High until R_DS(ON)is within

specification

t_{VIN_SW}

time

100

200

µs

POWER GOOD OUTPUT (PG)

t_delay

PGOOD delay time

Response time of PGOOD circuit; falling edge

OUTPUT

t_ONmin

Minimum ON time

Minimum OFF time

V_IN= 6 V, V_OUT= 2.0 V, I_OUT= 0 mA

V_IN= 3.3 V

256

50

ns

t_OFFmin

V_IN= 6 V, from transition EN = Low to High until

device starts switching, T_J= -40°C to 85°C

t_Start

Regulator start up time

15

50

ms

µs

Softstart time with reduced

switch current limit

t_Softstart

3.3 V ≤ V_IN≤ 10 V, EN = V_IN

700

8

TPS62745, TPS627451

www.ti.com.cn

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

8.7 Typical Characteristics

700

600

500

400

300

200

500

450

400

350

300

250

200

150

100

50

T_A= -40qC

T_A= 0qC

T_A= 25qC

T_A= 60qC

T_A= 85qC

T_A= -40qC

T_A= 60qC

T_A= 85qC

100

0

T_A= 0qC

T_A= 25qC

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Input Voltage (V)

D038

D039

EN = VIN, VOUT = 1.8 V,

EN_VIN_SW = GND

Device Not Switching

EN = GND, EN_VIN_SW = GND

Figure 2. Shutdown Current

Figure 1. Quiescent Current

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T_A= -40qC

T_A= 0qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 0qC

T_A= 25qC

T_A= 85qC

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Input Voltage (V)

D037

D040

Figure 3. R_DS(ON)High-Side MOSFET

Figure 4. R_DS(ON)Low-Side MOSFET

9

TPS62745, TPS627451

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

9 Detailed Description

9.1 Overview

The TPS62745 is the first dual-cell, ultra low power step down converter combining TI's DCS-Control™ topology

and ultra low quiescent current consumption (400 nA typical) while maintaining a regulated output voltage. The

device extends high efficiency operation to output currents down to a few micro amperes.

9.2 Functional Block Diagram

Current

Limit Comparator

Power Stage

PMOS

VIN

Timer

UVLO

EN

DCS

Control

VIN

Limit

High Side

Min. On

VOS

Min. OFF

VOUT

Control

Logic

Direct Control

& Compensation

Gate Driver

Anti

Comparator

SW

Shoot-Through

V_{OUT_SET}

NMOS

Limit

Low Side

Error

amplifier

GND

Current

Limit Comparator

UVLO

EN

Ultra Low Power

Reference 1.2V

V_OUT

Discharge

VOUT

Softstart

EN

V_REF

PG

VIN

VSEL 1

VSEL 2

Vin-switch

V_OUT

Selection +

V_{OUT_SET}

UVLO

Comp

PG Comp

EN_VIN_SW

V_OUT

EN

VIN

VSEL 3

VSEL 4

UVLO

Setting

V_{TH_PG}

UVLO

V_{TH_UVLO}

VIN_SW

9.3 Feature Description

9.3.1 DCS-Control™

TI's DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode) is an advanced regulation

topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS -

Control^TMare excellent AC load regulation and transient response, low output ripple voltage and a seamless

transition between pulse frequency modulation (PFM) and pulse width modulation (PWM) mode operation. DCS-

Control^TMincludes an AC loop which senses the output voltage (VOUT pin) and directly feeds the information to

a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state

operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate

DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves

fast and stable operation with small external components and low ESR capacitors. The DCS-Control^TMtopology

supports PWM mode for medium and high load conditions and a power save mode at light loads. During PWM

mode, it operates in continuous conduction. The switching frequency is up to 2.5 MHz with a controlled frequency

variation depending on the input voltage. If the load current decreases, the converter seamlessly enters power

save mode to maintain high efficiency down to very light loads. In power save mode the switching frequency

varies linearly with the load current. Since DCS-Control^TMsupports both operation modes within one single

building block, the transition from PWM to power save mode is seamless without effects on the output voltage.

The TPS62745 offers both excellent DC voltage and superior load transient regulation, combined with very low

10

TPS62745, TPS627451

www.ti.com.cn

ZHCSE11A –JUNE 2015–REVISED JUNE 2015

Feature Description (continued)

output voltage ripple, minimizing interference with RF circuits. At high load currents the converter operates in

quasi fixed frequency PWM mode operation and at light loads in PFM mode to maintain highest efficiency over

the full load current range. In PFM mode, the device generates a single switching pulse to ramp up the inductor

current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are

shutdown to achieve a quiescent current of typically 400-nA. During this time, the load current is supported by

the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.

9.3.2 Enable / Shutdown

The DC/DC converter is activated when EN pin is set to High. For proper operation, the pin must be terminated

and must not be left floating. With EN pin set to Low, the device enters shutdown mode with typical 130 nA

current consumption.

9.3.3 Power Good Output (PG)

The power good comparator features an open drain output. The PG comparator is active with EN pin set to high

and V_INabove the threshold V_{TH_UVLO+}. It is driven to high impedance once V_OUTtrips the threshold V_{TH_PG+}for

rising V_OUT. The output is pulled to low level once V_OUTfalls below the threshold V_{TH_PG-}. The output is as well

pulled to low level in case the input voltage V_INfalls below the undervoltage lockout threshold V_{TH_UVLO-}or the

device is disabled with EN = Low. With EN = High, the output is driven to high impedance state, once the load

current falls below ~1 mA. In this case the PG comparator is turned off to achieve lowest quiescent current. PG

will be triggered when a output voltage change is ongoing due to a change in VSEL pin levels if the new target is

high enough to trigger the PG threshold.

9.3.4 Output Voltage Selection (VSEL1 - 4)

The TPS62745 does not require an external resistor divider network to program the output voltage. The device

integrates a high impedance (typical 50 MΩ ) feedback resistor divider network which is programmed by the pins

VSEL1-4. TPS62745 supports an output voltage range of 1.8 V to 3.3 V in 100-mV steps while the TPS627451

supports an output voltage range of 1.3 V to 2.8 V. The output voltage can be changed during operation and

supports simple dynamic output voltage scaling; see the Application and Implementation section for further

details. The output voltage is programmed according to Table 1 for TPS62745 and Table 2 for TPS627451.

9.3.5 Input Voltage Switch

There is an internal switch that connects the input voltage applied at pin VIN to the VIN_SW output. The switch

can be used to connect an external voltage divider for an ADC monitoring to the input voltage. An enable pin

EN_VIN_SW turns the switch on and off, making sure there is no current through that external voltage divider

when not needed. A logic high level on EN_VIN_SW turns the switch on once the input voltage is above the

undervoltage lockout threshold and the device is enabled. The switch can be used for other purposes as long as

the current rating of 5 mA and its turn-on resistance is observed. An external voltage divider should be in a range

of 10 kΩ to 100 kΩ. Larger values than 100 kΩ can be used as long as the input resistance and capacitance of

the external circuit (e.g. ADC input) is observed.

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9.4 Device Functional Modes

9.4.1 Soft Start

When the device is enabled, the internal reference is powered up and after the startup delay time t _{Startup_delay}has

expired, the device enters soft start, starts switching and ramps up the output voltage. During soft start the

device operates with a reduced current limit, I_{LIM_softstart}, of typical 1/5 of the nominal current limit. This reduced

current limit is active during the soft start time t_Softstart. The current limit is increased to its nominal value, I_LIMF

,

once the soft start time has expired or the power good comparator detects that the output voltage reached its

target value.

9.5 VOUT Discharge

The VOUT pin has a discharge circuit to connect the rail to GND, once it is disabled. This feature prevents

residual charge voltages on the output capacitor, which may impact proper power up of the systems connected

to the converter. With the EN pin pulled to low, the discharge circuit at the VOUT pin becomes active. The

discharge circuit on VOUT is also associated with the UVLO comparator. The discharge circuit becomes active

once the UVLO comparator triggers and the input voltage V_INhas dropped below the UVLO comparator

threshold V_{TH_UVLO-}(typical 2.9 V).

9.6 Internal Current Limit

The TPS62745 integrates a current limit on the high side, as well on the low side MOSFETs to protect the device

against overload or short circuit conditions. The peak current in the switches is monitored cycle by cycle. If the

high side MOSFET current limit is reached, the high side MOSFET is turned off and the low side MOSFET is

turned on until the current decreases below the low side MOSFET current limit.

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10 Application and Implementation

10.1 Application Information

The TPS62745 devices are a step down converter family featuring typical 400-nA quiescent current and

operating with a tiny 4.7-μH inductor and a 10-μF output capacitor. These DCS-Control™ based devices extend

the light load efficiency range below 10-μA load currents. TPS62745 supports output currents up to 300 mA,

10.2 Typical Application

TPS62745

VIN = 3.3 V to 10 V

4.7 µH

L

VOUT = 1.8 V

VIN

SW

CIN

COUT

10 µF

EN

VOUT

PG

EN_VIN_SW

VIN_SW

VSEL1

VSEL2

VSEL3

VSEL4

GND

Figure 5. TPS62745 Typical Application

10.2.1 Design Requirements

The TPS62745 is a highly integrated DC/DC converter. The output voltage is set via the VSEL pin interface

without any additional external components. For proper operation only an input and output capacitor and an

inductor is required. When the input voltage switch is not used, its enable input should be tied to GND. The

output VIN_SW can either be left open or tied to GND. Table 3 shows the components used for the application

characteristic curves.

Table 3. List of Components

(1)

REFERENCE

DESCRIPTION

TPS62745

Value

MANUFACTURER

Texas Instruments

Toko

IC

L

DFE252010

4.7 µH

TMK212BBJ106MG

10 µF / 25 V / X5R /

0805

CIN

Taiyo Yuden

LMK212ABJ106KG-T

10 µF / 10 V / X5R /

0805

COUT

(1) See Third-Party Products Disclaimer

10.2.2 Detailed Design Procedure

10.2.2.1 Output Voltage Selection (VSEL1 - 4)

The VSEL pins select the output voltage of the converters. See the Output Voltage Selection (VSEL1 - 4) of the

Feature Descriptions. The output voltage can be changed during operation by changing the logic level of these

pins. The output voltage of the TPS62745 ramps to the new target with a slew rate as defined in the electrical

characteristics. Typically these pins are driven by an applications processor with an I/O voltage of either 1.8 V or

3.3 V or hard wired to a logic high or logic low signal. In case the pins are not driven from an applications

processor and the supply voltage is higher than the voltage rating of the VSEL pins, a logic high level can be

taken from the output voltage at pin VOUT. During start-up, when the output is rising from 0 V to its target, the

VSEL pins connected to VOUT will change their logic level from low to high. TPS62745 is designed such that

such a configuration ensures a steadily rising output voltage.

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10.2.2.2 Output Filter Design (Inductor and Output Capacitor)

The external components have to fulfill the needs of the application, but also the stability criteria of the devices

control loop. The TPS62745 is optimized to work within a range of L and C combinations. The LC output filter

inductance and capacitance have to be considered together, creating a double pole, responsible for the corner

frequency of the converter. Table 4 can be used to simplify the output filter component selection.

Table 4. Recommended LC Output Filter Combinations

Inductor Value [µH]⁽¹⁾

Output Capacitor Value [µF]⁽²⁾

10 µF

22 µF

(3)

4.7

3.3

√

(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and -

30%.

(2) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by

20% and -50%.

(3) This LC combination is the standard value and recommended for most applications.

10.2.2.3 Inductor Selection

The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage

ripple and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The

inductor ripple current (ΔI_L) decreases with higher inductance and increases with higher V_INor V_OUTand can be

estimated according to Equation 1.

Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 2. This is

recommended because during heavy load transient the inductor current will rise above the calculated value. A

more conservative way is to select the inductor saturation current according to the high-side MOSFET switch

current limit I_LIMF

.

Vout

Vin

1-

DI_L= Vout ´

L ´ ¦

(1)

DI

L

I

= I

+

Lmax

outmax

2

where:

•

f = Switching frequency

L = Inductor value

ΔI_L= Peak-to-peak inductor ripple current

I_Lmax= Maximum inductor current

(2)

In DC/DC converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality

factor) and by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting

inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces

lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance

usually results in an inductor with lower saturation current.

The total losses of the coil consist of both the losses in the DC resistance R_DC) and the following frequency-

dependent components:

•

The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

Additional losses in the conductor from the skin effect (current displacement at high frequencies)

Magnetic field losses of the neighboring windings (proximity effect)

Radiation losses

The following inductor series from different suppliers have been used:

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ZHCSE11A –JUNE 2015–REVISED JUNE 2015

Table 5. List of Inductors

INDUCTANCE

[µH]

DIMENSIONS

INDUCTOR

(1)

DCR [Ω], typical

SUPPLIER

[mm³]

TYPE

4.7

3.3

4.7

3.3

4.7

0.250

0.190

0.336

0.207

0.217

0.270

2.5 x 2.0 x 1.0

2.0 x 1.9 x 1.0

3.0 x 3.0 x 1.1

4.5 x 3.2 x 3.2

DFE252010

XPL2010

TOKO

Coilcraft

Bourns

XPL2010

XFL3010

CC453232

(1) See Third-Party Products Disclaimer

10.2.2.4 DC/DC Output Capacitor Selection

The DCS-Control™ scheme of the TPS62745 allows the use of tiny ceramic capacitors. Ceramic capacitors with

low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires

either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance

over temperature, become resistive at high frequencies. At light load currents, the converter operates in power

save mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor

current. A larger output capacitor can be used, but it should be considered that larger output capacitors lead to

an increased leakage current in the capacitor and may reduce overall conversion efficiency. Furthermore, larger

output capacitors impact the start up behavior of the DC/DC converter. Furthermore, the contol loop of the

TPS62745 requires a certain voltage ripple across the output capacitor. Super-capacitors can be used in parallel

to the ceramic capacitors when it is made sure that the super-capacitors series resistance is large enough to

provide a valid feedback signal to the error amplifier which is in phase with the inductor current. Applications

using an output capacitance above of what is stated under Recommended Operating Conditions should be

checked for stability over the desired operating conditions range.

10.2.2.5 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering to ensure proper function of the device and to minimize input voltage

spikes. For most applications a 10 µF or 4.7 µF ceramic capacitor is recommended. The input capacitor can be

increased without any limit for better input voltage filtering.

Table 6 shows a list of tested input/output capacitors.

Table 6. List of Input and Output Capacitors

(1)

CAPACITANCE [μF]

SIZE

0603

0805

CAPACITOR TYPE

GRM188R61C106MA73

EMK107BBJ106MA

EMK212ABJ475KG

TMK212BBJ106MG

LMK212ABJ106KG-T

SUPPLIER

Murata

10

4.7

10

Taiyo Yuden

(1) See Third-Party Products Disclaimer

15

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ZHCSE11A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

10.2.3 Application Curves

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1P

10P

100P

1m

10m

100m

1P

10P

100P

1m

10m

100m

Output Current (A)

D001

D002

Figure 6. V_OUT= 3.3 V

Figure 7. V_OUT= 2.5 V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1P

100P

Output Current (A)

1m

10m

100m

1P

10P

100P

Output Current (A)

1m

10m

100m

D003

D004

Figure 8. V_OUT= 1.8 V

Figure 9. V_OUT= 1.5 V

3.399

2.625

2.600

2.575

2.550

2.525

2.500

2.475

2.450

2.425

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

3.366

3.333

3.300

3.267

3.234

3.201

V_IN= 10.0V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1P

100P

Output Current (A)

1m

10m

100m

1P

10P

100P

Output Current (A)

1m

10m

100m

D005

D006

Figure 10. V_OUT= 3.3 V

Figure 11. V_OUT= 2.5 V

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ZHCSE11A –JUNE 2015–REVISED JUNE 2015

1.854

1.545

1.530

1.515

1.500

1.485

1.470

1.455

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1.836

1.818

1.800

1.782

1.764

1.746

1P

10P

100P

1m

10m

100m

1P

10P

100P

1m

10m

100m

Output Current (A)

D007

D009

D011

D008

D010

D012

Figure 12. V_OUT= 1.8 V

Figure 13. V_OUT= 1.5 V

1.6M

1.5M

1.4M

1.3M

1.2M

1.1M

1M

900k

800k

700k

600k

500k

400k

300k

200k

100k

0

1.6M

1.5M

1.4M

1.3M

1.2M

1.1M

1M

900k

800k

700k

600k

500k

400k

300k

200k

100k

0

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.4V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Output Current (A)

Figure 14. V_OUT= 3.3 V

Figure 15. V_OUT= 2.5 V

1.5M

1.4M

1.3M

1.2M

1.1M

1M

900k

800k

700k

600k

500k

400k

300k

200k

100k

0

1.6M

1.5M

1.4M

1.3M

1.2M

1.1M

1M

900k

800k

700k

600k

500k

400k

300k

200k

100k

0

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.4V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.4V

V_IN= 8.4V

V_IN= 10.0V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Output Current (A)

Figure 16. V_OUT= 1.8 V

Figure 17. V_OUT= 1.5 V

17

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10m

8m

6m

4m

2m

0

10m

8m

6m

4m

2m

0

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

1P

10P

100P

1m

10m

100m

1

1P

10P

100P

1m

10m

100m

1

Output Current (A)

D014

D015

Figure 18. V_OUT= 3.3 V

Figure 19. V_OUT= 2.5 V

10m

8m

6m

4m

2m

0

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

V_IN= 3.6V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 7.2V

V_IN= 8.4V

V_IN= 10.0V

8m

6m

4m

2m

0

1P

10P

100P

1m

10m

100m

1

1P

10P

100P

1m

10m

100m

1

Output Current (A)

D016

D017

Figure 20. V_OUT= 1.8 V

Figure 21. V_OUT= 1.5 V

Figure 22. Line Transient Response; V_OUT= 3.3 V

Figure 23. Line Transient Response; V_OUT= 2.5 V

18

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ZHCSE11A –JUNE 2015–REVISED JUNE 2015

Figure 24. Line Transient Response; V_OUT= 1.8 V

Figure 25. Line Transient Response; V_OUT= 1.5 V

Figure 26. Load Transient Response; V_OUT= 3.3 V

Figure 27. Load Transient Response; V_OUT= 2.5 V

Figure 28. Load Transient Response; V_OUT= 1.8 V

Figure 29. Load Transient Response; V_OUT= 1.5 V

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Figure 31. Startup with V_OUT= 2.5 V

Figure 30. Startup with V_OUT= 3.3 V

Figure 32. Startup with V_OUT= 1.8 V

Figure 33. Startup with V_OUT= 1.5 V

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10.3 System Examples

10.3.1 TPS62745 Set to a Fixed Voltage of 3.3 V

TPS62745

VIN = 3.9 V to 10 V

4.7 µH

L

VOUT = 3.3 V

VIN

SW

CIN

COUT

10 µF

EN

VOUT

PG

EN_VIN_SW

VIN_SW

VSEL1

VSEL2

VSEL3

VSEL4

GND

Figure 34. TPS62745 Typical Application for Vout = 3.3 V

10.3.1.1 Design Requirements

The minimum input voltage needs to be at least 700 mV above the desired output voltage for full output current.

Table 7. List of Components

(1)

REFERENCE

DESCRIPTION

TPS62745

Value

MANUFACTURER

Texas Instruments

Toko

IC

L

DFE252010

4.7 µH

CIN

COUT

TMK212BBJ106MG

LMK212ABJ106KG-T

10 µF / 25 V / X5R / 0805

10 µF / 10 V / X5R / 0805

Taiyo Yuden

(1) See Third-Party Products Disclaimer

21

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www.ti.com.cn

10.3.1.2 Detailed Design Procedure

The logic level of the VSEL pins sets the output voltage. The maximum high level does not allow a direct

connection to the supply voltage if it is above 6 V. The output voltage can be used instead to provide a logic high

level.

10.3.1.3 Application Curves

Figure 36. TPS62745 with V_OUT= 3.3 V; Output Voltage

Ripple for I_OUT= 1 mA

Figure 35. TPS62745 with V_OUT= 3.3 V Startup

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10.3.2 Dynamic Voltage Change on TPS62745

TPS62745 allows to change its output voltage during operation by changing the logic level of the VSEL pins.

TPS62745

VIN = 3.9 V to 10 V

4.7 µH

L

VOUT = 2.0 V / 3.3 V

VIN

SW

CIN

10 µF

COUT

10 µF

EN

VOUT

PG

EN_VIN_SW

VIN_SW

VSEL1

VSEL2

VSEL3

VSEL4

0: VOUT = 2.0 V

1: VOUT = 3.3 V

GND

Figure 37. TPS62745 Typical Application for Switching Between Two Output Voltages

10.3.2.1 Design Requirements

The minimum input voltage needs to be at least 700 mV above the maximum output voltage for full output

current. For an input voltage above 6V, the VSELx pins have to be tied to the output for a logic high level as their

voltage rating is 6V.

Table 8. List of Components

(1)

REFERENCE

DESCRIPTION

TPS62745

Value

MANUFACTURER

Texas Instruments

Toko

IC

L

DFE252010

4.7 µH

CIN

COUT

TMK212BBJ106MG

LMK212ABJ106KG-T

10 µF / 25 V / X5R / 0805

10 µF / 10 V / X5R / 0805

Taiyo Yuden

(1) See Third-Party Products Disclaimer

23

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www.ti.com.cn

10.3.2.2 Detailed Design Procedure

Toggle the logic level at VSEL1, VSEL3 and VSEL4 to change the output voltage from 2.0 V to 3.3 V and vice

versa. The slope from higher output voltage to the lower output voltage is determined by the load current and

output capacitance because the discharge of the output capacitor is through the load current only.

10.3.2.3 Application Curves

Figure 38. TPS62745 Output Voltage Change from 2.0 V to

3.3 V for I_OUT= 10 mA

Figure 39. TPS62745 Output Voltage Change from 3.3 V to

2.0 V for I_OUT= 10 mA

24

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11 Power Supply Recommendations

The power supply to the TPS62745 needs to have a current rating according to the supply voltage, output

voltage and output current of the TPS62745 shown in the Specifications section.

12 Layout

12.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Especially RF designs demand

careful attention to the PCB layout. Care must be taken in board layout to get the specified performance. If the

layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as

EMI problems and interference with RF circuits. It is critical to provide a low inductance, impedance ground path.

Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close

as possible to the IC pins as well as the inductor and output capacitor. Use a common power GND node and a

different node for the signal GND to minimize the effects of ground noise. Keep the common path to the GND

pin, which returns the small signal components and the high current of the output capacitors as short as possible

to avoid ground noise. The VOUT line should be connected to the output capacitor and routed away from noisy

components and traces (e.g. SW line).

12.2 Layout Example

GND

COUT

CIN

VIN

L

SW

VOUT

Figure 40. Recommended PCB Layout

25

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ZHCSE11A –JUNE 2015–REVISED JUNE 2015

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13 器件和文档支持

13.1 器件支持

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买

链接。

表 9. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

TPS62745

TPS627451

13.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.4 商标

DCS-Control, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

26

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS627451DSSR

TPS627451DSST

TPS62745DSSR

TPS62745DSST

WSON

DSS

12

3000

250

180.0

8.4

2.25

3.25

1.05

4.0

8.0

Q1

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS627451DSSR

TPS627451DSST

TPS62745DSSR

TPS62745DSST

WSON

DSS

12

3000

250

210.0

185.0

35.0

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

DSS0012A

WSON - 0.8 mm max height

SCALE 5.000

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

A

B

0.35

0.25

PIN 1 INDEX AREA

3.1

2.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.9±0.1

4X (0.2)

(0.7)

(0.2) TYP

EXPOSED

THERMAL PAD

0.05

0.00

6

7

SEE TERMINAL

DETAIL

2X

13

2.5

2±0.1

12

1

10X 0.5

0.35

0.25

0.3

0.2

12X

PIN 1 ID

(OPTIONAL)

0.1

C A

C

B

0.05

4222684/A 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSS0012A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

12X (0.5)

12

1

12X (0.25)

13

SYMM

10X (0.5)

(2)

(0.75)

(R0.05) TYP

(

0.2) VIA TYP

NOTE 5

6

7

SYMM

(1.9)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222684/A 02/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

It is recommended that vias located under solder paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSS0012A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

12X (0.5)

1

12

12X (0.25)

METAL

TYP

SYMM

10X (0.5)

13

(0.9)

(R0.05) TYP

6

7

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 13:

90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222684/A 02/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS627451
厂家：	TEXAS INSTRUMENTS
描述：	10Vin 超低 Iq 降压转换器转换器
文件：	总35页 (文件大小：5427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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