TPS62860 [TI]
1.8-V to 5.5-V Input, 0.6-/1-A Synchronous Step-Down Converter with I2C/VSEL Interface;
| 型号： | TPS62860 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.8-V to 5.5-V Input, 0.6-/1-A Synchronous Step-Down Converter with I2C/VSEL Interface |
| 文件： | 总39页 (文件大小：2668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62860, TPS62861
SLUSDU8B – APRIL 2020 – REVISED SEPTEMBER 2020
1.8-V to 5.5-V Input, 0.6-/1-A Synchronous Step-Down Converter with I2C/VSEL
Interface
1 Features
3 Description
•
•
•
•
2.3-μA operating quiescent current
Up to 4-MHz switching frequency
1% output voltage accuracy
DVS output from 0.4 V to 1.9875 V (12.5-mV
steps)
I2C user interface to adjust
The
TPS6286x
devices
are
high-frequency
synchronous step-down converters with I2C- and
VSEL-Interface. They provide an efficient, flexible,
and high-power density point-of-load DC/DC solution.
At medium to heavy loads, the converter operates in
PWM mode and automatically enters Power Save
Mode operation at light load to maintain high
efficiency over the entire load current range. The
device can also be forced in PWM mode operation for
the smallest output voltage ripple. Together, with its
DCS-control architecture, excellent load transient
performance and tight output voltage accuracy are
achieved. With the I2C interface and a dedicated
VSEL pin, the output voltage is quickly adjusted to
adapt the power consumption of the load to the ever-
changing performance needs of the application. The
TPS6286x family is available with two VSEL pins and
four factory preset voltages to allow usage without I2C
interface.
•
– Output voltage presets
– Ramp speed
•
•
•
•
•
•
VSEL-pin to toggle VOUT during operation
Power good indication
Supports <6-mm² solution size
Supports <0.6-mm solution height
Tiny 8-pin, 0.35-mm pitch WCSP package
Optimized pinout to support 0201 components
2 Applications
•
•
•
•
Wearable electronics
Portable electronics
Mobile phones
Medical sensor patches and patient monitors
Device Information
PART
CURRENT PACKAGE (1) BODY SIZE (NOM)
NUMBER
TPS628610
TPS628601
TPS628600
1 A
DSBGA (8)
DSBGA (8)
DSBGA (8)
0.7 x 1.4 x 0.4 mm
0.7 x 1.4 x 0.4 mm
0.7 x 1.4 x 0.4 mm
0.6 A
0.6 A
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPS628610
100
95
90
85
80
75
70
65
60
55
50
VIN
1.8V t 5.5V
0.47µH
VOUT
VIN
SW
10 …F
4.7 …F
GND
VOS
EN
SDA
SCL
VSEL
TPS628601
VIN
1.8V t 5.5V
1.0µH
VOUT
VIN
SW
10 …F
4.7 …F
GND
VOS
TPS628601
TPS628610
45
EN
PG
VSEL-1
VSEL-2
40
10m
100m
1m
10m
100m
1
Load Current [A]
Efficiency versus IOUT at 1.1 VOUT, 3.8 VIN
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62860, TPS62861
SLUSDU8B – APRIL 2020 – REVISED SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions, TPS628610 and TPS628600.................... 3
Pin Functions, TPS628601............................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics.............................................6
7.6 I2C Interface Timing Characteristics ......................... 7
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
8.4 Programming............................................................ 14
8.5 Register Map.............................................................17
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application, TPS628610............................... 20
10 Power Supply Recommendations..............................28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Device Support....................................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 Support Resources................................................. 30
12.4 Trademarks.............................................................30
12.5 Electrostatic Discharge Caution..............................30
12.6 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2020) to Revision B (September 2020)
Page
•
•
•
•
Changed device status of TPS62860 from Advance Information to Production Data ....................................... 1
Added "DVS output from 0.4 V to 1.9875 V (12.5-mV steps)" feature................................................................1
Updated value from 0x8E and 0x8F to 0x7E and 0x7F....................................................................................17
Updated value from 0x8E and 0x8F to 0x7E and 0x7F....................................................................................18
Changes from Revision * (April 2020) to Revision A (August 2020)
Page
Changed device status of TPS62861 from Advance Information to Production Data........................................ 1
Updated the numbering format for tables, figures and cross-references throughout the document. .................1
•
•
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5 Device Comparison Table
ORDERABLE PART NUMBER OUTPUT CURRENT
DEFAULT VO SETTING
0.6 V, 1.1 V
FSW
USER INTERFACE
EN, I2C, VSEL
TPS628600YCH
TPS628601YCH
TPS628610YCH
0.6 A
0.6 A
1 A
1.5 MHz
1.5 MHz
4 MHz
0.6 V, 0.7 V, 0.8 V, 1.0 V
0.6 V, 1.1 V
2x VSEL, EN, PG
EN, I2C, VSEL
6 Pin Configuration and Functions
1
2
A
B
C
D
Figure 6-1. 8-Pin DSBGA YCH Package (Top View)
Pin Functions, TPS628610 and TPS628600
PIN
I/O
DESCRIPTION
NAME
NO.
GND supply pin. Connect this pin close to the GND terminal of the input and output
capacitor.
GND
D2
PWR
Output voltage sense pin for the internal feedback divider network and regulation loop. This
pin also discharges VOUT by an internal MOSFET when the converter is disabled. Connect
this pin directly to the output capacitor with a short trace.
VOS
VIN
D1
C2
IN
VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage
spike suppression. A ceramic capacitor is required.
PWR
The switch pin is connected to the internal MOSFET switches. Connect the inductor to this
terminal.
SW
C1
B2
B1
PWR
IN
VSEL
EN
Voltage Selection Pin. Can be toggled during operation. LOW = 0.6 V, HIGH = 1.1 V
A high level enables the devices and a low level turns the device off. The pin features an
internal pulldown resistor, which is disabled once the device has started up.
IN
SDA
SCL
A2
A1
IN
IN
I2C serial data pin. Do not leave floating.
I2C serial clock pin. Do not leave floating.
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Pin Functions, TPS628601
PIN
I/O
DESCRIPTION
NAME
NO.
GND supply pin. Connect this pin close to the GND terminal of the input and output
capacitor.
GND
D2
PWR
IN
Output voltage sense pin for the internal feedback divider network and regulation loop. This
pin also discharges VOUT by an internal MOSFET when the converter is disabled. Connect
this pin directly to the output capacitor with a short trace.
VOS
VIN
D1
C2
VIN power supply pin. Connect the input capacitor close to this pin for best noise and
voltage spike suppression. A ceramic capacitor is required.
PWR
The switch pin is connected to the internal MOSFET switches. Connect the inductor to this
terminal.
SW
PG
EN
C1
B2
B1
PWR
OUT
IN
Open-drain power-good output
A high level enables the devices and a low level turns the device off. The pin features an
internal pulldown resistor, which is disabled once the device has started up.
VSEL-1
VSEL-2
A2
A1
IN
IN
Voltage Selection Pin. Can be toggled during operation.
Voltage Selection Pin. Can be toggled during operation.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–2.5
–0.3
–0.3
–40
MAX
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
TJ
VIN
6
SW, DC
VIN +0.3V
V
SW, transient < 10 ns, while switching
EN, VSEL, SDA, SCL, PG
VOS
9
6
V
V
5
V
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
1.8
0.4
0
NOM
MAX
5.5
UNIT
V
VIN
Input supply voltage range
Output voltage range
VOUT
1.9875
5.5
V
Pin voltage
SW
V
Pin voltage
EN, SDA, SCL, VSEL, PG
TPS628610, VIN > 2.3V
TPS628610, VIN <= 2.3V
TPS62860x
0
5.5
V
IOUT
IOUT
IOUT
IPG
Output current range
1
A
Output current range
0.7
A
Output current range
0.6
A
Power Good input current capability
Operating junction temperature
Effective Input Capacitance
Effective Inductance
1
mA
°C
µF
µH
µF
µH
µF
TJ
-40
2
125
CIN
L
4.7
0.33
2
0.47
0.82
26
TPS628610
TPS62860x
COUT
L
Effective Output Capacitance
Effective Inductance
0.7
3
1.0
1.2
26
COUT
Effective Output Capacitance
7.4 Thermal Information
TPS6286x
THERMAL METRIC(1)
YCH (DSBGA)
8 PINs
121.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
1.1
33.7
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UNIT
SLUSDU8B – APRIL 2020 – REVISED SEPTEMBER 2020
TPS6286x
YCH (DSBGA)
8 PINs
THERMAL METRIC(1)
ψJT
ψJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.7
°C/W
°C/W
33.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
7.5 Electrical Characteristics
TJ = –40°C to +125°C, VIN = 3.6 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, IOUT = 0μA, VOUT = 1.2 V
device not switching, TJ = -40°C to +85°C
IQ(VIN)
VIN quiescent current
2.3
2.5
4
µA
µA
nA
EN = VIN, IOUT = 0μA, VOUT = 1.2 V,
device switching
EN = GND, shutdown current into VIN
VSEL/MODE = GND, TJ = -40°C to +85°C
ISD(VIN)
VIN shutdown supply current
120
250
UVLO
VUVLO(R)
VUVLO(F)
VUVLO(H)
LOGIC PINs
VIH
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
VIN rising
VIN falling
1.65
1.56
100
1.8
1.7
V
V
mV
High-level input voltage threshold
Low-level input voltage threshold
0.8
V
V
VIL
0.4
25
ILKG
Input leakage current into SDA, SCL, VSEL Pin connected to VIN, -40°C to 85°C
10
0.5
10
nA
MΩ
nA
EN internal pull-down resistance
Input Leakage into EN
EN pin to GND
ILKG
Pin connected to VIN, -40°C to 85°C
25
VOUT VOLTAGE
VOUT
Output Voltage Accuracy
Output Voltage Accuracy
PWM Mode, no load, TJ = 25°C to 85°C
PWM Mode, no load, TJ = -40°C to 125°C
-1
-2
+1
%
%
VOUT
+1.7
EN = VIN, VOUT = 1.2 V (internal 12MΩ
resistor divider),
TJ = -40°C to +85°C
IVOS(LKG)
VOS input leakage current
100
4
400
nA
SWITCHING FREQUENCY
fSW(FCCM)
Switching frequency, FCCM operation
VIN = 3.6V, VOUT =1.2V, PWM operation
from VOUT = 0V to 0.95% of VOUT nominal
MHz
STARTUP
Internal fixed soft-start time
0.125
500
0.2
ms
µs
EN HIGH to start of switching delay
1000
POWER STAGE
RDSON(HS)
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
IOUT = 500 mA
IOUT = 500 mA
120
80
170
115
mΩ
mΩ
RDSON(LS)
OVERCURRENT PROTECTION
IHS(OC)
High-side peak current limit
TPS628610
1.3
1.2
1.45
1.35
1.1
1.55
1.45
1.2
A
A
A
A
A
ILS(OC)
Low-side valley current limit
High-side peak current limit
Low-side valley current limit
Low-side negative current limit
TPS628610
IHS(OC)
TPS62860x
0.95
0.85
ILS(OC)
TPS62860x
1.0
1.1
ILS(NOC)
POWER GOOD
VPGTH
Sinking current limit on LS FET
Power Good threshold
PGOOD low, VOS falling
PGOOD high, VOS rising
PG rising edge
93%
96%
16
VPGTH
Power Good threshold
tPG:DLY
Power good deglitch delay
Input leakage current into PG-pin
PG-pin output low-level voltage
µs
nA
mV
IPG;LKG
VPG = 5.0V
10
100
400
IPG = 1mA
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TJ = –40°C to +125°C, VIN = 3.6 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DISCHARGE
EN = GND, IVOS = –10 mA into VOS pin
TJ = -40°C to +85°C
Output discharge resistor on VOS pin
7
11
Ω
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising, PWM Mode
160
20
°C
°C
TJ(HYS)
(1) Specified by design. Not production tested.
7.6 I2C Interface Timing Characteristics
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
100
400
1
UNIT
kHz
kHz
MHz
µs
Standard mode
fSCL
SCL Clock Frequency
Fast mode
Fast mode plus
Standard mode
Fast mode
4.7
1.3
0.5
4
Bus Free Time Between a STOP and
START Condition
tBUF
µs
Fast mode plus
Standard mode
Fast mode
µs
µs
tHD, tSTA Hold Time (Repeated) START condition
600
260
4.7
1.3
0.5
4
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
tLOW
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
µs
Fast mode plus
Standard mode
Fast mode
µs
µs
tHIGH
600
260
4.7
600
260
250
100
50
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
Setup Time for a Repeated START
Condition
tSU, tSTA
ns
Fast mode plus
Standard mode
Fast mode
ns
ns
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
ns
Fast mode plus
Standard mode
Fast mode
ns
0
3.45
0.9
µs
0
µs
Fast mode plus
Standard mode
0
µs
1000
300
ns
20+0.1C
B
tRCL
tRCL1
tFCL
Rise Time of SCL Signal
Fast mode
ns
ns
ns
Fast mode plus
Standard mode
120
20+0.1C
B
1000
Rise Time of SCL Signal After a
Repeated START Condition and After an
Acknowledge BIT
20+0.1C
B
Fast mode
300
120
300
ns
ns
ns
Fast mode plus
Standard mode
20+0.1C
B
Fall Time of SCL Signal
Fast mode
300
120
ns
ns
Fast mode plus
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PARAMETER(1)
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
UNIT
1000
300
ns
20+0.1C
B
tRDA
Rise Time of SDA Signal
Fall Time of SDA Signal
Fast mode
ns
Fast mode plus
Standard mode
120
300
ns
ns
20+0.1C
B
tFDA
Fast mode
300
120
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
ns
ns
pF
pF
pF
4
600
260
tSU, tSTO Setup Time of STOP Condition
Fast mode plus
Standard mode
Fast mode
400
400
550
CB
Capacitive Load for SDA and SCL
Fast mode plus
(1) All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.
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7.7 Typical Characteristics
400
5
4.5
4
TJ = -40°C
375
TJ = 0°C
350
TJ = +25°C
TJ = +85°C
325
300
275
250
225
200
175
150
125
100
75
TJ = +125°C
3.5
3
2.5
2
1.5
1
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
50
0.5
0
25
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage [V]
Input Voltage [V]
EN = GND
EN = VIN
Device not switching
Figure 7-1. Shutdown Current ISD
Figure 7-2. Quiescent Current IQ
350
200
TJ = -40°C
TJ = -10°C
TJ = 30°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
325
300
275
250
225
200
175
150
125
100
75
TJ = -10°C
TJ = 30°C
TJ = 85°C
TJ = 125°C
175
150
125
100
75
50
50
25
25
0
0
1.5
2
2.5
3
3.5
VIN [V]
4
4.5
5
5.5
1.5
2
2.5
3
3.5
VIN [V]
4
4.5
5
5.5
Figure 7-3. High-side Switch Drain Source
Resistance RDS(ON)
Figure 7-4. Low-side Switch Drain Source
Resistance RDS(ON)
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8 Detailed Description
8.1 Overview
The TPS6286x is a high-frequency synchronous step-down converter with ultra-low quiescent current
consumption and flexible output voltage by I²C or VSEL interface. Using TI's DCS-Control™ topology, the device
extends the high efficiency operation area down to microamperes of load current during Power Save Mode
Operation. TI's DCS-Control (Direct Control with Seamless Transition into Power Save Mode) is an advanced
regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of
DCS-Control are excellent AC load regulation and transient response, low output ripple voltage, and a seamless
transition between PFM and PWM mode operation. DCS-Control includes an AC loop which senses the output
voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the
switching frequency, which is constant for steady state operating conditions, and provides immediate response
to dynamic load changes. To achieve accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
VI
HS Limit
Device Control
& Logic
Power Control
EN
SW
Power Save Mode
Forced PWM
Gate
Driver
Smart-Enable
Ref-System
UVLO
100% Mode
Start-up Handling
PG-Control
SDA
Thermal Shutdown
User Interface
DVS
/VSEL-1
SCL
/VSEL-2
LS Limit
VO
Direct
Control
VI
VOS
TON timer
VFB
œ
VO
+
VREF
DCS-ControlTM
Device
Control
GND
Figure 8-1. Functional Block Diagram
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8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. In Power Save
Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing
the output capacitor or inductor value.
8.3.2 Forced PWM Operation
Through I2C, set the device in forced PWM (FPWM) mode by the CONTROL register. The device switches
continuously, even with a light load. This reduces the output voltage ripple and allows simple filtering of the
switching frequency for noise-sensitive applications. Efficiency at light load is lower in FPWM mode.
8.3.3 Smart Enable and Shutdown (EN)
An internal 500-kΩ resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an
uncontrolled start-up of the device in case the EN pin cannot be driven to low level safely. With EN low, the
device is in shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit
disconnects the pulldown resistor on the EN pin once the internal control logic and the reference have been
powered up. With EN set to a low level, the device enters shutdown mode and the pulldown resistor is activated
again.
8.3.4 Soft Start
Once the device has been enabled with EN high, it initializes and powers up its internal circuits. This occurs
during the regulator start-up delay time, tDelay. Once tDelay expires, the internal soft-start circuitry ramps up the
output voltage within the soft-start time, tRamp. See Figure 8-2.
VIN
EN
VOUT
ttDelay
t
ttRamp
ttStartupt
t
Figure 8-2. Start-up Sequence
8.3.5 Output Voltage Selection (VSEL) for TPS62860x
The optional VSEL Interface allows setting the output voltage by a 2-pin HIGH/LOW setting. Using and applying
a digital pattern to the "VSEL-1" and "VSEL-2" pins sets the output voltage according to Table 8-1.
Table 8-1. Output Voltage Setting by VSEL Interface
VSEL-2
VSEL-1
TARGET OUTPUT VOLTAGE
OPERATION MODE
PFM Mode
0
0
1
1
0
1
0
1
0.6 V
0.7 V
0.8 V
1.0 V
PFM Mode
PFM Mode
PFM Mode
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8.3.6 Output Voltage Selection (VSEL and I2C) for TPS628610
The TPS628610 has two options to select the output voltage.
It can be changed by the VSEL pin. Putting this pin "HIGH" selects the output voltage according to VOUT register
2. Putting this pin "LOW" selects the voltage according to VOUT Register 1. The pin can be toggled during
operation.
It can also be selected by the value in the VOUT register that is chosen by VSEL at the moment. The voltage
changes right after the I2C command is received.
8.3.7 Forced PWM Mode During Output Voltage Change
In normal operation, the device does not force PWM operation during VOUT change after VSEL toggle or I2C
command. For ramping down, this mode provides the remaining energy, stored in the output capacitor to the
load of the DC/DC and save battery charge. See Figure 9-14.
Through I2C, the device can be set to forced PWM (FPWM) switching during output voltage change. This allows
a controlled ramp of VOUT up and especially down, regardless of the load condition. See Figure 9-15.
This feature follows the internal I2C ramp and is only recommended for the setting 1 mV/µs and 0.1 mV/µs.
During the faster slopes (10 mV/µs and 5 mV/µs), the mode is likely to be left before the voltage reached the
new target value.
8.3.8 Undervoltage Lockout (UVLO)
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) comparator monitors
the supply voltage. The UVLO comparator shuts down the device at an input voltage of 1.7 V (max) with falling
VIN. The device starts at an input voltage of 1.8 V (max) rising VIN. Once the device re-enters operation out of
an undervoltage lockout condition, it behaves like being enabled.
8.3.9 Power Good (PG)
The TPS6286x has a built-in Power-Good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails or to indicate
any overload behavior on the output. The PG pin is an open-drain output that requires a pullup resistor to any
voltage up to the recommended input voltage level. PG is low when the device is turned off due to EN or thermal
shutdown. VIN must remain present for the PG pin to stay LOW. When applying VIN the first time, PG stays
HIGH until the first enabling of the device.
If the power-good output is not used, it is recommended to tie to GND or leave open.
Table 8-2. Power Good Indicator Functional Table
LOGIC SIGNALS
PG STATUS
THERMAL
SHUTDOWN
DVS TRANSITION
ACTIVE
VI
EN-PIN
VO
NO
High Impedance
LOW
VO on target
NO
YES
HIGH
VI > UVLO
VI < UVLO
VO < target
x
x
x
x
LOW
YES
x
x
x
LOW
LOW
x
x
x
LOW
Undefined
The PG indicator triggers immediately (after internal comparator delay) when Vo crosses the lower VPGTH to
indicate that the voltage has left the target setting. It features a delay after crossing the upper VPGTH when going
high to make sure Vo has reached the target again. Figure 8-3 sketches the behavior.
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VO
VPGTH
VPGTH
PG-delay
PG
Figure 8-3. Power Good Transient and De-glitch Behavior
The PG Indicator is by default pulled low during DVS transition of the output voltage without any blanking or
delay time. Figure 8-3 shows an example of this behavior. After Vo has reached the new target, the PG is again
active as shown in Figure 8-3.
8.3.10 Switch Current Limit / Short Circuit Protection
The TPS6286x integrates a current limit on the high-side and low-side MOSFETs to protect the device against
overload or short circuit conditions. The current in the switches is monitored cycle by cycle. If the high-side
MOSFET current limit, ILIMF, trips, the high-side MOSFET is turned off and the low-side MOSFET is turned on
to ramp down the inductor current. Once the inductor current through the low-side switch decreases below the
low-side MOSFET current limit, ILIMF, the low-side MOSFET is turned off and the high-side MOSFET turns on
again.
8.3.11 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds the
thermal shutdown temperature TSD of 160°C (typ), the device enters thermal shutdown. Both the high-side and
low-side power FETs are turned off. When TJ decreases below the hysteresis amount of typically 20°C, the
converter resumes operation, beginning with a soft start to the originally set VOUT. The thermal shutdown is not
active in Power Save Mode.
8.3.12 Output Voltage Discharge
The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the
device is disabled and to keep the output voltage close to 0 V. The output discharge feature is only active once
the device has been enabled at least once since the supply voltage was applied. The output discharge function
is not active if the device is disabled and the supply voltage is applied the first time. The internal discharge
resistor is connected to the VOS pin. The discharge function is enabled as soon as the device is disabled. The
minimum supply voltage required to keep the discharge function active is VI > VTH_UVLO-
.
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8.4 Programming
8.4.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version .6, 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect
to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital
signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives, transmits data, or both on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The interface
adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending
on the instantaneous application requirements. Register contents remain intact as long as the input voltage
remains above 1.8 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different and must not be used.
It is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pullup voltages to ensure reset of the I2C engine.
8.4.2 Standard- and Fast-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 8-4. All I2C-compatible devices
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 8-4. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-5). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8-6) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 8-5. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
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acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 8-4). This releases the bus and stops the communication link with the
addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 8-6. Acknowledge on the I2C Bus
Figure 8-7. Bus Protocol
8.4.3 I2C Update Sequence
The requires the following:
•
•
•
•
A start condition
A valid I2C address
A register address byte
A data byte for a single update
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After the receipt of each byte, the device acknowledges by pulling the SDA line low during the high period of a
single clock pulse. A valid I2C address selects the device. The device performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
8
1
7
1
1
8
1
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
—0“ Write
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
Figure 8-8. “Write” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8
1
7
1
1
8
1
1
7
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
—0“ Write
—1“ Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
Figure 8-9. “Read” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8.4.4 I2C Register Reset
The I2C registers can be reset by the following:
•
•
Pull the input voltage below 1.8 V (typ).
A high to low transition on EN. The previous value of the "Enable Output Discharge" bit is latched until the
next EN rising edge or pulling the input voltage below 1.0 V (typ).
•
Set the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new start-up begins immediately. After tDelay, the I2C registers can be programmed again.
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8.5 Register Map
Table 8-3. Register Map
REGISTER ADDRESS
(HEX)
FACTORY DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x01
0x02
0x03
0x05
VOUT Register 1
VOUT Register 2
0x10
0x38
Sets the target output voltage
Sets the target output voltage
CONTROL Register
STATUS Register
Sets miscellaneous configuration bits
Returns status flags, cleared on read-out
0x00
8.5.1 Slave Address Byte
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
R/W
The slave address byte is the first byte received following the START condition from the master device. The 7-bit
slave address is 0x40 and internally set.
8.5.2 Register Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the device,
which contains the address of the register to be accessed.
8.5.3 VOUT Register 1
Table 8-4. VOUT Register 1 Description
REGISTER ADDRESS 0X01 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)Section 8.5.3
0.400 V
6:0
VO1_SET
0x00
0x01
...
0.4125 V
0x10
...
0.600 V (default value)
0x7E
0x7F
1.975 V
1.9875 V
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8.5.4 VOUT Register 2
Table 8-5. VOUT Register 2 Description
REGISTER ADDRESS 0X02 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)Section 8.5.4
7
Operation Mode
0x00
0 - Keep PFM/PWM selection as in
CONTROL-Register
1 - sets the device in PWM operation for this
Voltage selection
6:0
VO2_SET
0x00
0x01
...
0.400 V
0.4125 V
0x38
...
1.10 V (default value)
0x7E
0x7F
1.975 V
1.9875 V
8.5.5 CONTROL Register
Table 8-6. CONTROL Register Description
REGISTER ADDRESS 0X03 READ/WRITE
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7
Reset
W
0
1 - Reset all registers to default.
This bit triggers a shutdown followed by a re-reading of the
internal OTP settings and a new soft start.
6
5
Enable FPWM Mode during Output
Voltage Change
R/W
R/W
1
1
0 - Keep the current mode status during output voltage change.
1 - Force the device in FPWM during output voltage change.
Software Enable Device
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new start-up without the tDelay
period.
4
3
Enable FPWM Mode
R/W
R/W
0
1
0 - Set the device in power save mode at light loads.
1 - Set the device in forced PWM mode at light loads.
Enable Output Discharge
0 - Disable output discharge.
1 - Enable output discharge.
This setting is used for the next disable cycle (Software or
Hardware).
2
Reserved
0:1
Voltage Ramp Speed
R/W
11
00 - 10mV/µs
01 - 5 mV/µs
10 - 1 mV/µs
11 - 0.1 mV/µs
8.5.6 STATUS Register
Table 8-7. STATUS Register Description
REGISTER ADDRESS 0X05 READ ONLY(1)
BIT
7:5
4
FIELD
TYPE
DEFAULT DESCRIPTION
Reserved
Thermal Shutdown Tripped
R
0
0
1: Thermal Shutdown has tripped since the last reading.
0: No Thermal Shutdown event occurred during the last reading.
3
2
Reserved
Power Bad
R
1: Output voltage is or was below 0.95xVO
0: No Power Bad event occurred since last reading
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Table 8-7. STATUS Register Description (continued)
REGISTER ADDRESS 0X05 READ ONLY(1)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
1:0
Reserved
(1) All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application, TPS628610
TPS628610
VIN
1.8V t 5.5V
VOUT
0.47µH
0.4V t 1.9V
VIN
SW
10 …F
4.7 …F
GND
VOS
EN
SDA
SCL
VSEL
Figure 9-1. TPS628610, Typical Application
9.2.1 Design Requirements
Table 9-1 shows the list of components for the application circuit and the characteristic application curves.
Table 9-1. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
VALUE
SIZE [L x W X T]
MANUFACTURER(1)
TPS628610
Step down converter, 1 A
1.4 mm x 0.70 mm x 0.4 mm max.
Texas Instruments
Ceramic capacitor,
GRM155R60J475ME47D
CIN
4.7 µF
0402 (1 mm x 0.5 mm x 0.6 mm max.)
Murata
Ceramic capacitor,
GRM155R60J106ME15D
COUT
L
10 µF
0402 (1 mm x 0.5 mm x 0.65 mm max.)
0603 (1.6 mm x 0.8 mm x 1.0 mm max.)
Murata
Murata
Inductor DFE18SANR47MG0L
0.47 µH
(1) See Third-party Products Disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be
estimated according to Equation 1.
Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current, as calculated with Equation 2. This is
recommended because during a heavy load transient the inductor current rises above the calculated value. A
more conservative way is to select the inductor saturation current according to the high side MOSFET switch
current limit, ILIMF
.
Vout
Vin
1-
DIL = Vout ´
L ´ ¦
(1)
(2)
DI
L
I
= I
+
Lmax
outmax
2
where
•
•
•
•
f = Switching frequency
L = Inductor value
ΔIL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
Table 9-2 shows a list of possible inductors.
Table 9-2. List of Possible Inductors
SIZE IMPERIAL
(METRIC)
INDUCTANCE [µH]
INDUCTOR SERIES
DIMENSIONS L x W X T
SUPPLIER(1)
0.47
0.47
0.47
0.47
DFE18SAN_G0
HTEB16080F
0603 (1608)
0603 (1608)
0402 (1005)
0603 (1608)
1.6mm x 0.8mm x 1.0mm max
1.6mm x 0.8mm x 0.6mm max.
1.0mm x 0.5mm x 0.65mm max.
1.6mm x 0.8mm x 0.8mm max.
Murata
Cyntec
Cyntec
TDK
HTET1005FE
TFM160808ALC
(1) See Third-party Products Disclaimer
9.2.2.2 Output Capacitor Selection
The DCS-Control™ scheme of the TPS6286x allows the use of tiny ceramic capacitors. Ceramic capacitors with
low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires
either an X7R or X5R dielectric. At light load currents, the converter operates in Power Save Mode and the
output voltage ripple is dependent on the output capacitor value. A larger output capacitors can be used
reducing the output voltage ripple.
The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 9-3 outlines
possible inductor and capacitor value combinations.
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Table 9-3. Recommended LC Output Filter Combinations
NOMINAL OUTPUT CAPACITOR VALUE [µF]
NOMINAL INDUCTOR VALUE
[µH]
DEVICE
4.7 µF
10 µF
2 x 10 µF
22 µF
0.47(1)
1.0(2)
√
√
√
√
√
√
√
(3)
TPS628610
TPS62860x
(3)
√
(1) An effective inductance range of 0.33 µH to 0.82 µH is recommended. An effective capacitance range of 2 µF to 26 µF is
recommended.
(2) An effective inductance range of 0.7 µH to 1.2 µH is recommended. An effective capacitance range of 3 µF to 26 µF is recommended.
(3) Typical application configuration. Other check marks indicate alternative filter combinations.
9.2.2.3 Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR ceramic input capacitor is required for best
input voltage filtering to minimize input voltage spikes. For most applications, a 4.7-µF input capacitor is
sufficient. When operating from a high impedance source, like a coin cell, a larger input buffer capacitor ≥10 µF
is recommended to avoid voltage drops during start-up and load transients. The input capacitor can be
increased without any limit for better input voltage filtering. The leakage current of the input capacitor adds to the
overall current consumption.
Table 9-4 shows a selection of input and output capacitors.
Table 9-4. List of Possible Capacitors Section 9.2.2.3
SIZE IMPERIAL
(METRIC)
SUPPLIER(1)
CAPACITANCE [μF]
CAPACITOR PART NUMBER
DIMENSIONS L x W X T
4.7
4.7
10
GRM155R60J475ME47D
GRM035R60J475ME15
GRM155R60J106ME15D
0402 (1005)
0201 (0603)
0402 (1005)
1.0mm x 0.5mm x 0.6mm max.
0.6mm x 0.3mm x 0.55mm max
1.0mm x 0.5mm x 0.65mm max.
Murata
Murata
Murata
(1) See Third-party Products Disclaimer
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9.2.3 Application Curves
VIN = 3.8 V, VOUT = 1.1 V, TA = 25°C, BOM = Table 9-1, unless otherwise noted
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Load Current [A]
VOUT = 1.1 V
Auto Power Save Mode
VOUT = 0.6 V
Auto Power Save Mode
Figure 9-2. Efficiency
Figure 9-3. Efficiency
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Load Current [A]
VOUT = 1.9875 V
Auto Power Save Mode
VOUT = 0.4 V
Auto Power Save Mode
Figure 9-4. Efficiency
Figure 9-5. Efficiency
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
0
0
1m
10m
100m
1
1m
10m
100m
1
Load Current [A]
Load Current [A]
VOUT = 1.1 V
Forced PWM Operation
VOUT = 0.6 V
Forced PWM operation
Figure 9-6. Efficiency, Inductor Comparison
Figure 9-7. Efficiency
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4
3
2
1
1M
100k
10k
1k
VIN = 1.8V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
100
1m
10m
100m
1m
10m
100m
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Load Current [A]
Load Current [A]
VOUT = 1.1 V
VOUT = 1.1 V
Auto Power Save Mode
Figure 9-9. Switching Frequency
Figure 9-8. Switching Frequency
IOUT = 500 mA
VSEL = HIGH
VSEL = HIGH
Figure 9-11. PWM-Mode Operation
Figure 9-10. PFM Mode Operation
5mV/µs
5mV/µs
10mV/µs
10mV/µs
1mV/µs
1mV/µs
0.1mV/µs
Default voltage setting
Default voltage setting
Figure 9-13. DVS by VSEL, Different Ramp Speed
Settings
Figure 9-12. DVS by VSEL, Different Ramp Speed
Settings
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IL
IL
Power Save Mode is active
Power Save Mode is active
Figure 9-15. FPWM-Mode During VOUT Change
Enabled
Figure 9-14. Standard Operation: VOUT Change
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9.2.4 Typical Application, TPS628600, TPS62860x
TPS628600
VIN
1.8V t 5.5V
VOUT
0.4V t 1.9V
1µH
VIN
SW
10 …F
4.7 …F
GND
VOS
EN
SDA
SCL
VSEL
Figure 9-16. TPS628600, Typical Application
TPS628601
1.0µH
VIN
1.8V t 5.5V
VOUT
VIN
SW
10 …F
4.7 …F
GND
VOS
EN
PG
VSEL-1
VSEL-2
Figure 9-17. TPS62860x, Typical Application
9.2.4.1 Design Requirements
Table 9-5 shows the list of components for the application circuit and the characteristic application curves.
Table 9-5. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
VALUE
SIZE [L x W X T]
MANUFACTURER(1)
TPS628610
Step down converter, 1 A
1.4 mm x 0.70 mm x 0.4 mm max.
Texas Instruments
Ceramic capacitor,
GRM155R60J475ME47D
CIN
4.7 µF
0402 (1 mm x 0.5 mm x 0.6 mm max.)
Murata
Ceramic capacitor,
GRM155R60J106ME15D
COUT
L
10 µF
1 µH
0402 (1 mm x 0.5 mm x 0.65 mm max.)
0805 (2.0 mm x 1.6 mm x 1.0 mm max.)
Murata
Murata
Inductor DFE201610E
9.2.4.2 Detailed Design Procedure
See Section 9.2.2.
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9.2.4.3 Application Curves
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Load Current [A]
VOUT = 1.1 V
Auto Power Save Mode
VOUT = 0.7 V
Auto Power Save Mode
Figure 9-18. Efficiency
Figure 9-19. Efficiency
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10 Power Supply Recommendations
The power supply must provide a current rating according to the supply voltage, output voltage, and output
current of the TPS6286x.
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11 Layout
11.1 Layout Guidelines
The pinout of TPS6286x has been optimized to enable a single top layer PCB routing of the IC and its critical
passive components such as CIN, COUT, and L. Furthermore, this pin out allows you to connect tiny
components such as 0201 (0603) size capacitors and 0402 (1005) size inductor. A solution size smaller than 5
mm2 can be achieved with a fixed output voltage.
•
•
•
•
As for all switching power supplies, the layout is an important step in the design. Care must be taken in board
layout to get the specified performance.
It is critical to provide a low inductance, low impedance ground path. Therefore, use wide and short traces for
the main current paths.
The input capacitor must be placed as close as possible to the VIN and GND pins of the IC. This is the most
critical component placement.
The VOS line is a sensitive, high impedance line and must be connected to the output capacitor and routed
away from noisy components and traces (for example, SW line) or other noise sources.
11.2 Layout Example
VOUT
GND
VIN
Figure 11-1. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
DCS-Control™ and TI E2E™ are trademarks of Texas Instruments.
I2C™ is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS628600YCHR
TPS628601YCHR
TPS628610YCHR
ACTIVE
DSBGA
DSBGA
DSBGA
YCH
8
8
8
12000 Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
S
T
U
ACTIVE
ACTIVE
YCH
12000 Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
YCH
12000 Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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5-Oct-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS628600YCHR
TPS628601YCHR
TPS628610YCHR
DSBGA
DSBGA
DSBGA
YCH
YCH
YCH
8
8
8
12000
12000
12000
180.0
180.0
180.0
8.4
8.4
8.4
0.8
0.8
0.8
1.5
1.5
1.5
0.47
0.47
0.47
2.0
2.0
2.0
8.0
8.0
8.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS628600YCHR
TPS628601YCHR
TPS628610YCHR
DSBGA
DSBGA
DSBGA
YCH
YCH
YCH
8
8
8
12000
12000
12000
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YCH0008
DSBGA - 0.4 mm max height
SCALE 13.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.05 C
0.16
0.10
0.35
TYP
D
C
SYMM
1.05
TYP
D: Max = 1.391 mm, Min =1.331 mm
E: Max = 0.691 mm, Min =0.631 mm
B
A
0.35
TYP
0.225
0.185
8X
1
2
SYMM
0.015
C A B
4225328/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCH0008
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
8X ( 0.2)
2
1
A
(0.35) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MIN
0.0375 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4225328/A 09/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YCH0008
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
8X ( 0.21)
1
2
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4225328/A 09/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2020, Texas Instruments Incorporated
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