TPS62867RQYR [TI]

采用 1.5mm x 2.5mm QFN 封装的 2.4V 至 5.5V 输入、6A 同步降压转换器 | RQY | 9 | -40 to 125;


型号：	TPS62867RQYR
厂家：	TEXAS INSTRUMENTS
描述：	采用 1.5mm x 2.5mm QFN 封装的 2.4V 至 5.5V 输入、6A 同步降压转换器 \| RQY \| 9 \| -40 to 125 转换器
文件：	总29页 (文件大小：2069K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

TPS62865/TPS62867 采用1.5mm × 2.5mm QFN 封装的2.4V 至5.5V 输入电压、4A

和6A 同步降压转换器

1 特性

3 说明

• 可实现快速瞬态响应的DCS-Control 拓扑

• 11mΩ和10.5mΩ内部功率MOSFET

• 1% 的输出电压精度

TPS62865 和 TPS62867 器件是高频同步降压转换

器，可提供高效、灵活和高功率密度解决方案。这些转

换器在中高负载条件下以PWM 模式运行，并在轻负载

时自动进入省电模式运行，从而在整个负载电流范围内

保持高效率。这些器件还可强制进入PWM 模式运行，

尽量减少输出电压纹波。凭借其 DCS-Control 架构，

这些器件可实现出色的负载瞬态性能并符合严格的输出

电压精度要求。此类器件可提供电源正常信号和内部软

启动电路。这些器件能够以 100% 模式运行。在故障

保护方面，这些器件加入了断续短路保护以及热关断功

能。

• 4µA 工作静态电流

• 2.4V 至5.5V 输入电压范围

• 0.6V 至VIN 输出电压范围

• Voltage Selection Table 固定（可通过外部电阻器

进行选择）和可调节输出电压版本

• 2.4MHz 开关频率

• 强制PWM 或省电模式

• 输出电压放电

• 100% 占空比模式

• 断续短路保护

• 具有窗口比较器的电源正常指示器

• 热关断

• 解决方案尺寸可降至30mm2

• 采用具有0.5mm 间距的1.5mm × 2.5mm QFN 封

装

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS62865

TPS62867

QFN (9)

1.5 × 2.5 × 1mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 使用TPS62865 并借助WEBENCH^®Power

Designer 创建定制设计方案

• 使用TPS62867 并借助WEBENCH^®Power

Designer 创建定制设计方案

2 应用

• 为FPGA、CPU、ASIC 或视频芯片组提供内核电

源

• 机器视觉摄像机

• IP 网络摄像头

• 固态硬盘

• 光学模块

• 多功能打印机

0.22 µH

V_IN

V_OUT

0.9 V

V_OUT

1.8 V

0.22 µH

2.4 V to 5.5 V

VIN

C3, C4

2×22 µF

C3, C4

2×22 µF

VOS

C1, C2

2×10 µF

C1, C2

2×10 µF

VSET/MODE

133 k

PGND

AGND

PGND

AGND

典型应用原理图- 可调输出电压

典型应用原理图- 固定输出电压

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDN8

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................10

9 Application and Implementation..................................12

9.1 Application Information............................................. 12

9.2 Typical Application.................................................... 12

10 Power Supply Recommendations..............................19

11 Layout...........................................................................20

11.1 Layout Guidelines................................................... 20

11.2 Layout Example...................................................... 20

12 Device and Documentation Support..........................22

12.1 Device Support....................................................... 22

12.2 Documentation Support.......................................... 22

12.3 支持资源..................................................................22

12.4 Trademarks.............................................................22

12.5 静电放电警告.......................................................... 22

12.6 术语表..................................................................... 22

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Options................................................................ 3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................4

7.4 Thermal Information ...................................................5

7.5 Electrical Characteristics ............................................6

7.6 Typical Characteristics................................................7

8 Detailed Description........................................................8

8.1 Overview.....................................................................8

8.2 Functional Block Diagram...........................................8

8.3 Feature Description.....................................................8

Information.................................................................... 23

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

March 2021

Initial Release

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

5 Device Options

PART NUMBER⁽¹⁾

OUTPUT CURRENT

TPS62865

TPS62867

4 A

6 A

(1) For all available packages, see the orderable addendum at the end of the data sheet.

6 Pin Configuration and Functions

PGND

VIN

Not to scale

图6-1. 9-Pin RQY QFN Package (Top View)

表6-1. Pin Functions

DESCRIPTION

NAME

AGND

NO.

Analog ground pin

Feedback pin. For the fixed output voltage versions, the pin must be connected to the output directly.

Output voltage sense pin. This pin must be directly connected to the output capacitor.

Power ground pin

VOS

PGND

Switch pin of the power stage

VIN

Power supply input voltage pin

Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables

the device. Do not leave floating.

Voltage Set pin

In fixed output voltage applications, connect a resistor between this pin and GND to set the output

voltage (see 表8-2). After start-up, connect this pin to a high level to enable forced-PWM operation, or

to a low level to enable power-save mode.

VSET/MODE

In adjustable output voltage applications, connect this pin to a high level to enable forced-PWM

operation, or to a low level to enable power-save mode operation.

Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5 V. If

unused, leave it floating.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾

MIN

–0.3

–2.5

MAX

UNIT

VIN, EN, VOS, FB, PG, VSET/MODE

SW (DC)

V_IN+ 0.3

Voltage⁽²⁾

SW (AC, less than 10 ns)⁽³⁾

Sink current at PG

I_{SINK_PG}

T_J

°C

Junction temperature

Storage temperature

150

–40

–65

T_stg

150

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to network ground terminal.

(3) While switching

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

MIN

2.4

NOM

MAX

5.5

UNIT

V_IN

Supply Voltage Range

Output Voltage Range

Slew rate at VIN⁽¹⁾

V_OUT

0.6

V_IN

mV/µs

–10

Output current, TPS62865

Output current, TPS62867

Junction temperature

I_OUT

T_J

125

°C

–40

(1) The falling slew rate of V_INmust be limited if V_INgoes below V_UVLO

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

7.4 Thermal Information

TPS6286x

TPS62867EVM-121

THERMAL METRIC⁽¹⁾

JEDEC 51-7

9 PINS

90.9

UNIT

9 PINS

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

60.3

°C/W

68.2

n/a⁽²⁾

3.3

25.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.9

24.7

31.5

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Not applicable to an EVM

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

7.5 Electrical Characteristics

T_J= –40°C to 125°C, and V_IN= 2.4 V to 5.5 V. Typical values are at T_J= 25°C and V_IN= 5 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY

I_Q

Quiescent current

EN = High, no load, device not switching

µA

EN = High, no load, device not switching,

V_VOS= 1.8 V

I_{Q_VOS}

I_SD

V_UVLO

Operating quiescent current into VOS pin

Shutdown current

0.24

2.3

2.2

150

2.4

2.3

µA

EN = Low, T_J= –40℃to 85℃

V_INrising

V_INfalling

T_Jrising

T_Jfalling

2.2

2.1

Undervoltage lockout threshold

Thermal shutdown threshold

Thermal shutdown hysteresis

°C

T_JSD

LOGIC INTERFACE

High-level input threshold voltage at EN

and VSET/MODE

V_IH

0.84

Low-level input threshold voltage at

EN and VSET/MODE

V_IL

0.4

0.1

I_EN,LKG

Input leakage current into EN pin

0.01

µA

STARTUP, POWER GOOD

Time from EN high to device starts switching

249-kΩ resistor connected between VSET/MODE

and GND

t_Delay

Enable delay time

420

700 1100

µs

t_Ramp

V_PG

Output voltage ramp time

Power good lower threshold

Power good upper threshold

Low-level output voltage

Power good deglitch delay

Time from device starts switching to power good

V_VOSreferenced to V_OUTnominal

I_sink= 1 mA, PG pin version

0.8

1.5

85%

91%

96%

103% 111% 120%

V_PG,OL

0.36

t_PG,DLY

Rising and falling edges

µs

OUTPUT

Fixed voltage operation, FPWM, no load, T_J=

0°C to 85°C

–1%

V_OUT

Output voltage accuracy

Fixed voltage operation, FPWM, no load

Adjustable voltage operation

606

0.4

2.5

–2%

V_FB

Feedback voltage

594

600

0.01

0.2

µA

I_FB,LKG

Input leakage into FB pin

Adjustable voltage operation, V_FB= 0.6 V

Output discharge disabled, V_VOS= 1.8 V

I_VOS,LKGInput leakage current into VOS pin

R_DIS

Output discharge resistor at VOS pin

Load regulation

3.5

Ω

V_OUT= 0.9 V, FPWM

0.04

%/A

POWER SWITCH

High-side FET on-resistance

10.5

5.5

mΩ

R_DS(on)

Low-side FET on-resistance

TPS62865

High-side FET forward current limit

TPS62867

7.7

8.5

TPS62865

4.5

I_LIM

Low-side FET forward current limit

TPS62867

6.5

Low-side FET negative current limit

PWM switching frequency

TPS62865, TPS62867

I_OUT= 1 A, V_OUT= 0.9 V

–3

2.4

f_SW

MHz

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

7.6 Typical Characteristics

27.5

T_J= –40 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

T_J= –40 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

22.5

17.5

12.5

7.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Supply Voltage (V)

图7-1. High-Side FET On-Resistance

图7-2. Low-Side FET On-Resistance

1.0

0.8

0.6

0.4

0.2

0.0

T_J= –40 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

T_J= 25 °C

T_J= 85 °C

T_J= 125 °C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Supply Voltage (V)

图7-3. Quiescent Current

图7-4. Shutdown Current

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS62865 and TPS62867 synchronous step-down converters use the DCS-Control (Direct Control with

Seamless transition into Power Save Mode) topology. This is an advanced regulation topology that combines the

advantages of hysteretic and current-mode control schemes.

The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions

and in Power Save Mode at light load currents. In PWM mode, the converter operates with its 2.4-MHz nominal

switching frequency, having a controlled frequency variation over the input voltage range. Since DCS-Control

supports both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to

Power Save Mode is seamless and does not affect on the output voltage. The devices offer both excellent DC

voltage and superior load transient regulation combined with very low output voltage ripple.

8.2 Functional Block Diagram

VIN

91%

–

34-µs

Deglitch

V_X

Control Logic

Reference Selection

UVLO

–

AGND

111%

Thermal Shutdown

Startup Ramp

VSET/MODE

HS-FET Forward

Current Limit

V_SW

V_IN

T_ON

HICCUP

Direct Control

V_SW

Compensation

Gate

Driver

Modulator

V_ref

Comparator

V_X

–

LS-FET

VOS

Forward Current Limit

Zero Current Detect

Negative Current Limit

k = 1, 0.5, 0.25

PGND

R_DIS

PGND

AGND

8.3 Feature Description

8.3.1 Power Save Mode

As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the

inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. Power Save

Mode is based on a fixed on-time architecture, as shown in 方程式1.

V_OUT

t_ON

× 416 ns

(1)

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized

by increasing the output capacitor or inductor value.

When V_INdecreases to typically 15% above V_OUT, the TP6286x does enter Power Save Mode, regardless of the

load current. The device maintains output regulation in PWM mode.

8.3.2 Forced PWM Mode

Connecting the VSET/MODE pin to logic high after the start-up, the device switches at 2.4 MHz, even with a light

load. This reduces the output voltage ripple and allows simple filtering of the switching frequency for noise-

sensitive applications. Efficiency at light load is lower in Forced PWM mode (FPWM).

8.3.3 100% Duty Cycle Mode Operation

There is no limitation for small duty cycles since even at very low duty cycles, the switching frequency is reduced

as needed to always ensure a proper regulation.

If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side

switch is constantly turned on, the low-side switch is switched off. The difference between V_INand V_OUTis

determined by the voltage drop across the high-side MOSFET and the DC resistance of the inductor. The

minimum V_INthat is needed to maintain a specific V_OUTvalue is estimated as:

IN,MIN

= V_OUT+ (R_{DS (ON)}+ R_L)I_{OUT ,MAX}

(2)

where

• V_IN,MINis the minimum input voltage to maintain an output voltage

• I_OUT,MAXis the maximum output current

• R_DS(on)is the high-side FET ON-resistance

• R_Lis the inductor ohmic resistance (DCR)

8.3.4 Soft Start

After enabling the device, there is a 700-µs (typical) enable delay (t_delay) before the device starts switching. After

the enable delay, an internal soft start-up circuitry ramps up the output voltage with a period of 1 ms (t_Ramp). This

avoids excessive inrush current and creates a smooth output voltage rise-slope. It also prevents excessive

voltage drops of primary cells and rechargeable batteries with high internal impedance. The device is able to

start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the output voltage to its

nominal value.

V_IN

V_OUT

tt_Delay

tt_Ramp

tt_Startupt

图8-1. Start-up Sequence

8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection

The switch current limit prevents the device from high inductor current and from drawing excessive current from

the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy

load or shorted output circuit condition. If the inductor current reaches the threshold I_LIM, cycle by cycle, the high-

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

side MOSFET is turned off and the low-side MOSFET is turned on, while the inductor current ramps down to the

low-side MOSFET current limit.

When the high-side MOSFET current limit is triggered 32 times, the device stops switching. The device then

automatically re-starts with an internal soft start-up after a typical delay time of 128 µs has passed. This is

named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.

8.3.6 Undervoltage Lockout

To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) is implemented when

the input voltage is lower than V_UVLO. The device stops switching and the output voltage discharge is active

when the device is in UVLO. When the input voltage recovers, the device automatically returns to operation with

an internal soft start-up.

8.3.7 Thermal Shutdown

When the junction temperature exceeds T_JSD, the device goes into thermal shutdown, stops switching, and

activates the output voltage discharge. When the device temperature falls below the threshold by the hysteresis,

the device returns to normal operation automatically with an internal soft start-up. During thermal shutdown, the

internal register values are kept.

8.4 Device Functional Modes

8.4.1 Enable and Disable (EN)

The device is enabled by setting the EN pin to a logic high. In shutdown mode (EN = low), the internal power

switches and the entire control circuitry are turned off. An internal switch smoothly discharges the output through

the VOS pin in shutdown mode. Do not leave the EN pin floating.

8.4.2 Power Good (PG)

The device has an open-drain power-good pin, which is specified to sink up to 1 mA. The power-good output

requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG has a deglitch delay of 34 µs.

The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.

Leave the PG pin unconnected when not used.

表8-1. PG Function Table

DEVICE CONDITIONS

0.9 × V_{OUT_NOM}≤V_VOS≤1.1 × V_{OUT_NOM}

V_VOS< 0.9 × V_{OUT_NOM}or V_VOS> 1.1 × V_{OUT_NOM}

EN = low

PG PIN

Hi-Z

Enable

Low

Shutdown

Low

Thermal shutdown

UVLO

T_J> T_JSD

Low

1.8 V < V_IN< V_UVLO

Low

Power supply removal

V_IN< 1.8 V

Undefined

8.4.3 Voltage Setting and Mode Selection (VSET/MODE)

During the enable delay (t_Delay), the device configuration is set by an external resistor connected to the VSET/

MODE pin through an internal R2D (resistor to digital) converter. 表8-2 shows the options.

The R2D converter has an internal current source that applies current through the external resistor and an

internal ADC that reads back the resulting voltage level. Depending on the level, the output voltage is set. Once

this R2D conversion is finished, the current source is turned off to avoid current flowing through the external

resistor. Ensure that there is no additional current path or capacitance greater than 30 pF from this pin to GND

during R2D conversion. Otherwise, a false value is set.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

表8-2. Voltage Selection Table

RESISTOR (E96 SERIES, ±1% ACCURACY) AT VSET/MODE PIN

FIXED OR ADJUSTABLE OUTPUT VOLTAGE

adjustable

3.30 V

2.50 V

1.80 V

1.50 V

reserved

1.35 V

1.20 V

1.10 V

1.05 V

1.00 V

0.95 V

0.90 V

0.85 V

0.80 V

adjustable

249 kΩor logic high

205 kΩ

162 kΩ

133 kΩ

105 kΩ

86.6 kΩ

68.1 kΩ

56.2 kΩ

44.2 kΩ

36.5 kΩ

28.7 kΩ

23.7 kΩ

18.7 kΩ

15.4 kΩ

12.1 kΩ

10 kΩor logic low

When the device is set as a fixed output voltage converter, then FB pin must be connected to the output directly.

Refer to 图8-2.

0.22 µH

V_IN

V_OUT

1.8 V

2.4 V to 5.5 V

VIN

C3, C4

2×22 µF

VOS

C1, C2

2×10 µF

VSET/MODE

133 k

PGND

AGND

图8-2. Fixed Start-up Output Voltage Application Circuit

After the start-up period (t_Startup), a different operation mode can be selected. When VSET/MODE is high, the

device operates in forced PWM mode, otherwise the device operates in power save mode.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The following section discusses the design of the external components to complete the power supply design for

several input and output voltage options by using typical applications as a reference.

9.2 Typical Application

0.22 µH

V_IN

V_OUT

0.9 V

2.4 V to 5.5 V

VIN

C3, C4

2×22 µF

VOS

C1, C2

2×10 µF

VSET/MODE

PGND

AGND

图9-1. Typical Application

9.2.1 Design Requirements

For this design example, use the parameters listed in 表9-1 as the input parameters.

表9-1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

2.4 V to 5.5 V

0.9 V

Output voltage

Maximum output current

6 A

表9-2 lists the components used for the example.

表9-2. List of Components

REFERENCE

DESCRIPTION

MANUFACTURER⁽¹⁾

C1, C2

C3, C4

Murata

Coilcraft

Std

10 μF, ceramic capacitor, 10 V, X7R, size 0603,GRM188Z71A106KA73

22 µF, ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44

0.22 µH, power inductor, XAL4020-221ME (12 A, 5.81 mΩ)

Depending on the output voltage, chip resistor, 1/16 W, 1%, size 0402

100 kΩ, chip resistor, 1/16 W, 1%, size 0402

Std

100 kΩ, chip resistor, 1/16 W, 1%, size 0402

(1) See the Third-party Products disclaimer.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS62865 device with the WEBENCH® Power Designer.

Click here to create a custom design using the TPS62867 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Setting The Output Voltage

The output voltage is set by an external resistor divider according to 方程式3:

(3)

R2 must not be higher than 200 kΩ to achieve high efficiency at light load while providing acceptable noise

sensitivity.

For the fixed output versions, connect the FB pin to the output. R1 and R2 are not needed.

9.2.2.3 Output Filter Design

The inductor and the output capacitor together provide a low-pass filter. To simplify this process, 表 9-3 outlines

possible inductor and capacitor value combinations for most applications. Checked cells represent combinations

that are proven for stability by simulation and lab testing. Further combinations must be checked for each

individual application.

表9-3. Matrix of Output Capacitor and Inductor Combinations

NOMINAL C_OUT[µF]⁽³⁾

NOMINAL L [µH]⁽²⁾

0.22

2 × 22 or 47

3 × 22

150

(1)

(1) This LC combination is the standard value and recommended for most applications.

(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.

(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.

9.2.2.4 Inductor Selection

The main parameter for the inductor selection is the inductor value, then the saturation current of the inductor. To

calculate the maximum inductor current under static load conditions, 方程式4 is given.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

(4)

where

• I_OUT,MAXis the maximum output current

• ΔI_Lis the inductor current ripple

• f_SWis the switching frequency

• L is the inductor value

It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than

I_L,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate

inductor. 表9-4 lists recommended inductors.

表9-4. List of Recommended Inductors

DC RESISTANCE

INDUCTANCE CURRENT RATING

DIMENSIONS

[L × W × H mm]

PART NUMBER

[µH]⁽¹⁾

[A]

18.7

6.6

[mΩ]

0.22

4 × 4 × 2

5.81

Coilcraft, XAL4020-221ME

Murata, DFE201612E-R24M

0.24

2 × 1.6 × 1.2

(1) See the Third-party Products disclaimer.

9.2.2.5 Capacitor Selection

The input capacitor is the low-impedance energy source for the convertersm which helps to provide stable

operation. A low-ESR multilayer ceramic capacitor is recommended for the best filtering and must be placed

between VIN and GND as close as possible to those pins. For most applications, 8 μF of effective ¹capacitance

is sufficient, however, a larger value reduces input current ripple.

The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series

resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low

resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends

using X7R or X5R dielectrics. The recommended typical output capacitor value is 30 μF of effective

capacitance. This capacitance can vary over a wide range as outlined in the output filter selection table.

The effective capacitance is the capacitance after tolerance, temperature, and DC bias effects have been considered.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9.2.3 Application Curves

V_IN= 5.0 V, V_OUT= 0.9 V, T_A= 25 °C, BOM = 表9-2, unless otherwise noted.

100

0.610

0.605

0.600

0.595

0.590

0.585

0.580

0.575

0.570

+1%

–1%

V_IN= 2.4 V – FPWM

V_IN= 2.4 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 2.5 V – FPWM

V_IN= 2.5 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 0.6 V

图9-2. Efficiency

V_OUT= 0.6 V

图9-3. Load Regulation

100

0.92

0.91

0.90

0.89

0.88

0.87

0.86

0.85

0.84

+1%

–1%

V_IN= 2.4 V – FPWM

V_IN= 2.4 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 2.5 V – FPWM

V_IN= 2.5 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 0.9 V

图9-4. Efficiency

V_OUT= 0.9 V

图9-5. Load Regulation

100

1.22

1.21

1.20

1.19

1.18

1.17

1.16

1.15

1.14

+1%

–1%

V_IN= 2.4 V – FPWM

V_IN= 2.4 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 2.5 V – FPWM

V_IN= 2.5 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 1.2 V

图9-6. Efficiency

V_OUT= 1.2 V

图9-7. Load Regulation

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9.2.3 Application Curves (continued)

100

1.83

1.82

1.81

1.80

1.79

1.78

1.77

1.76

1.75

1.74

1.73

+1%

–1%

V_IN= 2.4 V – FPWM

V_IN= 2.5 V – FPWM

V_IN= 2.4 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 2.5 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 1.8 V

图9-8. Efficiency

V_OUT= 1.8 V

图9-9. Load Regulation

100

2.56

2.54

2.52

2.50

2.48

2.46

2.44

2.42

2.40

2.38

+1%

–1%

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 3.7 V – FPWM

V_IN= 3.7 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 3.3 V – FPWM

V_IN= 3.3 V – PSM

V_IN= 3.7 V – FPWM

V_IN= 3.7 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 2.5 V

图9-10. Efficiency

V_OUT= 2.5 V

图9-11. Load Regulation

100

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

3.18

+1%

–1%

V_IN= 3.7 V – FPWM

V_IN= 3.7 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

V_IN= 3.7 V – FPWM

V_IN= 3.7 V – PSM

V_IN= 5.0 V – FPWM

V_IN= 5.0 V – PSM

10m

100m

Output Current (A)

10m

100m

Output Current (A)

V_OUT= 3.3 V

图9-12. Efficiency

V_OUT= 3.3 V

图9-13. Load Regulation

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9.2.3 Application Curves (continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.5

2.0

1.5

V_OUT= 0.6 V – FPWM

1.0

0.5

0.0

V_OUT= 0.6 V – PSM

V_OUT= 1.8 V – FPWM

V_OUT= 1.8 V – PSM

V_OUT= 3.3 V – FPWM

V_OUT= 3.3 V – PSM

V_OUT= 0.6 V

V_OUT= 1.2 V

V_OUT= 3.3 V

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Output Current (A)

Input Voltage (V)

V_IN= 5 V

I_OUT= 1 A

图9-14. Switching Frequency

图9-15. Switching Frequency

I_OUT= 6 A

I_OUT= 0.1 A

图9-16. PWM Operation

图9-17. PSM Operation

I_OUT= 0.1 A

No Load

图9-18. Forced-PWM Operation

图9-19. Startup with No-Load

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

9.2.3 Application Curves (continued)

I_OUT= 0.6 A to 5.4 A

图9-21. Load Transient - PSM Operation

图9-20. Load Transient - PWM Operation

I_OUT= 1 A

图9-22. HICCUP Short Circuit Protection

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input

power supply has a sufficient current rating for the application.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching

frequencies. The PCB layout of the TPS62865 and TPS62867 devices requires careful attention to ensure best

performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI

radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter

technical brief for a detailed discussion of general best practices. The following are specific recommendations for

the TPS62865 and TPS62867:

• The input capacitor or capacitors must be placed as close as possible to the VIN and PGND pins of the

device. This is the most critical component placement. Route the input capacitor or capacitors directly to the

VIN and PGND pins, avoiding vias.

• Place the output inductor close to the SW pins. Minimize the copper area at the switch node.

• Place the output capacitor or capacitors ground close to the PGND pin and route it directly, avoiding vias.

Minimize the length of the connection from the inductor to the output capacitor. Connect the VOS pin directly

to the output capacitor.

• Sensitive traces, such as the connections to the VOS, FB, and VSEL pins, must be connected with short

traces and be routed away from any noise source, such as the SW pin.

• Make the connections from the input voltage of the system and the connection to the load as wide as

possible to minimize voltage drops.

• Have a solid ground plane between PGND and the input and output capacitor ground connections.

• The sensitive signal ground connections for the feedback voltage divider must be connected to a separate

signal ground trace.

11.2 Layout Example

Solution

Size 63mm²

VOUT

GND

VIN

GND

图11-1. Layout Example

11.2.1 Thermal Considerations

After the layout recommendations for component placement and routing have been followed, the PCB design

must focus on thermal performance. Thermal design is important and must be considered to remove the heat

generated in the device during operation. The device junction temperature must stay below its maximum rated

temperature of 125°C for correct operation.

Use wide traces and planes, especially to the PGND, VIN, and VOUT pins, and use vias to internal planes to

improve the power dissipation capability of the design. If the application allows it, use airflow in the system to

further improve cooling.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

The Thermal Information table provides the thermal parameters of the device and its package based on the

JEDEC standard 51-7. See the Semiconductor and IC Package Thermal Metrics application report for a detailed

explanation of each parameter. In addition to the JEDEC standard, the thermal information table also contains

the thermal parameters of the EVM. The EVM better reflects a real-world PCB design with thicker traces

connecting to the device.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.1.2 Development Support

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS62865 device with the WEBENCH® Power Designer.

Click here to create a custom design using the TPS62867 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs

application report

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

TPS62865, TPS62867

ZHCSNO7 –MARCH 2021

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS62865 TPS62867

PACKAGE OPTION ADDENDUM

www.ti.com

13-Apr-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS62865RQYR

TPS62867RQYR

ACTIVE

VQFN-HR

RQY

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

2EAH

2DWH

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

13-Apr-2021

Addendum-Page 2

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RQY0009A

1.6

1.4

2.6

2.4

PIN 1 INDEX AREA

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

0.85

0.65

(0.1) TYP

0.25

0.15

0.1

A B

0.05

PKG

2X 0.4

0.4

0.3

PIN 1 ID

(45° X 0.1)

0.3

0.2

4X 0.5

PKG

4225639/A 03/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RQY0009A

PKG

(0.95)

3X (0.95)

3X (0.2)

PKG

(2.35)

2X (0.4)

(R0.05) TYP

6X (0.55)

6X (0.25)

4X (0.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED

METAL

EXPOSED

METAL UNDER

SOLDER MASK

METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225639/A 03/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RQY0009A

PKG

(0.95)

3X (0.95)

3X (0.2)

PKG

(2.35)

2X (0.4)

(R0.05) TYP

6X (0.55)

6X (0.25)

4X (0.5)

SOLDER PASTE EXAMPLE

BASED ON 0.1mm THICK STENCIL

SCALE: 25X

4225639/A 03/2020

NOTES: (continued)

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TPS62867RQYR [TI]

相关型号：

TPS62868

TPS6286800CRQY

TPS6286800CRQYR

TPS628680ARQY

TPS628680ARQYR

TPS628680CRQY

TPS6286810CRQY

TPS6286810CRQYR

TPS628681ARQY

TPS628681ARQYR

TPS628681CRQY

TPS6286820CRQY