TPS6286X [TI]
2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter with I2C Interface in 1.05-mm x 1.78-mm WCSP Package;
| 型号： | TPS6286X |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter with I2C Interface in 1.05-mm x 1.78-mm WCSP Package |
| 文件： | 总40页 (文件大小：2745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62864, TPS62866
SLVSEI1C – JUNE 2019 – REVISED OCTOBER 2020
TPS62864/6 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter
with I2C Interface in WCSP Package
1 Features
2 Applications
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•
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•
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•
•
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7-mΩ and 6.5-mΩ internal power MOSFETs
>90% efficiency (0.9-V output)
DCS-control topology for fast transient response
1% output voltage accuracy
4-µA operating quiescent current
2.4-V to 5.5-V input voltage range
2.4-MHz switching frequency
•
Core supply for FPGAs, CPUs, ASICs or video
chipsets
Camera modules
Solid-state drives
Optical modules
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3 Description
The TPS62864 and TPS62866 devices are high-
frequency synchronous step-down converters with I2C
interface which provide an efficient, adaptive, and
high power-density solution. At medium to heavy
loads, the converter operates in PWM mode and
automatically enters Power Save Mode operation at
light load to maintain high efficiency over the entire
load current range. The device can also be forced in
PWM mode operation for smallest output voltage
ripple. Together with its DCS-control architecture,
excellent load transient performance and tight output
voltage accuracy are achieved. Via the I2C interface
and a dedicated VID pin, the output voltage is quickly
adjusted to adapt the power consumption of the load
to the ever-changing performance needs of the
application.
Selection by external resistor
– Start-up output voltage
– I2C slave address
•
Selection by I2C interface
– Power save mode or forced PWM mode
– Output discharge
– Hiccup or latching short-circuit protection
– Output voltage ramp speed
VID pin for dynamic voltage scaling (DVS)
Thermal pre-warning and thermal shutdown
Power good indicator pin option
I2C-compatible interface up to 3.4 Mbps
Available in 1.05-mm x 1.78-mm x 0.5-mm 15-pin
WCSP package with 0.35-mm pitch
Create a custom design using the TPS62866 with
the WEBENCH® Power Designer
•
•
•
•
•
•
Device Information
PART NUMBER
TPS62864
TPS62866
PACKAGE (1)
BODY SIZE (NOM)
WCSP (15)
1.05 x 1.78 x 0.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
95
90
85
80
75
TPS6286x
VIN
2.4 V to 5.5 V
VOUT
0.9 V
L1
0.24 µH
VIN
EN
SW
C1
2x10 µF
C2
2x22 µF
VOS
VSET/VID
or
VSET/PG
SCL
SDA
I2C
R1
AGND PGND
70
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
65
60
Typical Application
100m
1m
10m
Load (A)
100m
1
6
D004
Efficiency at VIN = 3.3 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62864, TPS62866
SLVSEI1C – JUNE 2019 – REVISED OCTOBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 I2C InterfaceTiming Characteristics ........................... 7
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
8.5 Programming............................................................ 14
8.6 Register Map.............................................................17
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Applications.................................................. 20
10 Power Supply Recommendations..............................27
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
11.3 Thermal Considerations..........................................28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Documentation Support.......................................... 29
12.3 Support Resources................................................. 29
12.4 Receiving Notification of Documentation Updates..29
12.5 Trademarks.............................................................29
12.6 Electrostatic Discharge Caution..............................29
12.7 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2020) to Revision C (October 2020)
Page
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•
•
•
•
Removed instances of QFN package.................................................................................................................1
Updated the numbering format for tables, figures and cross-references throughout the document. .................1
Updated Device Options ....................................................................................................................................3
Removed Power Good (PG) section................................................................................................................ 13
Updated I2C Register Reset section.................................................................................................................17
Changes from Revision A (December 2019) to Revision B (March 2020)
Page
•
Updated Figure 9-12 ........................................................................................................................................23
Changes from Revision * (June 2019) to Revision A (December 2019)
Page
•
Change device status from Advance Information to Production Data................................................................ 1
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5 Device Options
PART NUMBER(1)
TPS628640AYCG
TPS628640BYCG
TPS628660AYCG
TPS628660BYCG
START-UP OUTPUT VOLTAGE
OUTPUT CURRENT
VID OR PG PIN
VID
PG
VID
PG
4 A
6 A
0.4 V to 1.15 V, Selectable
(1) For all available packages, see the orderable addendum at the end of the data sheet.
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6 Pin Configuration and Functions
TOP VIEW
BOTTOM VIEW
2
1
2
3
3
1
VSET/
VID
VSET/
AGND
VOS
A
B
C
D
E
VOS
PGND
SW
AGND
VID
PGND
PGND
PGND
PGND
PGND
SW
SW
SW
SW
VIN
SW
VIN
VIN
VIN
VIN
VIN
EN
SDA
SCL
SCL
SDA
EN
Figure 6-1. YCG (15 Pin)
Table 6-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
A1
Analog ground pin
Start-up output voltage and device address selection pin. An external resistor must be connected. After
start-up, the pin can be used to select the VOUT registers for the output voltage. (Low = VOUT register 1;
High = VOUT register 2). See Section 8.4.4.
VSET/VID
VSET/ PG
A2
Start-up output voltage and device address selection pin. An external resistor must be connected. After
start-up, the pin is used for the power good indicator. When the output voltage is not regulated, the pin
is driven high. When the output voltage is regulated, the pin is pulled low through the external resistor.
The function after start-up depends on the device option. See Section 5.
A2
A3
VOS
PGND
SW
Output voltage sense pin. This pin must be directly connected to the output capacitor.
B1,B2,B3 Power ground pin
C1,C2,C3 Switch pin of the power stage
D1,D2,D3 Power supply input voltage pin
VIN
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables
the device. Do not leave floating.
EN
E1
SDA
SCL
E2
E3
I2C serial data pin. Do not leave it floating. Connect it to AGND if not used.
I2C serial clock pin. Do not leave it floating. Connect it to AGND if not used.
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7 Specifications
7.1 Absolute Maximum Ratings
MIN
-0.3
-0.3
-2.5
MAX
UNIT
VIN, EN, SDA, SCL, VOS, VSET/VID, VSET/PG
SW (DC)
6
Voltage(1)
VIN + 0.3
V
SW (AC, less than 10ns)(2)
Source current at VSET/PG
Sink current at SDA, SCL
Junction temperature
10
1
ISOURCE_PG
ISINK_SDA,SCL
TJ
mA
mA
°C
2
-40
-65
150
150
Tstg
Storage temperature
°C
(1) All voltage values are with respect to network ground terminal.
(2) While switching.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
10
UNIT
V
VIN
Input voltage
2.4
tF_VIN
Falling transition time at VIN(1)
Output current, TPS62864 (2)
Output current, TPS62866 (3)
Junction temperature
mV/µs
0
0
4
IOUT
TJ
A
6
-40
125
°C
(1) The falling slew rate of VIN should be limited if VIN goes below VUVLO
.
(2) Lifetime is reduced when operating continuously at 4-A output current and the junction temperature is higher than 105 °C.
(3) Lifetime is reduced when operating continuously at 6-A output current and the junction temperature is higher than 85 °C.
7.4 Thermal Information
TPS6286x YCG
THERMAL METRIC(1)
JEDEC 51-7
15 PINS
91.8
TPS62866EVM-051
UNIT
15 PINS
56.5
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.8
n/a(2)
n/a(2)
0.4
23.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
ΨJB
23.3
27.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching
4
0.1
2.3
2.2
130
20
10
1
µA
µA
V
ISD
Shutdown current
EN = Low, TJ = -40℃ to 85℃
VIN rising
2.2
2.1
2.4
2.3
VUVLO
Under voltage lock out threshold
VIN falling
V
Thermal warning threshold
Thermal warning hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
°C
°C
TJW
TJ falling
TJ rising
150
20
TJSD
TJ falling
LOGIC INTERFACE EN, SDA, SCL
High-level input threshold voltage at EN,
SCL, SDA, VSET/VID
VIH
VIL
1.0
V
V
Low-level input threshold voltage at EN,
SCL, SDA, VSET/VID
0.4
ISCL,LKG Input leakage current into SCL pin
ISDA,LKG Input leakage current into SDA pin
0.01
0.01
0.01
1
0.2
0.1
0.1
µA
µA
µA
pF
pF
IEN,LKG
CSCL
Input leakage current into EN pin
Parasitic capacitance at SCL
Parasitic capacitance at SCL
CSDA
2.4
STARTUP, POWER GOOD
Time from EN high to device starts switching, R1
= 249kΩ
tDelay
tRamp
Enable delay time
420
700 1100
µs
Output voltage ramp time
Power good lower threshold
Power good upper threshold
Power good deglitch delay
Time from device starts switching to power good
VVOS referenced to VOUT nominal
VVOS referenced to VOUT nominal
Rising and falling edges
0.9
85
1
91
1.5
96
ms
%
VPG
103
111
34
120
%
tPG,DLY
µs
OUTPUT
VOUT ≥ 0.59 V, FPWM, no Load, TJ = 25℃ to
125℃
-1
-2
1
2
%
VOUT
Output voltage accuracy(1)
VOUT < 0.59 V, FPWM, no Load, TJ = 25℃ to
125℃
%
EN = High, VVOS = 1.8 V
18
µA
µA
IVOS,LKG Input leakage current into VOS pin
EN = Low, Output discharge disabled, VVOS = 1.8
V
0.2
2.5
RDIS
Output discharge resistor at VOS pin
Load regulation
15
Ω
VOUT = 0.9 V, FPWM
0.04
%/A
POWER SWITCH
High-side FET on-resistance
7
6.5
5.5
7.7
4.5
6.5
-3
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
TPS62864
5
7
6
High-side FET forward current limit
TPS62866
8.5
A
ILIM
TPS62864
A
Low-side FET forward current limit
Low-side FET negative current limit
TPS62866
A
TPS62864, TPS62866
A
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7.5 Electrical Characteristics (continued)
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
fSW
PWM switching frequency
IOUT = 1 A, VOUT = 0.9 V
2.4 MHz
(1) Exclude codes: 0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
7.6 I2C InterfaceTiming Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
100
400
1
UNIT
Standard mode
Fast mode
kHz
kHz
MHz
MHz
MHz
MHz
MHz
µs
Fast mode plus
f(SCL)
SCL Clock Frequency
High-speed mode (write operation), CB – 100 pF max
High-speed mode (read operation), CB – 100 pF max
High-speed mode (write operation), CB – 400 pF max
High-speed mode (read operation), CB – 400 pF max
Standard mode
3.4
3.4
1.7
1.7
4.7
1.3
0.5
4
Bus Free Time Between a STOP and
START Condition
tBUF
Fast mode
µs
Fast mode plus
µs
Standard mode
µs
Fast mode
600
260
160
4.7
1.3
0.5
160
320
4
ns
Hold Time (Repeated) START
condition
tHD, tSTA
Fast mode plus
ns
High-speed mode
ns
Standard mode
µs
Fast mode
µs
tLOW
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Fast mode plus
µs
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
ns
ns
µs
Fast mode
600
260
60
ns
tHIGH
Fast mode plus
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
ns
120
4.7
600
260
160
250
100
50
ns
µs
Fast mode
ns
Setup Time for a Repeated START
Condition
tSU, tSTA
Fast mode plus
ns
High-speed mode
ns
Standard mode
ns
Fast mode
ns
tSU, tDAT Data Setup Time
Fast mode plus
ns
High-speed mode
10
ns
Standard mode
0
3.45
0.9
µs
Fast mode
0
µs
tHD, tDAT Data Hold Time
Fast mode plus
0
µs
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
0
70
ns
0
150
ns
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PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Standard mode
Fast mode
1000
ns
20 +
0.1 CB
300
ns
tRCL
Rise Time of SCL Signal
Fast mode plus
120
40
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
10
20
80
20 +
0.1 CB
Standard mode
Fast mode
1000
300
ns
ns
20 +
0.1 CB
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
tRCL1
Fast mode plus
120
80
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
10
20
160
20 +
0.1 CB
Standard mode
300
ns
Fast mode
300
120
40
ns
ns
ns
ns
ns
tFCL
tRDA
tFDA
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Fast mode plus
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
80
1000
20 +
0.1 CB
Fast mode
300
ns
Fast mode plus
120
80
ns
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
300
20 +
0.1 CB
Fast mode
300
ns
Fast mode plus
120
80
ns
ns
ns
µs
ns
ns
ns
pF
pF
pF
pF
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
4
Fast mode
600
260
160
tSU, tSTO Setup Time of STOP Condition
Fast mode plus
High-Speed mode
Standard mode
400
400
550
400
Fast mode
CB
Capacitive Load for SDA and SCL
Fast mode plus
High-Speed mode
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7.7 Typical Characteristics
30
30
20
10
0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
20
10
0
2.4
2.8
3.2
3.6
Input Voltage (V)
4.0
4.4
4.8
5.2
5.6
2.4
2.8
3.2
3.6
Input Voltage (V)
4.0
4.4
4.8
5.2
5.6
D002
D003
Figure 7-1. High-Side FET On-Resistance
Figure 7-2. Low-Side FET On-Resistance
7.0
0.15
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.10
0.05
0.00
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
D001
D000
Figure 7-4. Shutdown Current
Figure 7-3. Quiescent Current
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8 Detailed Description
8.1 Overview
The TPS62864 and TPS62866 synchronous step-down converters use the DCS-Control (Direct Control with
Seamless transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic and current-mode control schemes.
The DCS-Control™ topology operates in PWM (pulse width modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal
switching frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. Because
DCS-Control supports both operation modes (PWM and PFM) within a single building block, the transition from
PWM mode to Power Save Mode is seamless without affecting the output voltage. The devices offer both
excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple.
8.2 Functional Block Diagram
VIN
VIN
EN
Control Logic
Reference Selection
UVLO
Thermal Shutdown
Startup Ramp
VSET/VID
or
VSET/PG
VPG_H
+
œ
VFB
+
PG
SDA
SCL
VPG_L
I2C Interface
œ
HS-FET
Forward Current Limit
VSW
VIN
TON
HICCUP (1)
Modulator
Direct Control
&
Compensation
VSW
SW
Gate
Drive
VREF
+
_
EA
Comparator
VOS
LS-FET
(1)
RDIS
Forward Current Limit
Zero Current Detect
Negative Current Limit
PGND
AGND
(1) enabled via I2C
PGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. Power Save
Mode is based on a fixed on-time architecture, as shown in Equation 1.
V
OUT
t
∂416ns
ON
V
IN
(1)
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In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
8.3.2 Forced PWM Mode
With I2C, set the device in forced PWM (FPWM) mode by the CONTROL register. The device switches at 2.4
MHz, even with a light load. This reduces the output voltage ripple and allows simple filtering of the switching
frequency for noise-sensitive applications. Efficiency at light load is lower in FPWM mode.
8.3.3 Start-up
After enabling the device, there is an enable delay (tDelay) before the device starts switching. During this period,
the device sets the internal reference voltage, and determines the start-up output voltage through the resistor
connected to the VSET/VID or VSET/ PG pin. After tdelay, all registers can be read and written by the I2C
interface.
VIN
EN
VOUT
ttDelay
t
ttRamp
ttStartupt
t
Figure 8-1. Start-up Sequence
After the enable delay, an internal soft start-up circuitry ramps up the output voltage with a period of 1 ms (tRamp).
This avoids excessive inrush current and creates a smooth output voltage rising-slope. It also prevents
excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and drawing excessive current from the
battery or input voltage rail. Excessive current can occur with a shorted or saturated inductor or a heavy load or
shorted output circuit condition. If the inductor current reaches the threshold ILIM, cycle by cycle, the high-side
MOSFET is turned off and the low-side MOSFET is turned on, while the inductor current ramps down to the low-
side MOSFET current limit.
When the high-side MOSFET current limit is triggered 32 times, the device stops switching. The device then
automatically re-starts, with an internal soft start-up, after a typical delay time of 128 µs has passed. This is
named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.
The HICCUP is disabled by the CONTROL register bit Enable HICCUP. Disabling HICCUP changes the
overcurrent protection to latching protection. The device stops switching after the high-side MOSFET current
limit is triggered 32 times. Toggling the EN pin, removing and reapplying the input voltage, or writing to the
CONTROL register bit Software Enable Device unlatches the device.
8.3.5 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) is implemented when
the input voltage is lower than VUVLO. The device stops switching and the output voltage discharge is active (if
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enabled through I2C) when the device is in UVLO. When the input voltage recovers, the device automatically
returns to operation with an internal soft start-up. During UVLO, the internal register values are kept.
The UVLO bit in the STATUS Register is set when the input voltage is less than the UVLO falling threshold.
When the input voltage is below 1.8 V (typ), all registers are reset.
8.3.6 Thermal Warning and Shutdown
When the junction temperature goes up to TJW, the device gives a pre-warning indicator in the STATUS register.
The device keeps running.
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
activates the output voltage discharge. When the device temperature falls below the threshold by 20°C, the
device returns to normal operation automatically with an internal soft start-up. During thermal shutdown, the
internal register values are kept.
8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. In shutdown mode (EN = Low), the internal power
switches as well as the entire control circuitry are turned off, and all the registers are reset, except for the Enable
Output Discharge bit. Do not leave the EN pin floating.
In shutdown mode (EN = Low), all registers cannot be read and written by the I2C interface.
The typical threshold value of the EN pin is 0.61 V for rising input signals, and 0.51 V for falling input signals.
The device is also enabled or disabled by setting the bit, Software Enable Device in CONTROL register while EN
= High. After being disabled/enabled by this bit, the device stops switching and has a new start-up beginning
with tRamp. There is no TDelay time and the registers are not reset.
8.4.2 Output Discharge
An internal MOSFET switch smoothly discharges the output through the VOS pin in shutdown mode (EN = Low
or Software Enable Device bit = 0). The output discharge is also active when the device is in thermal shutdown
and UVLO.
When the Enable Output Discharge bit is set to 0, the output discharge function is disabled. The input voltage
must remain higher than 1 V (TYP) to keep the output discharge function operational and the status of the
Enable Output Discharge bit retained. The Enable Output Discharge bit is reset on the rising edge of the EN pin.
8.4.3 Start-up Output Voltage and I2C Slave Address Selection (VSET)
During the enable delay (tDelay), the start-up output voltage and device I2C slave address are set by an external
resistor connected to the VSET/VID or VSET/ PG pin through an internal R2D (resistor to digital) converter.
Table 8-1 shows the options.
Table 8-1. Start-up Output Voltage and I2C Slave Address Options
RESISTOR (E96 SERIES, ±1%
ACCURACY) AT VSET/VID OR VSET/ PG
START-UP OUTPUT VOLTAGE (TYP)
I2C SLAVE ADDRESS
249 kΩ
205 kΩ
162 kΩ
133 kΩ
105 kΩ
86.6 kΩ
68.1 kΩ
56.2 kΩ
44.2 kΩ
36.5 kΩ
1.15 V
1.10 V
1.05 V
1.00 V
0.95 V
0.90 V
0.85 V
0.80 V
0.75 V
0.70 V
1000 110
1000 101
1000 100
1000 011
1000 010
1000 001
1001 000
1001 001
1001 010
1001 011
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Table 8-1. Start-up Output Voltage and I2C Slave Address Options (continued)
RESISTOR (E96 SERIES, ±1%
ACCURACY) AT VSET/VID OR VSET/ PG
START-UP OUTPUT VOLTAGE (TYP)
I2C SLAVE ADDRESS
28.7 kΩ
23.7 kΩ
18.7 kΩ
15.4 kΩ
12.1 kΩ
10 kΩ
0.65 V
0.60 V
0.55 V
0.50 V
0.45 V
0.40 V
1001 100
1001 101
1001 110
1001 111
1000 000
1000 111
The R2D converter has an internal current source which applies current through the external resistor, and an
internal ADC which reads back the resulting voltage level. Depending on the level, the correct start-up output
voltage and I2C slave address are set. Once this R2D conversion is finished, the current source is turned off to
avoid current flowing through the external resistor. Ensure that there is no additional current path or capacitance
greater than 30 pF from this pin to GND during R2D conversion. Otherwise a false value is set.
During the ramp up period (tRamp), the output voltage ramps to the target value set by VSET first, then ramps up
or down to the new value when the value of the output register is changed by I2C interface commands.
8.4.4 Select Output Voltage Registers (VID)
After the start-up period (tStartup), the output voltage can be selected between two output voltage registers by the
VID pin. When VID is pulled low, the output voltage is set by Table 8-4. When VID is pulled high, the output
voltage is set by Table 8-5. This is also called dynamic voltage scaling (DVS).
During an output voltage change through I2C or the VSET/VID pin, the device can be set in FPWM by the
Enable FPWM Mode during Output Voltage Change bit in CONTROL register. The output voltage change speed
is set by the Voltage Ramp Speed bit.
8.4.5 Power Good (PG)
The TPS62864 and TPS62864 families provide device options with the VSET/ PG pin, instead of a VSET/VID
pin, shown in Figure 9-1.
After the enable delay (tDelay), the device starts to compare the output voltage with the nominal value set by the
external resistor or the output voltage registers. Table 8-2 shows the logic level of the PG pin. The pin is driven
up to the input voltage for a logic high. The pin is pulled down to GND by the external resistor R1 for a logic low.
For the VSET/ PG option devices, be aware of the following:
•
VSET/ PGcan not be connected to GND. A resistor, R1, must be connected between VSET/ PGand GND, for
the start-up output voltage and I2C slave address setup.
•
•
•
The source current of the VSET/ PG pin is up to 1 mA.
VOUT Register 2 is disabled.
When the device is in shutdown, the shutdown current is high because of the leakage current through the
external resistor, R1, when the VSET/ PG pin is high.
The VSET/ PG has a deglitch time, before the signal goes high or low, during normal operation. For start-up, the
VSET/ PG has a delay time of 200 µs after the output voltage reaches the nominal voltage.
Table 8-2. VSET/ PG Pin Logic
PG LOGIC STATUS
DEVICE CONDITIONS
HIGH
LOW
0.91 x VOUT_NOM ≤ VVOS ≤ 1.11 x VOUT_NOM
√
Enable
VVOS < 0.91 x VOUT_NOM or VVOS > 1.11 x VOUT_NOM
√
√
√
√
Shutdown
EN = Low
Thermal Shutdown
UVLO
TJ > TJSD
1.8 V < VIN < VUVLO
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Table 8-2. VSET/ PG Pin Logic (continued)
PG LOGIC STATUS
HIGH LOW
DEVICE CONDITIONS
Power Supply Removal VIN < 1.8 V
undefined
8.5 Programming
8.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors. The bus consists
of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives or transmits data on the bus under
control of the master device, or both.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps) and high-speed
mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as the input voltage remains above 1.8 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode.
It is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pullup voltages to ensure reset of the I2C engine.
8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 8-2. All I2C-compatible devices
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 8-2. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-3). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8-4) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
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DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 8-3. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 8-2). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
Figure 8-4. Acknowledge on the I2C Bus
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Figure 8-5. Bus Protocol
8.5.3 HS-Mode Protocol
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start
conditions must be used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
8.5.4 I2C Update Sequence
The sequence requires a start condition, a valid I2C slave address, a register address byte, and a data byte for a
single update. After the receipt of each byte, the device acknowledges by pulling the SDA line low during the
high period of a single clock pulse. A valid I2C address selects the device. The device performs an update on the
falling edge of the acknowledge signal that follows the LSB byte.
8
1
7
1
1
8
1
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
—0“ Write
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
Figure 8-6. “Write” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8
1
7
1
1
8
1
1
7
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
—0“ Write
—1“ Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
Figure 8-7. “Read” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
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F/S Mode
8
HS Mode
8
F/S Mode
8
1
1
1
7
1
1
1
1
1
S
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
(n x Bytes + Acknowledge)
HS Mode continues
Slave Address
A
A
S
= Acknowledge (SDA low)
= Not acknowledge (SDA high)
= START condition
From Master to Slave
From Slave to Master
Sr
Sr = REPEATED START condition
= STOP condition
P
Figure 8-8. Data Transfer Format in HS-Mode
8.5.5 I2C Register Reset
The I2C registers can be reset by:
•
•
•
Pulling the input voltage below 1.8 V (typ)
A high to low transition on EN.
Setting the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new start-up is begun immediately. After tDelay, the I2C registers can be programmed again.
8.6 Register Map
Table 8-3. Register Map
REGISTER ADDRESS
(HEX)
FACTORY DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
Sets the target output voltage
0x01
0x02
0x03
0x05
VOUT Register 1
VOUT Register 2
0x64
0x64
0x6F
0x00
Sets the target output voltage
Sets miscellaneous configuration bits
Returns status flags
CONTROL Register
STATUS Register
8.6.1 Slave Address Byte
7
6
5
4
3
2
1
0
1
x
x
x
x
x
x
R/W
The slave address byte is the first byte received following the START condition from the master device. The
slave addresses can be assigned by an external resistor, see Table 8-1.
8.6.2 Register Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the device,
which contains the address of the register to be accessed.
8.6.3 VOUT Register 1
Table 8-4. VOUT Register 1 Description
REGISTER ADDRESS 0X01 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)(1)
0x00
0x01
...
400 mV
405 mV
7:0
VO1_SET
0x64
...
900 mV
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Table 8-4. VOUT Register 1 Description (continued)
REGISTER ADDRESS 0X01 READ/WRITE
BIT FIELD
VALUE (HEX)
0xFE
OUTPUT VOLTAGE (TYP)(1)
1670 mV
1675 mV
0xFF
(1) It is not recommended to use the following codes, as their output voltage accuracy may have a wider tolerance than the specification:
0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
8.6.4 VOUT Register 2
Table 8-5. VOUT Register 2 Description
REGISTER ADDRESS 0X02 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)(1)
0x00
0x01
...
400 mV
405 mV
7:0
VO2_SET
0x64
...
900 mV (default value)
0xFE
0xFF
1670 mV
1675 mV
(1) It is not recommended to use the following codes, as their output voltage accuracy may have a wider tolerance than the specification:
0x20 (560 mV), 0x40 (720 mV), 0x60 (880 mV), 0x80 (1040 mV), 0xC4 (1360 mV), 0xE0 (1520 mV).
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8.6.5 CONTROL Register
Table 8-6. CONTROL Register Description
REGISTER ADDRESS 0X03 WRITE ONLY
BIT
7
FIELD
TYPE
R/W
DEFAULT DESCRIPTION
Reset
0
1
1 - Reset all registers to default.
6
Enable FPWM Mode during Output
Voltage Change
R/W
0 - Keep the current mode status during output voltage change
1 - Force the device in FPWM during output voltage change
5
Software Enable Device
R/W
1
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new startup without the tDelay
period.
4
3
Enable FPWM Mode
Enable Output Discharge
Enable HICCUP
R/W
R/W
R/W
R/W
0
1
0 - set the device in power save mode at light loads.
1 - set the device in forced PWM mode at light loads.
0 - Disable output discharge
1 - Enable output discharge
2
1
0 - Disable HICCUP. Enable latching protection.
1 - Enable HICCUP, Disable latching protection.
0:1
Voltage Ramp Speed
11
00 - 20mV/µs (0.25 µs/step)
01 - 10 mV/µs (0.5 µs/step)
10 - 5 mV/µs (1 µs/step)
11 - 1 mV/µs (5 µs/step, default)
8.6.6 STATUS Register
Table 8-7. STATUS Register Description
REGISTER ADDRESS 0X05 READ ONLY(1)
BIT
7:5
4
FIELD
TYPE
DEFAULT DESCRIPTION
Reserved
Thermal Warning
HICCUP
R
R
0
0
1: Junction temperature is higher than 130°C
3
1: Device has HICCUP status once
2
Reserved
Reserved
UVLO
1
0
R
0
1: The input voltage is less than UVLO threshold (falling edge)
(1) All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Applications
9.2.1 6-A Output Current Application
Figure 9-1. Typical Application
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.4 V to 5.5 V
0.9 V
Output voltage
Maximum output current
6 A
Table 9-2 lists the components used for the example.
Table 9-2. List of Components of Figure 9-1
REFERENCE
DESCRIPTION
MANUFACTURER(1)
Samsung Electro-
Mechanics
C1
10 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, CL10B106MQ8NRNC
C2
L1
R1
22 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44L
0.22 µH, Power inductor, XAL4020-221ME (12 A, 5.81 mΩ)
Depending on the start-up output voltage, size 0603
Murata
Coilcraft
Std
(1) See Third-party Products disclaimer.
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62866 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Setting The Output Voltage
The initial output voltage is set by an external resistor connected to the VSET/VID or VSET/PGpin, according to
Table 8-1. After the soft start-up, the output voltage can be changed in the VOUT Registers. Refer to Table 8-4
and Table 8-5.
9.2.1.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 9-3
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab test. Further combinations should be checked for
each individual application.
Table 9-3. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
22
2 x 22 or 47
3 x 22
150
(1)
0.24
+
+
+
(1) This LC combination is the standard value and recommended for most applications.
(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –30%.
9.2.1.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 2 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
(2)
where
•
•
•
IOUT,MAX = maximum output current
ΔIL = inductor current ripple
fSW = switching frequency
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•
L = inductor value
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate
inductor. Table 9-4 lists recommended inductors.
Table 9-4. List of Recommended Inductors
INDUCTANCE CURRENT RATING,
DIMENSIONS
[L x W x H mm]
DC RESISTANCE
[mΩ]
PART NUMBER (1)
[µH]
0.22
0.24
ISAT [A]
18.7
4 x 4 x 2
5.81
13
Coilcraft, XAL4020-221ME
Murata, DFE201612E-R24M
6.6
2 x 1.6 x 1.2
(1) See Third-party Products disclaimer.
9.2.1.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is recommended for best filtering and must be placed
between VIN and PGND as close as possible to those pins. For most applications, 8 μF is a sufficient value for
the effective input capacitance, though a larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended minimum output effective capacitance is 30 μF; this
capacitance can vary over a wide range as outline in the output filter selection table.
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9.2.1.3 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25°C, BOM = Table 9-2, unless otherwise noted.
0.612
0.606
0.600
0.594
0.588
90
85
80
75
70
65
60
55
50
45
40
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
100m
1m
10m
Load (A)
100m
1
6
100m
1m
10m
Load (A)
100m
1
6
D008
D005
VOUT = 0.6 V
Power Save Mode
VOUT = 0.6 V
Power Save Mode
Figure 9-3. Load Regulation
Figure 9-2. Efficiency
0.918
95
90
85
80
75
70
65
60
55
50
45
0.909
0.900
0.891
0.882
0.873
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
100m
1m
10m
Load (A)
100m
1
6
100m
1m
10m
Load (A)
100m
1
6
D009
D006
VOUT = 0.9 V
VOUT = 0.9 V
Figure 9-5. Load Regulation
Figure 9-4. Efficiency
1.212
1.200
1.188
1.176
1.164
95
90
85
80
75
70
65
60
55
50
45
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
100m
1m
10m
Load (A)
100m
1
6
100m
1m
10m
Load (A)
100m
1
6
D010
D007
VOUT = 1.2 V
Power Save Mode
VOUT = 1.2 V
Power Save Mode
Figure 9-7. Load Regulation
Figure 9-6. Efficiency
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3.0
3.0
2.0
1.0
0.0
2.0
VOUT = 0.6V, PSM
1.0
0.0
VOUT = 0.6V, FPWM
VOUT = 0.9V, PSM
VOUT = 0.9V, FPWM
VOUT = 1.2V, PSM
VOUT = 1.2V, FPWM
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load (A)
2.4
2.8
3
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
D017
D018
VIN = 5.0 V
IOUT = 1.0 A
Figure 9-8. Switching Frequency
Figure 9-9. Switching Frequency
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
45
55
65
75
Ambient Temperature (°C)
85
95
105
115
125
45
55
65
75
Ambient Temperature (°C)
85
95
105
115
125
D019
D020
VOUT = 0.9 V
θJA = 56.5°C/W
VOUT = 1.675 V
θJA = 56.5°C/W
Figure 9-10. Thermal Derating
Figure 9-11. Thermal Derating
VSW
VSW
5V/DIV
5V/DIV
VOUT
10mV/DIV
AC
VOUT
5mV/DIV
AC
ICOIL
ICOIL
1A/DIV
1A/DIV
6A Offset
Time - 2ꢀs/DIV
Time - 200ns/DIV
D031
D030
IOUT = 0.1 A
IOUT = 6.0 A
Figure 9-13. PSM Operation
Figure 9-12. PWM Operation
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VEN
2V/DIV
VSW
5V/DIV
_
VPG
5V/DIV
VOUT
10mV/DIV
AC
VOUT
0.5V/DIV
ICOIL
ICOIL
1A/DIV
1A/DIV
Time - 2ꢀs/DIV
Time - 0.5ms/DIV
D032
D033
IOUT = 0.1 A
No Load
Figure 9-14. Forced PWM Operation
Figure 9-15. Startup and Shutdown by EN Pin
VSDA
2V/DIV
VVID
2V/DIV
_
VPG
5V/DIV
VOUT
0.5V/DIV
VOUT
100mV/DIV
AC
ICOIL
1A/DIV
Time - 100ꢀs/DIV
Time - 0.2ms/DIV
D035
D034
IOUT = 1 A
VOUT = 0.9 V to 1.1 V
No Load
Figure 9-17. VOUT Transition with Different Slew
Rate Settings
Figure 9-16. Start-up by Software Enable Device
Bit
ILOAD
ILOAD
2A/DIV
2A/DIV
VOUT
50mV/DIV
AC
VOUT
50mV/DIV
AC
Time - 50ꢀs/DIV
Time - 50ꢀs/DIV
D036
D037
IOUT = 0.05 A to 4 A
PSM
IOUT = 0.05 A to 4 A
Forced PWM
Figure 9-18. Load Transient
Figure 9-19. Load Transient
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_
VPG
5V/DIV
VOUT
0.5V/DIV
ICOIL
5A/DIV
Time - 0.2ms/DIV
D038
IOUT = 2.5 A
TPS62866
Figure 9-20. HICCUP Protection
9.2.2 Smaller Application Solution
VIN
2.4 V to 5.5 V
VOUT
0.9 V
TPS6286x
SW
L1
0.24 µH
VIN
C1
22 µF
C2
2x22 µF
VOS
EN
VSET/VID
or
VSET/PG
SCL
SDA
I2C
R1
AGND PGND
Figure 9-21. Smaller Application
9.2.2.1 Design Requirements
For this design, use the parameters listed in Table 9-5 as the input parameters. The design (Table 9-6) is
optimized for the smallest solution size.
Table 9-5. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
3.3 V
0.9 V
4 A
Output voltage
Maximum output current
Ambient temperature
25°C
Table 9-6. List of Components of Table 9-5
REFERENCE
DESCRIPTION
22 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J226ME11
0.24 µH, Power inductor, size 0806, DFE201612E-R24M
Depending on the startup output voltage, size 0402
MANUFACTURER(1)
C1, C2
L1
Murata
Murata
Std
R1
(1) See Third-party Products disclaimer.
9.2.2.2 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25°C, BOM = Table 9-6, unless otherwise noted.
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95
90
85
80
75
70
65
60
55
50
45
VIN = 3.3V, PSM
VIN = 4.2V, PSM
VIN = 5.0V, PSM
100m
1m
10m
Load (A)
100m
1
4
D011
VOUT = 0.9 V
Figure 9-22. Efficiency
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application. The power supply must avoid a fast ramp down.
The falling ramp speed must be slower than 10 mV/µs, if the input voltage drops below VUVLO
.
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11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device.
•
The input/output capacitors and the inductor must be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
•
The low side of the input and output capacitors must be connected properly to the PGND to avoid a GND
potential shift.
The sense traces connected to the VOS pin is a signal trace. Special care must be taken to avoid noise being
induced. Keep the trace away from SW.
Refer to Figure 11-1 for an example of component placement, routing, and thermal design.
11.2 Layout Example
GND
VOUT
VIN
Figure 11-1. Layout Example
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are improving the power dissipation capability of the
PCB design and introducing airflow in the system. For more details on how to use the thermal parameters, see
the Semiconductor and IC Package Thermal Metrics Application Report.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Trademarks
DCS-Control™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
YCG0015
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.28
0.23
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
0.7 TYP
SYMM
E
D
C
1.4
SYMM
D: Max=1.8mm, Min=1.76mm
E: Max=1.07mm, Min=1.03mm
TYP
B
A
0.35
TYP
2
3
0.225
0.185
15X
0.35 TYP
0.015
C A B
4224261/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
3
15X ( 0.2)
1
2
A
(0.35) TYP
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
( 0.2)
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224261/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
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EXAMPLE STENCIL DESIGN
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
15X ( 0.21)
1
2
3
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224261/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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10-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS628640AYCGR
TPS628640BYCGR
TPS628660AYCGR
TPS628660BYCGR
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YCG
15
15
15
15
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8640A
ACTIVE
ACTIVE
ACTIVE
YCG
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
8640B
8660A
8660B
YCG
Green (RoHS
& no Sb/Br)
YCG
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS628640AYCGR
TPS628640BYCGR
TPS628660AYCGR
TPS628660BYCGR
DSBGA
DSBGA
DSBGA
DSBGA
YCG
YCG
YCG
YCG
15
15
15
15
3000
3000
3000
3000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
1.22
1.22
1.22
1.22
1.95
1.95
1.95
1.95
0.6
0.6
0.6
0.6
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS628640AYCGR
TPS628640BYCGR
TPS628660AYCGR
TPS628660BYCGR
DSBGA
DSBGA
DSBGA
DSBGA
YCG
YCG
YCG
YCG
15
15
15
15
3000
3000
3000
3000
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YCG0015
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.28
0.23
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
0.7 TYP
SYMM
E
D
C
1.4
TYP
SYMM
D: Max = 1.77 mm, Min = 1.71 mm
E: Max = 1.04 mm, Min = 0.98 mm
B
A
0.35
TYP
2
3
0.225
0.185
C A B
15X
0.015
0.35 TYP
4224261/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
15X ( 0.2)
3
1
2
A
(0.35) TYP
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224261/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
15X ( 0.21)
1
2
3
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224261/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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汽车级 2.7V 至 6V 输入、6A、可堆叠同步降压转换器 | RXS | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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