TPS62A01ADRLR [TI]
采用 SOT-563 封装并具有强制 PWM 的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DRL | 6 | -40 to 125;
| 型号： | TPS62A01ADRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-563 封装并具有强制 PWM 的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DRL | 6 | -40 to 125 转换器 |
| 文件： | 总23页 (文件大小：1838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62A01, TPS62A01A, TPS62A02, TPS62A02A
ZHCSN71B –JULY 2022 –REVISED JULY 2022
TPS62A0x 和TPS62A0xA 采用SOT-563 封装的1A 和2A 高效同步降压转换器
1 特性
3 说明
• 输入电压范围为2.5V 至5.5V
• 可调输出电压范围：0.6V 至VIN
• 180mΩ和120mΩ低RDSON 开关(1A)
• 100mΩ和67mΩ低RDSON 开关(2A)
• 小于25µA 的静态电流
• 1% 反馈精度（0°C 至125°C）
• 100% 模式运行
TPS62A0x 系列器件是经过优化而具有高效率和紧凑
型解决方案尺寸的同步降压直流/直流转换器。这些器
件集成了可提供高达 2A 输出电流的开关。在中等负载
至重负载情况下，这些器件将以2.4MHz 开关频率在脉
宽调制 (PWM) 模式下运行。在轻载情况下，这些器件
自动进入节能模式 (PSM)，从而在整个负载电流范围
内保持高效率。关断时，电流消耗量也最低。该器件系
列的 TPS62A0xA 型号在整个负载电流范围内以强制
PWM 模式运行。
• 2.4MHz 开关频率
• 支持节电模式或PWM 选项
• 电源正常状态输出引脚
• 短路保护(HICCUP)
• 内部软启动
• 有源输出放电
• 热关断保护
• 采用1.60mm × 1.60mm SOT563 封装
• 与TLV62585 引脚对引脚兼容
TPS62A0x 器件通过一个外部电阻分压器提供可调节
输出电压。内部软启动电路可限制启动期间的浪涌电
流。内置的其他特性包括过流保护、热关断保护和电源
正常指示。这些器件采用SOT-563 封装。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS62A01
TPS62A01A
TPS62A02
TPS62A02A
2 应用
SOT-563
1.60mm × 1.60mm
• 机顶盒
• 电视应用
• IP 网络摄像头
• 多功能打印机
• 无线路由器、固态硬盘
• 电池供电的应用
• 通用负载点电源
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TPS62A0x
100
95
90
85
80
75
70
65
VIN
2.5V t 5.5V
VOUT
0.6V - VIN
1µH
VIN
SW
FB
GND
VIN
VPG
EN
PG
60
VOUT=3.3V
55
VOUT=1.8V
VOUT=1.2V
50
1m
10m
100m
1
2
典型应用
IOUT [A]
效率与输出电流间的关系曲线（电压为5VIN 时）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEG9
TPS62A01, TPS62A01A, TPS62A02, TPS62A02A
ZHCSN71B –JULY 2022 –REVISED JULY 2022
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Table of Contents
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................14
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Device Support....................................................... 15
12.2 Documentation Support.......................................... 15
12.3 接收文档更新通知................................................... 15
12.4 支持资源..................................................................15
12.5 Trademarks.............................................................15
12.6 Electrostatic Discharge Caution..............................15
12.7 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (March 2022) to Revision B (July 2022)
Page
• Added TPS62A02 and TPS62A02A................................................................................................................... 3
Changes from Revision * (December 2021) to Revision A (March 2022)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Comparison Table
Device Number
TPS62A01
Output Current
Operation Mode
PSM, PWM
FPWM
1 A
1 A
2 A
2 A
TPS62A01A
TPS62A02
PSM, PWM
FPWM
TPS62A02A
6 Pin Configuration and Functions
GND
SW
1
2
3
6
5
4
PG
FB
EN
VIN
Not to scale
图6-1. 6-Pin DRL SOT-563 Package (Top View)
表6-1. Pin Functions
Pin
Type(1)
Description
Name
NO.
Device enable logic input. Logic high enables the device. Logic low disables the device and turns it into
shutdown. Do not leave the pin floating.
EN
4
I
FB
5
1
I
Feedback pin for the internal control loop. Connect this pin to an external feedback divider.
Ground pin
GND
G
Power-good open-drain output pin. The pullup resistor cannot be connected to any voltage higher than
5.5 V. If unused, leave the pin open or connect to GND.
PG
6
O
Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the
output filter to this pin.
SW
VIN
2
3
O
I
Power supply voltage pin
(1) I = Input, O = Output, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–3.0
–0.3
–40
–55
MAX
UNIT
V
VIN, EN, PG
6
VIN + 0.3
10
SW, DC
Pin voltage(2)
V
SW, transient < 10 ns
V
FB
3
V
TJ
Operating junction temperature
Storage temperature
150
°C
°C
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
2.5
0.6
0
NOM
MAX
5.5
VIN
1
UNIT
V
VIN
Input supply voltage range
Output voltage range
Output current range
Output current range (1)
Effective inductance
VOUT
IOUT
IOUT
L
V
TPS62A01
TPS62A02
A
0
2
A
1.0
44
22
10
µH
µF
µF
µF
mA
°C
VOUT < 1.2 V
COUT
Output capacitance
1.2 V ≤VOUT < 1.8 V
V
OUT ≥1.8 V
IPG
TJ
Power Good input current capability
Operating junction temperature
0
1
-40
125
(1) Operating continuously at 2-A with input voltages < 3.3V or at ambient temperatures > 85 °C might result in thermal shutdown, per
EVM measurements.
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7.4 Thermal Information
TPS62A0x
THERMAL METRIC(1)
DRL
6 PINS
157.3
92.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
45.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.0
45.0
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40°C to +125°C, VIN = 2.5 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
TPS62A01; Non-switching, VEN = High, VFB
= 610 mV
IQ(VIN)
VIN quiescent current
20
µA
TPS62A02; Non-switching, VEN = High, VFB
= 610 mV
IQ(VIN)
VIN quiescent current
23
µA
µA
ISD(VIN)
UVLO
VIN shutdown supply current
VEN = Low
0.01
2
VUVLO(R)
VUVLO(F)
ENABLE
VEN(R)
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN rising
VIN falling
2.3
2.2
2.4
2.3
2.5
2.4
V
V
EN voltage rising threshold
EN voltage falling threshold
EN Input leakage current
EN rising, enable switching
EN falling, disable switching
VEN = 5 V
1.2
V
V
VEN(F)
0.4
VEN(LKG)
100
nA
REFERENCE VOLTAGE
VFB
FB voltage
TJ = 0°C to 125°C, PWM mode
PWM mode
594
591
600
600
606
609
100
mV
mV
nA
VFB
FB voltage
IFB(LKG)
FB input leakage current
VFB = 0.6 V
SWITCHING FREQUENCY
fSW(FCCM)
Switching frequency, FPWM operation
VIN = 5 V, VOUT = 1.8 V
2400
kHz
ms
STARTUP
Internal fixed soft-start time
From EN = High to VFB = 0.56 V
1
POWER STAGE
RDSON(HS)
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
TPS62A01, VIN = 5V
TPS62A01, VIN = 5V
TPS62A02, VIN = 5V
TPS62A02, VIN = 5V
180
120
100
67
mΩ
mΩ
mΩ
mΩ
RDSON(LS)
RDSON(HS)
RDSON(LS)
OVERCURRENT PROTECTION
IHS(OC)
High-side peak current limit
TPS62A01
TPS62A01
TPS62A02
TPS62A02
1.3
2.7
1.8
1.8
3.4
4.2
0.4
A
A
A
A
A
ILS(OC)
Low-side valley current limit
High-side peak current limit
Low-side valley current limit
Min peak inductor current in PSM
IHS(OC)
ILS(OC)
ILPEAK(min)
POWER GOOD
VPGTH
Power-good threshold
Power-good threshold
PG delay falling
PG low, FB falling
PG high, FB rising
93.5%
96%
35
VPGTH
µs
µs
PG delay rising
10
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7.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C, VIN = 2.5 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
nA
PG pin Leakage current when open drain
output is high
IPG(LKG)
VPG = 5 V
100
PG pin output low-level voltage
IPG = 1 mA
400
mV
OUTPUT DISCHARGE
Output discharge current on SW pin
Output discharge current on SW pin
TPS62A01; VIN = 3 V, VOUT = 2.0 V
TPS62A02; VIN = 3 V, VOUT = 2.0 V
60
76
mA
mA
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold
Thermal shutdown hysteresis
Temperature rising
170
20
°C
°C
TJ(HYS)
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7.6 Typical Characteristics
28
26
24
22
20
18
16
14
12
28
26
24
22
20
18
16
14
12
TJ=-40èC
TJ=30èC
TJ=85èC
TJ=125èC
TJ=-40èC
TJ=30èC
TJ=85èC
TJ=125èC
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
图7-1. Quiescent Current vs Input Voltage
图7-2. Quiescent Current vs Input Voltage
(TPS62A01)
(TPS62A02)
0.25
VIN = 2.5V
VIN = 3.6V
VIN = 5.5V
0.2
0.15
0.1
0.05
0
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature [°C]
图7-3. Shutdown Current vs Junction Temperature
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8 Detailed Description
8.1 Overview
The TPS62A0x is a high-efficiency synchronous step-down converter. The device operates with an adaptive off
time with a peak current control scheme. The device operates typically at 2.4-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET, making the switching frequency relatively constant regardless of the
variation of the input voltage, output voltage, and load current.
8.2 Functional Block Diagram
VIN
VI
Device Control
& Logic
HS Limit
Peak Current Detect
EN
UVLO
Soft Start
HICCUP protection
Thermal Shutdown
Modulator &
Power Control
SW
Gate
Power Save Mode
& PWM
Driver
Operation
VFB
œ
VFB
+
100% Mode
VREF
LS Limit
Zero Current Detect
Active
Discharge
EN
PG
VI
TOFF timer
+
VFB
VPG
VO
œ
GND
图8-1. Functional Block Diagram
8.3 Feature Description
8.3.1 Power Save Mode
The device automatically enters power save mode to improve efficiency at light load when the inductor current
becomes discontinuous. In power save mode, the converter reduces the switching frequency and minimizes
current consumption. In power save mode, the output voltage rises slightly above the nominal output voltage.
This effect is minimized by increasing the output capacitor or adding a feedforward capacitor.
8.3.2 100% Duty Cycle Low Dropout Operation
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
(1)
where
• RDS(ON) = High-side FET on-resistance
• RL = Inductor ohmic resistance (DCR)
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8.3.3 Soft Start
After enabling the device, internal soft-start circuitry ramps up the output voltage, which reaches the nominal
output voltage during start-up time, avoiding excessive inrush current and creating a smooth voltage rise slope. It
also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.
The TPS62A0x is able to start into a prebiased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
8.3.4 Switch Current Limit and Short Circuit Protection (HICCUP)
The switch current limit prevents the device from high inductor current and drawing excessive current from the
battery or input rail. Due to internal propagation delay, the AC peak current can exceed the static current limit
during that time. Excessive current can occur with a shorted or saturated inductor, an overload or shorted output
circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is turned off and the
low-side MOSFET is turned on to ramp down the inductor current with an adaptive off time.
When this switch current limit is triggered 32 times, the device stops switching to protect the output. The device
then automatically starts a new start-up after a typical delay time of 100 µs has passed. This is named HICCUP
short circuit protection. The device repeats this mode until the high load condition disappears. HICCUP
protection is also enabled during the start-up.
8.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO
.
8.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Functional Modes
8.4.1 Enable and Disable
The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the
device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and should not be left floating.
8.4.2 Power Good
The TPS62A0x has a built-in power-good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is
an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.
PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must
remain present for the PG pin to stay low. If not used, the power-good can be tie to GND or left open. The PG
indicator has a de-glitch to avoid the signal indicating glitches or transient responses from the loop.
表8-1. Power Good indicator Functional Table
Logic Signals
PG Status
VI
EN Pin
Thermal Shutdown
VO
VO on target
High Impedance
LOW
NO
VO < target
HIGH
VI > UVLO
VI < 1.8 V
YES
LOW
YES
x
x
x
LOW
UVLO < VI < 1.8 V
x
x
x
LOW
Undefined
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
TPS62A01
VIN
2.5V t 5.5V
L1
1µH
VOUT
1.8V / 1A
VIN
SW
FB
R1
200kQ
C3*
GND
VIN
R4
499kQ
R2
100kQ
EN
PG
VPG
图9-1. TPS62A01 Typical Application Circuit
TPS62A02
VIN
2.5V – 5.5V
L1
1µH
VOUT
1.8V / 2A
VIN
SW
FB
R1
200k
C3*
GND
C1
4.7
C2
22 F
F
VIN
R4
499k
R2
100k
EN
PG
VPG
图9-2. TPS62A02 Typical Application Circuit
*C3 is optional
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as the input parameters
表9-1. Design Parameters
Design Parameter
Input voltage
Example Value
2.5 V to 5.5 V
Output voltage
1.8 V
Maximum output current
1.0 or 2.0 A
表9-2 lists the components used for the example.
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表9-2. List of Components
Reference
Description
Manufacturer(1)
4.7 µF, Ceramic Capacitor, 10 V, X7R, size
0805, GRM21BR71A475KA73L
C1
Murata
22 µF, Ceramic Capacitor, 10 V, X7R, size
0805, GRM21BZ71A226KE15L
C2
L1
Murata
1 µH, Power Inductor, DFE252012F-1R0M
(1A) / XGL3520-102MEC (2A)
Murata / Coilcraft
R1, R2
C3
Chip resistor, 1%, size 0603
Optional, 120 pF if it is needed
Std.
Std.
(1) See the Third-Party Products Disclaimer.
9.2.2 Detailed Design Procedure
9.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to 方程式2.
V
V
OUT
OUT
R1 = R2 ×
− 1 = R2 ×
− 1
0.6 V
(2)
V
FB
R2 must not be higher than 100 kΩto provide acceptable noise sensitivity.
9.2.2.2 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, 表 9-3 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Further combinations should be checked for each individual application.
表9-3. Matrix of Output Capacitor and Inductor Combinations
COUT [µF](2)
VOUT [V]
L [µH](1)
4.7
10
22
2 × 22
++(3)
+
100
1
1
1
0.6 ≤VOUT < 1.2
1.2 ≤VOUT < 1.8
1.8 ≤VOUT
++(3)
++(3)
(4)
+
+
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and –30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and –50%.
(3) This LC combination is the standard value and recommended for most applications.
(4) The minimum COUT of 10 µF does not support an additional feedforward capacitor.
A 0.47uH inductor may also be used with the same recommended output capacitors for the TPS62A02x. In case
a lower output ripple is desired, higher output capacitance may help reduce the ripple.
9.2.2.3 Input and Output Capacitor Selection
The architecture of the TPS62A0x allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low-ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, a 4.7-μF input
capacitor is sufficient; a larger value reduces input voltage ripple.
The TPS62A0x is designed to operate with an output capacitor of 10 μF to 47 μF, depending on the selected
output voltage, as outlined in 表9-3.
A feedforward capacitor reduces the output ripple in PSM and improves the load transient response. A 120-pF
capacitor is good for the 1.8-V output typical application.
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9.2.3 Application Curves
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
V
V
V
IN = 2.5V
IN = 3.3V
IN = 5.0V
V
V
V
IN = 2.5V
IN = 3.3V
IN = 5.0V
55
50
1m
10m
100m
500m
1
1m
10m
100m
500m
1
I
OUT [A]
I
OUT [A]
图9-3. 0.6-V Output Efficiency (TPS62A01)
图9-4. 1.2-V Output Efficiency (TPS62A01)
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
V
V
V
IN = 2.5V
IN = 3.3V
IN = 5.0V
V
V
V
IN = 2.5V
IN = 3.3V
IN = 5.0V
55
55
50
1m
50
1m
10m
100m
500m
1
10m
100m
500m
1
IOUT [A]
IOUT [A]
图9-5. 1.8-V Output Efficiency (TPS62A01)
图9-6. 1.8-V Output Efficiency (TPS62A01A)
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TPS62A01, TPS62A01A, TPS62A02, TPS62A02A
www.ti.com.cn
ZHCSN71B –JULY 2022 –REVISED JULY 2022
100
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
55
50
VIN=2.5V
VIN=3.3V
VIN=5.0V
VIN=2.5V
VIN=3.3V
VIN=5.0V
50
1m
10m
100m
1
2
1m
10m
100m
1
2
IOUT [A]
IOUT [A]
图9-7. 0.6-V Output Efficiency (TPS62A02)
图9-8. 1.2-V Output Efficiency (TPS62A02)
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
VIN=2.5V
VIN=2.5V
55
50
55
50
VIN=3.3V
VIN=5.0V
VIN=3.3V
VIN=5.0V
1m
10m
100m
1
2
1m
10m
100m
1
2
IOUT [A]
IOUT [A]
图9-9. 1.8-V Output Efficiency (TPS62A02)
图9-10. 1.8-V Output Efficiency (TPS62A02A)
CH1: 1.8V DC-offset
CH1: 1.8V DC-offset
IOUT = 100 mA
IOUT = 500 mA
图9-12. Power Save Mode Operation
图9-11. PWM Operation
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ZHCSN71B –JULY 2022 –REVISED JULY 2022
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CH1: 1.8V DC-offset
IOUT = 1 A
Load step: 0.3 A to 1 A
图9-13. Start-Up with Load
图9-14. Load Transient
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TPS62A01x
device.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the GND pin to avoid a ground
potential shift.
• The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
• A common ground should be used. GND layers might be used for shielding.
See 图11-1 for the recommended PCB layout.
11.2 Layout Example
图11-1. TPS62A0x PCB Layout Recommendation
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TPS62A01, TPS62A01A, TPS62A02, TPS62A02A
www.ti.com.cn
ZHCSN71B –JULY 2022 –REVISED JULY 2022
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
12.2.1 Related Documentation
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62A01ADRLR
TPS62A01DRLR
TPS62A02ADRLR
TPS62A02DRLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
6
6
6
6
4000 RoHS & Green
4000 RoHS & Green
4000 RoHS & Green
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1J8
1J7
1JM
1JL
Samples
Samples
Samples
Samples
Call TI | SN
Call TI | SN
Call TI | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62A01ADRLR
TPS62A01DRLR
TPS62A02ADRLR
TPS62A02DRLR
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
6
6
6
6
4000
4000
4000
4000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.0
2.0
2.0
2.0
1.8
1.8
1.8
1.8
0.75
0.75
0.75
0.75
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62A01ADRLR
TPS62A01DRLR
TPS62A02ADRLR
TPS62A02DRLR
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
6
6
6
6
4000
4000
4000
4000
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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