TPS65014_15_技术文档

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

POWER AND BATTERY MANAGEMENT IC

FOR LI-ION POWERED SYSTEMS

FEATURES

DESCRIPTION

•

Linear Charger Management for Single Li-Ion

or Li-Polymer Cells

The TPS65014 is an integrated power and battery

management IC for applications powered by one

Li-ion or Li-polymer cell and which require multiple

power rails. The TPS65014 provides two highly

efficient, step-down converters targeted at providing

the core voltage and peripheral, I/O rails in a

processor-based system. Both step-down converters

enter a low power mode at light load for maximum

efficiency across the widest possible range of load

currents. The LOW_PWR pin allows the core con-

verter to lower its output voltage when the application

processor goes into deep sleep. The TPS65014 also

integrates two 200-mA LDO voltage regulators, which

are enabled via the serial interface. Each LDO

operates with an input voltage range between 1.8 V

and 6.5 V, allowing them to be supplied from one of

the step-down converters or directly from the battery.

•

Dual Input Ports for Charging From USB or

From Wall Plug, Handles 100-mA / 500-mA

USB Requirements

•

Charge Current Programmable via External

Resistor

1-A, 95% Efficient Step-Down Converter for

I/O and Peripheral Components (VMAIN)

400-mA, 90% Efficient Step-Down Converter

for Processor Core (VCORE)

2x 200-mA LDOs for I/O and Peripheral

Components, LDO Enable via Bus

Serial Interface Compatible With I²C, Supports

100-kHz, 400-kHz Operation

The TPS65014 also has a highly integrated and

flexible Li-Ion linear charger and system power man-

agement. It offers integrated USB-port and

ac-adapter supply management with autonomous

power-source selection, power FET and current

sensor, high accuracy current and voltage regulation,

charge status, and charge termination.

LOW_PWR Pin to Lower or Disable Processor

Core Supply Voltage in Deep Sleep Mode

•

70-µA Quiescent Current

1% Reference Voltage

Thermal Shutdown Protection

APPLICATIONS

The TPS65014 charger automatically selects the

USB-port or the ac-adapter as the power source for

the system. In the USB configuration, the host can

increase the charge current from the default value of

maximum 100 mA to 500 mA via the interface. In the

ac-adapter configuration, an external resistor sets the

maximum value of charge current.

•

All Single Li-Ion Cell-Operated Products

Requiring Multiple Supplies Including:

– PDA

– Cellular/Smart Phone

– Internet Audio Player

– Digital Still Camera

Digital Radio Player

Split Supply DSP and µP Solutions

The battery is charged in three phases: conditioning,

constant current, and constant voltage. Charge is

normally terminated based on minimum current. An

internal charge timer provides a safety backup for

charge termination. The TPS65014 automatically

restarts the charge if the battery voltage falls below

an internal threshold. The charger automatically en-

ters sleep mode when both supplies are removed.

•

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

I²C is a trademark of Phillips.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The serial interface can be used for dynamic voltage scaling, for collecting information on and controlling the

battery charger status, for optionally controlling 2 LED driver outputs, a vibrator driver, masking interrupts, or for

disabling/enabling and setting the LDO output voltages. The interface is compatible with the fast/standard mode

I²C™ specification allowing transfers at up to 400 kHz.

ORDERING INFORMATION

T_A

PACKAGE

PART NUMBER⁽¹⁾⁽²⁾

-40°C to 85°C

7 mm × 7 mm, 48-pin QFN

TPS65014RGZ

(1) The RGZ package is available in tape and reel. Add R suffix (TPS65014RGZR) to order quantities of

2500 parts per reel.

(2) Add T suffix (TPS65014RGZT) to order quantities of 250 parts per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

UNIT

20 V

Input voltage on VAC pin with respect to AGND

Input voltage range on all other pins except AGND/PGND pins with respect to AGND

HBM and CDM capabilities at pins VIB, PG, and LED2

Current at AC, VBAT, VINMAIN, L1, PGND1

Peak current at all other pins

-0.3 V to 7 V

1 kV

1800 mA

1000 mA

Continuous power dissipation

See Dissipation Rating Table

-40°C to 85°C

125°C

Operating free-air temperature, T_A

Maximum junction temperature, T_J

Storage temperature, T_stg

-65°C to 150°C

260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE DISSIPATION RATINGS⁽¹⁾

AMBIENT

TEMPERATURE

MAX POWER DISSIPATION

DERATING FACTOR

ABOVE T_A= 55°C

FOR T_j= 125°C⁽²⁾

25°C

55°C

3 W

30 mW/°C

2.1 W

(1) The TPS65014 is housed in a 48-pin QFN package with exposed leadframe on the underside. This

7 mm × 7 mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted

on a JEDEC high-k board.

(2) Consideration needs to be given to the maximum charge current when the assembled application

board exhibits a thermal impedance which differs significantly from the JEDEC high-k board.

2

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

RECOMMENDED OPERATING CONDITIONS

MIN

4.5

4.4

2.5

1.8

-40

NOM

MAX

6.5

UNIT

V

V_(AC)

Supply voltage from ac adapter

Supply voltage from USB

V_(USB)

5.25

4.2

V

V_(BAT)

Voltage at charger output/battery

Input voltage range step-down converters

Input voltage range for LDOs

Operating ambient temperature

Operating junction temperature

V

V_I(MAIN),V_I(CORE),V_CC

6.0

V

V_I(LDO1), V_I(LDO2)

6.5

V

T_A

T_J

85

°C

125

Resistor from V_I(main),V_I(core)to V_CCused for

filtering, C_I(VCC)= 1 µF

R_(CC)

10

100

Ω

ELECTRICAL CHARACTERISTICS

V_I(MAIN)= V_I(CORE)= V_CC= V_I(LDO1)= V_I(LDO2)= 3.6 V, T_A= -40°C to 85°C, typical values are at T_A= 25°C battery charger

specifications are valid in the range 0°C < T_A< 85°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL SIGNALS: LOW_PWR, SCLK, SDAT (Input)

(1)

V_IH

V_IL

I_IB

High-level input voltage

Low-level input voltage

Input bias current

I_IH= 20 µA

I_IL= 10 µA

2

0

V_CC

0.8

1.0

V

0.01

µA

CONTROL SIGNALS: PB_ONOFF, HOT_RESET, BATT_COVER

V_IH

High-level input voltage

I_IH= 20 µA⁽¹⁾

I_IL= 10 µA

0.8 V_CC

0

6

V

V_IL

Low-level input voltage

0.4

R_{(pb_onoff)}

Pulldown resistor at PB_ONOFF

1000

kΩ

Pullup resistor at HOT_RESET,

connected to VCC

R_{(hot_reset)}

kΩ

R_{(batt_cover)}

t_(glitch)

Pulldown resistor at BATT_COVER

De-glitch time at all 3 pins

2000

56

kΩ

38

77

ms

Delay after t_(glitch)(PWRFAIL goes low)

before supplies are disabled when

BATT_COVER goes low.

t_{(batt_cover)}

1.68

2.4

3.2

ms

CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON, INT, SDAT (output)

V_OH

High-level output voltage

6

V

V_OL

Low-level output voltage

I_IL= 10 mA

0

100

80

0.3

t_{d(mpu_nreset)}

t_d(nrespwron)

Duration of low pulse at MPU_RESET

µs

Duration of low pulse at RESPWRON

after VMAIN is in regulation

TPOR = 0

TPOR = 1

100

120

ms

800

1000

1200

Time between UVLO going active

(PWRFAIL going low) and supplies be-

ing disabled

t_d(uvlo)

1.68

2.4

3.2

Time between chip overtemperature

condition being recognized (PWRFAIL

going low) and supplies being disabled

t_d(overtemp)

ms

SUPPLY PIN: VCC

I_(Q)

Operating quiescent current

Shutdown supply current

V_I= 3.6 V, current into Main + Core + V_CC

70

25

µA

V_I= 3.6 V, BATT_COVER = GND,

Current into Main + Core + V_CC

I_O(SD)

15

VMAIN STEP-DOWN CONVERTER

V_I

Input voltage range

2.5

6.0

V

I_O

Maximum output current

Shutdown supply current

P-channel MOSFET on-resistance

1000

mA

µA

I_O(SD)

r_DS(on)

BATT_COVER = GND

V_I(MAIN)= V_GS= 3.6 V

0.1

1

110

210

mΩ

(1) If the input voltage is higher than V_CC, an additional input current, limited by an internal 10-kΩ resister, flows.

3

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

V_I(MAIN)= V_I(CORE)= V_CC= V_I(LDO1)= V_I(LDO2)= 3.6 V, T_A= -40°C to 85°C, typical values are at T_A= 25°C battery charger

specifications are valid in the range 0°C < T_A< 85°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1

UNIT

µA

I_lkg(p)

r_DS(on)

I_lkg(N)

I_L

P-channel leakage current

N-channel MOSFET on-resistance

N-channel leakage current

P-channel current limit

V_(DS)= 6 V

V_I(MAIN)= V_GS= 3.6 V

V_(DS)= 6 V

110

200

1

mΩ

µA

2.5 V< V_I(MAIN)< 6 V

1.4

1

1.75

1.25

2.1

1.5

3%

A

f_S

Oscillator frequency

MHz

V_I(MAIN)= 2.7 V to 6 V; I_O= 0 mA

0%

2.5 V

V_I(MAIN)= 2.7 V to 6 V;

0 mA ≤ I_O≤ 1000 mA

3%

0%

3%

0%

3%

0%

3%

V_I(MAIN)= 2.95 V to 6 V; I_O= 0 mA

2.75 V

3.0 V

3.3 V

V_I(MAIN)= 2.95 V to 6 V;

0 mA ≤ I_O≤ 1000 mA

V_O(MAIN)

Fixed output voltage

V_I(MAIN)= 3.2 V to 6 V; I_O= 0 mA

V_I(MAIN)= 3.2 V to 6 V;

0 mA ≤ I_O≤ 1000 mA

V_I(MAIN)= 3.5 V to 6 V; I_O= 0 mA

V_I(MAIN)= 3.5 V to 6 V;

0 mA ≤ I_O≤ 1000 mA

Line regulation

V_I(MAIN)= V_O(MAIN)+ 0.5 V (min. 2.5 V) to 6 V,

I_O= 10 mA

0.5

%/V

Load regulation

I_O= 10 mA to 1000 mA

0.12

400

%/A

R_(VMAIN)

VMAIN discharge resistance

Ω

VCORE STEP-DOWN CONVERTER

V_I

Input voltage range

2.5

6.0

V

mA

µA

I_O

Maximum output current

Shutdown supply current

400

I_O(SD)

r_DS(on)

I_lkg(p)

r_DS(on)

I_lkg(N)

I_L

BATT_COVER = GND

V_I(CORE)= V_GS= 3.6 V

V_DS= 6 V

0.1

275

0.1

1

530

1

P-channel MOSFET on-resistance

P-channel leakage current

N-channel MOSFET on-resistance

N-channel leakage current

P-channel current limit

mΩ

µA

V_I(CORE)= V_GS= 3.6 V

V_DS= 6 V

275

0.1

500

1

mΩ

µA

2.5 V < V_I(CORE)< 6 V

600

1

700

1.25

900

1.5

mA

MHz

f_S

Oscillator frequency

4

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

V_I(MAIN)= V_I(CORE)= V_CC= V_I(LDO1)= V_I(LDO2)= 3.6 V, T_A= -40°C to 85°C, typical values are at T_A= 25°C battery charger

specifications are valid in the range 0°C < T_A< 85°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_I(CORE)= 2.5 V to 6 V;

I_O= 0 mA, C_O= 22 µF

0%

3%

0.85 V

1.0 V

1.1 V

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA, C_O= 22 µF

3%

0%

3%

0%

3%

V_I(CORE)= 2.5 V to 6 V;

I_O= 0 mA, C_O= 22 µF

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA, C_O= 22 µF

V_I(CORE)= 2.5 V to 6 V;

I_O= 0 mA, C_O= 22 µF

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA, C_O= 22 µF

V_I(CORE)= 2.5 V to 0 V; I_O= 0 mA

V_I(CORE)= 2.5 V to 6 V; 0 mA ≤ I_O≤ 400 mA

V_I(CORE)= 2.5 V to 6 V; I_O= 0 mA

0%

3%

0%

3%

1.2 V

1.3 V

V_O(CORE)

Fixed output voltage

V_I(CORE)= 2.5 V to 6 V;

3%

0%

3%

0%

3%

0%

3%

0 mA ≤ I_O≤ 400 mA

V_I(CORE)= 2.5 V to 6 V; I_O= 0 mA

1.4 V

1.5 V

1.8 V

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA

V_I(CORE)= 2.5 V to 6 V; I_O= 0 mA

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA

V_I(CORE)= 2.5 V to 6 V; I_O= 0 mA

V_I(CORE)= 2.5 V to 6 V;

0 mA ≤ I_O≤ 400 mA

V_I(CORE)= V_O(MAIN)+ 0.5 V

(min. 2.5 V) to 6 V, I_O= 10 mA

Line regulation

1

%/V

Load regulation

I_O= 10 mA to 400 mA

0.002

400

%/mA

R_(VCORE)

VCORE discharge resistance

Ω

VLDO1 and VLDO2 LOW-DROPOUT REGULATORS

LD01

1.8

0.9

485

1.8

200

30

6.5

V_CC

V_I

Input voltage range

V

LD02

V_O

V_ref

V_O

LDO1 output voltage range

Reference voltage

VINLDO1

515

V

mV

V

500

LDO2 output voltage range

3.3

Full-power mode

I_O

Maximum output current

mA

Low-power mode

I_(SC)

LDO1 and LDO2 short-circuit current

limit

VLDO1 = GND, VLDO2 = GND

650

Dropout voltage

Total accuracy

I_O= 200 mA, VINLDO1,2 = 1.8 V

300

mV

±3%

VINLDO1,2 = VLDO1,2 + 0.5 V

(min. 2.5 V) to 6.5 V, I_O= 10 mA

Line regulation

Load regulation

0.75

%/V

I_O= 10 mA to 200 mA

Load change from 10% to 90%

Low-power mode

0.011

%/mA

0.1

Regulation time

ms

0.1

16

I_(QFP)

LDO quiescent current (each LDO)

LDO shutdown current (each LDO)

Leakage current feedback

Full-power mode

30

18

1

µA

I_(QLPM)

I_O(SD)

I_lkg(FB)

Low-power mode

12

0.1

0.01

0.1

5

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

ELECTRICAL CHARACTERISTICS

Battery Charger, V_O(REG)+ V_(DO-MAX)≤ V_(CHG)= V_(AC)or V_(USB), I_(TERM)< I_O≤ 1 A, 0°C < T_A< 85°C

PARAMETER

Input voltage range

Supply current

TEST CONDITIONS

MIN

4.5

TYP

MAX

UNIT

V

V_(AC)

6.5

5.25

2

V_(USB)

I_CC(VCHG)

4.35

V

V_(CHG)> V_(CHG)min

Sum of currents into VBAT pin,

1.2

2

mA

I_CC(SLP)

Sleep current

V_(CHG)< V_(SLP-ENTRY)

,

5

µA

0°C≤ T_J≤ 85°C

Current into USB pin

Current into AC pin

45

I_CC(STBY)

Standby current

200

400

VOLTAGE REGULATOR

V_O

Output voltage

V_(CHG)min ≥ 4.5 V

4.15

4.20

500

4.25

800

V

V_O(REG)+ V_(DO-MAX)≤ V_(CHG)

I_O(OUT)= 1 A

,

Dropout voltage (V_(AC)- VBAT)

Dropout voltage (V_(USB)- VBAT)

V_O(REG)+ V_(DO-MAX)≤ V_(CHG)

I_O(OUT)= 0.5 A

,

V_DO

300

100

500

150

mV

V_O(REG)+ V_(DO-MAX)≤ V_(CHG)

I_O(OUT)= 0.1 A

,

CURRENT REGULATION

Output current range for ac operation⁽¹⁾

V

_CHG≥ 4.5V, V_I(OUT)> V_(LOWV)

,

I_O(AC)

100

1000

2.55

mA

V_(AC)- V_I(BAT)> V_(DO-MAX)

Output current set voltage for ac operation

at ISET pin. 100% output current I²C regis-

ter CHGCONFIG<4:3> = 11

2.45

2.50

75% output current I²C register

CHGCONFIG<4:3> = 10

1.83

1.23

0.76

1.91

1.31

0.81

1.99

1.39

0.86

V

_min≥ 4.5V, V_I(BAT)> V_(LOWV), V_(AC)-

V_(SET)

V

V_I(BAT)> V_(DO-MAX)

50% output current I²C register

CHGCONFIG<4:3> = 01

32% output current I²C register

CHGCONFIG<4:3> = 00

100 mA < I_O< 1000 mA

10 mA < I_O< 100 mA

310

300

330

340

350

380

KSET

Output current set factor for ac operation

V_(CHG)min ≥ 4.35 V, V_I(BAT)> V_(LOWV)

,

V_(USB)- V_I(BAT)> V_(DO-MAX)

,

80

100

I²C register CHGCONFIG<2> = 0

I_O(USB)

Output current range for USB operation

Resistor range at ISET pin

mA

V_(CHG)min ≥ 4.5 V, V_I(BAT)> V_(LOWV)

,

V_USB- V_I(BAT)> V_(DO-MAX)

,

400

825

500

I²C register CHGCONFIG<2> = 1

R_(ISET)

8250

Ω

PRECHARGE CURRENT REGULATION, SHORT-CIRCUIT CURRENT, AND BATTERY DETECTION CURRENT

Precharge to fast-charge transition

V_(LOWV)

threshold,

V_(CHG)min ≥ 4.5V

2.8

3

3.2

V

voltage on VBAT pin.

V_(CHG)min ≥ 4.5 V, V_I(OUT)de-

creasing below threshold; 100-ns fall

time, 10-mV overdrive

De-glitch time

8.8

10

23

60

ms

(2)

I_(PRECHG)

Precharge current

0 ≤ V_I(OUT)< V_(LOWV), t < t_(PRECHG)

100

mA

µA

I_(DETECT)

Battery detection current

Voltage at ISET pin

200

255

V_(SET-PRECHG)

0 ≤ V_I(OUT)< V_(LOWV), t < t_(PRECHG)

240

270

mV

KSET

V

(SET)

(ISET)

KSET

I

+

O(AC)

R

(1)

V

(SET_PRECHG)

I

+

(PRECHG)

R

(ISET)

(2)

6

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHARGE TAPER AND TERMINATION DETECTION

(3)

I_(TAPER)

Taper current detect range

V_I(OUT)> V_(RCH), t < t_(TAPER)

10

100

265

mA

mV

Voltage at ISET pin for charge TAPER

detection

V_{(SET_TAPER)}

235

250

18

Voltage at ISET pin for charger termination

detection⁽⁴⁾

V_{(SET_TERM)}

V_I(OUT)> V_(RCH)

11

25

60

mV

ms

V_(CHG)min ≥ 4.5V, charging current

increasing or decreasing above and

below; 100-ns fall time, 10-mV

overdrive

De-glitch time for I_(TAPER)

De-glitch time for I_(TERM)

8.8

23

V_(CHG)min ≥ 4.5 V, charging current

decreasing below;100-ns fall time,

10-mV overdrive

8.8

60

ms

TEMPERATURE COMPARATOR

V_(LTF)

V_(HTF)

I_(TS)

Low (cold) temperature threshold

2.475

0.485

95

2.50

0.5

102

23

2.525

0.515

110

V

High (hot) temperature threshold

TS current source

µA

ms

De-glitch time for temperature fault

8.8

60

BATTERY RECHARGE THRESHOLD

V_O(REG)

-0.115

V_O(REG)

-0.085

V_(RCH)

Recharge threshold

De-glitch time

V_(CHG)min ≥ 4.5 V

V_O(REG)-0.1

V

V_(CHG)min ≥ 4.5 V, V_I(OUT)decreasing

below threshold; 100-ns fall time,

10-mV overdrive

8.8

23

60

ms

TIMERS

t_(PRECHG)

t_(TAPER)

t_(CHG)

Precharge timer

Taper timer

V_(CHG)min ≥ 4.5 V

1500

1800

2160

s

Charge timer

15000

18000

21600

SLEEP AND STANDBY

V_(CHG)

V_I(OUT)

+150 mV

≤

Sleep-mode entry threshold, PG output =

high

V_(SLP-ENTRY)

2.3 V ≤ V_I(OUT)≤ V_O(REG)

V

V_(CHG)

V_I(OUT)

≥

+

V_{(SLP_EXIT)}

Sleep-mode exit threshold,PG output = low 2.3 V ≤ V_I(OUT)≤ V_O(REG)

250 mV

AC or USB decreasing below

De-glitch time for sleep mode entry and exit threshold; 100-ns fall time, 10-mV

overdrive

8.8

23

5

60

ms

Delay between valid USB voltage being

applied and start of charging process from

USB

t_{(USB_DEL)}

CHARGER POWER-ON-RESET, UVLO, AND V_(IN)RAMP RATE

V_(CHGUVLO)

Charger undervoltage lockout

Hysteresis

V_(CHG)decreasing

2.27

6.5

2.5

27

2.75

V

mV

V

V_(CHGOVLO)

Charger overvoltage lockout

CHARGER OVERTEMPERATURE SUSPEND

Temperature at which charger suspends

T_(suspend)

145

20

°C

operation

T_(hyst)

Hysteresis of suspend threshold

LOGIC SIGNALS DEFMAIN, DEFCORE, PS_SEQ, IFLSB

V_IH

V_IL

I_IB

High-level input voltage

Low-level input voltage

Input bias current

I_IH= 20 µA

I_IL= 10 µA

V_CC-0.5

0

V_CC

0.4

1.0

V

0.01

µA

KSET

V

(SET_TAPER)

I

+

(TAPER)

R

(ISET)

(3)

KSET

V

(SET_TERM)

I

+

(TERM)

R

(ISET)

(4)

7

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

PARAMETER

LOGIC SIGNALS GPIO1-4

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OL= 1 mA, configured as an

open-drain output

V_OL

Low-level output voltage

0.3

6

V

V_OH

V_IL

High-level output voltage

Low -level input voltage

High-level input voltage

Input leakage current

Internal NMOS

Configured as an open-drain output

V

0

2

0.8

(5)

V_IH

I_I

V_CC

V

1

µA

Ω

r_DS(on)

V_OL= 0.3 V

I_OL= 20 mA

150

LOGIC SIGNALS PG, LED2

V_OL

V_OH

Low-level output voltage

0.5

6

V

High-level output voltage

V_(BAT)+ xx

mV

V_(PG)

PG threshold voltage USB and AC

V

VIBRATOR DRIVER VIB

V_OL

V_OH

Low-level output voltage

High-level output voltage

I_OL= 100 mA

0.3

0.5

6

V

THERMAL SHUTDOWN

T_(SD)

Thermal shutdown

Increasing junction temperature

160

°C

UNDERVOLTAGE LOCKOUT

V_(UVLO)2.5 V

V_(UVLO)2.75 V

V_(UVLO)3.0 V

V_(UVLO)3.25 V

-3%

350

3%

450

Undervoltage lockout

threshold.

The default value for

UVLO is 2.75 V

Filter resistor = 10R in series

with V_CC,V_CCdecreasing

V_(UVLO)

V_{(UVLO_HYST)}

UVLO comparator hysteresis

V_CCrising

400

mV

POWER GOOD

VMAIN, VCORE, VLDO1, VLDO2

decreasing

-12%

-7%

-10%

-5%

-8%

-3%

VMAIN, VCORE, VLDO1, VLDO2

increasing

(5) If the input voltage is higher than V_CCan additional current, limited by an internal 10-kΩ resistor, flows.

8

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

SERIAL INTERFACE TIMING REQUIREMENTS

MIN MAX UNIT

Clock frequency, f_MAX

400

kHz

ns

Clock high time, t_wH(HIGH)

600

Clock low time, t_wL(LOW)

1300

DATA and CLK rise time, t_R

300

DATA and CLK fall time, t_F

Hold time (repeated) START condition (after this period the first clock pulse is generated), t_h(STA)

Setup time for repeated START condition, t_h(DATA)

Data input hold time, t_h(DATA)

600

0

Data input setup time, t_su(DATA)

100

600

1300

STOP condition setup time, t_su(STO)

Bus free time, t_(BUF)

PIN ASSIGNMENTS

RGZ PACKAGE

(TOP VIEW)

36 35 34 33 3231 30 29 28 27 26 25

VLDO1

37

38

39

40

41

42

43

44

45

46

47

24

23

22

21

20

19

18

17

16

15

14

13

ISET

TS

BATT_COVER

AC

VFB_LDO1

VINLDO1

AGND1

VLDO2

VINLDO2

GPIO3

VBAT_A

VBAT_B

USB

GPIO4

AGND2

AGND3

PGND2

PB_ONOFF

VCORE

PGND1_B

PGND1_A

PS_SEQ

VMAIN

48

1

2

3 4 5 6 7 8 9 10 11 12

NC − No internal connection

9

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

CHARGER SECTION

Charger input voltage from ac adapter. The AC pin can be left open or can be connected to

ground if the charger is not used.

AC

40

43

I

Charger input voltage from USB port. The USB pin can be left open or can be connected to

ground if the charger is not used.

USB

ISET

37

41

42

38

11

44

-

I

External charge current setting resistor connection for use with ac adapter

Sense input for the battery voltage. Connect directly with the battery.

Power output of the battery charger. Connect directly with the battery.

Battery temperature sense input

VBAT_A

VBAT_B

TS

O

I

PG

O

Indicates when a valid power supply is present for the charger (open drain)

Analog ground connection. All analog ground pins are connected internally on the chip.

Connect the PowerPAD to GND

AGND2

PowerPAD™

SWITCHING REGULATOR SECTION

AGND3

45

Analog ground connection. All analog ground pins are connected internally on the chip.

VINMAIN_A,

VINMAIN_B

7,8

I

Input voltage for VMAIN step-down converter. This must be connected to the same voltage

supply as VINCORE and VCC.

L1_A, L1_B

VMAIN

9,10

13

Switch pin of VMAIN converter. The VMAIN inductor is connected here.

VMAIN feedback voltage sense input, connect directly to VMAIN

I

Power supply for digital and analog circuitry of MAIN and CORE dc-dc converters. This

must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies

serial interface block

VCC

6

PGND1_A,

PGND1_B

Power ground for VMAIN converter

15,16

5

Input voltage for VCORE step-down converter. This must be connected to the same voltage

supply as VINMAIN and VCC.

VINCORE

I

L2

4

Switch pin of VCORE converter. The VCORE inductor is connected here.

VCORE feedback voltage sense input, connect directly to VCORE

Power ground for VCORE converter

VCORE

PGND2

48

46

LDO REGULATOR SECTION

AGND1

21

Analog ground connection. All analog ground pins are connected internally on the chip.

Input voltage for LDO1

VINLDO1

VLDO1

22

24

23

19

20

I

O

I

Output voltage for LDO1

VFB_LDO1

VINLDO2

VLDO2

Feedback input from external resistive divider for LDO1

Input voltage for LDO2

I

O

Output and feedback voltage for LDO2

DRIVER SECTION

LED2

2

3

O

LED driver, with blink rate programmable via serial interface

Vibrator driver, enabled via serial interface

VIB

CONTROL AND I2C SECTION

PS_SEQ

14

47

39

31

32

I

Sets power-up/down sequence of step-down converters

PB_ONOFF

BATT_COVER

HOT_RESET

MPU_RESET

Push-button enable pin, also used to wake up processor from low power mode

Indicates if battery cover is in place

I

Push-button reset input used to reboot or wake up processor via TPS65014

Open-drain reset output generated by user activated HOT_RESET

O

Open-drain system reset output, generated according to the state of the VMAIN output

voltage. If the main output is disabled, RESPWRON is active (i.e., low).

RESPWRON

TPOR

33

27

O

I

Sets the reset delay time at RESPWRON. TPOR = 0: T_n(RESPWRON)= 100 ms.

TPOR = 1: T_n(RESPWRON)= 1 s.

10

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

CHARGER SECTION

Open-drain output. Active low when UVLO comparator indicates low VBAT condition or

when shutdown is about to occur due to an overtemperature condition or when the battery

cover is removed (BATT_COVER has gone low).

PWRFAIL

34

35

O

Indicates a charge fault or termination, or if any of the regulator outputs are below the lower

tolerance level, active low (open drain)

INT

LOW_PWR

DEFMAIN

DEFCORE

SCLK

36

12

1

I

Input signal indicating deep sleep mode, VCORE is lowered to predefined value or disabled

Input signal indicating default VMAIN voltage, 0 = 3 V, 1 = 3.3 V

Input signal indicating default VCORE voltage, 0 = 1.5 V, 1 = 1.8 V

Serial interface clock line

I

30

29

28

26

25

18

17

I

SDAT

I/O

I

Serial interface data/address

IFLSB

LSB of serial interface address used to distinguish two devices with the same address

General-purpose open-drain input/output

GPIO1

I/O

GPIO2

General-purpose open-drain input/output

GPIO3

General-purpose open-drain input/output

GPIO4

General-purpose open-drain input/output

11

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

FUNCTIONAL BLOCK DIAGRAM

MAX(AC,USB,VBAT)

AC

USB

VBAT

PG

Linear Charge Controller

ISET

TS

AGND2

SCLK

SDAT

Serial

Interface

Thermal

Shutdown

IFLSB

VINMAIN

PS_SEQ

L1

LOW_PWR

VMAIN

DEFMAIN

PB_ONOFF

BATT_COVER

HOT_RESET

TPOR

Step-Down

Converter

Control

PGND1

RESPWRON

MPU_RESET

VCC

AGND3

VINCORE

INT

L2

UVLO

VREF

OSC

VCORE

PWRFAIL

Step-Down

Converter

DEFCORE

PGND2

GPIO1

GPIO2

GPIO3

GPIO4

GPIOs

VINLDO1

VIB

VLDO1

200-mA LDO

VFB_LDO1

AGND1

LED2

VINLDO2

VLDO2

200-mA LDO

12

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

1-4

5

Efficiency

vs Output current

vs Input voltage

vs Temperature

vs Output current

Quiescent current

Switching frequency

6

LDO1 Output voltage

7, 8, 9

10

LDO2 Output voltage

Line transient response (main)

Line transient response (core)

Line transient response (LDO1)

Line transient response (LDO2)

Load transient response (main)

Load transient response (core)

Load transient response (LDO1)

Load transient response (LDO2)

Output voltage ripple (PFM)

Output voltage ripple (PWM)

Start-up timing

11

12

13

14

15

16

17

18

19

20

21

Dropout voltage

vs Output current

vs Frequency

22, 23

24

PSRR (LDO1 and LDO2)

EFFICIENCY

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

100

90

100

90

100

V

= 1.6 V

Main:

V = 3.8 V,

I

O

90

T

= 25°C,

80

A

80

70

60

50

40

30

20

V

= 3.3 V

O

PFWM = 1

70

60

50

40

30

20

70

60

50

40

30

20

V

= 1.2 V

O

V

= 2.5 V

O

V

= 3.3 V

V

= 2.5 V

O

V

= 0.85 V

O

Main:

V = 3.8 V,

Core:

V = 3.8 V,

I

T

= 25°C,

T = 25°C,

A

FPWM = 0

A

10

0

10

0

10

0

FPWM = 0

0.01 0.10

1

10

100 1 k

10 k

0.01

0.10

1

10

100

1 k

0.10

1

0.01

10

100

1 k

10 k

I

− Output Current − mA

I

- Output Current - mA

I

- Output Current - mA

O

Figure 1.

Figure 2.

Figure 3.

13

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

EFFICIENCY

QUIESCENT CURRENT

vs

SWITCHING FREQUENCY

vs

OUTPUT CURRENT

INPUT VOLTAGE

TEMPERATURE

70

60

50

100

90

80

70

60

50

40

30

20

1.230

1.225

1.220

1.215

1.210

1.205

V

, + V

CC core

,+ V

main

V

= 1.6 V

Core:

V = 3.8 V,

O

V = 4.2 V

I

T

= 85°C

A

T

A

= 25°C,

PFWM = 1

V = 3.3 V

I

V

= 1.2 V

O

40

30

T

A

= -40°C

T

A

= 25°C

V

= 0.85 V

O

20

10

0

1.200

1.195

10

0

2.5

3

3.5

4

4.5

5

5.5

6

0.01

0.10

1

10

100

1 k

-40-30 -20 -10

0

10 20 30 40 50 60 7080 85

V - Input Voltage - V

I

T

A

- Free-Air Temperature - °C

I

− Output Current − mA

O

Figure 4.

Figure 5.

Figure 6.

LD01 OUTPUT VOLTAGE

vs

LD01 OUTPUT VOLTAGE

vs

LDO1 OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.401

3.381

3.361

3.341

3.321

3.301

1.652

3

2.90

2.80

2.70

2.60

2.50

T

A

= 25°C

T

A

= 25°C

1.642

1.632

1.622

1.612

1.602

V

= 2.8 V

O

V = 3.3 V

I

V = 6 V

I

V = 3.6 V

I

V = 5 V

I

V

= 2.5 V

O

V = 4.2 V

I

3.281

3.261

3.241

1.592

1.582

1.572

2.40

2.30

2.20

V = 4.2 V

I

V = 3.6 V

I

V = 5 V

I

V LDO1 = 3.8 V

I

3.221

3.201

1.562

1.552

2.10

2

V = 3.3 V

I

T

= 25°C

V = 6 V

I

A

0

10

100

1 k

10 k

100 k

0

10

100

1 k

10 k

100 k

0.01

0.1

10

100

1000

1

I

Output Current − mA

O

I

Output Current − mA

I

Output Current - mA

O

Figure 7.

Figure 8.

Figure 9.

LDO2 OUTPUT VOLTAGE

vs

LINE TRANSIENT RESPONSE

(MAIN)

LINE TRANSIENT RESPONSE

(CORE)

OUTPUT CURRENT

3.1

V = 3.6 V to 4.2 V, V = 1.6 V,

I

O

CH1 = V

I

= 400 mA, T = 25°C

L

A

V

= 3 V

2.9

2.7

2.5

2.3

2.1

O

CH1 = V

I

V = 3.6 to 4.2 V, V = 3.3 V,

I

O

I

= 500 mA T = 25°C

A

V

T

LDO2 = 3.8 V

= 25°C

L

O

A

CH2 = V

O

1.9

1.7

V

= 1.8 V

O

500 µs/div

0.01

0.1

1

10

100

1000

500 µs/div

I

- Output Current - mA

O

Figure 10.

Figure 11.

Figure 12.

14

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

LINE TRANSIENT RESPONSE

(LDO1)

LINE TRANSIENT RESPONSE

(LDO2)

LOAD TRANSIENT RESPONSE

(MAIN)

V = 3.3 to 3.8 V, V = 1.8 V,

CH4 = I

O

I

O

V = 3.3 to 3.8 V, V = 2.8 V,

I

O

R

L

= 100 mA to 1000 mA,

I

= 100 mA, T = 25°C

A

L

T

A

= 25°C

CH1 = V

I

V = 3.8 V, V = 3.3 V,

I

O

I

= 100 mA to 1000 mA,

L

T

A

= 25°C

CH2 = V

O

CH2 = V

O

CH2 = V

O

100 µs/div

500 µs/div

Figure 13.

Figure 14.

Figure 15.

LOAD TRANSIENT RESPONSE

(CORE)

LOAD TRANSIENT RESPONSE

(LDO1)

LOAD TRANSIENT RESPONSE

(LDO2)

V = 3.8 V, V LDO = 3.3 V,

I

V = 3.8 V, V = 1.6 V,

I

O

V

= 1.8 V, I = 2 mA to 180 mA,

O

L

I

= 40 mA to 400 mA,

L

T

A

= 25°C

T

A

= 25°C

CH4 = I

O

CH4 = I

O

CH4 = I

O

V = 3.8 V, V LDO = 3.3 V,

I

V

= 2.8 V, I = 2 mA to 180 mA,

O

L

T

A

= 25°C

CH2 = V

O

CH2 =V

O

100 µs/div

Figure 16.

OUTPUT RIPPLE (PFM)

Figure 17.

OUTPUT RIPPLE (PWM)

Figure 18.

START-UP TIMING

CH1 = V Main

O

CH1 = V Main

O

CH1 = V Main

O

CH3 = Iinductor Main

CH3 = I

Main

coil

CH2 = V Core

O

CH2 = V Core

O

CH2 = V Core

O

CH4 = I

Core

coil

CH4 = Iinductor Core

5

µs/div

500 ns/div

V = 3.8 V, T = 25°C

500 µs/div

V = 3.8 V, T = 25°C

I

A

I

A

V = 3.8 V, V Main = 3.3 V,

I

O

V

Main = 3.3 V I Main = 100 mA,

L

Core = 1.6 V, I Core = 40 mA

O

V

Main = 3.3 V R Main = 500 mA,

R

L

Main = 1 A, V Core = 1.6 V,

O

L

O

L

Core = 1.6 V, R Core = 400 mA

L

R

Core = 400 mA, T = 25°C

A

Figure 19.

Figure 20.

Figure 21.

15

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

DROPOUT VOLTAGE

vs

OUTPUT CURRENT

PSRR (LDO1, LDO2)

vs

OUTPUT CURRENT

FREQUENCY

0.25

0.2

80

70

0.05

0.045

0.04

LDOIN = 3.3 V

LDO Output Current 10 mA

LDO1 V = 2.5 V

O

LDO2 V = 1.8 V

O

60

50

LDO2 V = 1.8 V

O

LDO2 V = 3 V

O

0.035

0.03

LDO2 V = 3 V

O

0.15

0.1

LDO1 V = 2.8 V

O

0.025

0.02

40

30

LDO1 V = 2.8 V

O

LDO1 V = 2.5 V

O

0.015

20

LDO Output Current 200 mA

0.05

0

0.01

0.005

0

Low Power Mode

Normal Mode

10

0

T

A

= 25°C

T

A

= 25°C

0

20 40 60 80 100 120 140 160 180 200

1k

10k

100k

1M

10M

0

3

6

9

12 15 18 21 24 27 30

I

- Output Current - mA

O

I

- Output Current - mA

f - Frequency - Hz

O

Figure 22.

Figure 23.

Figure 24.

16

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

APPLICATION INFORMATION

AC Adapter

AC

BATT+

1 µF

X5R

VBAT

0.1 µF

USB port

BATT−

USB

ISET

1 µF

X5R

TPS65014

TEMP

TS

PG

CHARGER

PS_SEQ

GND

VBAT

POWER GOOD

LED2

VCC

DEFCORE

DEFMAIN

10 R

1 µF

X5R

VBAT

BATT_COVER

TPOR

VINCORE

22 µF

X5R

VCORE 1.5 V

PB_ONOFF

VBAT

GND

L2

10 µH

10 µF

X5R

HOT_RESET

VCORE

LOW_PWR

VINMAIN

VMAIN 3.3 V

VBAT

L1

6.2 µH

22 µF

X5R

VMAIN

GPIO1

GPIO2

GPIO3

CHARGER/REG INTERRUPT

nPOR

INT

RESPWRON

MPU_RESET

GPIO4

RESET to MPU

Battery Fail, Battery Cover

Removed, Over Temp.

VBAT

VIB

PWRFAIL

VLDO2

VINLDO1

VMAIN

0.1 µF

2.2 µF

1 µF

VINLDO2

X5R

1 MW Each

X5R

VMAIN

0.1 µF

VLDO1

2.2 µF

X5R

GND/VCC

IFLSB

SDAT

SCLK

VFB_LDO1

SCL

SDA

PGND

AGND

Figure 25. Typical Application Circuit

The VCORE and VMAIN converter are always enabled in a typical application. The VCORE output voltage can

be disabled or reduced from 1.5 V to a lower, preset voltage under processor control. When the processor enters

the sleep mode, a high signal on the LOW_PWR pin initiates the change.

VCORE typically supplies the digital part of the audio codec. When the processor is in sleep or low power mode,

the audio codec is powered off, so the VCORE voltage can be programmed to lower voltages without a problem.

A typical audio codec (e.g., TI AIC23) consumes about 20-mA to 30-mA current from the VCORE power supply.

17

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

APPLICATION INFORMATION (continued)

Supply LDO1 from VMAIN as shown in Figure 25. If this is not done, then subsequent to a UVLO, OVERTEMP,

or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and

stabilized. Therefore, the processor core does not receive a power-on-reset signal.

Touchscreen

Controller

AC Adapter

AC

BATT+

BATT−

VBAT

USB port

USB

ISET

USB DP, Camera i/f

TPS65014

TEMP

TS

PG

CHARGER

POWER GOOD

VBAT

TPOR

LED2

VCC

GND

VBAT

PS_SEQ

DEFCORE

DEFMAIN

OMAP1510

BATT_COVER

VBAT

VINCORE

VCORE 1.5V

VDD, VDD1,

VDD2, VDD3

L2

VBAT

GND

PB_ONOFF

HOT_RESET

VCORE

VINMAIN

LOW_PWR

VBAT

VMAIN 3.3V

VDDSHV2,8

GPIO

L1

VMAIN

CHARGER/REG INTERRUPT

GPIO1

GPIO2

GPIO3

INT

nPOR

RESPWRON

MPU_RESET

RESPWRON

MPU_RESET

GPIO4

RESET to MPU

VBAT

Battery Fail, Battery Cover

Removed, Overtemp.

VIB

FIQ_PWRFAIL

VDDSHV4,5

PWRFAIL

VLDO2

VINLDO1

VMAIN

VINLDO2

VMAIN

VDDSHV1,3,6,7,9

VLDO1

GND/VCC

IFLSB

SDAT

SCLK

VFB_LDO1

SCL

SDA

ARMIO_5/LOW_POWER

PGND

AGND

ARMIO,LCD,

Keyboard, USB

Host, SDIO

SDRAM, FLASH i/f

@ 1.8 V/2.8 V

Figure 26. Typical Application Circuit in Low Power Mode

18

TPS65014

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SLVS551–DECEMBER 2004

DETAILED DESCRIPTION

BATTERY CHARGER

The TPS65014 supports a precision Li-ion or Li-polymer charging system suitable for single cells with either coke

or graphite anodes. Charging the battery is possible even without the application processor being powered up.

The TPS65014 starts charging when an input voltage on either ac or USB input is present, which is greater than

the charger UVLO threshold. See Figure 27 for a typical charge profile.

Pre-

Conditioning

Phase

Voltage Regulation and Charge

Termination Phase

Current Regulation

Phase

Regulation Voltage

Regulation Current

Charge Voltage

Minimum Charge

Voltage

Charge Current

Preconditioning

and Taper Detect

t

(TAPER)

(PRECHG)

t

(CHG)

Figure 27. Typical Charging Profile

Autonomous Power Source Selection

Per default, the TPS65014 attempts to charge from the ac input. If ac input is not present, the USB is selected. If

both inputs are available, the ac input has priority. The charge current is initially limited to 100 mA when charging

from the USB input. This can be increased to 500 mA via the serial interface. The charger can be completely

disabled via the interface, and it is also possible just to disable charging from the USB port. The start of the

charging process from the USB port is delayed in order to allow the application processor time to disable USB

charging, for instance if a USB OTG port is recognized. The recommended input voltage for charging from the ac

input is 4.5 V < VAC < 6.5 V. However, the TPS65014 is capable of withstanding (but not charging from) up to 20

V. Charging is disabled if VAC is greater than typically 7 V.

Temperature Qualification

The TPS65014 continuously monitors battery temperature by measuring the voltage between the TS and AGND

pins. An internal current source provides the bias for most common 10K negative-temperature coefficient

thermistors (NTC) (see Figure 28). The IC compares the voltage on the TS pin against the internal V_(LTF)and

V_(HTF)thresholds to determine if charging is allowed. Once a temperature outside the V_(LTF)and V_(HTF)thresholds

is detected, the IC immediately suspends the charge. The IC suspends charge by turning off the power FET and

holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the

normal range.

The allowed temperature range for a 103AT-type thermistor is 0°C to 45°C. However, the user may modify these

thresholds by adding two external resistors. See Figure 29.

19

TPS65014

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SLVS551–DECEMBER 2004

DETAILED DESCRIPTION (continued)

bqTINY II

I

(TS)

TS

LTF

Pack+

Pack–

V

(LTF)

+

(HTF)

HTF

NTC

Battery Pack

TEMP

Figure 28. TS Pin Configuration

bqTINY II

I

(TS)

TS

LTF

Pack+

Pack–

V

(LTF)

+

(HTF)

HTF

RT1

RT2

NTC

Battery Pack

TEMP

Figure 29. TS Pin Threshold

Battery Preconditioning

On power up, if the battery voltage is below the V_(LOWV)threshold, the TPS65014 applies a precharge current,

I_(PRECHG), to the battery. This feature revives deeply discharged cells. The charge current during this phase is one

tenth of the value in current regulation phase which is set with I_O(out)= KSET × V_(SET)/R_(SET). The load current in

preconditioning phase must be lower than I_(PRECHG)and must allow the battery voltage to rise above V_(LOWV)

within t_(Prechg). VBAT_A is the sense pin to the voltage comparator for the battery voltage. This allows a power-on

sense measurement if the VBAT_A and VBAT_B pins are connected together at the battery.

The TPS65014 activates a safety timer, t_(PRECHG), during the conditioning phase. If V_(LOWV)threshold is not

reached within the timer period, the TPS65014 turns off the charger and indicates the fault condition in the

CHGSTATUS register. In the case of a fault condition, the TPS65014 reduces the current to I_(DETECT). I_(DETECT)is

used to detect a battery replacement condition. Fault condition is cleared by POR or battery replacement or via

the serial interface.

Battery Charge Current

TPS65014 offers on-chip current regulation. When charging from an ac adapter, a resistor connected between

the ISET1 and AGND pins determines the charge rate. A maximum of 1-A charger current from the ac adapter is

allowed. When charging from a USB port either a 100-mA or 500-mA charge rate can be selected via the serial

interface; default is 100 mA maximum. Two bits are available in the CHGCONFIG register in the serial interface

to reduce the charge current in 25% steps. These only influence charging from the ac input and may be of use if

charging is often suspended due to excessive junction temperature in the TPS65014 (e.g., at high ac input

voltages) and low battery voltages.

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TPS65014

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DETAILED DESCRIPTION (continued)

Battery Voltage Regulation

The voltage regulation feedback is through the VBAT pin. This pin is tied directly to the positive side of the

battery pack. The TPS65014 monitors the battery-pack voltage between the VBAT and AGND pins. The

TPS65014 is offered in a fixed-voltage version of 4.2 V.

As a safety backup, the TPS65014 also monitors the charge time in the fast-charge mode. If taper current is not

detected within this time period, t_(CHG), the TPS65014 turns off the charger and indicates FAULT in the

CHGSTATUS register. In the case of a FAULT condition, the TPS65014 reduces the current to I_(DETECT). I_(DETECT)

is used to detect a battery replacement condition. Fault condition is cleared by POR via the serial interface. Note

that the safety timer is reset if the TPS65014 is forced out of the voltage regulation mode. The fast-charge timer

is disabled by default to allow charging during normal operation of the end equipment. It is enabled via the

CHGCONFIG register.

Charge Termination and Recharge

The TPS65014 monitors the charging current during the voltage regulation phase. Once the taper threshold,

I_(TAPER), is detected, the TPS65014 initiates the taper timer, t_(TAPER). Charge is terminated after the timer expires.

The TPS65014 resets the taper timer in the event that the charge current returns above the taper threshold,

I_(TAPER). After a charge termination, the TPS65014 restarts the charge once the voltage on the VBAT pin falls

below the V_(RCH)threshold. This feature keeps the battery at full capacity at all times. The fast charge timer and

the taper timer must be enabled by programming CHGCONFIG(5)=1. A thermal suspend suspends the

fast-charge and taper timers.

In addition to the taper current detection, the TPS65014 terminates charge in the event that the charge current

falls below the I_(TERM)threshold. This feature allows for quick recognition of a battery removal condition. When a

full battery is replaced with an empty battery, the TPS65014 detects that the VBAT voltage is below the recharge

threshold and starts charging the new battery. The taper and termination bits are cleared in the CHGSTATUS

register and if the INT pin is still active due to these two interrupt sources, then it is de-asserted. Depending on

the transient seen at the VCC pin, all registers may be set to their default values and require reprogramming with

any nondefault values required, such as enabling the fast-charge timer and taper termination; this should only

happen if VCC drops below approximately 2 V.

Sleep Mode

The TPS65014 charger enters the low-power sleep mode if both input sources are removed from the circuit. This

feature prevents draining the battery during the absence of input power.

PG Output

The open-drain, power-good (PG) output indicates when a valid power supply is present for the charger. This can

be either from the ac adapter input or from the USB. The output turns ON when a valid voltage is detected. A

valid voltage is detected whenever the voltage on either pin AC or pin USB rises above the voltage on VBAT

plus 100 mV. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or

communicate to the host processor. A voltage greater than the V_(CHGOVLO)threshold (typ 7 V) at the AC input is

not valid and does not activate the PG output. The PG output is held in high impedance state if the charger is in

reset by programming CHGCONFIG(6)=1.

The PG output can also be programmed via the LED1_ON and LED1_PER registers in the serial interface. It can

then be programmed to be permanently on, off, or to blink with defined on- and period-times. PG is controlled per

default via the charger.

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TPS65014

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Thermal Considerations for Setting Charge Current

The TPS65014 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7

mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k

board with zero air flow.

AMBIENT TEMPERATURE

MAX POWER DISSIPATION FOR T_j= 125°C

DERATING FACTOR ABOVE T_A= 55°C

30 mW/°C

25°C

55°C

3 W

2.1 W

Consideration needs to be given to the maximum charge current when the assembled application board exhibits

a thermal impedance, which differs significantly from the JEDEC high-k board. The charger has a thermal

shutdown feature, which suspends charging if the TPS65014 junction temperature rises above a threshold of

145°C. This threshold is set 15°C below the threshold used to power down the TPS65014 completely.

STEP-DOWN CONVERTERS, VMAIN AND VCORE

The TPS65014 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed

frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the

converters automatically enter power-save mode and operate with pulse frequency modulation (PFM). The main

converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA.

The converter output voltages are programmed via the VDCDC1 and VDCDC2 registers in the serial interface.

The main converter defaults to 3-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if

DEFMAIN is tied to ground, the default is 3 V; if it is tied to V_CC, the default is 3.3 V. The core converter defaults

to either 1.5 V or 1.8 V depending on whether the DEFCORE configuration pin is tied to GND or to V_CC

,

respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up via the

serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in

the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An

active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.

The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of

which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged

when the dc-dc converters are disabled.

During PWM operation, the converters use a unique fast response voltage mode controller scheme with input

voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle, initiated by the clock signal, the P-channel MOSFET switch is

turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch.

The current limit comparator also turns off the switch in case the current limit of the P-channel switch is

exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on,

and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the

N-channel rectifier and turning on the P-channel switch.

The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and

therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a

good line and load transient regulation.

The two dc-dc converters operate synchronized to each other, with the MAIN converter as the master. A 270°

phase shift between the MAIN switch turnon and the CORE switch turnon decreases the input RMS current, and

smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter

regulates a Li-ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.

Power Save Mode Operation

As the load current decreases, the converter enters the power-save mode operation. During power-save mode,

the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to

maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the

inductor current remains below a certain threshold, and then power-save mode is entered. The typical threshold

can be calculated as follows:

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TPS65014

www.ti.com

SLVS551–DECEMBER 2004

V

I(MAIN)

17 W

I(CORE)

42 W

I

+

I

+

(skipmain)

(skipcore)

(1)

During the power-save mode, the output voltage is monitored with the comparator by the thresholds comp low

and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal

V_out, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the

load is below the delivered current, then the output voltage rises until the comp high threshold is reached,

typically 1.6% above the nominal V_out. At this point, all switching activity ceases, hence reducing the quiescent

current to a minimum until the output voltage has dropped below comp low again. If the load current is greater

than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold

(comp low 2 threshold), whereupon power-save mode is exited, and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 µA per converter and the switching frequency

to a minimum, achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and

1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving

lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a

small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute

voltage drop during heavy load transient changes. See Figure 30 for detailed operation of the power-save mode.

The power-save mode can be disabled through the I²C interface to force the converters to stay in fixed frequency

PWM mode.

PFM Mode at Light Load

1.6%

0.8%

Comp High

Comp Low

Comp Low 2

V

O

PFM Mode at Medium to Full Load

Figure 30. Power-Save Mode Thresholds and Dynamic Voltage Positioning

Forced PWM

The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is

used to minimize ripple on the output voltages.

Dynamic Voltage Positioning

As described in the power-save mode operation sections and as detailed in Figure 13, the output voltage is

typically 1.2% above the nominal output voltage at light load currents as the device is in power-save mode. This

gives additional headroom for the voltage drop during a load transient from light load to full load. During a load

transient from full load to light load, the voltage overshoot is also minimized due to active regulation turning on

the N-channel rectifier switch.

Soft Start

Both converters have an internal soft-start circuit that limits the inrush current during start-up. The soft start is

implemented as a digital circuit, increasing the switch current in 4 steps up to the typical maximum switch current

limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor

and load current.

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TPS65014

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100% Duty Cycle Low Dropout Operation

The TPS65014 converters offer a low input to output voltage difference while maintaining operation with the use

of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly

useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole

battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output

voltage and is calculated as:

ǒ_rDS(on)max_) RǓ

V

+ V

) I

I(min)

O(max)

L

(2)

with:

•

I_O(max)= maximum output current plus inductor ripple current

r_DS(on)max= maximum P-channel switch r_DSon

.

R_L= DC resistance of the inductor

V_O(max)= nominal output voltage plus maximum output voltage tolerance

Active Discharge When Disabled

When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER or OVERTEMP condition,

it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via

the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main

outputs are discharged by a 400-Ω (typical) load.

Power-Good Monitoring

Both the MAIN and CORE converters have power-good comparators. Each comparator indicates when the

relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these

comparators are available in the REGSTATUS register via the serial interface. A maskable interrupt is generated

when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are

disabled. The status of the power-good comparator for VMAIN is used to generate the RESPWRON signal.

Overtemperature Shutdown

The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see the

electrical characteristics). This detection is only active if the converters are in PWM mode, either by setting

FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.

LOW-DROPOUT VOLTAGE REGULATORS

The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors.

They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated

output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be

disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled)

are monitored by power-good comparators, the outputs of which are available via the serial interface. The LDOs

also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators

in parallel in systems with a backup battery.

Power-Good Monitoring

Both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the

relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these

comparators are available in the REGSTATUS register via the serial interface. An interrupt is generated when

any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled.

Enabling and Sequencing

Enabling and sequencing of the dc-dc converters and LDOs are described in the power-up sequencing section.

The OMAP1510 processor from Texas Instruments requires that the core power supply is enabled before the I/O

power supply, which means that the CORE converter should power up before the MAIN converter. This is

achieved by connecting PS_SEQ to GND.

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TPS65014

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UNDERVOLTAGE LOCKOUT

The undervoltage lockout circuit for the four regulators on TPS65014 prevents the device from malfunctioning at

low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning

on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by

default to 2.75 V. After power up, the threshold voltage can be reprogrammed through the serial interface. The

undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC

voltage drops below this threshold, the TPS65014 sets the PWRFAIL pin low and after a time t_(UVLO)disables the

voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65014

detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay

t_(overtemp). The TPS65014 automatically restarts when the UVLO (or overtemperature) condition is no longer

present.

The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared

with the voltage on AC and USB supply pins.

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TPS65014

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POWER-UP SEQUENCING

The TPS65014 power-up sequencing is designed to allow the maximum flexibility without generating excessive

logistical or system complexity. The relevant control pins are described in the following table:

Table 1. Control Pins

PIN NAME

PS_SEQ

INPUT/OUTPUT

FUNCTION

Input signal indicating power-up and power-down sequence of the switching converters. PS_SEQ = 0

forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up

first and down last.

I

Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V,

DEFCORE = VCC defaults VCORE to 1.8 V.

DEFCORE

DEFMAIN

I

Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3 V,

DEFMAIN = VCC defaults VMAIN to 3.3 V.

The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the

processor is in deep sleep mode. Alternatively, VCORE can be disabled in low power mode if the

LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in

the VDCDC1 register. The TPS65014 uses the rising edge of the internal signal formed by a logical AND

of LOW_PWR and ENABLE LP to enter low power mode. TPS65014 is forced out of low power mode by

de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating

the HOT_RESET pin. There are two ways to get the device back into low power mode: a) toggle the

LOW_PWR pin, or b) toggle the low power bit when the LOW_PWR pin is held high. The LOW_PWR pin

is also used to set the TPS65014 into WAIT mode. If USB or AC is present, the AUA bit (CHCONFIG<7>)

must be set to enter the WAIT mode, see Figure 31.

LOW_PWR

I

PB_ONOFF can be used to exit the low power mode and return the core voltage to the value before low

power mode was entered. If PB_ONOFF is used to exit the low power mode, then the low power mode

can be reentered by toggling the LOW_PWR pin or by toggling the low power bit when the LOW_PWR pin

is held high. A 1-MΩ pulldown resistor is integrated in TPS65014. PB_ONOFF is internally de-bounced by

the TPS65014. A maskable interrupt is generated when PB_ONOFF is activated.

PB_ONOFF

I

The HOT_RESET pin has a similar functionality to the PB_ONOFF pin. In addition, it generates a reset

(MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any

TPS65014 settings unless low power mode was active in which case it is exited. A 1-MΩ pullup resistor to

V_CCis integrated in TPS65014. HOT_RESET is internally de-bounced by the TPS65014.

HOT_RESET

The BATT_COVER pin is used as an early warning that the main battery is about to be removed.

BATT_COVER = V_CCindicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not

in place. TPS65014 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is

also held low when BATT_COVER goes low. This feature may be disabled by tying BATT_COVER

permanently to VCC. The TPS65014 shuts down the main and the core converter and sets the LDOs into

low power mode. A 2-MΩ pulldown resistor is integrated in the TPS65014 at the BATT_COVER pin.

BATT_COVER is internally de-bounced by the TPS65014.

BATT_COVER

I

RESPWRON is held low while the switching converters (and any LDOs defined as default on) are starting

up. It is determined by the state of MAIN's output voltage; when the voltage is higher than the power-good

comparator threshold; then RESPWRON is high when VMAIN is low; then RESPWRON is low.

RESPWRON is held low for t_n(RESPWRON)seconds after VMAIN has settled.

RESPWRON

MPU_RESET

O

MPU_RESET can be used to reset the processor if the user activates the HOT_RESET button. The

MPU_RESET output is active for t_{(MPU_nRESET)}sec. It also forces TPS65014 to leave low power mode.

MPU_RESET is also held low as long as RESPWRON is held low.

PWRFAIL indicates when V_CC< V_(UVLO), when the TPS65014 is about to shut down due to an internal

overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as

RESPWRON is held low.

PWRFAIL

TPOR

O

I

TPOR is used to set the delay time for the RESPWRON reset signal.

TPOR = 0 sets the delay time to 100 ms. TPOR = 1 sets the delay time to 1 s.

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TPS65014

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SLVS551–DECEMBER 2004

Figure 31 shows the state diagram for the TPS65014 power sequencing. The charger function is not shown in

the state diagram because this function is independent of these states.

Monitored Permanently

No

Power

TPS65011

RESPWRON,

PWRFAIL, INT,

MPU_RESET Low.

Reset

VMAIN

Voltage

Enabled and

Good?

No

AC and/or USB

Power Applied.

Main Battery Power

Applied

RESPWRON Timer

Monitored Permanently

Yes

VCC>UVOL,

Start

T <Tshtdwn,

j

No

WAIT

*1

RESPWRON

BATT_COVER

High ?

Timer if Not Running

No

AC and/or USB

Power Applied

or

PB_ONOFF or

HOT_RESET

Button Pressed.

Set PWRFAIL Low,

Start UVLO_TEMP

Timer if Not Running

RESPWRON

Timer Done ?

No

Yes

VCC>UVLO ?

BATT_COVER

High ?

Release

VCC>UVLO ?

BATT_COVER

High ?

No

RESPWRON,

PWRFAIL, INT,

MPU_RESET

UVLO_TEMP

Timer Done ?

Yes

Value

PS_SEQ ?

1

Yes

0

Boot VMAIN

Boot VCORE

Shutdown VCORE,

VMAIN + LDOs

According to

Converter + LDOs

Yes

PS_SEQ

Boot VCORE

Converter

Boot VCORE

Converter

LOW_PWR

De-asserted,

PB_ONOFF

Button Pressed

LOW_

POWER

Mode

Processor Initiated

Shutdown *3

LOW_PWR

Asserted *2

ON

HOT_RESET

Button Pressed

*1: All registers are reset to their default values in WAIT Mode

*2: ENABLE_LP bit, VDCDC1 <3> Must be set.

No

If AC or USB power is present, AUA bit, CHGCONFIG <7> must also be set.

Raise the low power pin to enter low power mode.

*3: ENABLE_SUPPLY bit, VDCDC1 <4> must be cleared.

ENABLE_LP bit, VDCDC1 <3> must be set.

Release

MPU_RESET

VCORE Voltage

Good ?

LDO2OFF/SLP and LDO1OFF/SLP <6,2> must be set or LDOs and voltage

reference remain enabled and registers not reset.

Yes

If AC or USB power is present, AUA bit, CHGCONFIG <7> must also be set.

Raise the low power pin to enter low power mode.

Set MPU_RESET

Low, Start

MPU_RESET Timer

MPU_RESET

Timer Done ?

ENABLE_LP default: cleared

ENABLE_SUPPLY default: set

AUA default: cleared

No

LDO1OFF/SLP default: cleared

LDO2OFF/SLP default: cleared

Figure 31. TPS65014 Power-On State Diagram

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TPS65014

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TPS65014 Power States Description

State 1: No Power

No batteries are connected to the TPS65014. When main power is applied, the bandgap reference, LDOs, and

UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When

BATT_COVER goes high (de-bounced internally by the TPS65014), indicating that the battery cover has been

put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ.

RESPWRON, PWRFAIL, INT, and MPU_RESET are released when the RESPWRON timer has timed out after

t_n(RESPWRON)seconds. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65014 arrives in

State 2: ON. If VCC < UVLO, the TPS65014 keeps the bandgap reference and UVLO comparator active such

that when VCC>UVLO (during battery charge), the supplies are automatically activated.

State 2: ON

In this state, the TPS65014 is fired up and ready for operation. The switching converter output voltages can be

programmed. The LDOs can be disabled or programmed. The TPS65014 can exit this state due to an

overtemperature condition, an undervoltage condition at VCC, BATT_COVER going low, or by the processor

programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.

State 3: Low Power Mode

This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the

LOW_PWR pin. The TPS65014 actually uses the rising edge of the internal signal formed by a logical AND of

the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains

active, but the VCORE converter may be disabled in low power mode through the serial interface by setting the

LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by

the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1

register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry

disabled in order to minimize quiescent current) in low power mode. All TPS65014 features remain addressable

through the serial interface. TPS65014 can exit this state either due to an undervoltage condition at VCC, due to

BATT_COVER going low, due to an OVERTEMP condition, by the processor de-asserting the LOW_POWER

pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin.

State 4: Shutdown

There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery

power is applied, the device automatically enters the WAIT mode.

The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting

the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR

pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then

disabled. In this state, the TPS65014 waits for the PB_ONOFF or HOT_RESET pin to be activated before

enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65014 powers

up the supplies according to the same constraints as at the initial application of power. Complete shutdown is

only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before

activating the shutdown.

In this case, the I²C interface is deactivated, and the registers are reset to their default value after leaving the

WAIT mode.

To enter the WAIT mode when USB or AC is present, the AUA bit (CHCONFIG<7>) must be set. The WAIT

mode is automatically left if bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the

AC pin or the USB pin in the appropriate range for charging, and the voltage at V_CCis above the UVLO

threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.

If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are

reset to their default state when the device returns to ON mode.

Table 2 shows possible configurations in LOW POWER mode and WAIT mode.

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Table 2. TPS65014 Possible Configurations

CONVERTER

MAIN

CORE

0/1

LDO1

0/1

LDO2

0/1

LOW POWER mode

WAIT mode

1

0

0/1

•

0 = converter is disabled

1 = converter is enabled

Table 3 indicates the typical quiescent current consumption in each power state.

Table 3. TPS65014 Typical Current Consumption

TOTAL QUIESCENT

CURRENT

STATE

QUIESCENT CURRENT BREAKDOWN

1

2

0

30 µA-70 µA

VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference +

PowerGood

3

4

30 µA-55 µA

13 µA

VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference +

PowerGood

UVLO + reference circuitry

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V

CC

BATT

COVER

t

(GLITCH)

BATT COVER

DEG*

PB_ONOFF

t

(GLITCH)

REFSYS

EN*

UVLO*

ENABLE

SUPPLIES*

VCORE

VMAIN

VLDO1

98%

VCORE

95%

VMAIN

VLDO2

RESPWRON

MPU_RESET

PWREFAIL

INT

t

n(RESPWRON)

*Internal Signal

A. Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.

Figure 32. State 1 to State 2 Transition (PS_SEQ = 0, V_CC> V_UVLO+ HYST)

If 2.4 ms after application, V_CCis still below the default UVLO threshold (3.15 V for V_CCrising), then start up is as

shown in Figure 33.

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AC (or USB)

V

CC

UVLO Threshold

BATT COVER

t

(GLITCH)

BAT COVER

DEG *

REFSYS

EN*

UVLO*

ENABLE

SUPPLIES*

VCORE

VMAIN

98%

VCORE

95%

VMAIN

VLDO1

VLDO2

RESPWRON

MPU_RESET

PWRFAIL

INT

t

n(RESPWRON)

* Internal Signal

A. Valid for LDO1 supplied from VMAIN as described earlier in this Application Section

Figure 33. State1-State4-State 2 Transition (Power up behavior when Charge Voltage is Applied)

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V

CC

UVLO Threshold With 400 mV Hysteresis

UVLO*

PWPFAIL

INT

t

UVLO

ENABLE

SUPPLIES*

VCORE

VMAIN

~0.8 V

VLDO1

VLDO2

RESPWRON

MPU_RESET

* Internal Signal

A. Valid for LDO1 supplied from VMAIN as described earlier in this Application Section

Figure 34. State2-State4 Transition

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ENABLE

LOW_POWER

LDO2

OFF/SLP

LOW_POWER

VMAIN

VCORE

VLDO1

VLDO2

INT

95% VCORE

95% VLDO2

Figure 35. State 2 to State 3 Transition. VCORE Lowered, LDO2 Disabled. Subsequent State 3 to State 2

Transition When LOW POWER Is De-asserted.

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PB_ONOFF

DEGLITCH

t

GLITCH

VCORE

VMAIN

VLDO1

VLDO2

INT

Figure 36. State 3 to State 2 Transition. PB_ONFF Activated (See Interrupt Management Section for INT

Behavior)

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HOT_RESET

DEGLITCH

t

(GLITCH)

VCORE

VMAIN

95% VCORE

VLDO1

VLDO2

95% VLDO2

INT

t(

MPU_RESET)

MPU_RESET

Figure 37. State 3 to State 2 Transition, HOT_RESET Activated (See Interrupt Management Section for INT

Behavior)

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ENABLE

LOW

POWER*

LDO1

OFF/SLP*

LDO2

OFF/SLP*

MAIN

DISCHARGE*

ENABLE

SUPPLY*

LOW POWER

VMAIN

VMAIN < ca 0.8 V

VCORE

VCORE < ca 0.4 V

VLDO1

VLDO2

RESPWRON

MPU_RESET

PWRFAIL

INT

REFSYS

ENABLE*

* Internal Signal

Figure 38. State 1 to State 4 Transition

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SYSTEM RESET AND CONTROL SIGNALS

The RESPWRON signal is used as a global reset for the application. It is an open-drain output. The

RESPWRON signal is generated according to the power good comparator linked to VMAIN and remains low for

t_n(RESPWRON)seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET, and INT

are also held low.

If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the

output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90%

window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65014 junction temperature has exceeded a

reliable value or if BATT_COVER is taken low. This open-drain output can be connected at a fast interrupt pin for

immediate attention by the application processor. All supplies are disabled t_(uvlo), t_(overtemp), or t_{(batt_cover)}seconds

after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.

BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the

TPS65014 generates a warning to the processor that the battery is likely to be removed and that it may be

prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER

pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER

has an internal 2-MΩ pulldown resistor.

The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The

HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low

power mode. In this case, the TPS65014 waits until the VCORE voltage has stabilized before generating the

MPU_RESET pulse. The MPU_RESET pulse is active low for t_{(mpu_nreset)}seconds. HOT_RESET has an internal

1-MΩ pullup resistor to V_CC

.

The PB_ONOFF input can be used to exit LOW POWER MODE. It is typically driven by a user-activated

pushbutton in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65014.

Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.

PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are

noted in the REGSTATUS register.

VIBRATOR DRIVER

The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register

VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit

the motor current and a freewheel diode to limit the VIB overshoot voltage at turnoff.

LED2 OUTPUT

The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off.

The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum

blink-on time is 10 ms, and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the

minimum blink period is 100 ms, and this can be increased in 127 100-ms steps to 12800 ms.

INTERRUPT MANAGEMENT

The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip

temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable

of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation

threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can

be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to

mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2,

or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS,

REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are

acknowledged by reading these registers. If a 1 is present in any location, then the TPS65014 automatically sets

the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register

contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor

should not normally need to access the ACKINT1 or ACKINT2 registers.

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Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active

due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before

unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO

registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the

corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically

acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant

bit(s). No interrupt should be missed during the read process because this process starts by latching the contents

of the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of

nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything

is, for practical purposes, zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

•

CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.

CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.

CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.

CHGSTATUS(7-6,4-1) clear when input signal is low.

ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.

REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.

REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.

REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.

REGSTATUS(3-0) clear when input signal is low.

ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not

usually written to by the CPU because the TPS65014 internally sets/clears these registers:

•

ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I²C.

ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.

ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I²C.

ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.

ACKINT1(7:0) - A bit set masks the corresponding CHGSTATUS bit from INT.

ACKINT2(7:0) - A bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

•

MASK1(7:0) - A bit set in this register masks CHGSTATUS from INT.

MASK2(7:0) - A bit set in this register masks REGSTATUS from INT.

MASK3(7:4) - A bit set in this register detects a rising edge on GPIO.

MASK3(7:4) - A bit cleared in this register detects a falling edge on GPIO.

MASK3(3:0) - A bit set in this register clears GPIO Detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read

from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on

which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines

whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by

setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO

interrupts.

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SERIAL INTERFACE

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to

400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored.

Register contents remain intact as long as V_CCremains above 2 V. The TPS65014 has a 7-bit address with the

LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The

6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh

being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start

condition and terminated with a stop condition. When addressed, the TPS65014 device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TPS65014 device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave TPS65014 device must leave the data line high to enable the master to generate the stop

condition.

The I²C interface accepts data as soon as the voltage at V_CCis higher than the undervoltage lockout threshold

and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I²C interface is

not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails

off.

When the device is in WAIT mode, the I²C registers are reset to their default values if all voltage rails are off. If

the device is in WAIT mode and one power rail is left on, the I²C interface is operating and the registers are not

reset after leaving the WAIT mode.

DATA

CLK

Change

of Data

Allowed

Data Line

Stable

Data Valid

Figure 39. Bit Transfer on the Serial Interface

CE

DATA

CLK

S

P

START Condition

STOP Condition

Figure 40. START and STOP Conditions

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...

_A4...

...

SCLK

... _R0

..._D0

A6

A5

A0 R/W ACK

R7

R6

R5

ACK

0

D7

D6 D5

ACK

SDAT

0

Start

Stop

Slave Address

Register Address

Data

A. NOTE^:SLAVE = TPS65014

Figure 41. Serial Interface WRITE to TPS65014 Device

...

..

...

..

...

..

...

..

SCLK

SDAT

A6

A0

R/W ACK

R7

R0

ACK

0

A6

A0

R/W ACK

D7

D0

ACK

0

1

0

Slave

Register

Address

Master

Start

Slave Address

Stop

Drives

The Data

ACK and Stop

A. NOTE^:SLAVE = TPS65014

Figure 42. Serial Interface READ From TPS65014: Protocol A

...

..

...

..

...

..

SCLK

SDAT

..

A6

A0 R/W ACK

R7

R0 ACK

0

A6

A0

R/W ACK D7

D0

ACK

0

1

0

Slave

Master

Drives

ACK and Stop

Stop Start

Register

Address

Drives

The Data

Slave Address

Start

Stop

A. NOTE^:SLAVE = TPS65014

Figure 43. Serial Interface READ From TPS65014: Protocol B

DATA

t

(BUF)

t

h(STA)

t

(LOW)

t

f

r

CLK

t

h(STA)

(HIGH)

t

su(STA)

su(STO)

t

su(DATA)

h(DATA)

STO

STA

STO

Figure 44. Serial Interface Timing Diagram

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CHGSTATUS Register (Address: 01h—Default Value: 00h)

CHGSTATUS

B7

B6

B5

B4

B3

B2

B1

B0

Thermal

Suspend

Taper

Timeout

Prechg

Timeout

BattTemp

Error

Name

USB Charge

AC Charge

Term Current

Chg Timeout

Default

0

Read/write

R

R/W

R

The CHGSTATUS register contents indicate the status of charge.

Bit 7 - USB charge:

•

0 = inactive.

1 = USB source is present and in the range valid for charging. B7 remains active as long as the charge

source is present.

Bit 6 - AC charge:

•

0 = wall plug source is not present and/or not in the range valid for charging.

1 = wall plug source is present and in the range valid for charging. B6 remains active as long as the charge

source is present.

Bit 5 - Thermal suspend:

•

0 = charging is allowed

1 = charging is momentarily suspended due to excessive power dissipation on chip.

Bit 4 - Term current:

•

0 = charging, charge termination current threshold has not been crossed.

1 = charge termination current threshold has been crossed and charging has been stopped. This can be due

to a battery reaching full capacity, or to a battery removal condition.

Bit 3 - 1 Prechg Timeout, Chg Timeout, Taper Timeout:

•

If CHCONFIG<5>=0: Bit 3 equals the output of the taper voltage comparator directly, without any timer delay.

If CHCONFIG<5>=1: there is a delay of 30 minutes because the timers have to time out first.

0 = charging, timers did not time out

1 = one of the timers has timed out and charging has been terminated.

Bit 0 - BattTemp error: Battery temperature error

•

0 = battery temperature is inside the allowed range and that charging is allowed.

1 = battery temperature is outside of the allowed range and that charging is suspended.

B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and

B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.

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REGSTATUS Register (Address: 02h—Default Value: 00h)

REGSTATUS

B7

B6

B5

B4

B3

B2

B1

B0

PGOOD

LDO2

PGOOD

LDO1

PGOOD

MAIN

PGOOD

CORE

Bit name

PB_ONOFF

BATT_COVER

UVLO

Default

0

Read/write

R

Bit 7 - PB_ONOFF:

•

0 = inactive

1 = user activated the PB_ONOFF switch to request that all rails are shut down.

Bit 6 - BATT_COVER:

•

0 = BATT_COVER pin is high.

1 = BATT_COVER pin is low.

Bit 5 - UVLO:

•

0 = voltage at the VCC pin above UVLO threshold.

1 = voltage at the VCC pin has dropped below the UVLO threshold.

Bit 4 - not implemented

Bit 3 - PGOOD LDO2:

•

0 = LDO2 output in regulation, or LDO2 disabled with VREGS1 < 7 > = 0

1 = LDO2 output out of regulation.

Bit 2 - PGOOD LDO1:

•

0 = LDO1 output in regulation, or LDO1 disabled with VREGS1 < 3 > = 0

1 = LDO1 output out of regulation.

Bit 1 - PGOOD MAIN:

•

0 = Main converter output in regulation.

1 = Main converter output out of regulation.

Bit 0 - PGOOD CORE:

•

0 = Core converter output in regulation.

1 = Core converter output out of regulation, or VDCDC2 < 7 > = 1 in low power mode

A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.

MASK1 Register (Address: 03h—Default Value: FFh)

MASK1

B7

B6

B5

B4

B3

B2

B1

B0

Mask Thermal

Suspend

Mask

BattTemp

Bit name

Mask USB

Mask AC

Mask Term

Mask Taper

Mask Chg Mask Prechg

Default

1

Read/write

R/W

The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0>

positions being indicated at the INT pin. Default is to mask all.

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MASK2 Register (Address: 04h—Default Value: FFh)

MASK2

B7

B6

B5

B4

B3

B2

B1

B0

Mask

PB_ONOFF

Mask

BATT_COVER

Mask PGOOD

LDO2

Mask PGOOD

LDO1

Mask PGOOD

MAIN

Bit name

Mask UVLO

Mask PGOOD CORE

Default

1

Read/write

R/W

The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0>

positions being indicated at the INT pin. Default is to mask all.

ACKINT1 Register (Address: 05h—Default Value: 00h)

ACKINT1

B7

B6

B5

B4

B3

B2

B1

B0

Ack Thermal

Shutdown

Ack

BattTemp

Bit name

Ack USB

Ack AC

Ack Term

Ack Taper

Ack Chg

Ack Prechg

Default

0

Read/write

R

The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding

CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT

pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes

high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding

interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access

the ACKINT1 register.

ACKINT2 Register (Address: 06h—Default Value: 00h)

ACKINT2

B7

B6

B5

B4

B3

B2

B1

B0

Bit name

and function

Ack

PB_ONOFF

Ack BATT_

COVER

Ack PGOOD Ack PGOOD Ack PGOOD Ack PGOOD

Ack UVLO

LDO2

LDO1

MAIN

CORE

Default

0

Read/write

R

The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding

REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT

pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes

high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding

interrupt condition in REGSTATUS is removed. The application processor should not normally need to access

the ACKINT2 register.

CHGCONFIG Register Address: 07h—Default Value: 1Bh

CHGCONFIG

B7

B6

B5

B4

B3

B2

B1

B0

Fast charge

Charger reset timer + taper

timer enabled

MSB charge

current

LSB charge

current

USB / 100

mA 500 mA

USB charge

allowed

Charge

enable

Bit name

AUA

Default

0

1

0

1

Read/write

R/W

The CHGCONFIG register is used to configure the charger.

Bit 7 - AUA:

•

0 = If a voltage is present at AC or USB in the appropriate range for charging, and if V_CC> UVLO, the

TPS65014 is forced into ON mode. The WAIT mode is disabled.

•

1 = If a voltage source at AC or USB is present, the WAIT mode is enabled, and the TPS65014 does not

automatically turn on the converters.

Bit 6 - Charger reset:

•

Clears all the timers in the charger and forces a restart of the charge algorithm.

0 / 1 = This bit must be set and then reset via the serial interface.

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Bit 5 - Fast charge timer + taper timer enabled:

•

0 = fast charge timer disabled (default), CHSTATUS < 3 >= status of the taper detect comparator output.

1 = enables the fast charge timer and taper timer. CHSTATUS < 3 >= status of the taper timer.

Bit 4, Bit 3 - MSB/LSB Charge current:

•

Used to set the constant current in the current regulation phase.

B4:B3

CHARGE CURRENT RATE

11

10

01

00

Maximum current set by the external resistor at the ISET pin

75% of maximun

50% of maximun

25% of maximun

Bit 2 - USB 100 mA / 500 mA:

•

0 = sets the USB charging current to max 100 mA.

1 = sets the USB charging current to max 500 mA. B2 is ignored if B1 = 0.

Bit 1 - USB charge allowed:

•

0 = prevents any charging from the USB input.

1 = charging from the USB input is allowed.

Bit 0 - Charge enable:

•

0 = charging is not allowed.

1 = charger is free to charge from either of the two input sources. If both sources are present and valid, the

TPS65014 charges from the AC pin source.

LED1_ON Register (Address: 08h—Default Value: 00h)

LED1_ON

Bit name

Default

B7

PG1

0

B6

LED1 ON6

0

B5

LED1 ON5

0

B4

LED1 ON4

0

B3

LED1 ON3

0

B2

LED1 ON2

0

B1

LED1 ON1

0

B0

LED1 ON 0

0

Read/write

R/W

The LED1_ON and LED1_PER registers can be used to take control of the PG open-drain output normally

controlled by the charger.

Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER

register

Bit 6 - BIT 0 - LED1_ON<6:0> are used to program the on-time of the open-drain output transistor at the PG pin.

The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

LED1_PER Register (Address: 09h—Default Value: 00h)

LED1_PER

Bit name

Default

B7

PG2

0

B6

B5

B4

B3

B2

B1

B0

LED1 PER6 LED1 PER5 LED1 PER4 LED1 PER3 LED1 PER2 LED1 PER1 LED1 PER 0

0

Read/write

R/W

44

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown

in bold.

PG1

PG2

BEHAVIOR OF PG OPEN-DRAIN OUTPUT

0

1

0

1

0

1

Under charger control

Blink

Off

Always On

Bit 6-Bit 0 - LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG

pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms, step change in the period.

LED2_ON Register (Address: 0Ah—Default Value: 00h)

LED2_ON

Bit name

Default

B7

LED21

0

B6

LED2 ON6

0

B5

LED2 ON5

0

B4

LED2 ON4

0

B3

LED2 ON3

0

B2

LED2 ON2

0

B1

LED2 ON1

0

B0

LED2 ON0

0

Read/write

R/W

The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.

Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin.

The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms, step change in the on-time.

LED2_PER (Register Address: 0Bh—Default Value: 00h)

LED2_PER

Bit name

Default

B7

LED22

0

B6

B5

B4

B3

B2

B1

B0

LED2 PER6 LED2 PER5 LED2 PER4 LED2 PER3 LED2 PER2 LED2 PER1 LED2 PER 0

0

Read/write

R/W

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in bold.

Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin.

The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms, step change in the on-time.

LED21

LED22

BEHAVIOR OF LED2 OPEN-DRAIN OUTPUT

0

1

0

1

0

1

Off

Blink

Off

Always On

VDCDC1 Register (Address: 0Ch—Default Value: 32h/33h)

VDCDC1

B7

B6

B5

B4

B3

B2

B1

B0

Bit name

FPWM

UVLO1

UVLO0

ENABLE

SUPPLY

ENABLE

LP

MAIN DIS-

CHARGE

MAIN1

MAIN0

Default

0

1

0

1

DEFMAIN

R/W

Read/write

R/W

The VDCDC1 register is used to program the VMAIN switching converter.

Bit 7 - FPWM: forced PWM mode for dc-dc converters.

•

0 = MAIN and the CORE dc-dc converter are allowed to switch into PFM mode.

1 = MAIN and the CORE dc-dc converter operate with forced fixed-frequency PWM mode and are not

allowed to switch into PFM mode, at light load.

Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to the

following table, with the default value in bold.

45

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

UVLO1

UVLO0

V_UVLO

2.5 V

0

1

0

1

0

1

2.75 V

3.0 V

3.25 V

Bit 4 - ENABLE SUPPLY (selects between LOW POWER mode and WAIT mode):

•

0 = WAIT mode allowed, activated when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.

1 = The TPS65014 enters LOW POWER mode when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.

Bit 3 - ENABLE LP:

•

0 = disables the low power function of the LOW_PWR pin.

1 = enables the low power function of the LOW_PWR pin.

Bit 2 - MAIN DISCHARGE:

•

0 = disables the active discharge of the VMAIN converter output.

1 = enables the active discharge of the VMAIN converter output, when the converter is disabled (i.e., in

WAIT mode).

Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the

default values in bold set by the DEFMAIN pin. The default voltage can subsequently be overwritten via the serial

interface after start-up.

MAIN1

MAIN0

VMAIN

2.5 V

0

1

0

1

0

1

2.75 V

3.0 V

3.3 V

VDCDC2 Register (Address: 0Dh—Default Value: 60h/70h)

VDCDC2

B7

B6

B5

B4

B3

B2

B1

B0

CORE

DISCHARGE

Bit name

LP_COREOFF

CORE2

CORE1

CORE0

CORELP1

CORELP0

VIB

Default

0

1

DEFCORE

R/W

1

0

Read/write

R/W

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8

steps between 0.85 V and 1.8 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an

output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.

Bit 7 - LP_COREOFF:

•

0 = VCORE converter is enabled in low power mode.

1 = VCORE converter is disabled in low power mode.

46

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The default value can

subsequently be overwritten via the serial interface after start-up.

CORE2

CORE1

CORE0

VCORE

0.85 V

1.0 V

1.1 V

1.2 V

1.3 V

1.4 V

1.5 V

1.8 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power

mode. In low power mode, CORE2 is effectively 0, and CORE1, CORE0 take on the values programmed at

CORELP1 and CORELP0, default 10 giving VCORE = 1.1 V as default in low power mode. When low power

mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.

Bit 1 - VIB:

•

0 = disables the VIB output transistor.

1 = enables the VIB output transistor to drive the vibrator motor.

Bit 0 - CORE DISCHARGE:

•

0 = disables the active discharge of the VCORE converter output.

1 = enables the active discharge of the VCORE converter output in WAIT mode, or if VDCDC2 < 7 >= 1 in

LOW POWER mode.

VREGS1Register (Address: 0Eh—Default Value: 88h)

VREGS1

B7

B6

B5

B4

B3

B2

B1

B0

Bit name

LDO2 enable

LDO2 OFF /

nSLP

LDO21

LDO20

LDO1 enable

LDO1 OFF /

nSLP

LDO11

LDO10

Default

1

0

1

0

Read/write

R/W

The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low power

mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or

simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.

Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in the following table. See the

power-on sequencing section for details of low power mode.

LDO2 ENABLE

LDO2 OFF / nSLP

LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE

0

1

X

0

1

OFF

ON, reduced power/performance

OFF

ON, full power

Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If desired, this can be changed at the same

time as it is enabled via the serial interface.

LDO21

LDO20

VLDO2

1.8 V

2.5 V

3.0 V

3.3 V

0

1

0

1

0

1

47

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the

power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage

may force a system power-on reset if the increase is in the 10% or greater range.

LDO1 ENABLE

LDO1 OFF / nSLP

LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE

0

1

X

0

1

OFF

ON, reduced power/performance

OFF

ON, full power

Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed

via the serial interface.

LDO11

LDO10

VLDO1

ADJ

0

1

0

1

0

1

2.5 V

2.75 V

3.0 V

MASK3 Register (Address: 0Fh—Default Value: 00h)

MASK3

B7

B6

B5

B4

B3

B2

B1

B0

Edge trigger

GPIO4

Edge trigger

GPIO3

Edge trigger

GPIO2

Edge trigger

GPIO1

Bit name

Mask GPIO4 Mask GPIO3 Mask GPIO2 Mask GPIO1

Default

0

Read/write

R/W

The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.

Bit 7-Bit 4 - Edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or

a falling edge.

•

0 = falling edge triggered.

1 = rising edge triggered.

Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (mask

GPIOx = 0).

DEFGPIO Register Address: (10h—Default Value: 00h)

DEFGPIO

Bit name

Default

B7

IO4

0

B6

IO3

0

B5

IO2

0

B4

IO1

0

B3

B2

B1

B0

Value GPIO4 Value GPIO3 Value GPIO2 Value GPIO1

0

Read/write

R/W

The DEFGPIO register is used to define the GPIO pins to be either input or output.

Bit 7-Bit 4 - IO<4:1>:

•

0 = sets the corresponding GPIO to be an input.

1 = sets the corresponding GPIO to be an output.

Bit 3-Bit 0 - Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by

the corresponding bit. The output circuit for each GPIO is an open-drain NMOS requiring an external pullup

resistor.

•

1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.

0 = turns the open-drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to

which the pullup resistor is connected.

If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the

logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an

input, then any attempt to write to the relevant bit in B3-0 is ignored.

48

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

DESIGN PROCEDURE

Inductor Selection for the Main and the Core Converter

The main and the core converters in the TPS65014 typically use a 6.2-µH and a 10-µH output inductor,

respectively. Larger or smaller inductor values can be used to optimize the performance of the device for specific

operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc

resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest

dc resistance is selected for highest efficiency.

Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is needed

because during heavy load transient, the inductor current rises above the value calculated under Equation 3.

V

O

1–

V

I

DI + V

L

O

L ƒ

(3)

(4)

DI

L

I

+ I

)

L(max)

O(max)

2

with:

•

f = Switching frequency (1.25 MHz typical)

L = Inductor value

∆I_L= Peak-to-peak inductor ripple current

I_Lmax= Maximum inductor current

The highest inductor current occurs at maximum V_I.

Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents

versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

TPS65014 (2 A for the main converter and 0.8 A for the core converter). Keep in mind that the core material from

inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.

See Table 4 and the typical applications for possible inductors

Table 4. Tested Inductors

DEVICE

INDUCTOR VALUE

10 µH

DIMENSIONS

COMPONENT SUPPLIER

Sumida CDRH5D18-100

Sumida CDRH4D28-100

Coilcraft LPO1704-472M

Sumida CDRH4D28C-4.7

Coiltronics SD25-4R7

6 mm × 6 mm × 2 mm

5 mm × 5 mm × 3 mm

5,5 mm × 6,6 mm x 1 mm

5 mm × 5 mm × 3 mm

5,2 mm × 5,2 mm × 2,5 mm

5,7 mm × 5,7 mm × 3 mm

7 mm × 7 mm × 3 mm

Core converter

10 µH

4.7 µH

Main converter

5.3 µH

Sumida CDRH5D28-5R3

Sumida CDRH5D28-6R2

Sumida CDRH6D28-6R0

6.2 µH

6 µH

Output Capacitor Selection

The advanced fast response voltage mode control scheme of the inductive converters implemented in the

TPS65014 allow the use of small ceramic capacitors with a typical value of 22 µF for the main converter and 10

µF for the core converter without having large output voltage under/overshoots during heavy load transients.

Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If

required tantalum capacitors with an ESR < 100 ΩR may be used as well.

See Table 5 for recommended components.

49

TPS65014

www.ti.com

SLVS551–DECEMBER 2004

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application

requirements. For completeness, the RMS ripple current is calculated as:

V

O

1–

V

I

1

I

+ V

RMSC(out)

O

Ǹ

L ƒ

2

3

(5)

At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is

the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

V

O

1–

V

I

1

DV + V

) ESR

ǒ

Ǔ

O

L ƒ

8 C ƒ

O

(6)

Where the highest output voltage ripple occurs at the highest input voltage V_I.

At light load currents, the converters operate in power save mode and the output voltage ripple is independent of

the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical

output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is

programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output

voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further

increases the output voltage even when the PMOS is off. This effect increases with low output voltages.

Input Capacitor Selection

A pulsating input current is the nature of the buck converter. Therefore, a low ESR input capacitor is required for

best input voltage filtering. It also minimizes the interference with other circuits caused by high input voltage

spikes. The main converter needs a 22-µF ceramic input capacitor and the core converter a 10-µF ceramic

capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF capacitor can

be used instead, because the two converters operate with a phase shift of 270 degrees. The input capacitor can

be increased without any limit for better input voltage filtering. The VCC pin should be separated from the input

for the main and the core converter. A filter resistor of up to 100 Ω and a 1-µF capacitor is used for decoupling

the VCC pin from switching noise.

Table 5. Possible Capacitors

CAPACITOR VALUE

CASE SIZE

1206

COMPONENT SUPPLIER

TDK C3216X5R0J226M

COMMENTS

Ceramic

22 µF

1206

Taiyo Yuden JMK316BJ226ML

Taiyo Yuden JMK325BJ226MM

Ceramic

1210

Ceramic

LDO1

Output Voltage Adjustment

The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must

not exceed 1 MR to minimize voltage changes due to leakage current into the feedback pin. The output voltage

for LDO1 after start-up is the voltage set by the external resistor divider. It can be reprogrammed with the I²C

interface to the three other values defined in the register VREGS1.

50

PACKAGE OPTION ADDENDUM

www.ti.com

19-May-2005

PACKAGING INFORMATION

Orderable Device

TPS65014RGZR

TPS65014RGZRG4

TPS65014RGZT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGZ

48

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RGZ

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS65014RGZTG4

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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型号：	TPS65014_15
厂家：	TEXAS INSTRUMENTS
描述：	Power- and Battery-Management IC 电池
文件：	总53页 (文件大小：1001K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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