TPS650244IRHBRQ1 [TI]
具有 3 个降压转换器和 3 个 LDO 的汽车类 1.5V 至 6.5V 电源管理 IC | RHB | 32 | -40 to 125;
| 型号： | TPS650244IRHBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 3 个降压转换器和 3 个 LDO 的汽车类 1.5V 至 6.5V 电源管理 IC | RHB | 32 | -40 to 125 转换器 |
| 文件： | 总34页 (文件大小：1408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
POWER MANAGEMENT ICs FOR Li-ION POWERED SYSTEMS
Check for Samples: TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
1
FEATURES
APPLICATIONS
•
•
•
•
•
PDA
•
•
Qualified for Automotive Applications
Cellular/Smart Phone
GPS
Digital Still Camera
Split Supply DSP and Microprocessor
Solutions: Samsung ARM-Based Processors,
etc.
1.6-A, 1.0-A or 0.8-A, 97% Efficient Step-Down
Converter for System Voltage (VDCDC1)
–
3.3-V or 2.80-V or Adjustable
•
1.6-A, 1.0-A or 0.8-A, up to 95% Efficient
Step-Down Converter for Memory Voltage
(VDCDC2)
–
1.8 V or 2.5 V or Adjustable
DESCRIPTION
•
•
0.8-A 90% Efficient Step-Down Converter for
Processor Core (VDCDC3)
The TPS65024x are integrated Power Management
ICs for applications powered by one Li-Ion or
Li-Polymer cell, which require multiple power rails.
The TPS65024x provide three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a
processor based system. All three step-down
converters enter a low power mode at light load for
maximum efficiency across the widest possible range
of load currents. The converters can be forced into
fixed frequency PWM mode by pulling the MODE pin
high. The TPS65024x also integrate two general
purpose 200-mA LDO voltage regulators, which are
enabled with an external input pin. Each LDO
operates with an input voltage range between 1.5 V
and 6.5 V, allowing them to be supplied from one of
the step-down converters or directly from the battery.
The output voltage of the LDOs can be set with an
external resistor divider for maximum flexibility.
Additionally there is a 30-mA LDO typically used to
provide power in a processor based system to a
voltage rail that is always on. TPS65024x provide
voltage scaling on DCDC3 using the DEFDCDC3 pin.
This pin either needs to be connected to a logic HIGH
or logic LOW level to set the output voltage of
DCDC3. TPS65024x come in a small 5-mm x 5-mm
32-pin QFN package (RHB).
Three Selectable Voltages for VDCDC3
–
–
–
TPS650241
–
–
DEFDCDC3 = LOW: VO = 0.9 V
DEFDCDC3 = HIGH: VO = 1.375 V
TPS650243
–
–
DEFDCDC3 = LOW: VO = 1.0 V
DEFDCDC3 = HIGH: VO = 1.2 V
TPS650244
–
–
DEFDCDC3 = LOW: VO = 1.55 V
DEFDCDC3 = HIGH: VO = 1.6 V
•
•
30-mA LDO for Vdd_alive
Two 200-mA General Purpose LDOs (LDO1
and LDO2)
•
Dynamic Voltage Management for Processor
Core
•
•
•
•
•
LDO1 and LDO2 Voltage Externally Adjustable
Separate Enable Pins for Inductive Converters
2.25-MHz Switching Frequency
85-μA Quiescent Current
Thermal Shutdown Protection
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS650241Q
TPS650241QRHBRQ1
TPS650243QRHBRQ1
TPS650244IRHBRQ1
–40°C to 125°C
–40°C to 85°C
QFN – RHB
Reel of 3000
TPS650243Q
TPS650244Q
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Input voltage range on all pins except A/PGND, VLDO1 and VLDO2 pins with respect to
AGND
–0.3 to 7
V
Voltage range on pins VLDO1 and VLDO2 with respect to AGND
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3
Peak current at all other pins
–0.3 to 3.6
V
2000
mA
mA
1000
See Dissipation Rating Table
–40 to 125
Continuous total power dissipation
TJ
Operating junction temperature
°C
°C
°C
Tst Storage temperature
–65 to 150
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
T
J ≤ 25°C
DERATING FACTOR
ABOVE TJ = 25°C
TJ = 70°C
POWER RATING
TJ = 85°C
POWER RATING
PACKAGE(1)
RθJA
POWER RATING
RHB
35°C/W
2.85 W
28 mW/°C
1.57 W
1.14 W
(1) The thermal resistance junction to ambient of the RHB package is measured on a high K board. The thermal resistance junction to
power pad is 1.5°C/W.
2
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
RECOMMENDED OPERATING CONDITIONS
MI NOM
N
MAX UNIT
VINDCDC1
VINDCDC2
,
,
2.5
6.0
V
Input voltage range step-down converters
VINDCDC3, VCC
VDCDC1
Output voltage range for VDCDC1 step-down converter(1)
Output voltage range for mem step-down converter(1)
Output voltage range for core step-down converter
Input voltage range for LDOs
0.6
0.6
0.9
1.5
VINDCDC1
VINDCDC2
1.5
V
V
V
V
VDCDC2
VDCDC3
VINLDO1
,
6.5
VINLDO2
VLDO1-2
Output voltage range for LDOs
Output current at L1
Inductor at L1(2)
1.0
3.3
V
IOUTDCDC1
L1
1600 mA
1.5
10
10
2.2
22
μH
(2)
CINDCDC1
COUTDCDC1
IOUTDCDC2
L2
Input capacitor at VINDCDC1
μF
(2)
Output capacitor at VDCDC1
μF
1600 mA
μH
Output current at L2
Inductor at L2(2)
1.5
10
10
2.2
22
(2)
CINDCDC2
COUTDCDC2
IOUTDCDC3
L3
Input capacitor at VINDCDC2
μF
(2)
Output capacitor at VDCDC2
μF
Output current at L3
Inductor at L3(2)
800 mA
μH
1.5
10
10
1
2.2
22
(2)
CINDCDC3
COUTDCDC3
CVCC
Input capacitor at VINDCDC3
μF
(2)
Output capacitor at VDCDC3
μF
Input capacitor at VCC(2)
μF
Cin1-2
Input capacitor at VINLDO(2)
Output capacitor at VLDO1, VLDO2(2)
Output current at VLDO1, VLDO2
Output capacitor at Vdd_alive(2)
Output current at Vdd_alive
1
μF
COUT1-2
ILDO1,2
2.2
μF
200 mA
μF
CVRTC
2.2
IVdd_alive
TA
30 mA
125 °C
85
Operating ambient temperature
TPS65024XQRHBRQ1
TPS650244IRHBRQ1
–40
–40
–40
TJ
Operating junction temperature
125 °C
RCC
Resistor from VINDCDC3,VINDCDC2, VINDCDC1 to Vcc used for filtering(3)
1
10
Ω
(1) When using an external resistor divider at DEFDCDC2, DEFDCDC1.
(2) See applications section for more information, for Vout > 2.85 V choose 3.3-μH inductor.
(3) Up to 2.5 mA can flow into Vcc when all three converters are running in PWM; this resistor causes the UVLO threshold to be shifted
accordingly.
Copyright © 2009–2011, Texas Instruments Incorporated
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3
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C
(unless otherwise noted)
CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE
PARAMETER
High level input
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
IH
1.45
VCC
V
voltage
Low level input
voltage
0
0.4
0.1
V
Input bias current
0.01
μA
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(qPFM)
Operating quiescent PFM All three dc-dc converters enabled, zero load Vcc = 3.6 V
135
75
170
100
μA
current
and no switching, LDOs enabled
PFM All three dc-dc converters enabled, zero load
and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON
PFM DCDC1 and DCDC2 converters enabled,
zero load and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON
55
80
60
PFM DCDC1 converter enabled, zero load and no
switching, LDO1, LDO2 = OFF, Vdd_alive = ON
40
2
IVCC(PWM)
Current into Vcc,
PWM
All three dc-dc converters enabled and running in
PWM, LDOs off
Vcc = 3.6 V
mA
PWM DCDC1 and DCDC2 converters enabled and
running in PWM, LDOs off
1.5
0.85
16
2.5
2.0
PWM DCDC1 converter enabled and running in
PWM, LDOs off
Iq
Quiescent current
All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = OFF
Vcc = 3.6 V
μA
All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = ON
26
4
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC1 STEP-DOWN CONVERTER
VVINDCDC1
IO
Input voltage range
2.5
1600
800
6.0
V
Maximum output current for TPS65024X VO = 3.3 V
Maximum output current for TPS650244 VO = 3.3 V
mA
IO
ISD
Shutdown supply current in VINDCDC1 EN_DCDC1 = GND
0.1
1
261
2
μA
mΩ
μA
mΩ
μA
A
RDS(ON)
ILP
RDS(ON)
ILN
P-channel MOSFET on-resistance
P-channel leakage current
VINDCDC1 = VGS = 3.6 V
125
VINDCDC1 = 6.0 V
VINDCDC1 = VGS = 3.6 V
VDS = 6.0 V
N-channel MOSFET on-resistance
N-channel leakage current
130
7
260
10
ILIMF
Forward current limit (P- and N-channel) 2.5V < VINMAIN < 6.0 V
1.7
1.97
2.2
for TPS65024X
ILIMF
Forward current limit (P- and N-channel) 2.5V < VINMAIN < 6.0 V
for TPS650244
0.88
1.10
2.25
1.28
fS
Oscillator frequency
1.95
–2%
–2%
–1%
–1%
–2%
2.55
2%
2%
1%
1%
2%
MHz
VDCDC1
Fixed output voltage
MODE = 0 (PWM/PFM)
2.80 V
3.3 V
VINDCDC1 = 3.3 V to 6.0 V;
0 mA ≤ IO ≤ 1.6A
Fixed output voltage
MODE = 1 (PWM)
2.80 V
3.3 V
VINDCDC1 = 3.7 V to 6.0 V;
0 mA ≤ IO ≤ 1.6 A
Adjustable output voltage with resistor
divider at DEFDCDC1 MODE = 0
(PWM/PFM)
VINDCDC1 = VDCDC1 + 0.4 V (min 2.5 V)
to 6.0 V; 0 mA ≤ IO ≤ 1.6 A
Adjustable output voltage with resistor
divider at DEFDCDC1; MODE = 1
(PWM)
VINDCDC1 = VDCDC1 + 0.4 V (min 2.5 V)
to 6.0 V; 0 mA ≤ IO ≤ 1.6 A
–1%
1%
Line regulation
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V)
to 6.0 V; IO = 10 mA
0.0
%/V
Load regulation
IO = 10 mA to 1.6 A
0.25
750
%/A
tSS
Soft start ramp time
VDCDC1 ramping from 5% to 95% of
target value
μs
R(L1)
Internal resistance from L1 to GND
1
MΩ
Copyright © 2009–2011, Texas Instruments Incorporated
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Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC2 STEP-DOWN CONVERTER
VVINDCDC2
IO
Input voltage range
2.5
1000
1600
6.0
V
Maximum output current for TPS65024X VO = 2.5 V
Maximum output current for TPS650244 VO = 2.5 V
mA
IO
ISD
Shutdown supply current in VINDCDC2 EN_DCDC2 = GND
0.1
1
300
2
μA
mΩ
μA
mΩ
μA
A
RDS(ON)
ILP
RDS(ON)
ILN
P-channel MOSFET on-resistance
P-channel leakage current
VINDCDC2 = VGS = 3.6 V
VINDCDC2 = 6.0 V
VINDCDC2 = VGS = 3.6 V
VDS = 6.0 V
140
N-channel MOSFET on-resistance
N-channel leakage current
150
7
297
10
ILIMF
Forward current limit (P- and N-channel) 2.5 V < VINDCDC2 < 6.0 V
for TPS65024X
1.22
1.50
1.35
1.50
ILIMF
Forward current limit (P- and N-channel) 2.5 V < VINDCDC2 < 6.0 V
for TPS650244
1.97
2.25
2.35
fS
Oscillator frequency
1.95
2.55
2%
MHz
VDCDC2
Fixed output voltage
MODE = 0 (PWM/PFM)
1.8V
2.5V
1.8V
2.5V
VINDCDC2 = 2.5 V to 6.0 V;
0 mA ≤ IO ≤ 1.6 A
–2%
VINDCDC2 = 3.0 V to 6.0 V;
0 mA ≤ IO ≤ 1.6 A
–2%
–2%
–1%
–2%
2%
2%
1%
2%
Fixed output voltage
MODE = 1 (PWM)
VINDCDC2 = 2.5 V to 6.0 V;
0 mA ≤ IO ≤ 1.6 A
VINDCDC2 = 3.0 V to 6.0 V;
0 mA ≤ IO ≤ 1.6 A
Adjustable output voltage with resistor
divider at DEFDCDC2 MODE = 0
(PWM)
VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V)
to 6.0 V; 0 mA ≤ IO ≤ 1.6 A
Adjustable output voltage with resistor
divider at DEFDCDC2; MODE = 1
(PWM)
VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V)
to 6.0 V; 0 mA ≤ IO ≤ 1.6 A
–1%
1%
Line regulation
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V)
to 6.0 V; IO = 10 mA
0.0
%/V
Load regulation
IO = 10 mA to 1.6 A
0.25
750
%/A
tSS
Soft start ramp time
VDCDC2 ramping from 5% to 95% of
target value
μs
R(L2)
Internal resistance from L2 to GND
1
MΩ
6
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.0
1
UNIT
VDCDC3 STEP-DOWN CONVERTER
VVINDCDC3
Input voltage range
2.5
V
IO
Maximum output current
VO = 1.6 V
800
mA
μA
ISD
Shutdown supply current in
VINDCDC3
EN_DCDC3 = GND
0.1
RDS(ON)
ILP
RDS(ON)
ILN
P-channel MOSFET on-resistance
P-channel leakage current
VINDCDC3 = VGS = 3.6 V
VINDCDC3 = 6.0V
VINDCDC3 = VGS = 3.6 V
VDS = 6.0 V
310
0.1
220
7
698
2
mΩ
μA
mΩ
μA
A
N-channel MOSFET on-resistance
N-channel leakage current
503
10
ILIMF
Forward current limit (P- and
N-channel)
2.5 V < VINDCDC3 < 6.0 V
1.00
1.20
1.40
fS
Oscillator frequency
1.95
2.25
2.55
2%
MHz
VDCDC3
Fixed output voltage VO = 0.9V to VINDCDC3 = 2.5 V to 6.0 V;
–2%
MODE = 0
1.6V
0 mA ≤ IO ≤ 800 mA
(PWM/PFM)
Fixed output voltage
MODE = 1 (PWM)
–1%
1%
Line regulation
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to
6.0 V; IO = 10 mA
0.0
%/V
Load regulation
IO = 10 mA to 600 mA
0.25
750
%/A
tSS
Soft start ramp time
VDCDC3 ramping from 5% to 95% of target
value
μs
R(L3)
Internal resistance from L3 to GND
1
MΩ
Copyright © 2009–2011, Texas Instruments Incorporated
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7
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 Low Dropout Regulators
I(q)
I(SD)
VINLDO
VFB
IO
Operating quiescent current
Current per LDO into VINLDO
16
30
2
μA
μA
V
Shutdown current
Total current into VINLDO, VLDO = 0 V
0.6
Input voltage range for LDO1, LDO2
LDO1 and LDO2 feedback voltage
Maximum output current for LDO1, LDO2
Maximum output current for LDO1, LDO2
LDO1 & LDO2 short circuit current limit
Minimum voltage drop at LDO1, LDO2
Minimum voltage drop at LDO1, LDO2
Minimum voltage drop at LDO1, LDO2
Output voltage accuracy for LDO1, LDO2
Line regulation for LDO1, LDO2
1.5
6.5
(1)
See
1.0
V
Vin = 1.8 V, Vo = 1.3 V
Vin = 1.5 V; Vo = 1.3 V
VLDO1 = GND, VLDO2 = GND
IO = 50 mA, VINLDO = 1.8 V
IO = 50 mA, VINLDO = 1.5 V
IO = 200 mA, VINLDO = 1.8 V
IO = 10 mA
200
mA
mA
mA
mV
mV
mV
IO
120
ISC
400
120
150
300
1%
65
–2%
–1%
VINLDO1,2 = VLDO1,2 + 0.5 V (min 2.5 V) to 6.5 V,
IO = 10 mA
1%
Load regulation for LDO1, LDO2
Regulation time for LDO1, LDO2
IO = 0 mA to 200 mA
–1%
1%
Load change from 10% to 90%
10
μs
Vdd_alive Low Dropout Regulator
Vdd_alive
Vdd_alive LDO output voltage
IO = 0 mA
1.2
V
IO
Output current for Vdd_alive
30
100
1 %
1 %
mA
mA
ISC
Vdd_alive short circuit current limit
Output voltage accuracy for Vdd_alive
Line regulation for Vdd_alive
Vdd_alive = GND
IO = 0mA
–1%
–1%
VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0 mA
Load change from 10% to 90%
Regulation time for Vdd_alive
10
μs
AnaLogic Signals DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
VIL
IH
High level input voltage
Low level input voltage
Input bias current
1.3
0
VCC
0.1
V
V
0.001
0.05
μA
THERMAL SHUTDOWN
TSD Thermal shutdown
Thermal shutdown hysteresis
INTERNAL UNDER VOLTAGE LOCK OUT
Increasing junction temperature
Decreasing junction temperature
160
20
°C
°C
UVLO
Internal UVLO
VCC falling
–3%
2.35
120
3%
V
VUVLO_HYST
Internal UVLO comparator hysteresis
mV
VOLTAGE DETECTOR COMPARATOR
PWRFAIL_SNS Comparator threshold
Hysteresis
Falling threshold
–2%
1.0
50
2%
60
V
mV
μs
V
40
Propagation delay
25-mV overdrive
IOL = 5 mA
10
VOL
Power fail output low voltage
0.3
(1) If the feedback voltage is forced higher than 1.2 V, a leakage current into the feedback pin may occur.
8
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Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
DEVICE INFORMATION
PIN ASSIGNMENTS
32 31 30 29 28 27 26 25
24
23
22
21
VDCDC3
PGND3
L3
EN_Vdd_alive
MODE
1
2
3
4
5
6
7
8
DEFDCDC2
PWRFAIL
VINDCDC3
VINDCDC1
L1
20
19
EN_DCDC1
EN_DCDC2
EN_DCDC3
EN_LDO
18
17
PGND1
VDCDC1
9 10 11 12 13 14 15 16
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
SWITCHING REGULATOR SECTION
AGND1
31
13
–
Analog ground connection. All analog ground pins are connected internally on the chip.
Analog ground connection. All analog ground pins are connected internally on the chip.
Connect the power pad to analog ground.
AGND2
PowerPad
VINDCDC1
5
I
Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as
VINDCDC2, VINDCDC3 and VCC.
L1
6
8
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
VDCDC1 feedback voltage sense input, connect directly to VDCDC1
Power ground for VDCDC1 converter
VDCDC1
PGND1
VINDCDC2
I
I
7
28
Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as
VINDCDC1, VINDCDC3 and VCC.
L2
27
25
26
4
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
VDCDC2 feedback voltage sense input, connect directly to VDCDC2
Power ground for VDCDC2 converter
VDCDC2
PGND2
VINDCDC3
I
I
Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as
VINDCDC1, VINDCDC2 and VCC.
L3
3
1
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
VDCDC3 feedback voltage sense input, connect directly to VDCDC3
Power ground for VDCDC3 converter
VDCDC3
PGND3
Vcc
I
2
29
I
I
Power supply for digital and analog circuitry of DCDC1, DCDC2 and DCDC3 DC-DC converters. This must be
connected to the same voltage supply as VINDCDC3, VINDCDC1 and VINDCDC2.
DEFDCDC1
DEFDCDC2
9
Input signal indicating default VDCDC1 voltage, 0 = 2.80 V, 1 = 3.3 V
This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output
voltage of the DCDC1 converter can be set in a range from 0.6 V to VINDCDC1.
22
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V
This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output
voltage of the DCDC2 converter can be set in a range from 0.6 V to VINDCDC2.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
DEFDCDC3
32
I
Input signal indicating VDCDC3 voltage.
TPS650241: 0 = 0.9 V, 1 = 1.375 V
TPS650243: 0 = 1.0 V, 1 = 1.2 V
TPS650244: 0 = 1.55 V, 1 = 1.6 V
EN_DCDC1
EN_DCDC2
EN_DCDC3
20
19
18
I
I
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO
15
16
14
17
24
12
11
10
I
O
O
I
Input voltage for LDO1 and LDO2
VLDO1
Output voltage of LDO1
VLDO2
Output voltage of LDO2
EN_LDO
EN_Vdd_alive
Vdd_alive
FB_LDO1
FB_LDO2
Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs
Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO
Output voltage for Vdd_alive
I
O
I
Feedback pin for LDO1
I
Feedback pin for LDO2
CONTROL AND I2C SECTION
MODE
23
I
Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe
Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is
selected. If Pin has low level, then Device operates in Power Safe Mode.
PWRFAIL
21
30
O
I
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
Input for the comparator driving the /PWRFAIL output
PWRFAIL_SNS
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SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
FUNCTIONAL BLOCK DIAGRAM
TPS650240
1R
VCC
Vbat
Vbat
1mF
VINDCDC1
L1
3.3V or 2.8V
DCDC1 (I/O)
2.2mH
10mF
VDCDC1
R1
22 mF
STEP-DOWN
CONVERTER
1000 mA
DEFDCDC1
PGND1
EN_DCDC1
VINDCDC2
ENABLE
R2
2.5V or 1.8V
L2
Vbat
DCDC2
(memory)
2.2mH
10mF
R3
VDCDC2
DEFDCDC2
PGND2
22 mF
STEP-DOWN
CONVERTER
800 mA
EN_DCDC2
VINDCDC3
ENABLE
R4
1.0V or 1.3V
22mF
L3
Vbat
DCDC3 (core)
2.2uH
10mF
VDCDC3
STEP-DOWN
CONVERTER
800 mA
DEFDCDC3
EN_DCDC3
1.0V / 1.3V
ENABLE
PGND3
MODE
PWM / PFM
VIN_LDO
EN_LDO
VIN
VLDO1
VLDO1
R5
R6
2.2mF
200 mA LDO
ENABLE
VLDO2
VLDO2
2.2mF
R7
R8
200 mA LDO
EN_Vdd_aliv
e
ENABLE
Vdd_alive
1.2 V
VLDO3
30 mA LDO
VCC
Vbat
2.2mF
R9
I/O voltage
R19
PWRFAIL _SNS
-
PWRFAIL
R10
+
Vref = 1 V
AGND1
AGND2
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TYPICAL CHARACTERISTICS
Parameter Measurement Information
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER
DCDC1
INDUCTOR
VLCF4020-3R3
VLCF4020-2R2
LPS3010-222
OUTPUT CAPACITOR
C2012X5R0J226M
C2012X5R0J226M
C2012X5R0J226M
OUTPUT CAPACITOR VALUE
22 μF
22 μF
22 μF
DCDC2
DCDC3
Table of Graphs
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
η
η
η
η
η
η
Efficiency VDCDC1
Efficiency VDCDC1
Efficiency VDCDC2
Efficiency VDCDC2
Efficiency VDCDC3
Efficiency VDCDC3
vs Load current PWM/PFM; VO = 3.3 V
vs Load current PWM; VO = 3.3 V
vs Load current PWM/PFM; VO = 1.8 V
vs Load current PWM; VO = 1.8 V
vs Load current PWM/PFM; VO = 1.3 V
vs Load current PWM; VO = 1.3 V
Line transient response VDCDC1
Line transient response VDCDC2
Line transient response VDCDC3
Load transient response VDCDC1
Load transient response VDCDC2
Load transient response VDCDC3
Output voltage ripple DCDC2; PFM mode
Output voltage ripple DCDC2; PWM mode
Load regulation for Vdd_alive
Start-up VDCDC1 to VDCDC3
Start-up LDO1 and LDO2
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SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
DCDC1: EFFICIENCY
vs
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
90
T
= 25°C,
A
90
80
70
60
50
V
= 3.3 V,
O
PWM Mode
V = 3.8 V
I
V = 4.2 V
I
80
70
60
50
V = 5 V
I
V = 3.8 V
I
V = 4.2 V
I
40
30
40
30
20
V = 5 V
I
T
= 25°C,
20
A
V
= 3.3 V,
O
PFM/PWM Mode
10
0
10
0
0.1
1
10 100
- Output Current - mA
1k
10k
0.1
1
10 100
- Output Current - mA
1k
10k
I
I
O
O
Figure 1.
Figure 2.
DCDC2: EFFICIENCY
vs
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
V = 2.5 V
I
V = 3.8 V
I
V = 3.8 V
I
V = 4.2 V
I
V = 2.5 V
V = 4.2 V
I
I
V = 5 V
I
V = 5 V
I
= 25oC
= 1.8 V
T
= 25oC
= 1.8 V
T
A
A
V
V
O
PWM Mode
O
PWM / PFM Mode
0.01
0.1
1
10
100
1 k
10 k
0.01
0.1
1
10
100
1 k
10 k
I
- Output Current - mA
I
- Output Current - mA
O
O
Figure 3.
Figure 4.
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DCDC3: EFFICIENCY
vs
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
90
100
T
= 25°C,
A
T
= 25°C,
A
V
= 1.5 V,
90
80
70
60
50
40
30
20
O
PWM/PFM Mode
V
= 1.5 V,
O
PWM Mode
80
70
60
50
40
30
20
V = 2.5 V
I
V = 3 V
I
V = 2.5 V
I
V = 3.8 V
I
V = 3 V
I
V = 4.2 V
I
V = 3.8 V
I
V = 5 V
I
V = 4.2 V
I
V = 5 V
I
10
0
10
0
0.01
1 10
- Output Current - mA
100
1k
0.1
0.1
0.01
1
10
- Output Current - mA
100
1k
I
O
I
O
Figure 5.
Figure 6.
VDCDC1 LINE TRANSIENT RESPONSE
VDCDC2 LINE TRANSIENT RESPONSE
Ch1 = V
I
Ch1 = V
I
Ch2 = V
O
Ch2 = V
O
I
= 100 mA
O
I
= 100 mA
O
V = 3 V to 4 V
I
V = 3.8 V to 4.5 V
I
V
= 1.8 V
O
V
= 3.3 V
O
PWM Mode
Figure 7.
Figure 8.
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SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
VDCDC3 LINE TRANSIENT RESPONSE
VDCDC1 LOAD TRANSIENT RESPONSE
Ch1 = V
I
Ch1 = V
I
Ch2 = V
O
Ch2 = V
O
I
= 160 mA to 14000 mA
I
= 100 mA
O
O
V = 3.3 V
V = 3 V to 4 V
I
I
V
= 1.375 V
V
= 4.2 V
O
O
Figure 9.
Figure 10.
VDCDC2 LOAD TRANSIENT RESPONSE
VDCDC3 LOAD TRANSIENT RESPONSE
Ch4 = I
O
Ch4 = I
O
Ch2 = V
O
Ch2 = V
O
I
= 80 mA to 720 mA
= 1.375 V
O
V
I
= 100 mA to 900 mA
= 1.8 V
O
O
V
O
Figure 11.
Figure 12.
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VDCDC2 OUTPUT VOLTAGE RIPPLE
VDCDC2 OUTPUT VOLTAGE RIPPLE
I
= 1 mA
T
= 25oC
A
V = 3.8 V
O
V = 3.8 V
I
I
V
I
= 1.8 V
V
= 1.8 V
O
O
PFM Mode
= 1 mA
= 25oC
O
T
A
PWM Mode
Figure 13.
Figure 14.
VDD_ALIVE OUTPUT VOLTAGE
vs
OUTPUT CURRENT
STARTUP VDCDC1, VDCDC2, VDCDC3
1.26
1.24
1.22
ENABLE
V
= 3.6 V
CC
VDCDC1
1.2
VDCDC2
VDCDC3
1.18
1.16
1.14
0
5
10
15
20
25
30 35
40
45
I
- Output Current - mA
O
Figure 15.
Figure 16.
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SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
STARTUP LDO1 AND LDO2
ENABLE
LDO1
LDO2
Figure 17.
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DETAILED DESCRIPTION
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2 AND VDCDC3
The TPS65024x incorporate three synchronous step-down converters operating typically at 2.25MHz fixed
frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the
converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).
VDCDC1 delivers up to 1.6A, VDCDC2 is capable of delivering up to 1.0A of output current while the VDCDC3
converter is capable of delivering up to 800mA.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
pins can either be connected to GND, VCC or to a resistor divider between the output voltage and GND. The
VDCDC1 converter defaults to 2.80V or 3.3V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is
tied to ground the default is 2.80V, if it is tied to VCC the default is 3.3V. When the DEFDCDC1 pin is connected
to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. Reference the section
on Output Voltage Selection for details on setting the output voltage range.
The VDCDC2 converter defaults to 1.8V or 2.5V depending on the DEFDCDC2 configuration pin, if DEFDCDC2
is tied to ground the default is 1.8V, if it is tied to VCC the default is 2.5V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.0V or 1.3V for the TPS650240 depending on the DEFDCDC3 configuration
pin, if DEFDCDC3 is tied to ground the default is 1.0V, if it is tied to VCC the default is 1.3V. The DEFDCDC3
pin cannot be connected to a resistor divider. In opposition to DEFDCDC1 and DEFDCDC2, the DEFDCDC3 pin
can be used to change the core voltage during operation by changing its logic level from HIGH to LOW or vice
versa. TPS65024x allow different voltages for the VDCDC3 converter. See Table 4 for the default voltage
options.
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier
is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The three DC/DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7V to 3.3V, the VDCDC2
converter from 3.7V to 2.5V and the VDCDC3 converter from 3.7V to 1.5V.
POWER SAVE MODE OPERATION
As the load current decreases, the converters enter Power Save Mode operation. During Power Save Mode the
converters operate in a burst mode (PFM mode) with a frequency between 1.125MHz and 2.25MHz for one burst
cycle. However, the frequency between different burst cycles depends on the actual load current and is typically
far less than the switching frequency, with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold
to enter Power Save Mode can be calculated as follows:
VINDCDC 1
I
+
PFMDCDC1enter
24 W
VINDCDC 2
I
+
PFMDCDC2enter
26 W
VINDCDC 3
+
I
PFMDCDC3leave
39 W
(1)
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During Power Save Mode the output voltage is monitored with a comparator and by maximum skip burst width.
As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the
converter effectively delivers a constant current as defined below.
VINDCDC 1
I
+
+
+
PFMDCDC1leave
18 W
VINDCDC 2
I
PFMDCDC2leave
20 W
VINDCDC 3
I
PFMDCDC3enter
29 W
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. The output voltage drops 2% below the nominal VO due to increased load current
2. The PFM burst time exceeds 16 × 1/fs (7.1μs typical)
These control methods reduce the quiescent current to typically 14μA per converter and the switching activity to
a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a very low output voltage ripple. The ripple depends on the
comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend
to zero. Power Save Mode can be disabled by pulling the MODE pin high. This forces all DC/DC converters into
fixed frequency PWM mode.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start
time is typically 750μs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already pre-charged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170μs between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is pre-charged, and if so, to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65024x converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load
current and output voltage and can be calculated as:
ǒRDSon
LǓ
Vin
+ Vout
) Iout
) R
max
max
min
min
(3)
With:
Ioutmax = Maximum load current (note: ripple current in the inductor is zero under these conditions)
RDSonmax = Maximum P-channel switch RDSon
RL = DC resistance of the inductor
Voutmin = Nominal output voltage minus 2% tolerance limit
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LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of
300mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the
EN_LDO pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external
regulators in parallel in systems with a backup battery. The TPS65024x step-down and LDO voltage regulators
automatically power down when the Vcc voltage drops below the UVLO threshold or when the junction
temperature rises above 160°C.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the five regulators on the TPS65024x prevents the device from
malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and
LDOs. The UVLO circuit monitors the Vcc pin; the threshold is set internally to 2.35V with 5% (120mV)
hysteresis. Note that when any of the DC/DC converters are running there is an input current at the Vcc pin,
which can be up to 3mA when all three converters are running in PWM mode. This current needs to be taken
into consideration if an external RC filter is used at the Vcc pin to remove switching noise from the TPS65024x
internal analog circuitry supply. See the Vcc-Filter section for details on the external RC filter.
POWER-UP SEQUENCING
The TPS65024x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved
simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1
and LDO2. The relevant control pins are described in Table 1.
Table 1. Control Pins for DCDC Converters
INPUT/
OUTPUT
PIN NAME
FUNCTION
DEFDCDC3
DEFDCDC2
I
I
Defines the default voltage of the VDCDC3 switching converter. See Table 4 for details.
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8V,
DEFDCDC2 = VCC defaults VDCDC2 to 2.5V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 2.80V,
DEFDCDC1 = VCC defaults VDCDC1 to 3.3V.
EN_DCDC3
EN_DCDC2
EN_DCDC1
I
I
I
Set EN_DCDC3 = 0 to disable or EN_DCDC3 = 1 to enable the VDCDC3 converter
Set EN_DCDC2 = 0 to disable or EN_DCDC2 = 1 to enable the VDCDC2 converter
Set EN_DCDC1 = 0 to disable or EN_DCDC1 = 1 to enable the VDCDC1 converter
PWRFAIL
The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is
compared to a 1V threshold (falling edge) with 5% (50mV) hysteresis. PWRFAIL is an open drain output which is
actively low when the input voltage at PWRFAIL_SNS is below the threshold.
DESIGN PROCEDURE
Inductor Selection for the dcdc Converters
The three converters operate with 2.2µH output inductors. Larger or smaller inductor values can be used to
optimize performance of the device for specific conditions. The selected inductor has to be rated for its dc
resistance and saturation current. The dc resistance of the inductor influences directly the efficiency of the
converter. Therefore, an inductor with the lowest dc resistance should be selected for the highest efficiency.
For a fast transient response, a 2.2μH inductor in combination with a 22μF output capacitor is recommended. For
an output voltage above 2.8V, an inductor value of 3.3μH minimum is required. Lower values result in an
increased output voltage ripple in PFM mode. The minimum inductor value is 1.5μH, but an output capacitor of
22μF minimum is needed in this case.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
20
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www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
Vout
Vin
L ƒ
1 *
DI
L
DI + Vout
I
+ I
)
outmax
L
Lmax
2
(4)
With:
f = Switching frequency (2.25MHz typical)
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consideration must be given to the difference in the core material from inductor to
inductor which has an impact on efficiency especially at high switching frequencies. See Table 2 and the typical
applications for possible inductors.
Table 2. Tested Inductors
INDUCTOR
VALUE
COMPONENT
SUPPLIER
DEVICE
TYPE
3.3μH
2.2μH
3.3μH
2.2μH
2.2μH
2.2μH
2.2μH
LPS3015-332 (output current up to 1A)
LPS3015-222 (output current up to 1A)
VLCF4020T-3R3N1R5
VLCF4020T-2R2N1R7
LPS3010-222
Coilcraft
Coilcraft
TDK
TDK
Coilcraft
Coilcraft
TDK
DCDC3 converter
LPS3015-222
VLCF4020-2R2
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the
TPS65024x allows the use of small ceramic capacitors with a typical value of 10uF for each converter, without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. Refer to Table 3 for recommended
components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. For completeness, the RMS ripple current is calculated as:
Vout
1 *
Vin
1
I
+ Vout
RMSCout
Ǹ
L ƒ
2 3
(5)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
Vout
1 *
Vin
1
ǒ
) ESRǓ
DVout + Vout
L ƒ
8 Cout ƒ
(6)
Where the highest output voltage ripple occurs at the highest input voltage, Vin.
At light load currents the converters operate in Power Save Mode and output voltage ripple is dependent on the
output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Typical output voltage ripple is less than 1% of the nominal output voltage.
Copyright © 2009–2011, Texas Instruments Incorporated
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TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing interference with other circuits caused by high input
voltage spikes. Each dcdc converter requires a 10uF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor can be increased without any limit for better input voltage filtering. The Vcc pin should be
separated from the input for the DC/DC converters. A filter resistor of up to 10Ω and a 1μF capacitor should be
used for decoupling the Vcc pin from switching noise. Note that the filter resistor may affect the UVLO threshold
since up to 3mA can flow via this resistor into the Vcc pin when all converters are running in PWM mode.
Table 3. Possible Capacitors
CAPACITOR
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
VALUE
22μF
22μF
22μF
22μF
10μF
10μF
1206
1206
0805
0805
0805
0805
TDK
C3216X5R0J226M
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Taiyo Yuden JMK316BJ226ML
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK
C2012X5R0J106M
Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 4 for the default voltages if the pins are pulled to GND or to Vcc.
Table 4. Voltage Options
PIN
LEVEL
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
DEFAULT OUTPUT VOLTAGE
DEFDCDC1
DEFDCDC2
DEFDCDC3
All versions
All versions
TPS650241
TPS650243
TPS650244
3.3V
2.80V
2.5V
1.8V
1.375V
0.9V
1.2V
1.0V
1.55V
1.6V
If a different voltage is needed, an external resistor divider can be added to the DEFDCDC1 or DEFDCDC2 pin
as shown below:
10 R
V
V
bat
CC
1 mF
VDCDC1
L1
V
VINDCDC1
OUT
L
C
IN
C
OUT
R1
R2
EN_DCDC1
AGND
DEFDCDC1
PGND
When a resistor divider is connected to DEFDCDC1 or DEFDCDC2, the output voltage can be set from 0.6V up
to the input voltage Vbat. The total resistance (R1+R2) of the voltage divider should be kept in the 1MΩ range in
order to maintain a high efficiency at light load. VDEFDCDCx = 0.6V
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www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
V
R1 ) R2
OUT
V
+ V
DEFDCDCx
ǒ Ǔ* R2
R1 + R2
OUT
R2
V
DEFDCDCx
Voltage Change on VDCDC3
The output voltage of VDCDC3 can be changed during operation from, for example, 0.9V to 1.375V
(TPS650241) and back. While the output voltage at VDCDC1 and VDCDC2 is fixed after the device exits
undervoltage lockout (UVLO), the status of the DEFDCDC3 pin is sensed during operation and the voltage is
changed as soon as the logic level on this pin changes from low to high or vice versa. Therefore it is not possible
to connect a resistor divider to DEFDCDC3 and set a voltage different from the predefined voltages.
Vdd_alive Output
The Vdd_alive LDO is typically connected to the Vdd_alive input of the Samsung application processor. It
provides an output voltage of 1.2V at 30mA. For the TPS650245, the output voltage is 1.1V. It is recommended
to add a capacitor of 2.2μF minimum to the Vdd_alive pin. The LDO can be disabled by pulling the
EN_Vdd_alive pin to GND.
LDO1 and LDO2
The LDOs in the TPS65024x are general purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2μF. The LDOs output voltage can be changed to different voltages
between 1.0V and Vin using an external resistor divider. Therefore they can also be used as general purpose
LDOs in the application. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the
flexibility to connect the lowest voltage available in the system and therefore providing the highest efficiency.
The total resistance (R5+R6) of the voltage divider should be kept in the 1MΩ range in order to maintain high
efficiency at light load. VFBLDOx= 1.0V.
V
R5 ) R6
OUT
V
+ V
FBLDOx
ǒ Ǔ* R6
R5 + R6
OUT
R6
V
FBLDOx
Vcc-Filter
An RC filter connected at the Vcc input is used to keep noise from the internal supply for the bandgap and other
analog circuitry. A typical value of 1Ω and 1μF is used to filter the switching spikes, generated by the DC/DC
converters. A larger resistor than 10Ω should not be used because the current into Vcc of up to 2.5mA causes a
voltage drop at the resistor causing the undervoltage lockout circuitry connected at Vcc internally to switch off too
early.
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TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
www.ti.com
APPLICATION INFORMATION
TYPICAL CONFIGURATION FOR THE TITAN 2 PROCESSOR
The core voltage is generated using DCDC2 with the output voltage set to 1.2V using a resistor divider at
DEFDCDC2 as only DCDC2 can support an output current of up to 1.6A. DCDC3 is used for the memory voltage
of 1.8V. As DCDC3 does not support an external resistor divider, the output voltage is programmed to 1.6V by
setting DEFDCDC3 = HIGH. In addition, there is a resistor at the input of the internal voltage divider at pin
VDCDC3 which adds another 200mV. The internal resistance at VDCDC3 when programmed to 1.6V is 480kΩ,
so the external resistance needed to increase the output voltage from 1.6V to 1.8V is 60kΩ (62kΩ). The typical
configuration for the Titan 2 processor is shown in Figure 18.
Vcc
VIN
1mF
Titan
TPS650244
VINDCDC1
VIN
10mF
3.3mH
LPS3015
L1
(3.3V)
VDDIO
VINDCDC2
DCDC1
800mA
VIN
VIN
10mF
10mF
VDCDC1
2.2mH
VINDCDC3
LPS3015
L3
(1.8V)
VDD _MEM
10mF
DCDC3
800mA
62kW
22mF
VDCDC3
DEFDCDC1
VIN
VIN
DEFDCDC3
(set to1.8V)
VLCF4020
2.2mH
L2
core (1.2V)
DCDC2
1600mA
VDCDC2
VDCDC2
LDO2
22mF
220kW
220kW
DEFDCDC2
(3.3V)
RTC I /O
LDO2
300kW
FB_LDO2
2.2mF
200mA
EN_DCDC1
130kW
EN_DCDC2
EN_DCDC3
LDO1
RTC core
(1.2V)
LDO1
100kW
2.2mF
200mA
FB_LDO1
510kW
VINLDO1/2
VIN
mF
1
Vdd_alive 1.2V
VIO
(not used)
open
EN_LDO1/2
EN_VDDalive
1MW
POWERFAIL
PWRFAIL_SNS
Input Voltage
TBD
-
+
Figure 18. Titan Processor Configuration
24
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Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1
TPS650241-Q1, TPS650243-Q1, TPS650244-Q1
www.ti.com
SLVS994A –SEPTEMBER 2009–REVISED MARCH 2011
TYPICAL CONFIGURATION FOR THE SAMSUNG PROCESSOR S3C6400-533MHz
The typical configuration for the Samsung processor S3C6400-533MHz is shown in Figure 19.
S3C6400-
Vcc
533MHz
VIN
TPS650245
1mF
VDDEXT (3.3V)
VDDMMC (3.3V)
VDDHI (3.3V)
3.3mH
L1
VINDCDC1
VIN
VIN
DCDC1
10mF
10mF
10mF
VDDLCD (3.3V)
VDDPCM (3.3V)
1000mA
VDCDC1
VINDCDC2
VDDSYS (3.3V)
2.2mH
L2
10mF
VDD_MEM0 (1.8V)
VDD_MEM1 (1.8V)
DCDC2
800mA
VINDCDC3
VDCDC2
VIN
10mF
2.2mH
L3
VDDARM (0.9V/1.1V)
DCDC3
800mA
DEFDCDC1
DEFDCDC2
VIN
VDCDC3
LDO2
10mF
VDDADC (3.3V)
VDDDAC (3.3V)
300kW
LDO2
2.2mF
200mA
FB_LDO2
VDDOTG (3.3V)
VDDUH (3.3V)
DEFDCDC3
EN_DCDC1
130kW
0.9V/1.1V
LDO1
VDDOTGI (1.1V)
LDO1
EN_DCDC2
EN_DCDC3
33kW
2.2mF
200mA
FB_LDO1
330kW
VINLDO1/2
VIN
1
mF
Vdd_alive 1.1V
VDDALIVE
EN_LDO1/2
EN_VDDalive
1mF
VIO
VIN VIN
1MW
R2
PWRFAIL
PWRFAIL_SNS
-
R3
+
1V
APLL (1.0V)
EPLL (1.0V)
MPLL (1.0V)
VDDINT (1.0V)
GND
AGND , PowerPAD
2.2mH
VIN
VIN
SW
EN
100kW
150kW
10mF
10mF
TPS62260
EN
22pF
FB
MODE
GND
Figure 19. Samsung Processor Configuration
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS650241QRHBRQ1
TPS650243QRHBRQ1
TPS650244IRHBRQ1
ACTIVE
VQFN
VQFN
VQFN
RHB
32
32
32
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
TPS
650241Q
ACTIVE
ACTIVE
RHB
NIPDAU
NIPDAU
TPS
650243Q
RHB
TPS
650244Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS650241-Q1, TPS650243-Q1, TPS650244-Q1 :
Catalog: TPS650241, TPS650243, TPS650244
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS650241QRHBRQ1
TPS650243QRHBRQ1
TPS650244IRHBRQ1
VQFN
VQFN
VQFN
RHB
RHB
RHB
32
32
32
3000
3000
3000
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
1.5
1.5
1.5
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS650241QRHBRQ1
TPS650243QRHBRQ1
TPS650244IRHBRQ1
VQFN
VQFN
VQFN
RHB
RHB
RHB
32
32
32
3000
3000
3000
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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