TPS65052QRSMRQ1_技术文档

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

www.ti.com

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS

AND 4 LOW-INPUT-VOLTAGE LDOs

, TPS65051-Q1

1

FEATURES

•

Two General-Purpose 200-mA, High-PSRR

LDOs

2

•

Qualified for Automotive Applications

•

V_IRange for LDOs from 1.5 V to 6.5 V

Digital Voltage Selection for the LDOs

AEC-Q100 Qualified With the Following

Results:

Available in a 4-mm × 4-mm 32-Pin QFN

Package

–

Device Temperature Grade 1: –40°C to

125°C Ambient Operating Temperature

Range

APPLICATIONS

–

Device HBM ESD Classification Level H2

Device CDM ESD Classification Level C3B

Automotive

•

Up To 95% Efficiency

DESCRIPTION

Output Current for DC-DC Converters:

The TPS6505x-Q1 devices are integrated power-

management ICs for applications powered by one Li-

Ion or Li-Polymer cell, which require multiple power

rails. The TPS6505x-Q1 provides two efficient, 2.25-

MHz step-down converters targeted at providing the

core voltage and I/O voltage in a processor-based

system. Both step-down converters enter a low-power

mode at light load for maximum efficiency across the

widest possible range of load currents.

–

TPS65050-Q1: 2 × 0.6 A

TPS65051-Q1: DCDC1 = 1 A; DCDC2 = 0.6 A

TPS65052-Q1: DCDC1 = 1 A; DCDC2 = 0.6 A

TPS65054-Q1: 2 × 0.6 A

TPS65056-Q1: DCDC1 = 1 A; DCDC2 = 0.6 A

•

Output Voltages for DC-DC Converters:

–

TPS65050-Q1: Externally Adjustable

TPS65051-Q1: Externally Adjustable

For low-noise applications, the user can force the

devices into fixed-frequency PWM mode by pulling

the MODE pin high. Operating in the shutdown mode

reduces the current consumption to less than 1 μA.

The devices allow the use of small inductors and

capacitors to achieve a small solution size. The

TPS6505x-Q1 provides an output current of up to 1 A

on each dc-dc converter. The TPS6505x-Q1 also

integrates two 400-mA LDO and two 200-mA LDO

voltage regulators, which one can turn on or off using

separate enable pins on each LDO. Each LDO

operates with an input voltage range between 1.5 V

and 6.5 V, allowing their supply to be from one of the

step-down converters or directly from the main

battery.

TPS65052-Q1: DCDC1 = Fixed at 3.3 V;

DCDC2 = 1 V or 1.3 V for Samsung

Application Processors

–

TPS65054-Q1: DCDC1 = Externally

Adjustable; DCDC2 = 1.3 V or 1.05 V for

OMAP™1710 Processor

TPS65056-Q1: DCDC1 = Fixed at 3.3 V;

DCDC2 = 1 V or 1.3 V for Samsung

Application Processors

•

V_IRange for DC-DC Converters

From 2.5 V to 6 V

•

2.25-MHz Fixed-Frequency Operation

Power-Save Mode at Light Load Current

180° Out-of-Phase Operation

Four digital input pins set the output voltage of the

LDOs from a set of 16 different combinations for

LDO1 to LDO4 on TPS65050-Q1 and TPS65052-Q1.

In TPS65051-Q1, TPS65054-Q1, and TPS65056-Q1,

the LDO voltages are adjustable using external

resistor dividers.

Output-Voltage Accuracy in PWM Mode ±1%

Low-Ripple PFM Mode

Total Typical 32-μA Quiescent Current for Both

DC-DC Converters

The TPS6505x-Q1 devices come in a small 32-pin

leadless package (4-mm × 4-mm QFN) with a 0.4-

mm pitch.

•

100% Duty Cycle for Lowest Dropout

Two General-Purpose 400-mA, High-PSRR

LDOs

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

OMAP is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OUTPUT CURRENT

FOR DC-DC

CONVERTERS

PART

NUMBER

QFN⁽¹⁾

PACKAGE

MARKING

T_A

OPTION

PACKAGE⁽²⁾

TPS65050QRSMRQ1

TPS65050-Q1

LDO voltages according to Table 1

DC-DC converters externally adjustable

2 x 600 mA

On demand

TPS65051Q

On demand

TPS65051QRSMRQ1

TPS65051-Q1

LDO voltages externally adjustable

DC-DC converters externally adjustable

DCDC1 = 1 A

DCDC2 = 600 mA

TPS65052QRSMRQ1

TPS65052-Q1

LDO voltages according to Table 1

DCDC1 = 3.3 V; DCDC2 = 1 V or 1.3 V

DCDC1 = 1 A

DCDC2 = 600 mA

–40°C to 125°C

RSM

LDO voltages externally adjustable

DCDC1 = externally adjustable

DCDC2 = 1.3 V or 1.05 V

TPS65054QRSMRQ1

TPS65054-Q1

2 x 600 mA

On demand

LDO voltages externally adjustable

DCDC1 = 3.3 V

TPS65056QRSMRQ1

TPS65056-Q1

DCDC1 = 1A

DCDC2 = 600 mA

DCDC2 = 1 V or 1.3 V

(1) The RSM package is available in tape and reel. Add the R suffix (TPS65050RSMR) to order quantities of 3000 parts per reel. Add the T

suffix (TPS65050RSMT) to order quantities of 250 parts per reel.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

UNITS

Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with respect

–0.3 V to 7 V

to AGND

V_I

Input voltage range on EN_LDO1 pins with respect to AGND

Current at VINDCDC1/2, L1, PGND1, L2, PGND2

Current at all other pins

–0.3 V to V_CC+ 0.5 V

1800 mA

I_I

1000 mA

V_O

Output voltage range for LDO1, LDO2, LDO3, and LDO4

Continuous total power dissipation

–0.3 V to 4.0 V

See the Thermal Table

2 kV

ESD rating Human-body model (HBM) AEC-Q100 Classification Level H2

Charged-device model (CDM) AEC-Q100 Classification Level C3B

750 V

T_A

Operating free-air temperature

Storage temperature range

–40°C to 125°C

–65°C to 150°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

THERMAL INFORMATION

TPS6505x-Q1

THERMAL METRIC⁽¹⁾

RSM

32 PINS

37.2

30.1

7.8

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C / W

θ_JCtop

θ_JB

ψ_JT

0.4

ψ_JB

7.6

θ_JCbot

2.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

spacer

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

2.5

0.6

1.5

1

NOM

MAX UNIT

V_I

Input voltage range for step-down converters, VINDCDC1/2

Output voltage range for step-down converter, VDCDC1

Output voltage range for step-down converter, VDCDC2

Input voltage range for LDOs, VINLDO1, VINLDO2, VINLDO3/4

Output voltage range for LDO1 and LDO2

Output voltage range for LDO3 and LDO4

Output current at L1 (DCDC1) for TPS65051-Q1, TPS65052-Q1

Output current at L1 (DCDC1) for TPS65050-Q1, TPS65054-Q1

Output current at L1 (DCDC2)

6

V

VINDCDC1/2

V_O

V_I

VINDCDC1/2

V

6.5

3.6

V

V_O

1

3.6

V

1000

600

400

200

mA

μH

μF

°C

Ω

I_O

Output current at VLDO1, VLDO2

Output current at VLDO3, VLDO4

Inductor at L1, L2⁽¹⁾

1.5

10

2.2

22

Output capacitor at VDCDC1, VDCDC2⁽¹⁾

Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4⁽¹⁾

Input capacitor at VCC⁽¹⁾

Input capacitor at VINLDO1, VINLDO2⁽¹⁾

Input capacitor at VINLDO3/4⁽¹⁾

C_O

2.2

1

C_I

2.2

–40

T_A

Operating ambient temperature range

Resistor from battery voltage to V_CCused for filtering⁽²⁾

125

10

1

(1) See the Application Information section of this data sheet for more details.

(2) Up to 2 mA can flow into V_CC; when both converters are running in PWM, this resistor causes the UVLO threshold to shift accordingly.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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ELECTRICAL CHARACTERISTICS

V_CC= VINDCDC1/2 = 3.6 V, EN = V_CC, MODE = GND, L = 2.2 μH, C_O= 10 μF, T_A= –40°C to 125°C, typical values are at

T_A= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT

V_I

Input voltage range at VINDCDC1/2

2.5

6

V

One converter, I_O= 0 mA.

PFM mode enabled (Mode = GND) device not switching,

EN_DCDC1 = V_IOR EN_DCDC2 = V_I;

EN_LDO1= EN_LDO2 = EN_LDO3 = EN_LDO = GND

20

32

30

μA

Two converters, I_O= 0 mA

Operating quiescent current

PFM mode enabled (Mode = 0) device not switching,

EN_DCDC1 = V_IAND EN_DCDC2 = V_I;

EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND

I_Q

Total current into V_CC, VINDCDC1/2,

VINLDO1, VINLDO2, VINLDO3/4

40

μA

One converter, I_O= 0 mA.

PFM mode enabled (Mode = GND) device not switching,

EN_DCDC1 = V_IOR EN_DCDC2 = V_I;

180

0.85

1.25

250

EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = V_I

One converter, I_O= 0 mA.

Switching with no load (Mode = V_I), PWM operation EN_DCDC1 = V_I

OR EN_DCDC2 = V_I; EN_LDO1 = EN_LDO2 = EN_LDO3 =

EN_LDO = GND

mA

I_Q

Operating quiescent current into V_CC

Two converters, I_O= 0 mA

Switching with no load (Mode = V_I), PWM operation EN_DCDC1 = V_I

AND EN_DCDC2 = V_I; EN_LDO1 = EN_LDO2 = EN_LDO3 =

EN_LDO = GND

EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 =

EN_LDO3 = EN_LDO4 = GND

I_(SD)

Shutdown current

9

12

2

μA

Undervoltage lockout threshold for

DCDC converters and LDOs

V_(UVLO)

Voltage at V_CC

1.8

V

EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4

MODE, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1,

V_IH

V_IL

High-level input voltage

Low-level input voltage

DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,

EN_LDO4

1.2

0

V_CC

0.4

V

MODE, EN_DCDC1, EN_DCDC2, DEFLDO1, DEFLDO2,

DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4,

DEFDCDC2

MODE = GND or V_IMODE, EN_DCDC1, EN_DCDC2, DEFDCDC2,

DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2,

EN_LDO3, EN_LDO4

0.01

1

μA

I_lB

Input bias current

TPS65051-Q1 and TPS65052-Q1 only V_FB_LDOx = 1 V

FB_LDO1, FB_LDO2, FB_LDO3, FB_LDO4

100

nA

POWER SWITCH

VINDCDC1/2 = 3.6 V

280

400

280

400

630

DCDC1

VINDCDC1/2 = 2.5 V

r_DS(on)

P-channel MOSFET on-resistance

mΩ

μA

mΩ

μA

A

VINDCDC1/2 = 3.6 V

DCDC2

VINDCDC1/2 = 2.5 V

I_lkg

P-channel leakage current

VDCDCx = V_(DS)= 6 V

1

VINDCDC1/2 = 3.6 V

220

320

220

320

7

450

DCDC1

VINDCDC1/2 = 2.5 V

r_DS(on)

N-channel MOSFET on-resistance

N-channel leakage current

VINDCDC1/2 = 3.6 V

450

DCDC2

VINDCDC1/2 = 2.5 V

I_lkg

VDCDCx = V_(DS)= 6 V

10

TPS65050-Q1,

TPS65054-Q1

0.85

1.19

0.85

1

1.4

1

1.15

DCDC1:

2.5 V ≤ VINDCDC1/2 ≤ 6 V

Forward current limit

TPS65051-Q1,

TPS65052-Q1,

TPS65056-Q1

I_(LIMF)

PMOS (high side) and

NMOS (low side)

1.65

1.15

TPS65050-

DCDC2:

2.5 V ≤ VINDCDC1/2 ≤ 6 V

Q1–TPS65056-Q1

A

Thermal shutdown

Increasing junction temperature

Decreasing junction temperature

150

20

°C

Thermal shutdown hysteresis

4

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

ELECTRICAL CHARACTERISTICS (continued)

V_CC= VINDCDC1/2 = 3.6 V, EN = V_CC, MODE = GND, L = 2.2 μH, C_O= 10 μF, T_A= –40°C to 125°C, typical values are at

T_A= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OSCILLATOR

f_SW

Oscillator frequency

2.025

2.25

2.475

MHz

OUTPUT

Output-voltage range for DCDC1,

DCDC2

V_O

Externally adjustable versions

0.6

VINDCDC1/2

600

V

V_ref

Reference voltage

Externally adjustable versions

mV

VINDCDC1/2 = 2.5 V to 6 V, 0 mA < I_O= < I_O(maximum)

MODE = GND, PFM operation

–2%

–1%

0

2%

1%

DC output-voltage

accuracy

DCDC1,

V_O

DCDC2⁽¹⁾

VINDCDC1/2 = 2.5 V to 6 V, 0 mA < I_O= < I_O(maximum)

MODE = V_I, PWM operation

ΔV_O

t_Start

t_Ramp

Power-save-mode ripple voltage⁽²⁾

Start-up time

I_O= 1 mA, MODE = GND, V_O= 1.3 V, bandwith = 20 MHz

Time from active EN to start switching

25

170

750

100

32

mV_PP

μs

VOUT ramp-up time

Time to ramp from 5% to 95% of V_O

μs

RESET delay time

Input voltage at threshold pin rising

80

26

120

38

ms

V

PB-ONOFF debounce time

RESET, PB_OUT output low voltage

RESET, PB_OUT sink current

V_OL

I_OL

I_OL= 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V

0.2

1

10

1

mA

After PB_IN has been pulled high once; Vthreshold > 1 V and

Vhysteresis > 1 V, V_OH= 6 V

RESET, PB_OUT output leakage current

Vthreshold, Vhysteresis threshold

nA

V

V_th

0.98

1.5

1.02

6.5

VLDO1, VLDO2, VLDO3 and VLDO4 Low-Dropout Regulators

Input-voltage range for LDO1, LDO2,

LDO3, LDO4

V_I

V

LDO1 output-voltage range

LDO2 output-voltage range

LDO3 output-voltage range

LDO4 output-voltage range

TPS65050-Q1, TPS65052-Q1 only

1.2

1.8

1.1

1.2

3.3

TPS65050-Q1, TPS65052-Q1 only

V_O

3.3

2.85

Feedback voltage for FB_LDO1,

FB_LDO2, FB_LDO3, and FB_LDO4

V_(FB)

TPS65051-Q1, TPS65054-Q1, and TPS65056-Q1 only

1

V

Maximum output current for LDO1,

LDO2

400

200

I_O

mA

Maximum output current for LDO3,

LDO4

LDO1 short-circuit current limit

LDO2 short-circuit current limit

VLDO1 = GND

VLDO2 = GND

750

850

I_(SC)

mA

LDO3 and LDO4 short-circuit current

limit

VLDO3 = GND, VLDO4 = GND

420

Dropout voltage at LDO1

Dropout voltage at LDO2

Dropout voltage at LDO3, LDO4

I_O= 400 mA, VINLDO = 3.4 V

I_O= 400 mA, VINLDO = 1.8 V

I_O= 200 mA, VINLDO = 1.8 V

400

280

mV

Leakage current from VinLDOx to

VLDOx

I_lkg

V_O

LDO enabled, VINLDO = 6.5 V, V_O= 1 V at T_A= 140°C

I_O= 10 mA

3

μA

Output voltage accuracy for LDO1,

LDO2, LDO3, LDO4

–2%

–1%

1%

VINLDO1,2 = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,

VINLDO3,4 = VLDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V,

I_O= 10 mA

Line regulation for LDO1, LDO2, LDO3,

LDO4

Load regulation for LDO1, LDO2, LDO3, I_O= 0 mA to 400 mA for LDO1, LDO2

LDO4

I_O= 0 mA to 200 mA for LDO3, LDO4

Regulation time for LDO1, LDO2, LDO3,

LDO4

Load change from 10% to 90%

10

70

μs

PSRR

Power-supply rejection ratio

f = 10 kHz; I_O= 50 mA; V_I= V_O+ 1 V

dB

(1) Output voltage specification does not include tolerance of external voltage-programming resistors.

(2) In power-save mode, device typically enters operation at I_PSM= V_I/ 32 Ω.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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ELECTRICAL CHARACTERISTICS (continued)

V_CC= VINDCDC1/2 = 3.6 V, EN = V_CC, MODE = GND, L = 2.2 μH, C_O= 10 μF, T_A= –40°C to 125°C, typical values are at

T_A= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

Active when LDO is disabled

MIN

TYP

MAX UNIT

Internal discharge resistor at VLDO1,

VLDO2, VLDO3, VLDO4

R_(DIS)

350

R

Thermal shutdown

Increasing junction temperature

Decreasing junction temperature

140

20

°C

Thermal shutdown hysteresis

6

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

PIN ASSIGNMENTS

RSM PACKAGE

(TOP VIEW)

EN_DCDC1

EN_LDO4

EN_LDO3

RESET

FB4

EN_DCDC1

EN_DCDC2

EN_LDO1

EN_LDO2

VINLDO1

EN_LDO4

EN_LDO3

PB_OUT

DEFLDO4

VLDO4

EN_DCDC2

EN_LDO1

EN_LDO2

VINLDO1

TPS65051-Q1

TPS65054-Q1

TPS65056-Q1

TPS65050-Q1

VLDO4

VLDO1

FB1

VINLDO3/4

VLDO3

FB3

VLDO1

DEFLDO1

MODE

VINLDO3/4

VLDO3

MODE

DEFLDO3

EN_DCDC1

EN_LDO4

EN_LDO3

RESET

EN_DCDC2

EN_LDO1

EN_LDO2

VINLDO1

DEFLDO4

VLDO4

TPS65052-Q1

VLDO1

DEFLDO1

MODE

VINLDO3/4

VLDO3

DEFLDO3

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

TPS65050 TPS65051 TPS65052 TPS65054 TPS65056-

NAME

-Q1

Q1

AGND

BP

2

I

Analog GND, connect to PGND and thermal pad

Input for bypass capacitor for internal reference

1

TPS65050-Q1 and TPS65051-Q1: Feedback pin for converter 2.

Connect DEFDCDC2 to the center of the external resistor divider.

TPS65052-Q1 and TPS65056-Q1: Select pin of converter 2 output

voltage.

DEFDCDC2

17

I

High = 1.3 V, Low = 1 V

TPS65054-Q1: Select pin of converter 2 output voltage.

High = 1.05 V, Low = 1.3 V

Digital input, used to set the default output voltage of LDO1 to

LDO4; LSB

DEFLDO1

DEFLDO2

DEFLDO3

DEFLDO4

31

6

--

31

6

--

I

Digital input, used to set the default output voltage of LDO1 to

LDO4

Digital input, used to set the default output voltage of LDO1 to

LDO4

9

Digital input, used to set the default output voltage of LDO1 to

LDO4; MSB

13

EN_DCDC1

EN_DCDC2

25

26

25

26

25

26

25

26

25

26

I

Enable input for converter 1, active-high

Enable input for converter 2, active-high

Enable input for LDO1. Logic high enables the LDO, logic low

disables the LDO.

EN_LDO1

EN_LDO2

EN_LDO3

EN_LDO4

27

28

15

16

27

28

15

16

27

28

15

16

27

28

15

16

27

28

15

16

I

Enable input for LDO2. Logic high enables the LDO, logic low

disables the LDO.

Enable input for LDO3. Logic high enables the LDO, logic low

disables the LDO.

Enable input for LDO4. Logic high enables the LDO, logic low

disables the LDO.

FB1

FB2

FB3

FB4

--

31

6

--

31

6

31

6

I

Feedback input for the external voltage divider

9

13

Input to adjust output voltage of converter 1 between 0.6 V and V_I.

Connect an external resistor divider between VOUT1, this pin, and

GND.

FB_DCDC1

24

I

GND

8

--

8

--

8

--

8

--

8

-

I

Connect to GND

HYSTERESIS

--

Input for hysteresis on reset threshold

Switch pin of converter 1. Connected to inductor

Switch pin of converter 2. Connected to inductor

L1

L2

22

20

22

20

22

20

22

20

22

20

O

Select between power-safe mode and forced-PWM mode for

DCDC1 and DCDC2. In power-safe mode, the device uses PFM at

light loads, PWM for higher loads. Setting this pin to high level

selects forced-PWM mode. If this pin has low level, then the device

operates in power-safe mode.

MODE

32

I

PB_IN

7

--

I

Input for the pushbutton ON-OFF function

Open-drain output. Active-low after the supply voltage (V_CC

exceeds the undervoltage-lockout threshold. Toggle the pin by

pulling PB_IN high.

)

PB_OUT

14

O

PGND1

23

19

--

23

19

14

7

23

19

14

7

23

19

14

7

23

19

14

7

I

GND for converter 1

PGND2

GND for converter 2

RESET

O

I

Open-drain active-low reset output, 100-ms reset-delay time

Reset input

THRESHOLD

--

Power supply for digital and analog circuitry of DCDC1, DCDC2

and LDOs. Connect this pin to the same voltage supply as

VINDCDC1/2.

V_CC

3

I

Feedback voltage-sense input, connect directly to the output of

converter 2.

VDCDC2

18

Input voltage for VDCDC1 and VDCDC2 step-down converters.

VINDCDC1/2

VINLDO1

21

29

21

29

21

29

21

29

21

29

I

Connect this pin to the same voltage supply as V_CC

.

Input voltage for LDO1

8

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

TPS65050 TPS65051 TPS65052 TPS65054 TPS65056-

NAME

-Q1

Q1

VINLDO2

VINLDO3/4

VLDO1

4

I

Input voltage for LDO2

11

30

5

11

30

5

11

30

5

11

30

5

11

30

5

I

Input voltage for LDO3 and LDO4

Output voltage of LDO1

Output voltage of LDO2

Output voltage of LDO3

Output voltage of LDO4

Connect to GND.

O

VLDO2

VLDO3

10

12

--

10

12

--

10

12

--

10

12

--

10

12

--

VLDO4

Thermal pad

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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FUNCTIONAL BLOCK DIAGRAM

TPS65050-Q1

VINDCDC1/2

1 W

Vbat

V_CC

10 mF

1 mF

2.2 mH

L1

DCDC1 (I/O)

Cff

EN_DCDC1

R1

R2

ENABLE

MODE

FB_DCDC1

PGND1

STEP-DOWN

CONVERTER

600 mA

10 mF

DEFLDO1

DEFLDO2

DEFLDO3

DEFLDO4

Interface

L2

2.2 mH

DCDC2 (core)

R3

R4

VDCDC2

10 mF

STEP-DOWN

CONVERTER

600 mA

EN_DCDC2

DEFDCDC2

PGND2

ENABLE

VLDO1

VIN_LDO1

EN_LDO1

VLDO1

VIN

4.7 mF

2.2 mF

400-mA LDO

ENABLE

VIN_LDO2

EN_LDO2

VLDO2

VIN

VLDO2

ENABLE

400-mA LDO

VIN_LDO3/4

EN_LDO3

VIN

VLDO3

BP

200-mA LDO

ENABLE

0.1 mF

EN_LDO4

VLDO4

ENABLE

Vbat

200-mA LDO

I/Ovoltage

R19

PB_OUT

default

turned on

Flipflop with

32-ms debounce

PB_IN

AGND

10

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TPS65051-Q1

VINDCDC1/2

1 W

Vbat

V_CC

22 mF

1 mF

2.2 mH

L1

DCDC1 (I/O)

STEP-DOWN

CONVERTER

1 A

Cff

EN_DCDC1

R1

R2

ENABLE

FB_DCDC1

PGND1

10 mF

MODE

L2

2.2 mH

DCDC2 (core)

VDCDC2

R3

R4

10 mF

STEP-DOWN

CONVERTER

600 mA

EN_DCDC2

DEFDCDC2

PGND2

ENABLE

VLDO1

FB1

VIN_LDO1

EN_LDO1

VLDO1

VIN

4.7 mF

2.2 mF

R5

R6

400-mA LDO

ENABLE

VIN_LDO2

EN_LDO2

VLDO2

FB2

VIN

VLDO2

ENABLE

R7

R8

400-mA LDO

VIN_LDO3/4

EN_LDO3

VIN

VLDO3

FB3

VLDO3

R9

200-mA LDO

ENABLE

BP

R10

0.1 mF

EN_LDO4

VLDO4

ENABLE

VLDO4

FB4

200-mA LDO

2.2 mF

R11

R12

I/Ovoltage

R19

THRESHOLD

HYSTERESIS

RESET

AGND

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

www.ti.com

TPS65052-Q1

VINDCDC1/2

1 W

Vbat

V_CC

10 mF

1 mF

3.3 mH

L1

DCDC1 (I/O)

EN_DCDC1

FB_DCDC1

PGND1

ENABLE

MODE

STEP-DOWN

CONVERTER

1 A

10 mF

DEFLDO1

DEFLDO2

DEFLDO3

DEFLDO4

Interface

L2

DCDC2 (core)

2.2 mH

VDCDC2

PGND2

VLDO1

10 mF

STEP-DOWN

CONVERTER

600 mA

EN_DCDC2

DEFDCDC2

ENABLE

1 V/1.3 V

VIN_LDO1

EN_LDO1

VLDO1

VIN

4.7 mF

400-mA LDO

ENABLE

VIN_LDO2

EN_LDO2

VLDO2

VIN

VLDO2

ENABLE

4.7 mF

2.2 mF

400-mA LDO

VIN_LDO3/4

EN_LDO3

VIN

VLDO3

BP

VLDO3

200-mA LDO

ENABLE

0.1 mF

EN_LDO4

VLDO4

RESET

VLDO4

ENABLE

200-mA LDO

I/Ovoltage

R19

THRESHOLD

HYSTERESIS

RESET

AGND

12

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TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TPS65054-Q1

VINDCDC1/2

1 W

Vbat

V_CC

22 mF

1 mF

2.2 mH

L1

DCDC1 (I/O)

STEP-DOWN

CONVERTER

600 mA

Cff

EN_DCDC1

R1

R2

ENABLE

FB_DCDC1

PGND1

10 mF

MODE

L2

DCDC2 (core)

2.2 mH

VDCDC2

PGND2

10 mF

STEP-DOWN

CONVERTER

600 mA

EN_DCDC2

DEFDCDC2

ENABLE

1.3 V/1.05 V

VLDO1

FB1

VIN_LDO1

EN_LDO1

VLDO1

VIN

4.7 mF

2.2 mF

R5

R6

400-mA LDO

ENABLE

VIN_LDO2

EN_LDO2

VLDO2

FB2

VIN

VLDO2

ENABLE

R7

R8

400-mA LDO

VIN_LDO3/4

EN_LDO3

VIN

VLDO3

R9

FB3

BP

200-mA LDO

ENABLE

R10

0.1 mF

EN_LDO4

VLDO4

ENABLE

VLDO4

FB4

200-mA LDO

2.2 mF

R11

R12

I/Ovoltage

R19

THRESHOLD

HYSTERESIS

RESET

AGND

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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TPS65056-Q1

VINDCDC1/2

1 W

Vbat

V_CC

22 mF

1 mF

3.3 mH

L1

DCDC1 (I/O)

EN_DCDC1

ENABLE

FB_DCDC1

PGND1

STEP-DOWN

CONVERTER

1 A

10 mF

MODE

L2

2.2 mH

DCDC2 (core)

VDCDC2

PGND2

10 mF

STEP-DOWN

CONVERTER

600 mA

EN_DCDC2

DEFDCDC2

ENABLE

1 V / 1.3 V

VLDO1

FB1

VIN_LDO1

EN_LDO1

VLDO1

VIN

4.7 mF

2.2 mF

R5

R6

400-mA LDO

ENABLE

VIN_LDO2

EN_LDO2

VLDO2

FB2

VIN

VLDO2

ENABLE

R7

R8

400-mA LDO

VIN_LDO3/4

EN_LDO3

VIN

VLDO3

R9

FB3

BP

200-mA LDO

ENABLE

R10

0.1 mF

EN_LDO4

VLDO4

ENABLE

VLDO4

FB4

200-mA LDO

2.2 mF

R11

R12

I/Ovoltage

R19

THRESHOLD

HYSTERESIS

RESET

AGND

14

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Efficiency converter 1

versus Output current

PWM or PFM mode = low

PWM mode = high

Efficiency converter 2

Efficiency converter 1

Efficiency converter 2

Output voltage ripple

DCDC1 startup timing

LDO1 to LDO4 startup timing

DCDC1 load transient response

DCDC2 load transient response

DCDC1 line transient response

DCDC2 line transient response

LDO1 load transient response

LDO4 load transient response

LDO1 line transient response

Power supply rejection ratio

PWM mode = high

PFM mode = low

PWM mode = high

PFM mode = low

vesus Frequency

EFFICIENCY

versus

EFFICIENCY

versus

OUTPUT CURRENT

100

90

100

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

3.8 V

5 V

3.8 V

5 V

4.2 V

3.4 V

4.2 V

V

T

= 3.3 V

= 25^oC

V

O

= 3.3 V

= 25^oC

O

T

A

PWM/PFM Mode

A

10

0

10

PWM Mode

0

0.0001

0.001

0.01

0.1

1

10

0.001

I

0.01

0.1

1

10

I

− Output Current − A

O

Figure 1.

Figure 2.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

versus

EFFICIENCY

versus

OUTPUT CURRENT

100

90

100

90

3.3 V

V

T

= 1.3 V

= 25^oC

O

A

PWM Mode

80

70

60

50

40

30

20

80

70

60

50

40

30

20

3.8 V

4.2 V

5 V

3.3 V

5 V

4.2 V

V

O

= 1.3 V

= 25^oC

T

A

PFM Mode

10

0

10

0

0.0001

0.001

0.01

0.1

1

0.0001

0.001

0.01

0.1

1

I

− Output Current − A

I

− Output Current − A

O

Figure 3.

Figure 4.

OUTPUT VOLTAGE RIPPLE

PWM or PFM MODE = LOW

OUTPUT VOLTAGE RIPPLE

PWM MODE = HIGH

V

= 4.2 V,

T

= 25^oC

CH1 (VDCDC1 = 3.3 V)

= 25^oC

A

I

A

V

= 4.2 V,

T

CH1 (VDCDC1 = 3.3 V)

I

CH1 (VDCDC2 = 1.5 V)

CH2 (VDCDC2 = 1.5 V)

CH3 (I DCDC2 = 600 mA)

L

CH3 (I DCDC2 = 80 mA)

L

CH4 (I DCDC1 = 600 mA)

L

CH4 (I DCDC1 = 80 mA)

L

t − Time = 500 ns/div

t − Time = 2 ms/div

Figure 5.

Figure 6.

16

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TYPICAL CHARACTERISTICS (continued)

DCDC1 STARTUP TIMING

LDO1 TO LDO4 STARTUP TIMING

CH1 (EN)

CH4 (VLDO1)

EN

CH1 (VLDO1)

CH2 (VLDO2)

V

T

= 3.6 V

= 25^oC

I

A

Mode = Low

CH3 (VLDO3)

CH4 (VLDO4)

CH3

(VDCDC2 = 1.5 V)

V

T

= 3.6 V

= 25^oC

I

A

CH2

(VDCDC1 = 3.3 V)

Load DCDC1 = 600 mA

Load DCDC2 = 600 mA

ILDO1/2/3/4 = 100 mA

Mode = Low

t − Time = 200 ms/div

Figure 7.

t − Time = 20 ms/div

Figure 8.

DCDC1 LOAD TRANSIENT RESPONSE

CH1 (VDCDC1)

V

T

= 4.2 V

= 25^oC

I

V

T

= 4.2 V

= 25^oC

I

A

Mode = Low

Mode = High

CH2

I(DCDC1)

CH2

I(DCDC1)

VDCDC1 = 3.3 V

ENDCDC1 = High

ENDCDC2 = Low

VDCDC1 = 3.3 V

ENDCDC1 = High

ENDCDC2 = Low

Load Current = 60 mA to 540 mA

t − Time = 100 ms/div

Figure 9.

Figure 10.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

DCDC2 LOAD TRANSIENT RESPONSE

CH1 (VDCDC2)

V

T

= 3.6 V

= 25^oC

I

V

T

= 3.6 V

= 25^oC

I

A

Mode = High

Mode = Low

CH2

I(DCDC2)

CH2

I(DCDC2)

VDCDC2 = 1.5 V

ENDCDC1 = Low

ENDCDC2 = High

VDCDC2 = 1.5 V

ENDCDC1 = Low

ENDCDC2 = High

Load Current = 60 mA to 540 mA

t − Time = 100 ms/div

Figure 11.

Figure 12.

DCDC1 LINE TRANSIENT RESPONSE

DCDC2 LINE TRANSIENT RESPONSE

CH1

VIN (VDCDC1)

CH1

VIN (VDCDC2)

V

T

= 3.6 V to 4.5 V to 3.6 V

= 25^oC

I

A

Mode = High

VDCDC1 = 3.3 V

ENDCDC1 = High

ENDCDC2 = Low

Load Current = 600 mA

CH2 (VDCDC2)

CH2 (VDCDC1)

VDCDC2 = 1.5 V

ENDCDC1 = Low

ENDCDC2 = High

V

T

= 3.4 V to 4.4 V to 3.4 V

= 25^oC

I

A

Mode = High

Load Current = 600 mA

t − Time = 100 ms/div

Figure 13.

Figure 14.

18

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

TYPICAL CHARACTERISTICS (continued)

LDO1 LOAD TRANSIENT RESPONSE

LDO4 LOAD TRANSIENT RESPONSE

CH1 (VLDO4)

CH1 (VLDO1)

V

= 3.6 V

I

VLDO4 = 1.3 V

V

T

= 3.6 V

= 25^oC

I

A

VLDO4 = 20 mA to 180 mA

= 25^oC

VLDO1 = 3.3 V

VLDO1 = 40 mA to 360 mA

T

A

CH2

I(LDO4)

CH2

I(LDO1)

t − Time = 100 ms/div

Figure 15.

Figure 16.

POWER-SUPPLY REJECTION RATIO

versus

LDO1 LINE TRANSIENT RESPONSE

FREQUENCY

100

90

CH1

VIN (LDO1)

80

70

60

50

40

30

20

CH2 (VLDO1)

V

T

= 3.6 V to 4.2 V to 3.6 V

= 25^oC

I

A

VLDO1 = 3.3 V

VLDO1 = 100 mA

Mode = High

10

0

t − Time = 100 ms/div

10

100

1k

10k

100k

1M

10M

f − Frequency − Hz

Figure 17.

Figure 18.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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DETAILED DESCRIPTION

Operation

The TPS6505x-Q1 devices each include two synchronous step-down converters. The converters operate with

2.25-MHz (typical) fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light

load currents, the converters automatically enter power-save mode and operate with PFM (pulse-frequency

modulation).

During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input

voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns

on, the inductor current ramps up until the current comparator trips, and the control logic turns off the switch. The

current-limit comparator turns off the switch if the current exceeds the limit of the P-channel switch. After the

adaptive dead time, which prevents shoot-through current, the N-channel MOSFET rectifier turns on, and the

inductor current ramps down. The clock signal turning off the N-channel rectifier and turning on the on the P-

channel switch initiates the next cycle.

The two dc-dc converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift

between converter 1 and converter 2 decreases the input rms current, allowing the use of smaller input

capacitors.

DCDC1 Converter

An external resistor divider connected to FB_DCDC1 pin for TPS65050-Q1, TPS65051-Q1, and TPS65054-Q1

sets the converter 1 output voltage. For TPS65052-Q1, with its output voltage fixed to 3.3 V, connect this pin

directly to the output. See the Application Information section for more details. The maximum output current on

DCDC1 is 600 mA for TPS65050-Q1 and TPS65054-Q1. For TPS65051-Q1, TPS65052-Q1, and TPS65056-Q1,

the maximum output current is 1 A.

DCDC2 Converter

Connect he VDCDC2 pin directly to the DCDC2 converter output voltage. The DEFDCDC2 pin selects the

DCDC2 converter output voltage.

TPS65050-Q1 and TPS65051-Q1: An external resistor divider sets the output voltage. Connect the DEFDCDC2

pin to the external resistor divider.

TPS65052-Q1, TPS65054-Q1, and TPS65056-Q1: Connect the DEFDCDC2 pin either to GND, or to V_CC. The

converter 2 output voltage defaults to:

Device

DEFDCDC2 = Low

DEFDCDC2 = High

1.3 V

TPS65052-Q1 , TPS65056-Q1

TPS65054-Q1

1 V

1.3 V

1.05 V

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Power-Save Mode

Setting the MODE pin to 0 enables the power-save mode. If the load current decreases, the converters enter the

power-save mode of operation automatically. During power-save mode, the converters operate with reduced

switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency. The

converters position the output voltage 1% above the nominal output voltage. This voltage-positioning feature

minimizes voltage drops caused by a sudden load step.

To optimize the converter efficiency at light load, the TPS6505x-Q1 monitors average current. If in PWM mode,

the inductor current remains below a certain threshold, then the device enters power-save mode. Use Equation 1

to calculate the typical threshold:

VINDCDC

I_{(PFM_enter)}

=

32 W

A. Average output current threshold to enter PFM mode.

(1)

VINDCDC

I_{(PSMDCDC_leave)}

=

24 W

B. Average output current threshold to leave PFM mode.

(2)

During power-save mode, a comparator monitors the output voltage. As the output voltage falls below the skip-

comparator (skip comp) threshold, the P-channel switch turns on, and the converter effectively delivers a

constant current. If the load is below the delivered current, the output voltage rises until it crosses the skip comp

threshold again; then all switching activity ceases, reducing the quiescent current to a minimum until the output

voltage has dropped below the threshold. If the load current is greater than the delivered current, the output

voltage falls until it crosses the skip-comparator-low (skip comp low) threshold set to 1% below nominal V_O; then

the device exits power-save mode, and the converter returns to the PWM mode.

These control methods reduce the quiescent current to 12 μA per converter and the switching frequency to a

minimum, achieving the highest converter efficiency. The PFM mode operates with low output-voltage ripple. The

ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor value

decreases the output ripple voltage.

Disable the power-save mode by driving the MODE pin high. In forced-PWM mode, both converters operate with

fixed-frequency PWM mode regardless of the load.

Dynamic Voltage Positioning

This feature reduces the voltage under- and overshoots at load steps from light to heavy load and vice versa. It

is activated In the power-save mode of operation, running the converter in PFM mode activates dynamic voltage

positioning. Dynamic voltage positioning provides more headroom for both the voltage drop at a load step and

the voltage increase at a load throw-off, thereby improving load-transient behavior.

At light loads, in which the converters operate in PFM mode, the typical output-voltage regulation is 1% higher

than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops

until it reaches the skip-comparator-low threshold, set to 1% below the nominal value, and enters PWM mode.

During a release from heavy load to light load, active regulation turning on the N-channel switch minimizes the

voltage overshoot.

Smooth

Increased Load

Fast Load Transient

+1%

OUT_NOM

-1%

PFM Mode

Light Load

PFM Mode

Light Load

V

PFM Mode

Medium/Heavy Load

PFM Mode

Medium/Heavy Load

COMP_LOW Threshold

Figure 19. Dynamic Voltage Positioning

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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Soft Start

The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft

start, control of the output-voltage ramp-up is as shown in Figure 20.

EN

95%

5%

V

OUT

t

RAMP

Start

Figure 20. Soft Start

100% Duty-Cycle Low-Dropout Operation

The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the

100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This operational mode is useful in

battery-powered applications to achieve longest operation time by taking full advantage of the whole battery

voltage range, (that is, the minimum input voltage to maintain regulation depends on the load current and output

voltage) and can be calculated as:

V_I(min) = V_O(max) + I_O(max) x (r_DS(on)(max) + R_L)

(3)

with:

•

I_Omax = maximum output current plus inductor ripple current

r_DS(on)max = maximum P-channel switch r_DS(on)

R_L= dc resistance of the inductor

V_O(max) = nominal output voltage plus maximum output-voltage tolerance

Undervoltage Lockout

The undervoltage-lockout circuit prevents the device from malfunctioning at low input voltages and from

excessive discharge of the battery, and disables all internal circuitry. The undervoltage-lockout threshold, sensed

at the V_CCpin, is typically 1.8 V, maximum 2 V.

Mode Selection

The MODE pin allows mode selection between forced PWM mode and power-save mode for both converters.

Connecting this pin to GND enables the automatic PWM and power-save mode of operation. The converters

operate in fixed-frequency PWM mode at moderate-to-heavy loads and in the PFM mode during light loads,

maintaining high efficiency over a wide load-current range.

22

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load

currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the

switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-

save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced-

PWM mode during operation. This allows efficient power management by adjusting the operation of the

converters to the specific system requirements.

Enable

To start up each converter independently, the device has a separate enable pin for each dc-dc converter and for

each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, or EN_LDO4 is set to high, the

corresponding converter starts up with soft start as previously described.

Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the

electrical characteristics. In this mode, the P- and N-Channel MOSFETs turn off, and the entire internal control

circuitry switches off. If disabled, internal 350-Ω resistors pull the outputs of the LDOs low, actively discharging

the output capacitor. Proper operation requires termination of the enable pins. Do not leave them unconnected.

RESET

The TPS65051-Q1, TPS65052-Q1, TPS65054-Q1, and TPS65056-Q1 contain circuitry that can generate a reset

pulse for a processor with a 100-ms delay time. The device senses the input voltage for a comparator at the

THRESHOLD pin. When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. An

external resistor connected to the HYSTERESIS input defines the hysteresis. This circuitry is functional as soon

as the supply voltage at V_CCexceeds the undervoltage-lockout threshold. The TPS6505x-Q1 has a shutdown

current (all dc-dc converters and LDOs are off) of 9 μA.

Vbat

HYSTERESIS

RESET

THRESHOLD

+

100 ms

Delay

-

V

= 1 V

ref

Vbat

THRESHOLD

THRESHOLD - HYSTERESIS

Comparator

Output (Internal)

t

NRESET

RESET

Figure 21. RESET Pulse Circuit

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

www.ti.com

Push-Button ON-OFF (PB-ON-OFF)

The TPS65050-Q1 provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold and

hysteresis inputs. The device holds the output at PB_OUT low after application of voltage at V_CC. Only after

pulling the input at PB_IN high once, the output driver at PB_OUT goes to its inactive state, driven high with its

external pullup resistor. Further low-high pulses at PB_IN toggle the status of the PB_OUT output. Connecting

the PB_OUT output to the enable input of the converters allows shutdown and start-up of the converters with a

single push on a button.

Vbat

PB_OUT

JK-

PB_IN

Debounce

32 ms

Flipflop

Default

Low

Min Pulse

Width 32 ms

PB_IN

PB_OUT

32 ms

Figure 22. Push-Button Circuit

Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.

Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 150°C (typically) for the dc-dc converters, the device goes into

thermal shutdown. In this mode, the P- and N-channel MOSFETs turn off. The device continues its operation

when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of

the dc-dc converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs is typically 140°C. Therefore, an LDO used to power an

external voltage never heats up the chip high enough to turn off the dc-dc converters. If one LDO exceeds the

thermal shutdown temperature, all LDOs turn off simultaneously.

24

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Low Dropout Voltage Regulators

The design of the low-dropout voltage regulators allows them to operate well with small ceramic input and output

capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of

280 mV at rated output current. Each LDO supports a current-limit feature. The EN_LDO1, ENLDO2, EN_LDO3,

and EN_LDO4 pins enable the LDOs. In TPS65050-Q1 and TPS65052-Q1, the the use of four pins sets the

output voltage of the LDOs. Connect the DEFLDO1 to DEFLDO4 pins either to GND or Vbat (V_CC) to define a set

of output voltages for LDO1 to LDO4 according to Table 1. Connecting the DEFLDOx pins to a voltage different

from GND or V_CCcauses increased leakage current into V_CC. In TPS65051-Q1 and TPS65054-Q1, the use of

external resistor dividers sets the output voltage of the LDOs .

TPS65050-Q1 and TPS65052-Q1 default voltage options are adjustable with DEFLDO4…DEFLDO1 according to

Table 1.

Table 1. Default Options

DEFLDO1

DEFLDO2

DEFLDO3

DEFLDO4

VLDO1

VLDO2

VLDO3

VLDO4

400-mA LDO

200-mA LDO

1.8 V–5.5 V Input

1.5 V–5.5 V Input

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3.3 V

2.85 V

2.7 V

2.5 V

1.85 V

1.8 V

1.2 V

3.3 V

1.85 V

1.5 V

1.85 V

1.5 V

2.7 V

2.5 V

1.85 V

1.5 V

1.3 V

1.85 V

1.2 V

1.5 V

1.3 V

1.35 V

2.85 V

1.3 V

2.85 V

3.3 V

2.85 V

1.85 V

1.5 V

1.1 V

1.85 V

1.2 V

3.3 V

1.5 V

3.3 V

1.5 V

1.85 V

2.5 V

1.35 V

3.3 V

1.8 V

1.1 V

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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APPLICATION INFORMATION

Output-Voltage Setting

Converter 1 (DCDC1)

An external resistor network can set the output voltage of converter 1. Calculate the output voltage using

Equation 4,

R1

V_O= V_ref

x

1 +

(

)

R2

(4)

with an internal reference voltage V_ref, 0.6 V.

TI recommends setting the total resistance of R1 + R2 to less than 1 MΩ. The resistor network connects to the

input of the feedback amplifier, therefore requiring a small feed-forward capacitor in parallel with R1. A typical

value of 47 pF is sufficient.

Converter 2 (DCDC2)

Select the output voltage of converter 2 as follows:

•

Adjustable output voltage defined with external resistor network on pin DEFDCDC2. This option is available

for TPS65050-Q1 and TPS65051-Q1.

•

Two default fixed output voltages selectable by pin DEFDCDC2, see Table 2. This option is available for

TPS65052-Q1, TPS65054-Q1, and TPS65056-Q1.

Table 2. Default Fixed Output Voltages

Converter 2

TPS65050-Q1

TPS65051-Q1

TPS65052-Q1

TPS65054-Q1

TPS65056-Q1

DEFDCDC2 = Low

DEFDCDC2 = High

—

1 V

1.3 V

1 V

1.3 V

1.05 V

1.3 V

Calculation of the adjustable output voltage is similar to that for the DCDC1 converter. TI recommends setting the

total resistance of R3 + R4 to less than 1 MΩ. Route the DEFDCDC2 line separate from noise sources, such as

the inductor or the L2 line. Connect the VDCDC2 line directly to the output capacitor. As VDCDC2 is the sense

pin for the output of L2, there is no need for a feedforward capacitor in conjunction with R3.

Using an external resistor divider at DEFDCDC2:

1 W

V

Vbat

CC

1 mF

VDCDC2

L2

V

O

VINDCDC1/2

ENDCDC2

L

C

I

C

O

R3

R4

DEFDCDC2

AGND PGND

Figure 23. External Resistor Divider

26

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

V_(DEFDCDC2)= 0.6 V

V_O

R3 + R4

R4

V_O= V_(DEFDCDC2)

x

R3 = R4 x

- R4

(

)

V_(DEFDCDC2)

(5)

See Table 3 for typical resistor values:

Table 3. Typical Resistor Values

OUTPUT VOLTAGE

R3

R4

NOMINAL VOLTAGE

Typical CFF

47 pF

3.3 V

3 V

680 kΩ

510 kΩ

560 kΩ

510 kΩ

300 kΩ

200 kΩ

300 kΩ

330 kΩ

150 kΩ

130 kΩ

150 kΩ

160 kΩ

150 kΩ

120 kΩ

200 kΩ

330 kΩ

3.32 V

2.95 V

2.84 V

2.51 V

1.8 v

47 pF

2.85 V

2.5 V

1.8 V

1.6 V

1.5 V

1.2 V

47 pF

1.6 V

47 pF

1.5 V

47 pF

1.2 V

47 pF

Output Filter Design (Inductor and Output Capacitor)

Inductor Selection

The two converters operate with a 2.2-μH output inductor. A designer can use larger or smaller inductor values to

optimize the performance of the device for specific operation conditions. The selected inductor must be rated for

its dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of

the converters. Therefore, select an inductor with lowest dc resistance for highest efficiency. The minimum

inductor value is 1.5 μH, but the circuit requires an output capacitor of 22 μF minimum in this case. For an output

voltage above 2.8 V, TI recommends an inductor value of 3.3 μH minimum. Lower values result in an increased

output-voltage ripple in PFM mode.

Equation 6 calculates the maximum inductor current under static load conditions. The saturation-current rating of

the inductor should be higher than the maximum inductor current as calculated with Equation 6. This

recommendation is because during heavy load transient the inductor current rises above the calculated value.

V_O

1 -

V_I

DI_L

DI_L= V_O

x

I_L(max) = I_O(max) +

2

L x ¦

(6)

with:

•

f = Switching frequency (2.25-MHz typical)

L = Inductor value

Δ I_L= Peak-to-peak inductor ripple current

I_Lmax = Maximum inductor current

The highest inductor current occurs at maximum V_I. Open-core inductors have a soft saturation characteristic,

and they can normally handle higher inductor currents versus a comparable shielded inductor.

A more-conservative approach is to select the inductor current rating just for the maximum switch current of the

corresponding converter. Give consideration to the difference in the core material from inductor to inductor, which

has an impact on the efficiency, especially at high switching frequencies. See Table 4 and the typical applications

for possible inductors.

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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Table 4. Tested Inductors

Inductor Type

LPS3010

Inductor Value

2.2 μH

Supplier

Coilcraft

TDK

LPS3015

3.3 μH

LPS4012

2.2 μH

VLF4012

2.2 μH

Output-Capacitor Selection

The advanced fast-response voltage-mode control scheme of the two converters allows the use of small ceramic

capacitors with a value of 22-μF (typical), without having large output-voltage undershoots and overshoots during

heavy load transients. TI recommends ceramic capacitors having low ESR values, which result in the lowest

output-voltage ripple.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application

requirements. For completeness, the RMS ripple current is calculated as:

V_O

1 -

V_I

1

x

I_(RMSCout)= V_O

x

2 x Ö3

L x ¦

(7)

At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple is

the sum of the voltage spike caused by the output-capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

V_O

1 -

V_I

1

8 x C_Ox ¦

x

+ ESR

DV_O= V_O

x

(

)

L x ¦

(8)

where the highest output voltage ripple occurs at the highest input voltage V_I.

At light load currents, the converters operate in power-save mode and the output-voltage ripple depends on the

output-capacitor value. The internal comparator delay and the external capacitor set the output-voltage ripple.

The typical output-voltage ripple is less than 1% of the nominal output voltage.

Input-Capacitor Selection

The nature of the buck converters having a pulsating input current requires a low-ESR input capacitor for best

input-voltage filtering and minimizing the interference with other circuits caused by high input-voltage spikes. The

converters require a ceramic input capacitor of 10 μF. Increase the input capacitor as desired for better input-

voltage filtering, without any limit.

Table 5. Possible Capacitors

Capacitor Value

2.2 μF

Size

0805

0603

Supplier

Type

TDK C2012X5R0J226MT

Taiyo Yuden JMK212BJ226MG

Taiyo Yuden JMK212BJ106M

TDK C2012X5R0J106M

Ceramic

2.2 μF

10 μF

Taiyo Yuden JMK107BJ106MA

28

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

Low-Dropout Voltage Regulators (LDOs)

An external resistor network sets the output voltage of all four LDOs in TPS65051-Q1, TPS65054-Q1, and

TPS65056-Q1. Calculate the output voltage using Equation 9:

R5

V_O= V_ref

x

1 +

(

)

R6

(9)

with an internal reference voltage, V_ref, of 1 V (typical).

TI recommends setting the total resistance of R5 + R6 to less than 1 MΩ. Typically, there is no feedforward

capacitor needed at the voltage dividers for the LDOs.

V_O

R5 + R6

V_O= V_{(FB_LDOs)}

x

R5 = R6 x

- R6

(

)

V_{(FB_LDOs)}

R6

(10)

Typical resistor values:

Table 6. Typical Resistor Values

OUTPUT VOLTAGE

R5

R6

NOMINAL VOLTAGE

3.3 V

3 V

300 kΩ

240 kΩ

360 kΩ

300 kΩ

240 kΩ

150 kΩ

36 kΩ

130 kΩ

150 kΩ

130 kΩ

200 kΩ

300 kΩ

120 kΩ

510 kΩ

330 kΩ

3.31 V

3 V

2.85 V

2.8 V

2.5 V

1.8 V

1.5 V

1.3 V

1.2 V

1.1 V

2.85 V

2.8 V

2.5 V

1.8 v

1.5 V

1.3 V

1.19 V

1.1 V

100 kΩ

33 kΩ

LAYOUT CONSIDERATIONS

Application Circuits

PB_IN and Sequencing

One can use the PB_OUT pin to enable one or several converters. After power up, the PB_OUT pin is low, and

pulls down the enable pins connected to PB_OUT; EN_DCDC1, and EN_LDO1 in Figure 24. Pulling PB_IN to

V_CCfor longer than 32 ms turns off the PB_OUT pin. Hence, a pullup resistor to V_CCpulls the enable pins high,

enabling the DCDC1 converter and LDO1. The enable signal for DCDC2 and LDO2 to LDO4 is the output

voltage of DCDC1 (V_OUT1). The battery (V_(bat)) directly powers LDO1 with its output voltage of 3.3 V and LDO2

for an output voltage of 2.5 V. To save power, the input voltage for the lower voltage rails at LDO3 and LDO4

derives from the output of the step-down converters, keeping the voltage drop at the LDOs low to increase

efficiency. Because the output of DCDC1 powers LDO3 and LDO4, the total output current on V_OUT1, LDO3, and

LDO4 must not exceed the maximum rating of DCDC1.

Figure 25 shows the power up timing for this application.

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TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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1 W

VINDCDC1/2

Vbat

V

Vbat

CC

10 mF

1 mF

2.2 mH

L1

Vout1 = 2.85 V

Cff

FB_DCDC1

MODE

R1

R2

GND

10 mF

DEFLDO1

DEFLDO2

DEFLDO3

DEFLDO4

GND

Vbat

PGND1

2.2 mH

L2

Vbat Vbat

Vout2 = 1.575 V

VDCDC2

DEFDCDC2

PGND2

PB_IN

R3

R4

10 mF

TPS65050-Q1

PB_OUT

VLDO1

VLDO1 = 3.3 V

4.7 mF

EN_DCDC1

EN_LDO1

VLDO2

VLDO3

VLDO4

VLDO2 = 2.5 V

4.7 mF

VDCDC1

EN_DCDC2

EN_LDO2

EN_LDO3

EN_LDO4

VLDO3 = 1.5 V

2.2 mF

VIN_LDO1

VIN_LDO2

Vbat

VLDO4 = 1.3 V

2.2 mF

VIN_LDO3/4

Vout1

BP

AGND

0.1 mF

Figure 24. PB_OUT Circuit

30

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SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

Vbat

PB_IN

32 ms

EN_DCDC1

EN_LDO1

32 ms

Vout1

1.2V

170 ms

VLDO1

EN_DCDC2

EN_LDO3

EN_LDO4

EN_LDO2

Vout2

VLDO2

VLDO3

170 ms

VLDO4

Figure 25. Power-Up Timing

RESET

TPS65051-Q1, TPS65052-Q1, TPS65054-Q1, and TPS65056-Q1 contain a comparator for supervising a voltage

connected to an external voltage divider, and generating a reset signal if the voltage is lower than the threshold.

The rising-edge delay is 100 ms at the open-drain RESET output. Calculate the values for the external resistors

R3 to R5 as follows:

V_L= lower voltage threshold

V_H= higher voltage threshold

V_REF= reference voltage (1 V)

Example:

•

V_L= 3.3 V

V_H= 3.4 V

Set R5 = 100 kΩ

→ R3 + R4 = 240 kΩ

→ R4 = 3.03 kΩ

→ R3 = 237 kΩ

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TPS65051-Q1

TPS65050-Q1, TPS65051-Q1, TPS65052-Q1

TPS65054-Q1, TPS65056-Q1

SLVSBJ1A –SEPTEMBER 2012–REVISED NOVEMBER 2012

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V_H

R3 + R4 = R5

x

- 1

(

)

V_ref

V_H- V_L

V_L

R4 = R5

x

(11)

VINDCDC1/2

1 W

V

CC

Vbat

2.2 mH

1 mF

L1

Cff

Vout1 = 2.85 V

R1

FB_DCDC1

10 mF

R2

PGND1

L2

2.2 mH

Vout2 = 1.575 V

R3

VDCDC2

Vbat

Vout1

DEFDCDC2

PGND2

10 mF

R3

R4

R5

HYSTERESIS

THRESHOLD

R4

VLDO1

FB1

VLDO1 = 3.3 V

R5

R6

1 MW

4.7 mF

TPS65051-Q1

RESET

Vbat

VLDO2

FB2

EN_DCDC1

EN_DCDC2

VLDO2 = 1.8 V

R7

R8

4.7 mF

EN_LDO1

EN_LDO2

EN_LDO3

EN_LDO4

VLDO3

VLDO3 = 1.2 V

R9

FB3

BP

2.2 mF

R10

VIN_LDO1

VIN_LDO2

Vbat

0.1 mF

Vbat

VIN_LDO3/4

Vout1

VLDO4

FB4

VLDO4 = 1.3 V

MODE

R11

R12

Vbat

2.2 mF

AGND

Figure 26. RESET Circuit

32

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PACKAGE MATERIALS INFORMATION

www.ti.com

9-Nov-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65051QRSMRQ1

VQFN

RSM

32

3000

330.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Nov-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RSM 32

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPS65051QRSMRQ1

3000

Pack Materials-Page 2

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Products

Applications

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www.ti.com/audio

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dataconverter.ti.com

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logic.ti.com

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RFID

power.ti.com

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www.ti.com/omap

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TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

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型号：	TPS65052QRSMRQ1
厂家：	TEXAS INSTRUMENTS
描述：	IC POWER SUPPLY SUPPORT CKT, Power Management Circuit
文件：	总39页 (文件大小：1398K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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